Current compensation circuit and current mirror image error compensation circuit

Abstract

The invention provides a current compensation circuit. The current compensation circuit comprises a sampling circuit, a variable resistance circuit and a first current mirror circuit, wherein the sampling circuit is used for obtaining a difference value between a first sampling voltage and a second sampling voltage, the variable resistance circuit outputs different resistance values based on the control current, and the first current mirror circuit is used for mirroring a second output end current of the sampling circuit in proportion and outputting a compensation current based on a difference value between the second output end current and a first output end current of the sampling circuit. The voltage difference value between the two sampling ends is detected and converted into the compensation current, the current error of the circuit is corrected, meanwhile, the adjustable compensation current is output by adjusting the input control current, and the requirement for correcting the circuit error is met. The invention further provides a current mirror image error compensation circuit.

Description

Technical Field

[0001] The present invention relates to the field of electronics, and specifically but not limited to, relates to a current compensation circuit and a current mirror error compensation circuit. Background Art

[0002] When there is an error between two branches in the circuit, the current compensation circuit compensates one or both branches with a certain current, so that the errors of the two branches are corrected. For example, when the operational amplifier is offset, it can be adjusted to compensate for a certain current, thereby achieving the purpose of eliminating the offset. In addition, the error caused by the base current of the transistor can also be eliminated by base current compensation.

[0003] The channel length modulation effect of MOS tubes is an unavoidable problem. Generally, in current mirrors, the influence of the channel length modulation effect can be reduced by increasing the channel length L and adding cascode MOS tubes. However, in the mirroring process of power tubes and sampling tubes, neither of the above two methods can be used. In order to achieve a certain on-resistance and use a smaller area, the channel length of the power tube is the minimum value of the process. The smaller the channel length L, the more obvious the channel length modulation effect. The addition of cascode MOS tubes will increase the on-resistance. In order to achieve the target on-resistance, the chip area will also be increased. The deviation of the current mirror can be compensated by the current.

[0004] In addition, errors caused by circuit offsets, such as comparators, op amps, etc., also need to be compensated.

[0005] That is, the error of a particular circuit can be corrected by detecting the voltage difference between the two ends and then compensating for a certain current.

[0006] In view of this, it is necessary to provide a new structure or control method to solve at least part of the above problems. Summary of the invention

[0007] To address at least one or more problems in the background technology, the present invention provides a current compensation circuit.

[0008] According to one aspect of the present invention, a current compensation circuit includes:

[0009] A sampling circuit, comprising a first sampling terminal, a second sampling terminal, a first control terminal, a second control terminal, a first output terminal and a second output terminal, wherein the first sampling terminal is connected to a first sampling voltage, the second sampling terminal is connected to a second sampling voltage, the first control terminal and the second control terminal are both coupled to a variable resistor circuit, and the first output terminal and the second output terminal are both coupled to a first current mirror circuit, for obtaining a difference between the first sampling voltage and the second sampling voltage;

[0010] A variable resistor circuit, comprising an input terminal, a first terminal and a second terminal, wherein the input terminal is connected to a control current, the first terminal is coupled to the first control terminal of the sampling circuit, the second terminal is coupled to the second control terminal of the sampling circuit, and outputs different resistance values ​​based on the control current;

[0011] The first current mirror circuit has a first end and a second end, wherein the first end is coupled to the first output end of the sampling circuit and outputs a compensation current, and the second end is coupled to the second output end of the sampling circuit, and is used to proportionally mirror the second output end current of the sampling circuit and output the compensation current based on the difference between the second output end current and the first output end current of the sampling circuit.

[0012] Optionally, the sampling circuit includes:

[0013] A first field effect transistor, having a drain, a source and a gate, wherein the drain is coupled to the first end of the first current mirror circuit, the source is coupled to the first end of the variable resistor circuit, and the gate is connected to the first sampling voltage for obtaining the first sampling voltage;

[0014] The second field effect transistor has a drain, a source and a gate, wherein the drain is coupled to the second end of the first current mirror circuit, the source is coupled to the second end of the variable resistor circuit, and the gate is connected to the second sampling voltage for obtaining the second sampling voltage.

[0015] Optionally, the variable resistance circuit includes:

[0016] A control circuit having an input terminal and an output terminal, wherein the input terminal is connected to a control current and the output terminal is coupled to a variable resistor, and is used to generate a control signal based on the control current;

[0017] The variable resistor has a first end, a second end and a control end, wherein the first end is coupled to the source of the first field effect transistor, the second end is coupled to the source of the second field effect transistor, and the control end is coupled to the output end of the control circuit, and is used to adjust the output resistance value based on the control signal.

[0018] Optionally, the variable resistor includes:

[0019] The fourth field effect transistor has a drain, a source and a gate, wherein the drain is coupled to the source of the first field effect transistor, the source is coupled to the source of the second field effect transistor, and the gate is coupled to the output end of the control circuit, and is used to adjust the output resistance based on the control signal.

[0020] Optionally, the control circuit includes:

[0021] The third field effect transistor has a drain, a source and a gate. The drain is coupled to its gate and the gate of the fourth field effect transistor and connected to the control current. The source is coupled to the source of the fourth field effect transistor and is used to provide a gate bias voltage for the fourth field effect transistor based on the control current.

[0022] Optionally, the control circuit further includes:

[0023] A second current mirror circuit comprises a third transistor, a fourth transistor and a fifth transistor, wherein the drain of the third transistor is coupled to the gate thereof, the gate of the fourth transistor and the gate of the fifth transistor and connected to the control current, the source of the third transistor is grounded; the source of the fourth transistor is grounded; the drain of the fifth transistor is coupled to the drain of the third field effect transistor, and the source of the fifth transistor is grounded; the second current mirror circuit is used to mirror the current of the third transistor to the fourth transistor and the fifth transistor in proportion;

[0024] The third current mirror circuit includes a sixth field effect transistor and a seventh field effect transistor, wherein the drain of the sixth field effect transistor is coupled to its gate, the gate of the seventh field effect transistor and the drain of the fourth transistor, and the source of the sixth field effect transistor is coupled to the power supply voltage; the drain of the seventh field effect transistor is coupled to the source of the third field effect transistor, and the source of the seventh field effect transistor is coupled to the power supply voltage; the third current mirror circuit is used to proportionally mirror the current of the sixth field effect transistor to the seventh field effect transistor.

[0025] Optionally, the third current mirror circuit further includes:

[0026] an eighth field effect transistor, having a drain, a source and a gate, wherein the drain is coupled to the source of the fourth field effect transistor and the source of the second field effect transistor, the source is connected to the power supply voltage, and the gate is coupled to the gate of the sixth field effect transistor; the eighth field effect transistor is used to proportionally mirror the current of the sixth field effect transistor;

[0027] The ninth field effect transistor has a drain, a source and a gate, wherein the drain is coupled to the drain of the fourth field effect transistor and the source of the first field effect transistor, the source is connected to the power supply voltage, and the gate is coupled to the gate of the sixth field effect transistor; the ninth field effect transistor is used to proportionally mirror the current of the sixth field effect transistor.

[0028] Optionally, the current mirror ratios of the eighth field effect transistor and the ninth field effect transistor are the same.

[0029] Optionally, the first current mirror circuit includes:

[0030] A first transistor having a drain, a source and a gate, wherein the drain is coupled to the drain of the first field effect transistor and serves as an output end of the first current mirror circuit, the source is grounded, and the gate is coupled to the gate and drain of the second transistor;

[0031] The second transistor has a drain, a source and a gate. The drain is coupled to the gate and the drain of the second field effect transistor, and the source is grounded.

[0032] According to another aspect of the present invention, a current mirror error compensation circuit includes:

[0033] Any of the above current compensation circuits;

[0034] A first PMOS tube, having a drain, a source and a gate, wherein the drain is coupled to the first sampling terminal of the current compensation circuit, the source is connected to the power supply voltage, and the gate is connected to the control voltage;

[0035] A second PMOS tube has a drain, a source and a gate, wherein the drain is coupled to the drain of the first NMOS tube and connected to the compensation current output by the current compensation circuit, the source is connected to the power supply voltage, and the gate is connected to the control voltage;

[0036] A first NMOS transistor has a drain, a source and a gate, wherein the drain is coupled to the gate and the gate of the second NMOS transistor, the source is grounded, and the gate is coupled to the second sampling terminal of the current compensation circuit;

[0037] The second NMOS tube has a drain, a source and a gate, and the source is grounded.

[0038] The current compensation circuit proposed in the present invention detects the voltage difference between the two sampling terminals and converts it into a compensation current to correct the current error of the circuit. At the same time, the output adjustable compensation current is achieved by adjusting the input control current to meet the needs of correcting the circuit error. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the present invention and are used together with the description to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0040] Figure 1 A current compensation circuit according to an embodiment of the present invention is shown;

[0041] Figure 2 A current mirror error compensation circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0043] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The combination of different embodiments, the mutual replacement of some technical features in different embodiments, and the mutual replacement of the same or similar prior art means with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0044] "Coupled" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conductive medium such as a conductor, wherein the electrical conductive medium may contain parasitic inductance or parasitic capacitance, or a connection through an intermediate circuit or component described in the embodiments in the specification; indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functions, such as a connection through circuits or components such as switches, signal amplification circuits, and follower circuits. "Multiple" or "many" means two or more.

[0045] Reference Figure 1 An embodiment of the present invention provides a current compensation circuit, including a sampling circuit, a variable resistance circuit and a first current mirror circuit.

[0046] The sampling circuit has a first sampling terminal, a second sampling terminal, a first control terminal, a second control terminal, a first output terminal and a second output terminal, wherein the first sampling terminal INN is connected to the first sampling voltage, the second sampling terminal INP is connected to the second sampling voltage, the first control terminal and the second control terminal are both coupled to the variable resistance circuit, and the first output terminal and the second output terminal are both coupled to the first current mirror circuit for obtaining the difference between the first sampling voltage and the second sampling voltage.

[0047] The variable resistor circuit has an input terminal, a first terminal and a second terminal, wherein the input terminal is connected to a control current I in, the first terminal is coupled to the first control terminal of the sampling circuit, and the second terminal is coupled to the second control terminal of the sampling circuit, and outputs different resistance values ​​based on the control current I in.

[0048] The first current mirror circuit has a first end and a second end, wherein the first end is coupled to the first output end of the sampling circuit and outputs a compensation current Iout, and the second end is coupled to the second output end of the sampling circuit, and is used to proportionally mirror the second output end current of the sampling circuit and output the compensation current Iout based on the difference between the second output end current of the sampling circuit and the first output end current of the sampling circuit.

[0049] In one embodiment, if Figure 1 As shown, the sampling circuit includes a first field effect transistor PM1 and a second field effect transistor PM2. The first field effect transistor PM1 has a drain, a source and a gate, wherein the drain is coupled to the first end of the first current mirror circuit, the source is coupled to the first end of the variable resistor circuit, and the gate is connected to the first sampling voltage for obtaining the first sampling voltage. The second field effect transistor PM2 has a drain, a source and a gate, wherein the drain is coupled to the second end of the first current mirror circuit, the source is coupled to the second end of the variable resistor circuit, and the gate is connected to the second sampling voltage for obtaining the second sampling voltage.

[0050] In a specific embodiment, Figure 1As shown, the variable resistor circuit includes a control circuit and a variable resistor. The control circuit has an input end and an output end, the input end of which is connected to the control current I in, and the output end of which is coupled to the variable resistor, and is used to generate a control signal based on the control current I in. The variable resistor has a first end, a second end and a control end, the first end of which is coupled to the source of the first field effect transistor PM1, the second end of which is coupled to the source of the second field effect transistor PM2, and the control end of which is coupled to the output end of the control circuit, and is used to adjust the output resistance value based on the control signal.

[0051] In a specific embodiment, the variable resistor includes a fourth field effect transistor PM4. The fourth field effect transistor PM4 has a drain, a source and a gate, wherein the drain is coupled to the source of the first field effect transistor PM1, the source is coupled to the source of the second field effect transistor PM2, and the gate is coupled to the output end of the control circuit, and is used to adjust the output resistance value based on the control signal.

[0052] In a specific embodiment, the control circuit includes a third field effect transistor PM3. The third field effect transistor PM3 has a drain, a source and a gate, wherein the drain is coupled to the gate and the gate of the fourth field effect transistor PM4 and connected to the control current Iin, and the source is coupled to the source of the fourth field effect transistor PM4, and is used to provide a gate bias voltage for the fourth field effect transistor PM4 based on the control current Iin.

[0053] In another specific embodiment, the control circuit includes a third field effect transistor PM3, a second current mirror circuit and a third current mirror circuit. The third field effect transistor PM3 has a drain, a source and a gate, the drain of which is coupled to its gate and the gate of the fourth field effect transistor PM4 and connected to the control current I in, and the source of which is coupled to the source of the fourth field effect transistor PM4, for providing a gate bias voltage for the fourth field effect transistor PM4 based on the control current I in. The second current mirror circuit includes a third transistor NM3, a fourth transistor NM4 and a fifth transistor NM4, wherein the drain of the third transistor NM3 is coupled to its gate, the gate of the fourth transistor NM4 and the gate of the fifth transistor NM5 and connected to the control current I in, and the source of the third transistor NM3 is grounded. The source of the fourth transistor NM4 is grounded. The drain of the fifth transistor NM5 is coupled to the drain of the third field effect transistor NM3, and the source of the fifth transistor NM5 is grounded. The second current mirror circuit is used to mirror the current of the third transistor NM3 to the fourth transistor NM4 and the fifth transistor NM5 in proportion. The third current mirror circuit includes a sixth field effect transistor PM6 and a seventh field effect transistor PM7, wherein the drain of the sixth field effect transistor PM6 is coupled to its gate, the gate of the seventh field effect transistor PM7 and the drain of the fourth transistor NM4, and the source of the sixth field effect transistor PM6 is coupled to the power supply voltage VDD. The drain of the seventh field effect transistor PM7 is coupled to the source of the third field effect transistor NM3, and the source of the seventh field effect transistor PM7 is coupled to the power supply voltage VDD. The third current mirror circuit is used to mirror the current of the sixth field effect transistor PM6 to the seventh field effect transistor PM7 in proportion.

[0054] In another specific embodiment, the control circuit includes a third field effect transistor PM3, a second current mirror circuit and a third current mirror circuit. The third field effect transistor PM3 has a drain, a source and a gate, the drain of which is coupled to its gate and the gate of the fourth field effect transistor PM4 and connected to the control current I in, and the source of which is coupled to the source of the fourth field effect transistor PM4, for providing a gate bias voltage for the fourth field effect transistor PM4 based on the control current I in. The second current mirror circuit includes a third transistor NM3, a fourth transistor NM4 and a fifth transistor NM4, wherein the drain of the third transistor NM3 is coupled to its gate, the gate of the fourth transistor NM4 and the gate of the fifth transistor NM5 and connected to the control current I in, and the source of the third transistor NM3 is grounded. The source of the fourth transistor NM4 is grounded. The drain of the fifth transistor NM5 is coupled to the drain of the third field effect transistor NM3, and the source of the fifth transistor NM5 is grounded. The second current mirror circuit is used to mirror the current of the third transistor NM3 to the fourth transistor NM4 and the fifth transistor NM5 in proportion. The third current mirror circuit includes a sixth field effect transistor PM6, a seventh field effect transistor PM7, an eighth field effect transistor PM8 and a ninth field effect transistor PM9, wherein the drain of the sixth field effect transistor PM6 is coupled to its gate, the gate of the seventh field effect transistor PM7 and the drain of the fourth transistor NM4, and the source of the sixth field effect transistor PM6 is coupled to the power supply voltage VDD. The drain of the seventh field effect transistor PM7 is coupled to the source of the third field effect transistor NM3, and the source of the seventh field effect transistor PM7 is coupled to the power supply voltage VDD. The third current mirror circuit is used to mirror the current of the sixth field effect transistor PM6 to the seventh field effect transistor PM7 in proportion. The eighth field effect transistor PM8 has a drain, a source and a gate, wherein the drain is coupled to the source of the fourth field effect transistor PM4 and the source of the second field effect transistor PM2, the source is connected to the power supply voltage VDD, and the gate is coupled to the gate of the sixth field effect transistor PM6; the eighth field effect transistor PM8 is used to proportionally mirror the current of the sixth field effect transistor PM6. The ninth field effect transistor PM9 has a drain, a source and a gate, wherein the drain is coupled to the drain of the fourth field effect transistor PM4 and the source of the first field effect transistor PM1, the source is connected to the power supply voltage VDD, and the gate is coupled to the gate of the sixth field effect transistor PM6; the ninth field effect transistor PM9 is used to proportionally mirror the current of the sixth field effect transistor PM6. Preferably, the current mirroring ratio of the eighth field effect transistor and the ninth field effect transistor is the same.

[0055] In a specific embodiment, Figure 1As shown, the first current mirror circuit includes a first transistor NM1 and a second transistor NM2. The first transistor NM1 has a drain, a source and a gate, wherein the drain is coupled to the drain of the first field effect transistor PM1 and serves as the output end of the first current mirror circuit, the source is grounded, and the gate is coupled to the gate and drain of the second transistor NM2. The second transistor NM2 has a drain, a source and a gate, wherein the drain is coupled to the gate and the drain of the second field effect transistor PM2, and the source is grounded.

[0056] The working principle of the current compensation circuit is as follows:

[0057] The input control current I in is mirrored to the third field effect transistor PM3 through the fifth transistor NM5, so the |VGS| of the third field effect transistor PM3 will change with the change of the input current I in. When the input current I in increases, the |VGS| of the third field effect transistor PM3 increases. The gate and source of the third field effect transistor PM3 and the fourth field effect transistor PM4 are short-circuited respectively, so the |VGS| of the fourth field effect transistor PM4 will also increase with the increase of the control current I in. The fourth field effect transistor PM4 works in the deep linear region, which is equivalent to a resistor R. According to R∝1 / (|VGS|-|VTH|), the resistance R will decrease with the increase of the fourth field effect transistor I in, realizing a variable resistor R.

[0058] The first sampling tube PM1 and the second sampling tube PM2 are connected to the two voltages to be detected through the input terminal INN and the input terminal INP respectively, and the voltage difference between the two is converted from the gate to the source, and then a current will flow through the fourth field effect tube PM4. The current of the second sampling tube PM2 flows through the second transistor NM2 and then is mirrored to the first transistor NM1, Iout = I PM1 -I NM1 =I PM1 -I PM2 Therefore, the function of the first transistor NM1 and the second transistor NM2 is to subtract the current flowing through the first sampling tube PM1 from the current flowing through the second sampling tube PM2.

[0059] If the current of the seventh field effect transistor PM7 is set equal to the current of the fifth transistor NM5, the current of the seventh field effect transistor PM7 will all pass through the third field effect transistor PM3 and then flow to the fifth transistor NM5. If the current of the tenth field effect transistor PM10 is equal to the current of the sixth transistor NM6, the current of the tenth field effect transistor PM10 will all pass through the fifth field effect transistor PM5 and then flow to the sixth transistor NM6. None of the above will affect the branches where the eighth field effect transistor PM8 and the ninth field effect transistor PM9 are located.

[0060] The current flowing through the eighth field effect transistor PM8 and the current flowing through the ninth field effect transistor PM9 are set to be equal, both are I1. Assuming that the |VGS| of the first sampling transistor PM1 and the |VGS| of the second sampling transistor PM2 are equal, then the current flowing through the fourth field effect transistor PM4 (resistance R) is I2 = (INP-INN) / R, then the current flowing through the first sampling transistor PM1 is I1+I2, and the current flowing through the second sampling transistor PM2 is I1-I2. Subtracting the two, Iout = 2*I2, and Iout is the output compensation current.

[0061] Reference Figure 2 Another embodiment of the present invention provides a current mirror error compensation circuit, including the above-mentioned current compensation circuit, a first PMOS tube PM1, a second PMOS tube PM2, a first NMOS tube NM1 and a second NMOS tube NM2.

[0062] The first PMOS transistor PM1 has a drain, a source and a gate, wherein the drain is coupled to the first sampling terminal INN of the current compensation circuit, the source is connected to the power supply voltage VDD, and the gate is connected to the control voltage Vgate. The second PMOS transistor PM2 has a drain, a source and a gate, wherein the drain is coupled to the drain of the first NMOS transistor NM1 and connected to the compensation current I in output by the current compensation circuit, the source is connected to the power supply voltage VDD, and the gate is connected to the control voltage Vgate. The first NMOS transistor NM1 has a drain, a source and a gate, wherein the drain is coupled to the gate and the gate of the second NMOS transistor NM2, the source is grounded, and the gate is coupled to the second sampling terminal INP of the current compensation circuit. The second NMOS transistor NM2 has a drain, a source and a gate, wherein the source is grounded.

[0063] The current compensation circuit is applied to the current mirror error compensation circuit that produces the current error due to the channel length modulation effect. The specific application circuit is as follows Figure 2 As shown, the second PMOS transistor PM2 needs to mirror the current of the first PMOS transistor PM1. When the output terminal VOUT is short-circuited, that is, VOUT=0V, the voltage of VA is |VGS|. The first PMOS transistor PM1 and the second PMOS transistor PM2 both work in the saturation region, but their |VDS| are not equal. Due to the channel length modulation effect, the current mirrored by the second PMOS transistor PM2 will be smaller than expected. By adding Figure 1 The current compensation circuit shown can solve the problem of small mirror current of the second PMOS tube PM2: by connecting VA and the output terminal VOUT to the first sampling terminal INP and the second sampling terminal INN of the current compensation circuit respectively, a compensation current Iout will be obtained to compensate the mirror current of the second PMOS tube PM2, and by adjusting the control current Iin and the equivalent resistance R of the fourth field effect tube PM4, a suitable compensation current can be obtained.

[0064] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input terminal" and "inverting input terminal" in the logic controls involved in the specification or drawings can be interchanged or changed with each other, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic controls.

[0065] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the effects or advantages are not used to limit the scope of the invention. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A current compensation circuit, characterized in that: include: A sampling circuit, comprising a first sampling terminal, a second sampling terminal, a first control terminal, a second control terminal, a first output terminal and a second output terminal, wherein the first sampling terminal is connected to a first sampling voltage, the second sampling terminal is connected to a second sampling voltage, the first control terminal and the second control terminal are both coupled to a variable resistor circuit, and the first output terminal and the second output terminal are both coupled to a first current mirror circuit, for obtaining a difference between the first sampling voltage and the second sampling voltage; A variable resistor circuit, comprising an input terminal, a first terminal and a second terminal, wherein the input terminal is connected to a control current, the first terminal is coupled to the first control terminal of the sampling circuit, the second terminal is coupled to the second control terminal of the sampling circuit, and outputs different resistance values ​​based on the control current; The first current mirror circuit has a first end and a second end, wherein the first end is coupled to the first output end of the sampling circuit and outputs a compensation current, and the second end is coupled to the second output end of the sampling circuit, and is used to proportionally mirror the second output end current of the sampling circuit and output the compensation current based on the difference between the second output end current and the first output end current of the sampling circuit.

2. The current compensation circuit according to claim 1, characterized in that: The sampling circuit comprises: A first field effect transistor, having a drain, a source and a gate, wherein the drain is coupled to the first end of the first current mirror circuit, the source is coupled to the first end of the variable resistor circuit, and the gate is connected to the first sampling voltage for obtaining the first sampling voltage; The second field effect transistor has a drain, a source and a gate, wherein the drain is coupled to the second end of the first current mirror circuit, the source is coupled to the second end of the variable resistance circuit, and the gate is connected to the second sampling voltage for obtaining the second sampling voltage.

3. The current compensation circuit according to claim 2, characterized in that: The variable resistance circuit comprises: A control circuit having an input terminal and an output terminal, wherein the input terminal is connected to a control current and the output terminal is coupled to a variable resistor, and is used to generate a control signal based on the control current; The variable resistor has a first end, a second end and a control end, wherein the first end is coupled to the source of the first field effect transistor, the second end is coupled to the source of the second field effect transistor, and the control end is coupled to the output end of the control circuit, and is used to adjust the output resistance value based on the control signal.

4. The current compensation circuit according to claim 3, characterized in that: The variable resistor comprises: The fourth field effect transistor has a drain, a source and a gate, wherein the drain is coupled to the source of the first field effect transistor, the source is coupled to the source of the second field effect transistor, and the gate is coupled to the output end of the control circuit, and is used to adjust the output resistance based on the control signal.

5. The current compensation circuit according to claim 3, characterized in that: The control circuit comprises: The third field effect transistor has a drain, a source and a gate. The drain is coupled to its gate and the gate of the fourth field effect transistor and connected to the control current. The source is coupled to the source of the fourth field effect transistor and is used to provide a gate bias voltage for the fourth field effect transistor based on the control current.

6. The current compensation circuit according to claim 5, characterized in that: The control circuit further comprises: A second current mirror circuit comprises a third transistor, a fourth transistor and a fifth transistor, wherein the drain of the third transistor is coupled to the gate thereof, the gate of the fourth transistor and the gate of the fifth transistor and connected to the control current, the source of the third transistor is grounded; the source of the fourth transistor is grounded; the drain of the fifth transistor is coupled to the drain of the third field effect transistor, and the source of the fifth transistor is grounded; the second current mirror circuit is used to mirror the current of the third transistor to the fourth transistor and the fifth transistor in proportion; The third current mirror circuit includes a sixth field effect transistor and a seventh field effect transistor, wherein the drain of the sixth field effect transistor is coupled to its gate, the gate of the seventh field effect transistor and the drain of the fourth transistor, and the source of the sixth field effect transistor is coupled to the power supply voltage; the drain of the seventh field effect transistor is coupled to the source of the third field effect transistor, and the source of the seventh field effect transistor is coupled to the power supply voltage; the third current mirror circuit is used to proportionally mirror the current of the sixth field effect transistor to the seventh field effect transistor.

7. The current compensation circuit according to claim 6, characterized in that: The third current mirror circuit further includes: an eighth field effect transistor, having a drain, a source and a gate, wherein the drain is coupled to the source of the fourth field effect transistor and the source of the second field effect transistor, the source is connected to the power supply voltage, and the gate is coupled to the gate of the sixth field effect transistor; the eighth field effect transistor is used to proportionally mirror the current of the sixth field effect transistor; The ninth field effect transistor has a drain, a source and a gate, wherein the drain is coupled to the drain of the fourth field effect transistor and the source of the first field effect transistor, the source is connected to the power supply voltage, and the gate is coupled to the gate of the sixth field effect transistor; the ninth field effect transistor is used to proportionally mirror the current of the sixth field effect transistor.

8. The current compensation circuit according to claim 7, characterized in that: The current mirror ratio of the eighth field effect transistor and the ninth field effect transistor is the same.

9. The current compensation circuit according to claim 2, characterized in that: The first current mirror circuit comprises: A first transistor having a drain, a source and a gate, wherein the drain is coupled to the drain of the first field effect transistor and serves as an output end of the first current mirror circuit, the source is grounded, and the gate is coupled to the gate and drain of the second transistor; The second transistor has a drain, a source and a gate. The drain is coupled to the gate and the drain of the second field effect transistor, and the source is grounded.

10. A current mirror error compensation circuit, characterized in that: include: The current compensation circuit as claimed in any one of claims 1 to 9; A first PMOS tube, having a drain, a source and a gate, wherein the drain is coupled to the first sampling terminal of the current compensation circuit, the source is connected to the power supply voltage, and the gate is connected to the control voltage; A second PMOS tube has a drain, a source and a gate, wherein the drain is coupled to the drain of the first NMOS tube and connected to the compensation current output by the current compensation circuit, the source is connected to the power supply voltage, and the gate is connected to the control voltage; A first NMOS transistor has a drain, a source and a gate, wherein the drain is coupled to the gate and the gate of the second NMOS transistor, the source is grounded, and the gate is coupled to the second sampling terminal of the current compensation circuit; The second NMOS tube has a drain, a source and a gate, and the source is grounded.

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