Macro-instruction set architecture based on row-wise partitioning

Abstract

A macro instruction set architecture based on row-wise partitioning comprises six macro instructions including args, regs, load, store, remap and complex, the args configure key parameters used for operation calculation, the reg configures macro registers needed by the complex instruction, the load and the store control data movement between an off-chip memory and an on-chip memory, the remap is used for remapping data from one macro register to another macro register, and the remap is used for remapping data from the other macro register to the other macro register. The method comprises the following steps of: firstly, constructing a kernel function by using a complex macro instruction without actual data movement, starting operator calculation by using the complex macro instruction, constructing the kernel function by using the regs and the complex, and preparing operands by using other macro instructions. The macro instruction set architecture can perform complex operations within one instruction. This ability enables programmers to achieve more functions with fewer instructions, thereby simplifying programming and debugging processes.

Description

Technical Field

[0001] The present invention relates to a computer instruction system, and more particularly to a macro instruction set architecture based on row-wise blocking. Background Art

[0002] Deep Neural Network (DNN) has brought unprecedented breakthroughs in the field of artificial intelligence with its excellent performance. However, DNN still faces major challenges in achieving optimal energy efficiency on general-purpose processors, which are mainly reflected in the high power consumption and long latency of general-purpose processors. The frequent off-chip memory accesses generated during DNN operations are the main cause of high power consumption and long latency. Fully exploiting data locality can effectively reduce the number of off-chip memory accesses. In recent years, many domain-specific architectures (DSA) have utilized data locality through technologies such as data stationary, operator fusion, and tiling. Compared with general-purpose processors, DSA has achieved better energy efficiency. However, the new requirements of the continuous development of DNN have brought new challenges to DSA, including: wider operand bit width, larger memory usage, and more complex network models. Although DSA can effectively utilize data locality, the inflexibility of its memory architecture hinders the efficient use of on-chip memory (OCM), making it difficult to meet DNN's requirements for wider operands and larger memory usage. In addition, traditional fine-grained operand scheduling and scalar or vector register-based programming are not suitable for DNN operations optimized at the block or layer level. Existing memory allocation and recycling mechanisms cannot effectively cope with frequent reloading, thus creating performance bottlenecks. Summary of the invention

[0003] In order to solve the above technical problems, the present disclosure discloses a macro instruction set architecture based on row-wise blocking, including six macro instructions: parameter args, register regs, load, store, remap and compute. The parameter args macro instruction configures key parameters for operation calculation, the register regs macro instruction configures macro registers required for compute instructions, the load macro instruction and the store macro instruction control data movement between off-chip memory and on-chip storage, the remap macro instruction is used to remap data from one macro register to another macro register without actual data movement, and the compute macro instruction is used to start operator calculation, wherein the register regs macro instruction and the compute macro instruction are used to construct kernel functions, and other macro instructions are used to prepare operands.

[0004] Through the above technical solutions, the macro instruction set architecture is a flexible CISC-style macro instruction set architecture (mISA), including variable-size macro registers (mReg), which synergistically optimizes data locality from hardware and software to improve DNN reasoning performance. The key advantage of mISA is its ability to perform complex operations within a single instruction. This capability allows programmers to achieve more functions with fewer instructions, thereby simplifying the programming and debugging process. This flexibility also allows mISA instructions to adapt to various applications and tasks more effectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 It is a structural diagram of a macro instruction set architecture based on row-wise blocking provided in one embodiment of the present disclosure;

[0006] Figure 2 is a row-wise tiling schematic diagram provided in one embodiment of the present disclosure;

[0007] Figure 3 is a schematic diagram of the workflow of the remapping mechanism provided in one embodiment of the present disclosure;

[0008] Figure 4 is a schematic diagram of an Input List provided in one embodiment of the present disclosure;

[0009] Figure 5 is a schematic diagram of Address Mapping provided in one embodiment of the present disclosure;

[0010] Figure 6is a schematic diagram of the execution process of a load instruction provided in one embodiment of the present disclosure;

[0011] Figure 7 is a schematic diagram of overlapping calculation areas of operator fusion provided in one embodiment of the present disclosure;

[0012] Figure 8 is a schematic diagram for comparing remap instruction codes provided in one embodiment of the present disclosure;

[0013] Fig. 9 is a schematic diagram of the remap instruction execution process provided in one embodiment of the present disclosure;

[0014] Fig.10 It is a schematic diagram of row-wise tiling convolution provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] In order to make those skilled in the art understand the technical solutions disclosed in the present disclosure, the following will be combined with the embodiments and related appended Figures 1 to 10 , the technical solutions of various embodiments are described, and the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. The terms "first", "second", etc. used in the present disclosure are used to distinguish different objects, rather than to describe a specific order. In addition, "including" and "having" and any variations thereof are intended to cover and not exclude inclusion. For example, a process, or method, or system, or product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, systems, products or devices.

[0016] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0017] See also Figure 1In one embodiment, the present disclosure discloses a macro instruction set architecture based on row-wise blocking, including six macro instructions: parameter args, register regs, load, store, remap and compute. The parameter args macro instruction configures key parameters for operation calculation, the register regs macro instruction configures macro registers required for compute instructions, the load macro instruction and the store macro instruction control data movement between off-chip memory and on-chip storage, the remap macro instruction is used to remap data from one macro register to another macro register without actual data movement, and the compute macro instruction is used to start operator calculation, wherein the register regs macro instruction and the compute macro instruction are used to construct kernel functions, and other macro instructions are used to prepare operands.

[0018] For this embodiment, the args instruction configures key parameters for operation calculations, such as kernel size, stride, and padding for convolution operations. Each instruction can transmit 32-bit parameters. Multiple steps may be required to complete all parameter configurations.

[0019] The regs instruction configures the macro registers required by the compute instruction. Multiple regs instructions are generated based on the number of mRegs actually used. The mReg_s1 of the first regs instruction defaults to the destination register, and the mReg_s1 and mReg_s2 in the subsequent instructions both represent the source register.

[0020] Load / store instructions control the movement of data between off-chip memory (Dynamic Random Access Memory, DRAM) and on-chip storage.

[0021] The remap instruction is used to remap data from one macro register to another macro register without actually moving the data. This can effectively reduce data reloading and redundant calculations.

[0022] The compute instruction is used to start the operator calculation. PC indicates the entry address of the operator function. mReg_d and size indicate that the calculation result needs to be stored in mReg_d and the required storage space size.

[0023] The benefits of macro instructions: (a) Same as the usual instruction set architecture, as the interface between software and hardware, the advantage is that it decouples the design of software and hardware, allowing software and hardware developers to focus on their own fields. (b) remap is an instruction designed for macro registers, the advantage is that it can reuse data across data scopes, improving software programming efficiency. (c) compute jumps to the function entry through the PC, and the function's function can be customized by the user, so it is flexible and scalable.

[0024] These macros work together, and their fundamental purpose is to support efficient scheduling and computation of row-wise partitioned convolutional data. This is because row-wise partitioned data has good data locality, but the existing instruction set architecture and microarchitecture do not support row-wise partitioning well.

[0025] The macroinstruction set architecture of the present invention can be applied to the following fields: 1) Image and video processing: real-time image recognition, video analysis, augmented reality and other applications. 2) Natural language processing: real-time speech recognition, text translation, sentiment analysis and other applications. 3) Autonomous driving: vehicle perception system, path planning, driving decision-making, etc. 4) Medical image analysis: automatic diagnosis of medical images, lesion detection, etc. 5) Intelligent monitoring: behavior analysis, face recognition in security monitoring systems, etc. 6) Robot control: intelligent control and environmental perception of industrial robots, service robots, etc.

[0026] The macroinstruction set architecture of the present invention has the following features: 1) Dynamic tiling mechanism based on MISA: a mechanism for dynamically adjusting the tiling factor, which improves data locality utilization and memory management efficiency. 2) Multi-core collaborative scheduling mechanism: a scheduling mechanism that improves inter-core communication and synchronization efficiency. 3) Advanced memory management and remapping mechanism: a memory management and remapping mechanism that improves OCM utilization and data reuse efficiency. 4) Diversified operator fusion strategy: an operator fusion strategy that adapts to different DNN models. 5) Reconfigurable hardware architecture: an architecture design that dynamically adjusts hardware configuration to adapt to different application requirements.

[0027] In another embodiment, each macroinstruction uses one or more of eight fields, including: a specific kernel kernel_id specifying the current instruction operation, a destination macro register mReg_d, a source macro register mReg_s1, a source macro register mReg_s2, a program counter PC, an address address, a size size, and parameters params.

[0028] For this embodiment, a macroinstruction can use one or more of these fields. For example, the args instruction only uses the parameter field. MISA contains eight fields: kernel_id, mReg_d, mReg_s1, mReg_s2, program counter (PC), address, size, and parameters (params).

[0029] The fields are defined as follows:

[0030] kernel_id specifies the specific kernel on which the current instruction operates.

[0031] mReg_d and mReg_s represent the target mReg and the source mReg, respectively.

[0032] The information field contains parameters related to the specific macro instruction.

[0033] PC is unique to the compute instruction and represents the entry address of the program. It enables developers working on different operators to write different macro kernel functions and combine them seamlessly. For example, Conv1 and Conv2 can be connected continuously within the residual block. This feature enhances the composability of the operator library, enabling it to be seamlessly integrated into the deep learning software stack.

[0034] In another embodiment, multiple blocks obtained by row-wise blocking are stored in macro registers of variable size.

[0035] In this embodiment, the data block object is a feature map or an activation. Figure 2 As shown in the figure, row-wise tiling requires dividing the data into multiple tiles along the row direction. This tile is used as the operand of the macro instruction set architecture (mISA) and stored in mReg.

[0036] Usually DNN uses multi-batch processing and block processing, which results in the size of tiles being in KB. Therefore, misa uses 4KB as the basic unit, and the on-chip memory OCM consists of multiple banks, each of which is 4KB in size, and each bank has independent read and write ports. When allocating OCM space for mReg, it can be adjusted between 4KB and 32KB according to actual needs.

[0037] For example, in the instruction load(A2, base+40K, 8KB), the size of a row of data is 8KB, so two banks are allocated. The two banks allocated for this row of data do not have to be continuous in space, but are allocated only based on the availability of OCM. At the same time, the hardware analyzes the life cycle of the data and releases the data that is no longer used in time.

[0038] The macro-architecture register is used on the software side, such as load (A1, addr1, 8KB) in the embodiment, where A1 is the architecture register and the real physical register is allocated through hardware renaming, assuming P4 is allocated.

[0039] At the software level, macro registers are similar to scalar registers, which are abstract concepts. When programmers write assembly code or low-level language code, they directly use the name or number of the register to perform data operations. At the hardware level, macro registers and scalar registers are actual storage units. However, the two are slightly different. Scalar registers directly store operands, while macro registers store the OCM.id of operands (that is, the number stored on the chip, which indirectly stores operands). A macro register can store 1 to 8 OCM.ids, and each OCM.id points to a 4KB storage space. Therefore, a macro register can represent a data size of 4KB to 32KB. Therefore, the data stored in the macro register is of variable size.

[0040] Row-wise block division is to divide the data into rows to obtain a row of data. Subsequent control and calculation are based on a row of data as the minimum unit (similar to vector calculation). The advantage of managing with a row of granularity is that the control logic is concise, parallelization can be achieved, data reuse is convenient, and data locality can be mined. The disadvantage is that the size of a row of data is uncertain, and there is currently no variable-length register for managing data of this granularity.

[0041] Therefore, we designed an instruction set and a hardware scheduler to support the row-wise block method. We assume that the data size does not exceed 32KB and is managed in 4KB units. For example, if a row of data is 7KB, two 4KB storage units are allocated. In other words, two OCM.ids are allocated to a macro register, and the data space indicated by one OCM.id is 4KB.

[0042] In another embodiment, the macro register is represented by 6 bits, wherein the upper 2 bits represent the type of the operand, and the remaining 4 bits represent the index value 0-15.

[0043] For this embodiment, mReg helps software to more effectively utilize data locality through explicit programming. To address the challenges of memory management, our mReg uses 6 bits, where the upper 2 bits represent the type of operand and the remaining 4 bits represent the index value 0 to 15. For example, for a convolutional neural network, the operand types include feature maps and weights.

[0044] There are 16 architectural registers, so 4 bits are needed. There are three types of operands: feature map, weight, and bias, so 2 bits are needed to represent the type. Not limited to 6 bits.

[0045] In another embodiment, the macro registers include macro architectural registers and macro physical registers.

[0046] In this embodiment, mReg is divided into two types: macro architectural register (macro ArchitecrueRegister, mAR, abbreviated as A in the code) and macro physical register (macro Physical Register, mPR, abbreviated as P in the code).

[0047] In another embodiment, a hardware remapping mechanism is further included, wherein the hardware remapping mechanism includes: an input table, renaming, and address mapping.

[0048] In this embodiment, in order to support KB-level on-chip storage management, the present invention designs a corresponding OCM management mechanism, called remapping. Figure 3 The figure shows the workflow of the remapping mechanism. The hardware remapping mechanism consists of three parts: Input List, Renaming, and Address Mapping.

[0049] When a macro instruction is input into the hardware, it will first enter the Remapping process, which completes the data mapping between DRAM and OCM. This allows the computing core (kernel) to obtain the correct operands and perform calculations. Finally, the calculation results are written back to the specified location of the OCM.

[0050] In another embodiment, the structure of the input table includes a macro physical register, a tag bit, and a valid bit.

[0051] In this embodiment, the structure of Input List is as follows: Figure 4 As shown in the figure, there are 64 entries in total, and the three fields are mPR (physical macro register), tag (tag bit), and valid (valid bit). The tag bit contains address and size.

[0052] In another embodiment, the renamed structure includes a rename map table and a free list.

[0053] In this embodiment, the structure of Renaming is the same as the traditional renaming mechanism, including a renaming mapping table (Register Alias ​​Table, RAT) and a free list (Free List, FL), wherein the RAT has 16 entries and the FL has 64 entries.

[0054] In another embodiment, the address mapping structure includes a macro physical register, a reference counter, and an on-chip stored number OCM.id.

[0055] In this embodiment, the structure of Address Mapping is as follows: Figure 5 There are 64 entries in total, and the three fields are mPR, ref_cnt (reference counter) and OCM.id.

[0056] ref_cnt is used to facilitate hardware analysis of data life cycle. The value in ref_cnt indicates how many instructions are using the data stored in the current mPR. OCM.id indicates the bank number in OCM, such as Figure 5 As shown in the figure, each mPR can be allocated 1 to 8 banks, that is, 4KB to 32KB of storage space. The bank number used by a certain mPR will be recorded in the OCM.id of Address Mapping.

[0057] In another embodiment, the value in the reference counter indicates how many instructions are using the data stored in the current macro physical register.

[0058] In another embodiment, the execution process of the load instruction is as follows: Figure 6 As shown in the code of two adjacent iterations, two load instructions load the same data, which is called shared data. The two adjacent iterations load the shared data into different mARS (A0 and A1), which makes it difficult to analyze the life cycle of the shared data. When the time interval between the two load instructions is relatively long, the shared data may be loaded again due to the limitations of the OCM storage and register recycling strategy. Therefore, an effective hardware mechanism to record the data life cycle is crucial.

[0059] To determine whether the required data has been loaded into the OCM, the address and size specified in the load instruction are compared with the corresponding tag in the InputList.

[0060] If a miss occurs (the first load instruction), and there is enough space in OCM, the load instruction is executed according to standard procedures. Figure 6 A2 in mPR (corresponding to Figure 6 In P3, mPR is selected from the free list FL. At the same time, two available banks in OCM are selected to store data, and the corresponding entries in RAT, FL and Address Mapping are updated. Finally, the Input List caches the address and size of the new data to the corresponding mPR.id (corresponding Figure 6 The required data is loaded from DRAM to the location specified in OCM (corresponding to P3 in Figure 6 5 and 7 in the OCM.id).

[0061] Conversely, if the Input List hits (the second load instruction), it means that the data already exists in the OCM. Then the mPR.id is obtained from the associated entry, and then the mAR.id (corresponding to Figure 6 A1 in the RAT) is redirected to mPR.id in the RAT (corresponding to Figure 6 in P3).

[0062] In another embodiment, the execution process of the remap instruction: operator fusion may cause repeated calculation problems. Figure 7 The figure shows two adjacent convolution calculations (Conv1 and Conv2) in ResNet18. After the operator fusion, each iteration will output a row ofm_tile. For any two adjacent outputs ofm_tile1 and ofm_tile2, the value in the dark area of ​​the second activation layer (activation) needs to be used as input. However, operator fusion only saves input data and output data, but not the intermediate calculation results. Therefore, when calculating ofm_tile2, the dark area needs to be calculated repeatedly. The dark area is the overlapping area of ​​two adjacent calculations. Caching this part of the intermediate results can reduce this redundant calculation, but OCM needs to be precisely controlled.

[0063] From Figure 8 As shown in code 1, in the second iteration, the calculation results of Conv1 are the same as the results A4 and A5 in the first iteration. To this end, a remap instruction is added, and multiple mARs can be mapped to the same mPR through the remap instruction, thereby completing the reuse of overlapping area data.

[0064] like Figure 8Code 2 shown in the figure verifies the mPR.id referenced by A4 in the RAT for the instruction remap(A3, A4) and directly remaps A3 to this mPR.id (corresponding to Fig. 9 P2 in ), without physically moving the data, such as Fig. 9 shown.

[0065] In another embodiment, the release of Remapping resources: To facilitate hardware analysis of data life cycle, we implement a reference counter (ref_cnt) in Address Mapping. Ref_cnt indicates the number of instructions that use the data stored in Address Mapping. Figure 6 In the scene, the ref_cnt corresponding to P3 will increase by 1. Fig. 9 In the scene, the ref_cnt corresponding to P2 will be increased to 2.

[0066] When the instruction with P2 as the source operand completes the calculation of the output feature map element, the corresponding ref_cnt value is reduced by 1. When the value of ref_cnt is equal to 0, it means that the associated Address Mapping and OCM resources can be safely released. Otherwise, the related table entries will not be allocated by the new instruction.

[0067] It should be noted that Address Mapping has 64 entries, which can dynamically allocate space for 1 to 8 4KB units, and the theoretical OCM size is 2048KB. When the tile size is 8×4KB, only 8 mPRs can be used at the same time due to the physical 256KB limitation of OCM. On the contrary, setting the row size to 1 allows all 64 mPRs to make full use of OCM without waste, thereby optimizing space utilization. If OCM space is insufficient or FL is empty, back pressure will occur and instructions will need to wait for resources to be released. The completed load or remap operation dispatches the macroinstruction to the issue queue, indicating that the processing and allocation are successful, thereby simplifying execution.

[0068] In another embodiment, the implementation of the ResNet18 convolution operator: Taking a residual block of ResNet18 as an example, the parameter information of a convolution is as follows:

[0069] kernel_size = 3

[0070] stride = 1

[0071] padding = 1

[0072] The corresponding args(kernel_size, stride, padding) directive is as follows:

[0073] args(3, 1, 1)

[0074] Among them, kernel_size=3 means that 3 rows of input feature map tiles are required to perform the convolution operation, and then 1 row of output feature map tile is output, such as Fig.10 Therefore, the three rows of input tiles (e.g., input_tile1~input_tile3) required for the calculation are respectively allocated three source mRegs (assuming A0~A2), and one destination mReg (assuming A3) is allocated for one row of output_tile (output_tile2).

[0075] The corresponding regs(mReg_s1, mReg_s2) instructions are as follows:

[0076] regs(A3, A0)

[0077] regs(A1, A2)

[0078] Because each regs instruction can only configure two macro registers, two regs instructions are required to complete the above register allocation. Among them, the value in mReg_s1 of the first regs instruction represents the destination register.

[0079] After allocating the logical registers, the operands required for calculation need to be loaded into the specified registers. Assuming that the addresses of input_tile1~input_tile3 in DRAM are addr1~addr3 respectively, and the size of a row of tiles is 8KB, the corresponding load(mReg, address, size) instruction is as follows:

[0080] load(A1, addr1, 8KB)

[0081] load(A2, addr2, 8KB)

[0082] load(A3, addr3, 8KB)

[0083] During the loading process, Remapping completes the automatic allocation of on-chip storage and the mapping of logical registers to physical registers.

[0084] After input_tile1~input_tile3 are loaded into the on-chip storage, the compute instruction is started. Assume that the PC of the compute function entry is hexadecimal 0x0000 0001 (i.e., the entry of the convolution operator function). The destination register is A3, and the size of the tile is 8KB (padding=1, stride=1, the output feature map is the same size as the input feature map, so the size is also 8KB). The corresponding compute(mReg_d, PC, size) instruction is as follows:

[0085] compute(A3, 0x0000 0001, 8KB)

[0086] After the calculation is completed, the result in register A3 is stored in addr_o of DRAM. The corresponding store(mReg,address,size) is as follows:

[0087] store(A3, addr_o, 8KB)

[0088] In summary, a convolution operator process code is as follows:

[0089] args(3, 1, 1)

[0090] regs(A3, A0)

[0091] regs(A1, A2)

[0092] load(A1, addr1, 8KB)

[0093] load(A2, addr2, 8KB)

[0094] load(A3, addr3, 8KB)

[0095] compute(A3, 0x0000 0001, 8KB)

[0096] store(A3, addr_o, 8KB)

[0097] In order to facilitate calling, multiple macro instructions can be flexibly encapsulated into a function, so that programmers can flexibly develop and call them repeatedly.

[0098] In another embodiment, macro-based convolution function: We use miSA to design a programming paradigm similar to CUDA kernel functions, which simplifies project migration for developers familiar with CUDA. In this paradigm, when the host code launches the kernel, it sets Tile_shape (the dimension of the input data) by executing configuration parameters. Taking a convolution operator as an example, its function declaration is as follows:

[0099] Conv<<<Tile_shape> >>(output, input, weight, stride, padding, …)

[0100] The configuration of output and input is completed through the regs instruction; the configuration of weight is similar; the configuration of parameters such as stride and padding is completed through the args instruction.

[0101] For ease of understanding, assume that the PC address after the function is instantiated is 0x0000 0001. When all parameters are configured and operands are ready, the compute instruction starts the calculation from the PC.

[0102] In another embodiment, implementation of ResNet18 residual block fusion: This operator startup method of the present invention supports function calls within runtime kernel functions, which enables developers working on different operators to write different macro kernel functions and combine them seamlessly.

[0103] The residual block in ResNet18 contains two convolution operators, named Conv1 and Conv2. You can declare a residual block function and then call the Conv function multiple times to achieve operator fusion of the residual block. The fused code is as follows:

[0104] Residual_fusion<<<Tile_shape1, Tile_shape2> >>(output, input, weight1,weight2, stride1, stride2, padding1, padding2, …)

[0105] {

[0106] for(int i = 0; i <output_height; i++):

[0107] / / overlapping calculation

[0108] remap(activation[A3], activation[A4])

[0109] remap(activation[A4], activation[A5])

[0110] / / New calculation

[0111] Conv1<<<Tile_shape1> >>(activation, input, weight1, stride1,padding1, …)

[0112] Conv2<<<Tile_shape2> >>(output, activation, weight2, stride2,padding2, …)

[0113] }

[0114] Although the embodiments of the present invention are described above in conjunction with the accompanying drawings, the present invention is not limited to the above specific embodiments and application fields, and the above specific embodiments are only illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present invention, all of which belong to the protection of the present invention.

Claims

1. A macro instruction set architecture based on row-wise blocking, comprising: There are six macro instructions: parameter args, register regs, load, store, remap and compute. The parameter args macro instruction configures the key parameters for operation calculation, the register regs macro instruction configures the macro registers required for the compute instruction, the load macro instruction and the store macro instruction control the data movement between the off-chip memory and the on-chip storage, the remap macro instruction is used to remap data from one macro register to another macro register without actual data movement, and the compute macro instruction is used to start operator calculation. Among them, the register regs macro instruction and the compute macro instruction are used to construct kernel functions, and other macro instructions are used to prepare operands.

2. The macroinstruction set architecture of claim 1, wherein each macroinstruction preferably uses one or more of eight fields, wherein the eight fields include: Specifies the specific kernel kernel_id, destination macro register mReg_d, source macro register mReg_s1, source macro register mReg_s2, program counter PC, address address, size size and parameters params for the current instruction operation.

3. The macroinstruction set architecture of claim 1, wherein: The multiple blocks obtained by row-wise blocking are stored in macro registers of variable size.

4. The macroinstruction set architecture of claim 1, wherein: The macro register is represented by 6 bits, wherein the upper 2 bits represent the type of the operand, and the remaining 4 bits represent the index value 0-15.

5. The macroinstruction set architecture of claim 1, wherein: The macro registers include macro architectural registers and macro physical registers.

6. The macroinstruction set architecture of claim 1, further comprising a hardware remapping mechanism, the hardware remapping mechanism comprising: an input table, renaming, and address mapping.

7. The macro instruction set architecture of claim 6, wherein the structure of the input table comprises a macro physical register, a tag bit, and a valid bit.

8. The macroinstruction set architecture of claim 6, wherein the renamed structure comprises a rename mapping table and a free table.

9. The macro instruction set architecture as claimed in claim 6, wherein the structure of the address mapping comprises a macro physical register, a reference counter and an on-chip stored number OCM.id.

10. The macroinstruction set architecture of claim 9, wherein: The value in the reference counter indicates how many instructions are using the data stored in the current macro physical register.

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