Memory fault processing method and device, electronic equipment and readable storage medium

Abstract

The invention provides a memory fault processing method and device, electronic equipment and a readable storage medium, and in the method, the electronic equipment can determine a first storage unit with a fault and isolate the first storage unit. The electronic equipment can carry out pressure measurement on the first storage unit to obtain the fault level of the first storage unit, the electronic equipment executes corresponding operation on the first storage unit according to the fault level of the first storage unit, and when the fault level of the first storage unit indicates that the first storage unit is in a first risk level, the first storage unit is in a second risk level. The operations include de-isolating the first memory cell. According to the method and the device, after the faulted storage unit is isolated, the voltage of the storage unit can be measured, and the real fault level of the storage unit is obtained. Wherein when the fault level of the first storage unit is the first risk level, the electronic equipment can remove isolation of the first storage unit, the first storage unit can be continuously used, and the number of available storage units can be increased.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of storage technology, and in particular, to a memory failure processing method, device, electronic device, and readable storage medium. Background Art

[0002] Memory is an important component of electronic devices, used to temporarily store the operation data of the processor in the electronic device, as well as the data exchanged with external devices such as hard disks. Electronic devices may include a memory controller, which is used to manage the memory and is responsible for data exchange between the memory and the processor.

[0003] Currently, a memory controller can verify whether the data stored in a storage unit of the memory is correct. When the data is wrong, the memory controller can report memory fault information to the operating system through the processor, and the operating system can isolate the failed storage unit.

[0004] As the operation time of electronic devices increases, more and more memory cells are isolated, resulting in a decrease in the number of available memory cells. Summary of the invention

[0005] The embodiments of the present application provide a memory fault processing method, device, electronic device and readable storage medium, which can release storage units with low fault levels and increase the number of available storage units.

[0006] In the first aspect, an embodiment of the present application provides a memory fault processing method, and the execution subject of the method can be an electronic device or a chip in the electronic device. The following description will be made using an electronic device as an example. The electronic device can detect a storage unit and determine a faulty first storage unit. In order to avoid obtaining erroneous data from the faulty first storage unit, the electronic device can isolate the first storage unit. In an embodiment of the present application, after isolating the first storage unit, the electronic device can perform a stress test on the first storage unit to obtain the fault level of the first storage unit. Because the failure mode of some faulty storage units is a reversible or recoverable failure such as a soft failure, if the electronic device keeps isolating the first storage unit, the number of available storage units will become smaller and smaller.

[0007] In the embodiment of the present application, the electronic device can perform a corresponding operation on the first storage unit according to the fault level of the first storage unit, wherein when the fault level of the first storage unit is the first risk level, the operation includes releasing the isolation of the first storage unit. Since the electronic device can release the isolation of the first storage unit, the first storage unit can continue to be used by the electronic device, and the available storage units in the electronic device can be increased.

[0008] In a possible implementation, the failure level of the first storage unit may further include a second risk level, and the first risk level is lower than the second risk level. When the failure level is the second risk level, performing the corresponding operation on the first storage unit may specifically include: releasing the isolation of the first storage unit and establishing a memory pool, the memory pool is used to manage the first storage unit, and the first storage unit is used to store data with external memory backup.

[0009] In this implementation, for a second risk level higher than the first risk level, in order to prevent the first storage unit of the second risk level from continuing to evolve into a storage unit with a higher risk, the electronic device can de-isolate the first storage unit and establish a memory pool, wherein the memory pool is used to manage the first storage unit, and the first storage unit is used to store data with external memory backup.

[0010] In this implementation, on the one hand, the electronic device releases the isolation of the first storage unit, which can increase the available storage units in the electronic device. On the other hand, the first storage unit can store data with external storage backup, so that even when the first storage unit fails or evolves to a higher risk level, the electronic device can obtain the backup data from the external storage without affecting the normal data reading of the electronic device.

[0011] In some embodiments, the first risk level and the second risk level may indicate that the failure mode of the first storage unit is a soft failure.

[0012] In a possible implementation, when the fault level is a third risk level, the operation is to continue isolating the first storage unit, and the second risk level is lower than the third risk level.

[0013] In this implementation, the third risk level is used to indicate that the failure level of the first storage unit is high, so the electronic device can continue to isolate the first storage unit to avoid reading erroneous data from the first storage unit.

[0014] In some embodiments, the third risk level may indicate that the failure mode of the first storage unit is a hard failure.

[0015] The following describes the stress test process of the electronic device on the first storage unit with a fault:

[0016] In some embodiments, the stress test includes at least one of the following: at least one mode of read / write test, at least one mode of write disturb test. Exemplarily, the stress test may include at least one mode of read / write test. Alternatively, the stress test may include at least one mode of write disturb test. Alternatively, the stress test includes at least one mode of read / write test and at least one mode of write disturb test.

[0017] In a possible implementation, the number of the first storage unit is at least one, and the stress test may include at least one mode of read and write test. The electronic device may perform the following steps:

[0018] Step A: writing preset data into at least one first storage unit.

[0019] Step B, reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0020] Step C: when the verification is successful, writing the complement of the preset data into the at least one first storage unit.

[0021] Step D, reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0022] Step E, when the verification is successful, return to execute step A-step D, repeat the execution n times and execute step F after all the verifications are successful, and determine that the read-write test has not passed when any verification fails; or, when the verification fails, determine that the read-write test has not passed; wherein n is an integer greater than or equal to 1;

[0023] Step F: writing preset data into the at least one first storage unit.

[0024] Step G, reading data from the at least one first storage unit in sequence from high address to low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0025] Step H: when the verification succeeds, writing the complement of the preset data into the at least one first storage unit.

[0026] Step I, according to the address of the at least one first storage unit, read data from the at least one first storage unit in order from high address to low address, and verify the data in the first storage unit.

[0027] Step J, when the verification is successful, return to execute step F-step I, repeat the execution m times and determine that the read-write test has passed after the verification is successful. When any verification fails, it is determined that the read-write test has not passed; or, when the verification fails, it is determined that the read-write test has not passed; m is an integer greater than or equal to 1.

[0028] In a possible implementation, there is at least one first storage unit, and the stress test may include at least one mode of write interference test. The electronic device may write preset data in a storage unit near the at least one first storage unit, and record the first storage unit, as well as the data in the adjacent rows and columns of the first storage unit. Among them, the storage unit near the first storage unit can be understood as a storage unit that is X rows and Y columns away from the first storage unit, and X and Y are both integers greater than or equal to 1.

[0029] The electronic device can read data from the first storage unit, and the adjacent rows and columns of the first storage unit, and verify the data in the first storage unit, and the adjacent rows and columns of the first storage unit. When the verification succeeds, the electronic device can determine that the write test passes, and when the verification fails, the electronic device can determine that the write test fails.

[0030] In some embodiments, when the stress test includes a read-write test and a write disturbance test, the electronic device may obtain the fault level of the first storage unit according to the following method: Exemplarily, when the first storage unit passes the read-write test and the write disturbance test, the fault level is determined to be the first risk level. When the first storage unit passes the read-write test but fails the write disturbance test, the fault level is determined to be the second risk level. When the first storage unit fails the read-write test and the write disturbance test, the fault level is determined to be the third risk level, the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

[0031] In some embodiments, when the first storage unit passes the read and write test and the write interference test, or when the first storage unit passes the read and write test but fails the write interference test, the fault level is determined to be the second risk level; when the first storage unit fails the read and write test and the write interference test, the fault level is determined to be the third risk level.

[0032] In a possible implementation, the electronic device may also use a preset processing algorithm based on the faulty first storage unit to predict the faulty second storage unit and isolate the second storage unit. In this way, the electronic device may perform stress testing on the second storage unit to obtain the fault level of the second storage unit, and the electronic device may perform corresponding operations on the second storage unit based on the fault level of the second storage unit. The electronic device may perform stress testing on the second storage unit and perform corresponding operations on the second storage unit based on the fault level of the second storage unit, as described in the relevant description of the first storage unit.

[0033] In an embodiment of the present application, the electronic device can predict a faulty second storage unit based on the faulty first storage unit, and the electronic device can perform stress testing on the faulty first storage unit and the second storage unit, and can more completely detect the fault level of the faulty storage unit, so as to accurately handle the faulty storage unit.

[0034] In a possible implementation, a method of isolating a storage unit by an electronic device is described here. Taking a first storage unit as an example, the electronic device may use the preset processing algorithm to isolate the first storage unit.

[0035] In a possible implementation, after obtaining the fault level of the first storage unit and the fault level of the second storage unit, the electronic device may optimize the preset processing algorithm according to the fault level of the first storage unit and the fault level of the second storage unit.

[0036] For example, if the preset processing algorithm is: a storage unit with a number of errors greater than or equal to a number threshold within a preset time period is determined as a faulty storage unit, if the number threshold is set too low, many non-faulty storage units will be isolated, and the number threshold in the preset processing algorithm is inaccurate. For example, the electronic device can increase the number threshold to optimize the preset processing algorithm.

[0037] For example, when the preset processing algorithm is a machine learning algorithm, the electronic device can optimize the parameters in the machine learning algorithm according to the storage units with medium risk levels and low risk levels, so that the faulty storage unit can be more accurately determined based on the optimized preset processing algorithm.

[0038] In this implementation, the electronic device can also optimize the preset processing algorithm based on the fault level of the first storage unit and the fault level of the second storage unit, which can improve the accuracy of the preset processing algorithm and reduce the isolated storage units.

[0039] In a second aspect, an embodiment of the present application provides a memory fault processing device, including a module for executing the method in the first aspect.

[0040] In a possible implementation, the memory fault processing device may be an operating system in an electronic device.

[0041] In a possible implementation, the memory fault processing device may include: a fault determination module, an isolation module, a memory fault processing module, and a fault level management module. In some embodiments, the fault determination module may be a central processing unit or a memory controller in an electronic device.

[0042] Wherein, the fault determination module is used to determine the faulty first storage unit.

[0043] An isolation module is used to isolate the first storage unit.

[0044] A fault level management module is used to perform stress testing on the first storage unit to obtain the fault level of the first storage unit, and perform corresponding operations on the first storage unit according to the fault level of the first storage unit, wherein when the fault level of the first storage unit is a first risk level, the operation includes releasing the isolation of the first storage unit.

[0045] In a possible implementation manner, the failure level of the first storage unit further includes a second risk level, and the first risk level is lower than the second risk level.

[0046] When the fault level is the second risk level, the fault level management module is specifically used to release the isolation of the first storage unit and establish a memory pool, the memory pool is used to manage the first storage unit, and the first storage unit is used to store data with backup.

[0047] In a possible implementation, when the fault level is a third risk level, the operation is to continue isolating the first storage unit, and the second risk level is lower than the third risk level.

[0048] In a possible implementation, the stress test includes at least one of the following: at least one mode of read and write test and at least one mode of write disturbance test.

[0049] In a possible implementation, the number of the first storage unit is at least one, and the stress test includes at least one mode of read and write test. The fault level management module is specifically configured to perform the following steps:

[0050] Step A: writing preset data into at least one first storage unit.

[0051] Step B, reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0052] Step C: when the verification is successful, writing the complement of the preset data into the at least one first storage unit.

[0053] Step D, reading data from the at least one first storage unit in sequence from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0054] Step E, when the verification is successful, return to execute step A-step D, repeat n times and execute step F after the verification is successful. When any verification fails, it is determined that the read-write test has not passed; or, when the verification fails, it is determined that the read-write test has not passed; said n is an integer greater than or equal to 1.

[0055] Step F: writing preset data into the at least one first storage unit.

[0056] Step G, reading data from the at least one first storage unit in sequence from high address to low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit.

[0057] Step H: when the verification succeeds, writing the complement of the preset data into the at least one first storage unit.

[0058] Step I, according to the address of the at least one first storage unit, read data from the at least one first storage unit in order from high address to low address, and verify the data in the first storage unit.

[0059] Step J, when the verification is successful, return to execute step F-step I, repeat the execution m times and determine that the read-write test has passed after the verification is successful. When any verification fails, it is determined that the read-write test has not passed; or, when the verification fails, it is determined that the read-write test has not passed; m is an integer greater than or equal to 1.

[0060] In a possible implementation, there is at least one storage unit, and the stress test includes a write interference test. The fault level management module is specifically used to write preset data in the at least one storage unit, and record the data in the adjacent rows and columns of the storage unit; read data from the adjacent rows and columns of the storage unit, and verify the data in the adjacent rows and columns of the storage unit; when the verification is successful, determine that the write test is passed, and when the verification fails, determine that the write test is not passed.

[0061] In one possible implementation, when the stress test includes a read-write test and a write interference test, the fault level management module is specifically used to determine that the fault level is a first risk level when the storage unit passes the read-write test and the write interference test; when the storage unit passes the read-write test but fails the write interference test, the fault level is determined to be a second risk level; when the storage unit fails the read-write test and the write interference test, the fault level is determined to be a third risk level, the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

[0062] In a possible implementation, the memory fault processing module is used to predict a faulty second storage unit by using a preset processing algorithm according to the first storage unit.

[0063] The fault level management module is further used to perform stress testing on the second storage unit to obtain the fault level of the second storage unit, and perform corresponding operations on the second storage unit according to the fault level of the second storage unit.

[0064] In a possible implementation, the isolation module is specifically configured to isolate the first storage unit by adopting the preset processing algorithm.

[0065] In a possible implementation, the fault level management module is further used to optimize the preset processing algorithm according to the fault level of the first storage unit and the fault level of the second storage unit.

[0066] In a third aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory. The memory is used to store computer executable program code, and the program code includes instructions; when the processor executes the instructions, the instructions cause the electronic device to execute the method in the first aspect.

[0067] In a fourth aspect, an embodiment of the present application provides an electronic device, which may be the memory fault processing device of the second aspect or the electronic device of the first aspect. The electronic device may include a unit, module or circuit for executing the method provided in the first aspect above.

[0068] In a fifth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the first aspect.

[0069] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the computer executes the method in the above-mentioned first aspect.

[0070] The beneficial effects of the possible implementation methods of the second to sixth aspects mentioned above can be referred to the beneficial effects brought about by the first aspect mentioned above, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0072] Figure 2 A flowchart of an embodiment of a method for handling a memory failure provided in an embodiment of the present application;

[0073] Figure 3 A schematic diagram of a stress test process provided in an embodiment of the present application;

[0074] Figure 4 A flowchart of another embodiment of a method for handling a memory failure provided in an embodiment of the present application;

[0075] Figure 5 A flowchart of another embodiment of a method for handling a memory failure provided in an embodiment of the present application;

[0076] Figure 6 A flowchart of another embodiment of a method for handling a memory failure provided in an embodiment of the present application;

[0077] Figure 7 A flowchart of another embodiment of a method for handling a memory failure provided in an embodiment of the present application;

[0078] Figure 8 A flowchart of another embodiment of a method for handling a memory failure provided in an embodiment of the present application;

[0079] Fig. 9 Another schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] Definitions of terms used in the embodiments of this application:

[0081] Memory: A storage space in an electronic device used to temporarily store data. Memory can be used to temporarily store the calculation data of the processor in the electronic device, as well as data exchanged with external devices such as hard disks.

[0082] Cell: The smallest unit of data storage. A memory may include multiple cells, each of which may include a transistor and a capacitor. The capacitor can store charge, and the charge stored in the capacitor can represent a binary number 0 or 1. A number can be called a bit (1 bit), and 8 bits are a byte. Each cell has a unique address, and the data in the corresponding cell can be accessed through the address.

[0083] In some embodiments, the storage unit may also be referred to as a memory unit, or a memory unit, etc., which is not limited in the embodiments of the present application.

[0084] Memory bank: In some embodiments, a memory bank can be understood as a logical storage library in a memory. The memory can include multiple memory banks, and each memory bank can include storage cells arranged in a two-dimensional matrix.

[0085] Rows and columns in memory: A memory bank often has multiple memory banks. The storage cells in a memory bank are arranged in a two-dimensional matrix. The rows and columns in the two-dimensional matrix are the rows and columns in the memory. In some embodiments, specifying the rows and columns in a memory bank can uniquely identify a storage cell.

[0086] A memory row can be understood as a row to which a storage unit belongs, and a memory column can be understood as a column to which a storage unit belongs.

[0087] Physical address: The address of the location actually occupied by a storage unit in the memory. For example, if the size of the memory is 2GB, the range of the physical address can be 0-2GB.

[0088] Logical address: It is the form of address of storage unit faced by the operating system. At present, the segmented storage management method can divide the memory into multiple logical segments, thereby isolating different data storage. In this case, the address of the storage unit is described in the form of "segment start address + segment offset address". The logical address of the storage unit can include the segment start address and the segment offset address.

[0089] In some embodiments, the logical address of a storage unit may be viewed as a specific description of the virtual address of the storage unit.

[0090] Virtual address: It is the address used by the central processing unit (CPU) to find the storage unit. Since the processor can only use physical addresses, the virtual address needs to be converted to a physical address before it can be used by the processor. This conversion process can be completed by the memory management unit (MMU) in the operating system (OS). For example, in a 32-bit operating system, the size of the virtual memory space can be 0-4GB.

[0091] The page table is used to store the mapping relationship between virtual addresses and physical addresses. The MMU can find the physical address mapped by the virtual address from the page table, and then submit the physical address to the processor. The processor can write or read data in the corresponding storage unit according to the physical address. Among them, memory mapping is based on memory pages. Usually, the size of a memory page is 4KB. For example, the size of data that the processor can access at one time is 4KB.

[0092] It can be understood that each storage unit has a corresponding physical address, a virtual address and a logical address, and the physical address, the virtual address and the logical address of each storage unit are in one-to-one correspondence.

[0093] Correctable error (CE): usually refers to a single-bit error in the data. The memory controller can detect which bit in the data has an error through verification, and the error correction effect can be achieved by flipping the erroneous bit.

[0094] Uncorrectable error (UCE): Usually refers to multiple bit errors in data. For uncorrectable errors, the memory controller cannot correct them.

[0095] Soft failure: The physical structure of the memory is not damaged, but the data in the storage unit is wrong due to electromagnetic radiation, charge loss, etc., which can be restored to normal by recharging and discharging. For example, when high-energy subatomic particles pass through the storage unit in the memory, free charges are generated at the same time. These free charges will accumulate on the storage unit in a very short time interval. When the accumulated free charges exceed a certain level, the data stored in the storage unit will change, and data errors will occur. The damage to the storage unit caused by soft failure is not permanent. When the data is corrected and written back to the memory, the data error can be restored.

[0096] Bit inversion: The charge stored in the memory cell changes, causing the data read out to be opposite to the expected value. For example, a memory cell that should store 0 reads out 1, or a memory cell that should store 1 reads out 0. In some embodiments, the bit inversion of a memory cell may be caused by electromagnetic radiation, charge loss, etc.

[0097] Hard failure: The physical structure of the memory is damaged and cannot be restored even if the system is restarted or the storage unit is charged and discharged again.

[0098] Risk memory: refers to a storage unit that has failed. In some embodiments, risk memory may also be referred to as failed memory.

[0099] The electronic device in the embodiment of the present application is a device containing a memory, such as a server, a storage controller, a switch, a router, a base station controller, a computing offload card, a computing acceleration card, or a terminal device, etc. In some embodiments, the terminal device can be called a user equipment (UE), a terminal, etc. For example, the terminal device can be a mobile phone, a portable android device (PAD), a personal digital assistant (PDA), a handheld device with a wireless communication function, a computing device, a vehicle-mounted device or a wearable device, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a terminal in industrial control, a terminal in a smart home, etc. The form of the electronic device in the embodiment of the present application is not specifically limited.

[0100] The electronic device may include a memory controller, a processor, and an operating system. Currently, error checking and correction (ECC) algorithms, on-die ECC algorithms, etc. are error checking and correction algorithms applicable to memory, cache, or other storage media.

[0101] Taking the memory controller running ECC as an example, when the memory controller needs to write data to the memory, the memory controller will calculate the check code based on the data to be written, and write the data and the check code of the data into the storage unit. When the memory controller needs to read data from the storage unit, the memory controller will also read the check code in the storage unit when reading data from the storage unit. The memory controller can recalculate the check code using the acquired data, and compare the check code read from the storage unit with the recalculated check code. If the check code read from the storage unit is consistent with the recalculated check code, it means that the data is correct and the check is successful. If the check code read from the storage unit is inconsistent with the recalculated check code, it means that the data is wrong and the check fails.

[0102] When the check fails, the memory controller attempts to correct the error through the checksum and reports the memory fault information to the processor, which can report the memory fault information to the operating system. Depending on whether the memory controller can successfully correct the error, the fault information is divided into correctable faults and uncorrectable faults. Generally, single-bit reversal can be corrected, but multi-bit reversal cannot be corrected. Currently, hardware isolation or software isolation can be used to handle failed storage units.

[0103] Among them, taking hardware isolation as an example, the basic input output system (BIOS) can handle the failed storage unit. Exemplarily, the BIOS can count the number of times the memory fault information is reported. When the number of times the memory fault information of the same storage unit is reported is greater than the number threshold, the BIOS can issue a command to isolate the storage unit. For example, the BIOS can issue a command to isolate the memory row or memory bank to which the failed storage unit belongs. Among them, the operation of isolating the memory bank is irreversible.

[0104] Among them, taking software isolation as an example, the OS can count the number of times memory fault information is reported. When the number of times the memory fault information of the same storage unit is reported is greater than the number threshold, the OS can issue a command to trigger memory page isolation, and isolate the virtual space of the fault area corresponding to the faulty memory unit in the OS. In this method, the OS can only isolate the virtual space of the fault area in the OS, and cannot call the storage unit resources in the memory. In addition, the memory space will be reduced after the OS layer is isolated, especially for large page isolation. The isolation risk is relatively high, which can easily cause system downtime.

[0105] In summary, in the current memory fault handling methods, whether hardware isolation or software isolation, the faulty storage unit will be permanently isolated. Even if the isolation operation is reversible, as the running time of the electronic device increases, more and more storage units will be isolated, resulting in a decrease in the number of available storage units and a reduction in available memory.

[0106] Considering the current development of memory technology, the diameter of memory cells is getting smaller and smaller. Memory cells are more likely to have bit inversion problems due to the charge and discharge operations of surrounding memory cells, resulting in row hammer phenomenon, which will increase the proportion of memory cell soft failures. However, soft failure does not mean that the physical structure of the memory is damaged. In fact, the memory cell is still available. Currently, hardware isolation and software isolation will permanently isolate the soft-failed memory cells, resulting in the part of the originally available memory cells being unable to be used by electronic devices, which will cause the number of available memory cells to gradually decrease.

[0107] Accordingly, an embodiment of the present application provides a method for handling memory failures, which can perform stress testing on a failed storage unit to determine the failure level of the failed storage unit. When the failure level of a storage unit is low, such as when the storage unit is a soft failure, the electronic device can release the isolation of the storage unit so that the storage unit can continue to store data, thereby increasing the number of available storage units. In addition, in an embodiment of the present application, for storage units with different failure levels, the electronic device can perform different operations on the storage unit, which not only increases the number of available storage units, but also improves the flexibility of memory management.

[0108] Before introducing the memory failure processing method provided in the embodiment of the present application, the structure of the electronic device provided in the embodiment of the present application is first introduced:

[0109] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 1 , an electronic device may include a hardware layer and a software layer, and the software layer may include program codes running on the hardware layer.

[0110] In some embodiments, the software layer can be divided into several layers, and the layers communicate with each other through software interfaces. For example, the software layer may include an application layer, an OS, and a BIOS. It should be understood that Figure 1 Only the OS involved in the embodiments of the present application is shown.

[0111] OS is a system running in the CPU. In some embodiments, OS may include but is not limited to Linux, Windows, Android or vx Works, etc., and this embodiment of the application does not limit this.

[0112] Reference Figure 1 In some embodiments, the OS may include: an isolation module, a memory fault processing module, and a fault level management module. In some embodiments, the OS may also include an MMU, which may store a page table to implement the conversion between the physical address and the virtual address of the storage unit. The function of the MMU may also refer to the relevant description in the prior art. It should be understood that Figure 1 Only the isolation module, memory fault processing module, and fault level management module involved in the embodiments of the present application are shown.

[0113] The isolation module is used to receive memory fault information from the processor and report it to the memory fault processing module and the fault level management module.

[0114] The memory fault management module can obtain a processing decision for the faulty storage unit based on a preset processing algorithm, and send the processing decision to the isolation module.

[0115] The isolation module is used to isolate the failed storage unit according to the processing decision.

[0116] The fault level management module is used to perform stress testing on the faulty storage unit according to the memory fault information to obtain the fault level of the storage unit.

[0117] In some embodiments, after obtaining the processing decision, the memory fault management module may also send the processing decision to the fault level management module. Accordingly, the fault level management module may also be used to perform stress testing on the faulty storage unit according to the memory fault information and the processing decision to obtain the fault level of the storage unit.

[0118] The fault level management module may also be used to perform different operations on the storage unit according to the fault level of the storage unit. For details, please refer to the relevant description in the following embodiments.

[0119] It can be understood that the steps executed by the isolation module, the memory fault processing module, and the fault level management module in the following embodiments can be regarded as steps executed by the OS.

[0120] In some embodiments, the hardware layer may include a processor CPU, a memory, a BIOS chip, and a baseboard management controller (BMC).

[0121] In some embodiments, the memory may include internal memory and external memory. Figure 1 Only the processor and memory involved in the embodiments of the present application are shown, and Figure 1 It is shown that the electronic device may include at least one memory, Figure 1 In the example, an electronic device including three memories is used for explanation. In some embodiments, the memory may be a memory stick.

[0122] In some embodiments, the hardware layer may further include a memory controller. In some embodiments, the memory controller may be provided in the processor, or may be provided separately from the processor, which is not limited in the embodiments of the present application. Figure 1 The memory controller is set in the processor as an example.

[0123] The memory controller is used to verify the data in the storage unit and report memory fault information to the processor when the data is wrong. It should be understood that when the memory controller is set in the processor, the steps performed by the memory controller can be regarded as the steps performed by the processor. In some embodiments, the processor can verify the data in the storage unit and report memory fault information to the operating system (such as the isolation module in the operating system) when the data is wrong.

[0124] It can be understood that the steps executed by the isolation module, the memory fault processing module, the fault level management module, and the processor in the following embodiments can be regarded as steps executed by the electronic device.

[0125] The memory fault processing method provided by the embodiment of the present application is described below in conjunction with specific embodiments. The following embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Figure 2 The memory fault handling method provided in the embodiment of the present application is explained by taking the perspective of internal module interaction in an electronic device as an example.

[0126] Figure 2A flowchart of an embodiment of a memory fault processing method provided in an embodiment of the present application. Figure 2 , the memory fault processing method provided in the embodiment of the present application may include:

[0127] S201: The processor reports memory fault information to the isolation module.

[0128] In the embodiment of the present application, the processor may use an ECC algorithm or an on-die ECC algorithm to verify the data in the storage unit. When the verification fails, the processor may determine that the storage unit is faulty, and the processor may report memory fault information to the isolation module. Alternatively, the memory controller may use an ECC algorithm or an on-die ECC algorithm to verify the data in the storage unit. When the verification fails, the memory controller may determine that the storage unit is faulty, the memory controller may report memory fault information to the processor, and the processor may report memory fault information to the isolation module.

[0129] In some embodiments, the memory fault information may include: the physical address and logical address of the failed storage unit. In some embodiments, the logical address of the storage unit may be the logical address of the cache line to which the storage unit belongs, or the logical address of the memory page to which the storage unit belongs, which is not limited in the embodiments of the present application.

[0130] S202: The isolation module sends memory fault information to the memory fault processing module.

[0131] S203, the memory fault processing module obtains a processing decision of the faulty storage unit according to the memory fault information.

[0132] A preset processing algorithm may be preset in the memory fault processing module, and the memory fault processing module may use the preset processing algorithm to process memory fault information and obtain a processing decision for the faulty storage unit.

[0133] In some embodiments, the preset processing algorithm may be: determining a storage unit whose number of error reports within a preset time period is greater than or equal to a number threshold as a faulty storage unit. In this embodiment, the memory fault processing module may increase the number of error reports of the faulty unit involved in the memory fault information by 1 each time it receives memory fault information. When the number of error reports of a storage unit reaches the number threshold, the memory fault processing module may determine that the storage unit is a faulty storage unit.

[0134] In some embodiments, the handling decision for a failed storage unit may be to "isolate the failed storage unit."

[0135] In some embodiments, for a storage unit in use, the processing decision for a failed storage unit may be "remapping, i.e., migrating the data in the failed storage unit to a safe storage unit, and isolating the failed storage unit". The safe storage unit may be a storage unit that has not failed, the physical address of the safe storage unit may be referred to as a safe physical address, and the logical address of the safe storage unit may be referred to as a safe logical address. In some embodiments, the safe physical address and the safe logical address may be referred to as safe addresses.

[0136] In some embodiments, the processing decision may also include an isolation method of the storage unit, and the isolation method may include but is not limited to hardware isolation and software isolation. Exemplarily, hardware isolation may include but is not limited to: isolating a faulty storage unit, isolating a cache line to which a faulty storage unit belongs, isolating a memory page to which a faulty storage unit belongs, etc. Software isolation may include but is not limited to: page isolation, address isolation, process isolation, etc.

[0137] In some embodiments, the memory fault information may further include a fault type. Exemplarily, the fault type may include but is not limited to: page fault, single bit fault, cell fault, row fault, column fault, bank fault, etc.

[0138] The preset processing algorithm may be, for example, to determine the isolation method of the processing storage unit according to the fault type. Accordingly, the processing decision may include the isolation method of the faulty storage unit.

[0139] In some embodiments, the preset processing algorithm may be a preset machine learning algorithm, and the memory fault processing module may input the memory fault information into the machine learning algorithm, and the machine learning algorithm may output the processing decision of the faulty storage unit. Exemplarily, the machine learning algorithm may include, but is not limited to, a decision tree algorithm, a supervised machine learning algorithm, an unsupervised machine learning algorithm, etc. For example, the memory fault processing module may determine the fault type of the storage unit based on a decision tree algorithm, a random forest algorithm, or a neural network algorithm, and based on the fault type, determine whether the isolation method of the storage unit is hardware isolation or software isolation.

[0140] In the embodiment of the present application, there is no limitation on the preset processing algorithm preset in the memory fault processing module.

[0141] S204, the memory fault processing module sends a processing decision to the isolation module.

[0142] In some embodiments, the processing decision may include: an address to be isolated and an isolation method. The address to be isolated may include but is not limited to: an address of a failed storage unit, an address of a cache line to which the failed storage unit belongs, an address of a memory page to which the failed storage unit belongs, etc.

[0143] In some embodiments, the address to be isolated may be a physical address, a logical address, or a virtual address.

[0144] In some embodiments, the processing decision may include: an address to be isolated, an isolation method, and a secure address, wherein the secure address is used to indicate that data at the address to be isolated is migrated to the secure address.

[0145] S205: The isolation module isolates the failed storage unit according to the processing decision.

[0146] In some embodiments, the isolation module can isolate the faulty storage unit according to the address to be isolated and the isolation method. Specifically, the isolation module can isolate the faulty storage unit, isolate the cache line to which the faulty storage unit belongs, or isolate the memory page to which the faulty storage unit belongs.

[0147] In some embodiments, the isolation module may also migrate the data corresponding to the address to be isolated to the safe address first, and then isolate the faulty storage unit according to the address to be isolated and the safe address.

[0148] In the embodiment of the present application, the reason why the isolation module isolates the faulty storage unit first according to the processing decision is that: because the faulty storage unit is the storage unit where an error occurs, and the data in the storage unit is erroneous, the isolation module isolates the faulty storage unit first to prevent the electronic device from accessing the risky memory, reading erroneous data, and preventing the electronic device from malfunctioning.

[0149] S206: The isolation module sends memory fault information to the fault level management module.

[0150] There is no order distinction between S206 and S202, and the two can be executed at the same time.

[0151] S207, the fault level management module performs stress testing on the faulty storage unit according to the memory fault information to obtain the fault level of the faulty storage unit.

[0152] The fault level management module can determine the faulty storage unit according to the memory fault information. In the embodiment of the present application, the fault level management module can perform stress testing on the faulty storage unit to obtain the fault mode and fault level of the faulty storage unit. Stress testing can be understood as pressure testing.

[0153] In some embodiments, in order not to affect the normal execution of services in the electronic device, the fault level management module can perform stress testing on the faulty storage unit when the electronic device is idle. The electronic device idle can be understood as: the CPU utilization is lower than the preset utilization, or when the user does not use the electronic device in the early morning every day.

[0154] In some embodiments, the stress test on the failed memory cell may include: a read / write test or a write disturb test.

[0155] Exemplarily, when the stress test includes a read and write test, the fault level management module may send a write instruction to the processor, and the write instruction is used to instruct the processor to write preset data in the faulty storage unit. After the processor writes the preset data in the faulty storage unit, the fault level management module may send a read instruction to the processor, and the read instruction is used to instruct the processor to read the preset data in the faulty storage unit and verify whether the data in the faulty storage unit is correct. When the data in the faulty storage unit is correct, such as the preset data, it can be determined that the verification of the faulty storage unit is successful, and the faulty storage unit can be a low-risk level fault. When the data in the faulty storage unit is wrong, such as not the preset data, it can be determined that the verification of the faulty storage unit fails, and the faulty storage unit can be a high-risk level fault.

[0156] In some embodiments, a high-risk level fault may include a hard failure, and a low-risk level fault may include a soft failure. In the embodiments of the present application, there is no limitation on which failure modes the high-risk level fault and the low-risk level fault specifically include.

[0157] In some embodiments, the read-write test may include at least one mode of read-write test. Exemplarily, at least one mode of read-write test includes: a first read-write test and a second read-write test. The embodiment of the present application does not elaborate on the process of the fault level management module and the processor interacting to complete the first read-write test and the second read-write test, and the relevant description of the above read-write test can be referred to.

[0158] Among them, when the faulty storage unit passes the first read-write test and the second read-write test, it can be determined that the faulty storage unit may be a low-risk level fault; when the faulty storage unit passes the first read-write test but fails the second read-write test, it can be determined that the faulty storage unit may be a medium-risk level fault; when the faulty storage unit fails the first read-write test and the second read-write test, it can be determined that the faulty storage unit may be a high-risk level fault.

[0159] Exemplarily, when the stress test includes a write disturbance test, the fault level management module may issue a write instruction to the processor, and the write instruction is used to instruct the processor to write preset data near the faulty storage unit. In some embodiments, the vicinity of the faulty storage unit may be: a storage unit X rows and Y columns away from the faulty storage unit, where X and Y are both integers greater than or equal to 1. Before the processor writes preset data in the faulty storage unit, the processor may record the data in the faulty storage unit and the storage units in its adjacent rows and columns. After the processor writes preset data at least once near the faulty storage unit, the fault level management module may issue a read instruction to the processor, and the read instruction is used to instruct the processor to read data in the faulty storage unit and the storage units in its adjacent rows and columns. Wherein, when the data read in the faulty storage unit and the storage units in its adjacent rows and columns is correct, it can be determined that the faulty storage unit may be a low-risk level fault. Wherein, when the faulty storage unit and the read data thereof are erroneous, it can be determined that the faulty storage unit may be a high-risk level fault.

[0160] In some embodiments, the write disturbance test may include at least one mode of write disturbance test. Exemplarily, at least one mode of write disturbance test includes: a first write disturbance test and a second write disturbance test. The embodiment of the present application does not elaborate on the process of the interaction between the fault level management module and the processor to complete the first write disturbance test and the second write disturbance test, and the relevant description of the above-mentioned write disturbance test can be referred to.

[0161] Among them, when the faulty storage unit passes the first write disturbance test and the second write disturbance test, it can be determined that the faulty storage unit may be a low-risk level fault; when the faulty storage unit passes the first write disturbance test but fails to pass the second write disturbance test, it can be determined that the faulty storage unit may be a medium-risk level fault; when the faulty storage unit fails the first write disturbance test and the second write disturbance test, it can be determined that the faulty storage unit may be a high-risk level fault.

[0162] In some embodiments, stress testing of a failed storage unit may include: a read-write test and a write interference test. In some embodiments, stress testing may include at least one mode of read-write testing, and at least one mode of write interference testing. In the following example, stress testing including multiple read-write tests and a write interference test is used as an example for explanation. The embodiments of the present application do not limit the stress testing method of a failed storage unit.

[0163] In some embodiments, there may be at least one faulty storage unit, and the fault level management module may perform stress testing on each faulty storage unit in turn, or perform stress testing on at least one faulty storage unit at the same time. In order to improve the stress testing efficiency, in an embodiment of the present application, stress testing may be performed on at least one faulty storage unit at the same time.

[0164] For example, refer to Figure 3 The stress testing process provided in the embodiment of the present application may include:

[0165] S301, the fault level management module sends a first write instruction to the processor, where the first write instruction is used to instruct the processor to write preset data into a faulty storage unit.

[0166] The preset data may be all 0s or all 1s, or data arranged in a preset mode. The preset mode may be alternating 0s and 1s, or writing M 0s and N 1s alternately, which is not limited in the present embodiment. It should be understood that M and N are both integers greater than or equal to 1.

[0167] S302: The processor writes preset data into the failed storage unit.

[0168] S303, the fault level management module sends a first read instruction to the processor, where the first read instruction is used to instruct the processor to read data from the faulty storage unit in sequence from low address to high address.

[0169] The address can be the physical address, logical address or virtual address of the storage unit. The physical address is obtained by sorting the actual location of the storage unit in the memory, and the logical address and virtual address are obtained by mapping the physical address, so the addresses of the storage units are sorted. For example, taking the physical address as an example, if the physical address of the memory is 0-2GB, the address increases from 0 to 2GB, 0 is a lower address than 1GB, and 1GB is a lower address than 2GB.

[0170] S304, the processor reads preset data from the failed storage unit in order from low address to high address, and verifies the data in the failed storage unit. When the verification succeeds, S305 is executed, and when the verification fails, S319 is executed.

[0171] The embodiment of the present application does not elaborate on the process of the processor verifying the data in the faulty storage unit, and reference may be made to the relevant description in the above embodiment.

[0172] S305: The processor feeds back a message indicating that the verification is successful to the fault level management module.

[0173] S306, the fault level management module sends a second write instruction downward, where the second write instruction is used to instruct the processor to write a complement set of preset data into the faulty storage unit.

[0174] The complement can be understood as data opposite to the preset data. For example, if the preset data is all 1, the complement of the preset data is all 0. If the preset data is 0 and 1 alternating, the complement of the preset data is 1 and 0 alternating. If the preset data is to write M 0s and N 1s alternating, the complement of the preset data is to write M 1s and N 0s alternating.

[0175] S307: The processor writes a complement of preset data into the failed storage unit.

[0176] S308, the fault level management module sends a second read instruction to the processor, where the second read instruction is used to instruct the processor to read data from the failed storage unit in sequence from low address to high address.

[0177] S309, the processor reads preset data from the faulty storage unit in order from low address to high address, and verifies the data in the faulty storage unit. If the verification is successful, it returns to execute S301-S309, repeats n times and executes S310 after all verifications are successful. If any verification fails, it executes S319; if the verification fails, it executes S319.

[0178] Wherein, n is an integer greater than or equal to 1.

[0179] S310, the fault level management module sends a third write instruction to the processor, where the third write instruction is used to instruct the processor to write preset data into the faulty storage unit.

[0180] S311, the processor writes preset data into the failed storage unit.

[0181] S312, the fault level management module sends a third read instruction to the processor, where the third read instruction is used to instruct the processor to read data from the faulty storage unit in sequence from high address to low address.

[0182] S313, the processor reads preset data from the failed storage unit in order from high address to low address, and verifies the data in the failed storage unit. If the verification succeeds, S314 is executed, and if the verification fails, S319 is executed.

[0183] S314, the processor feeds back a message indicating that the verification is successful to the fault level management module.

[0184] S315, the fault level management module sends a fourth write instruction downward, where the fourth write instruction is used to instruct the processor to write a complementary set of preset data into the faulty storage unit.

[0185] S316: The processor writes a complement of preset data into the failed storage unit.

[0186] S317, the fault level management module sends a fourth read instruction to the processor, where the fourth read instruction is used to instruct the processor to read data from the faulty storage unit in sequence from high address to low address.

[0187] S318, the processor reads preset data from the failed storage unit in order from high address to low address, and verifies the data in the failed storage unit. When the verification is successful, it returns to execute S310-S317, repeats m times and determines that the read and write test is successful after all verifications are successful. When any verification fails, execute S319; when the verification fails, execute S319.

[0188] Wherein, m is an integer greater than or equal to 1, and m and n may be the same or different.

[0189] S319: The processor feeds back a verification failure message to the fault level management module.

[0190] S301-S319 can be regarded as a read-write test, wherein S301-S304 can be regarded as a read-write test of a mode, S306-S309 can be regarded as a read-write test of a mode, S310-S313 can be regarded as a read-write test of a mode, and S315-S318 can be regarded as a read-write test of a mode.

[0191] In the embodiment of the present application, when the storage unit passes the read / write test of all modes, it can be determined that the storage unit passes the read / write test. When the storage unit fails to pass the read / write test of any mode or fails to pass any verification, it can be determined that the storage unit fails to pass the read / write test.

[0192] S320, the fault level management module sends a fifth write instruction to the processor, where the fifth write instruction is used to instruct the processor to write preset data into a storage unit near the faulty storage unit.

[0193] S321, the processor writes preset data in the storage unit near the failed storage unit, and records the data in the failed storage unit, as well as the data in the adjacent rows and adjacent columns of the failed storage unit.

[0194] In some embodiments, the processor may record data in adjacent x rows and adjacent y columns of the failed storage unit. Both x and y are integers greater than or equal to 1, and x and y may be the same or different.

[0195] S322, the fault level management module sends a fifth read instruction to the processor, where the fifth read instruction is used to instruct the processor to read data in the faulty storage unit, and read data in adjacent rows and adjacent columns of the faulty storage unit.

[0196] S323, the processor reads data from the data in the failed storage unit, and the adjacent rows and columns of the failed storage unit, and verifies the data in the failed storage unit, and the adjacent rows and columns of the failed storage unit. When the verification succeeds, S324 is executed, and when the verification fails, S319 is executed.

[0197] S324, the processor feeds back a message indicating that the verification is successful to the fault level management module.

[0198] S320-S323 can be regarded as a write disturbance test. In S323, when the verification succeeds, it can be determined that the storage unit has passed the write disturbance test. When the verification fails, it can be determined that the storage unit has not passed the write disturbance test.

[0199] It should be understood that the embodiments of the present application do not limit the order of the read / write test and the write disturb test, nor do they limit the number of times the read / write test and the write disturb test are performed. Figure 3 This is an example. In one embodiment, Figure 3 Some of the steps shown in are optional steps, and the steps can be combined with each other.

[0200] In some embodiments, when a faulty storage unit passes the read-write test and the write interference test, the fault level management module can determine that the fault level is a low risk level; when the faulty storage unit passes the read-write test but fails the write interference test, the fault level management module can determine that the fault level is a medium risk level; when the faulty storage unit fails the read-write test and the write interference test, the fault level management module can determine that the fault level is a high risk level.

[0201] In some embodiments, in a scenario with high reliability requirements, when the failed storage unit passes the read / write test and the write disturb test, and when the failed storage unit passes the read / write test but fails the write disturb test, the fault level management module may determine that the fault level is a medium risk level. When the failed storage unit fails the read / write test and the write disturb test, the fault level management module may determine that the fault level is a high risk level.

[0202] In an embodiment of the present application, the fault level management module can adaptively adjust the method for determining the fault level of a faulty storage unit based on a specific application scenario and a stress test result. In some embodiments, the fault level management module can store a mapping relationship between an application scenario and a method for determining the fault level of a faulty storage unit. When determining the fault level of a faulty storage unit based on a stress test result, the fault level management module can use the method for determining the fault level of a faulty storage unit corresponding to the application scenario to determine the fault level of the storage unit.

[0203] S208: The fault level management module performs corresponding operations on the storage unit according to the fault level of the faulty storage unit.

[0204] In some embodiments, the failure of a storage unit with a high risk level can be regarded as a hard failure, and the failure of a storage unit with a medium risk or a low risk level can be regarded as a soft failure. In the embodiments of the present application, different processing methods are used for storage units with different failure levels.

[0205] In some embodiments, for storage units with high risk levels, the use of the storage units with high risk levels can continue to be prohibited, such as the storage units with high risk levels can continue to be isolated. In some embodiments, for storage units with high risk levels, the fault level management module can feedback the storage units with high risk levels to the memory fault processing module, and the memory fault processing module can write the fault into a log, or feedback to the background management page for operation and maintenance alarm.

[0206] For storage units with medium risk levels, in order to prevent the storage unit from evolving into a high-risk storage unit, its use can be restricted. Exemplarily, the fault level management module can establish a separate memory pool to manage the storage unit, which is used to store data that is not sensitive to hardware failures. For example, the storage unit can store files, documents, and other data that have external storage backups, so that even if the storage unit fails, the electronic device can still obtain the corresponding data from the backup.

[0207] For storage units with low risk levels, normal use can be restored. For example, the fault level management module can send a release request to the isolation module to request the isolation module to release the isolation of the storage unit so that the storage unit can continue to store data.

[0208] In some embodiments, for storage units with medium risk level and low risk level, these storage units are still usable, and there is no irreversible problem in physical structure. It may be that the preset processing algorithm in the memory fault processing module is not accurate enough. In this embodiment, the fault level management module can feedback the storage units with medium risk level and low risk level to the memory fault processing module so that the memory fault processing module can optimize the preset processing algorithm.

[0209] For example, if the preset processing algorithm is: a storage unit with a number of errors greater than or equal to a number threshold within a preset time period is determined as a faulty storage unit, if the number threshold is set too low, many non-faulty storage units will be isolated, and the number threshold in the preset processing algorithm is inaccurate. For example, the memory fault processing module can increase the number threshold to optimize the preset processing algorithm.

[0210] For example, when the preset processing algorithm is a machine learning algorithm, the memory fault processing module can optimize the parameters in the machine learning algorithm according to the storage units with medium risk levels and low risk levels, so that the faulty storage unit can be more accurately determined based on the optimized preset processing algorithm.

[0211] In some embodiments, a low risk level may be used as a first risk level, a medium risk level may be used as a second risk level, and a high risk level may be used as a third risk level, wherein the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

[0212] In some embodiments, a low risk level and a medium risk level may be used as the first risk level, and a high risk level may be used as the second risk level.

[0213] In some embodiments, the fault levels may be further divided into fewer or more levels, which is not limited in this embodiment of the present application.

[0214] Figure 4 The process of the fault level management module performing stress testing on the faulty storage unit and performing corresponding operations on the storage unit according to the stress testing result is exemplarily shown in FIG. 5 . For details, please refer to the description in S207-S208.

[0215] In an embodiment of the present application, based on the memory fault information reported by the processor, the faulty storage unit can be isolated first to avoid access to erroneous data in the storage unit. In addition, the operating system can further perform stress testing on the faulty storage unit to obtain the fault level of the faulty storage unit, and the operating system can perform different operations for storage units with different fault levels. Exemplarily, for medium-risk and low-risk storage units, the failure is due to soft failure, and the operating system can release the isolation of these storage units, which can continue to store data and increase the available storage units in the electronic device. However, in order to avoid the evolution of medium-risk storage units to high-risk, medium-risk storage units can be used to store insensitive data. In an embodiment of the present application, different operations can be performed for faulty storage units with different fault levels, which can not only increase the available storage units, but also improve the flexibility of memory management.

[0216] In some embodiments, reference Figure 5 , after S205, you can also execute S205A:

[0217] S205A, the isolation module detects whether the faulty storage unit is isolated successfully. If so, continue to execute S207-S208, if not, use the native fault tolerance mechanism to handle it.

[0218] In some embodiments, whether the faulty storage unit is successfully isolated can be detected based on whether the faulty storage unit can still be accessed. It should be noted that when the faulty storage unit is successfully isolated, the fault level management module can continue to perform stress testing on the faulty storage unit. When the faulty storage unit fails to be isolated, in order to avoid accessing erroneous data in the storage unit, a native fault tolerance mechanism can be used.

[0219] In some embodiments, the native fault-tolerance mechanism may be: re-isolating the failed storage unit until the isolation is successful, or isolating the storage unit after killing the process using the storage unit. The embodiments of the present application do not elaborate on the native fault-tolerance mechanism, and the fault-tolerance mechanism of isolating storage units in the current operating system may be referred to.

[0220] In the embodiment of the present application, it is also possible to detect whether the faulty storage unit is successfully isolated, thereby improving the isolation accuracy and avoiding access to erroneous data.

[0221] In some embodiments, the memory fault processing module can not only obtain the processing decision of the faulty storage unit based on the preset processing algorithm preset therein, but also predict the storage unit that has not currently reported the memory fault information but may have a fault based on the memory fault information. In this way, the operating system can isolate the predicted storage unit in advance to avoid accessing the erroneous data in these storage units, thereby improving the isolation accuracy.

[0222] In some embodiments, the processing decision of the failed storage unit may also include: the predicted address of the failed storage unit, the isolation method, and the safety address.

[0223] Reference Figure 6 , the memory fault processing method provided in the embodiment of the present application may include:

[0224] S601: The processor reports memory fault information to the isolation module.

[0225] S602: The isolation module sends memory fault information to the memory fault processing module.

[0226] S603: The isolation module sends memory fault information to the fault level management module.

[0227] There is no order distinction between S602 and S603, and the two can be executed at the same time.

[0228] S604: The memory fault processing module obtains a processing decision of the faulty storage unit according to the memory fault information.

[0229] In some embodiments, the processing decision of the failed storage unit may include: the address, isolation mode, and safety address of the failed storage unit indicated by the memory fault information, and the address, isolation mode, and safety address of the failed storage unit predicted based on the memory fault information. Among them, the failed storage unit indicated by the memory fault information can be understood as the failed storage unit included in the memory fault information, and the failed storage unit predicted based on the memory fault information can be understood as: the failed storage unit predicted based on the memory fault information using a preset processing algorithm.

[0230] In some embodiments, a faulty storage unit indicated by the memory fault information may be referred to as a first storage unit, and a faulty storage unit predicted based on the memory fault information may be referred to as a second storage unit.

[0231] S605: The memory fault processing module sends a processing decision to the isolation module.

[0232] S606: The isolation module isolates the failed storage unit according to the processing decision.

[0233] S607, the memory fault processing module sends a processing decision to the fault level management module.

[0234] There is no order distinction between S605 and S607, and the two can be executed at the same time.

[0235] Among them, S601-S606 can refer to the description in S201-S206.

[0236] S608, the fault level management module performs stress testing on the faulty storage unit according to the memory fault information and the processing decision to obtain the fault level of the faulty storage unit.

[0237] Different from S207, because the memory fault processing module in the embodiment of the present application can predict the faulty storage unit based on the preset processing algorithm, in S608, the fault level management module not only needs to stress test the faulty storage unit indicated by the memory fault information, but also needs to stress test the predicted faulty storage unit. The specific stress testing method can refer to the description in S207.

[0238] S609: The fault level management module performs corresponding operations on the storage unit according to the fault level of the faulty storage unit.

[0239] S609 may refer to the description in S208.

[0240] Figure 7 A schematic diagram of a processing flow of memory fault information provided by an embodiment of the present application. Figure 7 , the memory fault processing method provided in the embodiment of the present application may include:

[0241] Step 1: Report memory fault information.

[0242] The memory fault information reporting may include: the processor reporting the memory fault information to the operating system (such as the isolation module in the operating system), and the isolation module reporting the memory fault information to the memory fault processing module and the fault level management module.

[0243] Step 2: Remap the faulty memory.

[0244] In an embodiment of the present application, the memory fault processing module can obtain a processing decision for a faulty storage unit based on the memory fault information. In some embodiments, the processing decision can include: the address and safety address of the faulty storage unit indicated by the memory fault information, and the address and safety address of the faulty storage unit predicted based on the memory fault information. Figure 7 ,The CE address and the UCE address can be regarded as the addresses of the faulty storage units indicated by the memory fault information, and the predicted address can be regarded as the addresses of the faulty storage units predicted based on the memory fault information.

[0245] Step 3: Stress testing.

[0246] For stress testing, refer to the description in S207.

[0247] Step 4: Process the failed storage unit according to the failure level.

[0248] For example, the storage units with high risk levels can continue to be isolated, and the storage units with medium risk levels and low risk levels can be released from isolation. The storage units with medium risk levels can be restricted in use, while the storage units with low risk levels can resume normal use.

[0249] Step 5: Information feedback.

[0250] Exemplarily, the information feedback may include: the fault level management module feeds back the storage unit of the high risk level to the memory fault processing module, so that the memory fault processing module can perform operations and maintenance alarms. Exemplarily, the information feedback may include: the fault level management module feeds back the storage unit of the medium risk level and the low risk level to the memory fault processing module, so that the memory fault processing module can optimize the preset processing algorithm. The information feedback method can refer to the description in S208.

[0251] In an embodiment of the present application, when the memory fault processing module can predict the faulty storage unit based on the memory fault information, the fault level management module can also perform stress testing on the faulty storage unit according to the processing decision and the memory fault information, and can more completely detect the fault level of the faulty storage unit so as to accurately process the faulty storage unit.

[0252] Taking the electronic device as the execution subject, in some embodiments, referring to Figure 8 , the memory fault processing method provided in the embodiment of the present application may include:

[0253] S801, determine a failed first storage unit.

[0254] In the embodiment of the present application, a processor or a memory controller in the electronic device can detect the memory to determine the faulty first storage unit.

[0255] S802, isolate the first storage unit.

[0256] In some embodiments, the electronic device may adopt a preset processing algorithm to obtain a processing decision of the first storage unit based on memory fault information, and then isolate the first storage unit based on the processing decision. For details, please refer to the description in S203-S205.

[0257] S803: Perform stress testing on the first storage unit to obtain a fault level of the first storage unit.

[0258] S803 may refer to the description in S207.

[0259] S804, performing a corresponding operation on the first storage unit according to the fault level of the first storage unit, wherein when the fault level of the first storage unit is a first risk level, performing the operation on the first storage unit includes releasing the isolation of the first storage unit.

[0260] In some embodiments, the first risk level may include a low risk level. In some embodiments, the first risk level may include a low risk level and a medium risk level.

[0261] In some embodiments, the first risk level may be used to indicate that the failure mode of the storage unit is a soft failure.

[0262] S804 may refer to the description in S208.

[0263] The principles and technical effects of the memory fault handling method provided in the embodiment of the present application are the same as those in the above embodiment, and can be referred to the description in the above embodiment, which will not be repeated here.

[0264] It should be noted that the data involved in this application (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0265] In one embodiment, the present application also provides an electronic device, referring to Fig. 9 , the electronic device may include: a processor 901 (such as a CPU), and a memory 902. The memory 902 may include a high-speed random access memory (RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory. The memory 902 may store various instructions for completing various processing functions and implementing the method steps of the present application.

[0266] Optionally, the electronic device involved in the present application may further include: a power supply 903, a communication bus 904 and a communication port 905. The above-mentioned communication port 905 is used to realize the connection and communication between the electronic device and other peripherals. In the embodiment of the present application, the memory 902 is used to store computer executable program code, and the program code includes instructions; when the processor 901 executes the instruction, the instruction causes the processor 901 of the electronic device to perform the action in the above-mentioned method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0267] It should be noted that the modules or components described in the above embodiments may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (FPGAs), etc. For another example, when a module above is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call program codes, such as a controller. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0268] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0269] The term "plurality" in this article refers to two or more than two. The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship; in the formula, the character " / " indicates that the previous and next associated objects are in a "division" relationship. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0270] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0271] It can be understood that in the embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Claims

1. A memory fault processing method, characterized in that: Applied to electronic equipment, the method comprises: determining a failed first storage unit; isolating the first storage unit; Performing a stress test on the first storage unit to obtain a fault level of the first storage unit; According to the fault level of the first storage unit, a corresponding operation is performed on the first storage unit, wherein when the fault level of the first storage unit is a first risk level, the operation includes releasing the isolation of the first storage unit.

2. The method according to claim 1, characterized in that: The failure level of the first storage unit further includes a second risk level, the first risk level being lower than the second risk level; When the fault level is the second risk level, performing a corresponding operation on the first storage unit includes: The first storage unit is de-isolated, and a memory pool is established, wherein the memory pool is used to manage the first storage unit, and the first storage unit is used to store data with an external memory backup.

3. The method according to claim 2, characterized in that When the fault level is a third risk level, the operation is to continue isolating the first storage unit, and the second risk level is lower than the third risk level.

4. The method according to any one of claims 1 to 3, characterized in that The stress test includes at least one of the following: at least one mode of read and write test, and at least one mode of write disturbance test.

5. The method according to claim 4, characterized in that There is at least one first storage unit, and the stress test includes at least one mode of read and write test; and the stress test on the first storage unit includes: Step A, writing preset data into at least one first storage unit; Step B, reading data from the at least one first storage unit in order from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step C, when the verification is successful, writing the complement of the preset data into the at least one first storage unit; Step D, reading data from the at least one first storage unit in order from a low address to a high address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step E, when the verification is successful, return to execute step A-step D, repeat the execution n times and execute step F after all the verifications are successful, and determine that the read-write test has not passed when any verification fails; or, when the verification fails, determine that the read-write test has not passed; wherein n is an integer greater than or equal to 1; Step F, writing preset data into the at least one first storage unit; Step G, reading data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step H, when the verification is successful, writing the complement of the preset data into the at least one first storage unit; Step I, reading data from the at least one first storage unit in sequence from a high address to a low address according to the address of the at least one first storage unit, and verifying the data in the first storage unit; Step J, when the verification is successful, return to execute step F-step I, repeat the execution m times and determine that the read-write test has passed after the verification is successful. When any verification fails, it is determined that the read-write test has not passed; or, when the verification fails, it is determined that the read-write test has not passed; m is an integer greater than or equal to 1.

6. The method according to claim 4 or 5, characterized in that: There is at least one first storage unit, and the stress test includes a write disturbance test; and the stress test on the first storage unit includes: Writing preset data into a storage unit near the at least one first storage unit, and recording the data in the first storage unit, and in adjacent rows and columns of the first storage unit; Reading data from the first storage unit, and adjacent rows and adjacent columns of the first storage unit, and verifying the data in the first storage unit, and adjacent rows and adjacent columns of the first storage unit; When the verification succeeds, it is determined that the write test has passed, and when the verification fails, it is determined that the write test has not passed.

7. The method according to claim 6, characterized in that When the stress test includes a read / write test and a write disturb test, obtaining the failure level of the first storage unit includes: When the first storage unit passes the read / write test and the write disturb test, determining the fault level to be a first risk level; When the first storage unit passes the read-write test but fails the write disturb test, determining the fault level to be a second risk level; When the first storage unit fails the read / write test and the write disturb test, the fault level is determined to be a third risk level, the first risk level is lower than the second risk level, and the second risk level is lower than the third risk level.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: According to the first storage unit, a preset processing algorithm is used to predict a faulty second storage unit; isolating the second storage unit; Performing a stress test on the second storage unit to obtain a fault level of the second storage unit; According to the fault level of the second storage unit, a corresponding operation is performed on the second storage unit.

9. The method according to claim 8, characterized in that The isolating the first storage unit comprises: The preset processing algorithm is used to isolate the first storage unit.

10. The method according to claim 9, characterized in that The method further comprises: The preset processing algorithm is optimized according to the fault level of the first storage unit and the fault level of the second storage unit.

11. A memory failure device, characterized in that: include: Module for performing the method according to any one of claims 1-10.

12. The memory failure device according to claim 11, characterized in that: The memory failure device is an operating system in an electronic device.

13. An electronic device, characterized in that: include: Processor and memory; The memory stores computer instructions; The processor executes the computer instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 10.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program or instruction, and when the computer program or instruction is executed, the method according to any one of claims 1 to 10 is implemented.

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