Full-chip configuration device and method based on address auto-increase mechanism

Abstract

The invention discloses a full-chip configuration device and method based on an address auto-increase mechanism. The device comprises a data transmission module, an address self-increasing module and a data configuration module. The data transmission module is used for processing a data read-write request and generating a corresponding read-write control signal according to the request; the address self-increasing module is used for determining the step length of each address increase according to the bit width of the input data and the bit width of the single address configuration data, and automatically calculating and updating the configuration address based on the current address; and the data configuration module is used for executing data writing or reading operation of a specified address based on the updated address output by the address self-increasing module and the read-write control signal output by the data transmission module. According to the method, an efficient and reliable data configuration scheme is provided for full-chip configuration of the chip through a unified configuration process and an address self-increasing mechanism, and compared with a traditional scheme, the method has the advantages that a more efficient full-chip configuration process can be realized, and meanwhile, the complexity of hardware design and verification is reduced.

Description

Technical Field

[0001] The invention proposes a full-chip configuration device and method based on an address self-increment mechanism, belonging to the field of digital integrated circuits. Background Art

[0002] The working efficiency and stability of the chip depend largely on the accurate configuration and efficient management of its internal data. Traditionally, data configuration is mainly carried out through communication protocols (such as IIC, SPI, UART, JTAG, etc.). These protocols are responsible for controlling the writing and reading of data in the chip's internal registers or specific addresses, thereby ensuring the normal operation of the chip.

[0003] There are two main mainstream chip data configuration schemes: manual configuration scheme and automatic configuration scheme. In the first scheme, during the hardware design or software programming process, engineers need to clearly define the target address of each configuration data, and enter the address one by one manually or relying on a preset fixed address mapping table to achieve data configuration of the registers or storage units inside the chip. This scheme has a simple circuit design and is suitable for small-scale or single configuration scenarios. The disadvantage is that it is inefficient and prone to human errors in large-scale or complex configuration scenarios.

[0004] The second solution usually relies on automatically generated configuration scripts or configuration tools to automatically handle data mapping and communication. Through the high-level programming interface (API) to interact with the chip, the tool will automatically generate and write configuration data for registers or storage cells according to the high-level configuration requirements provided by the engineer. This solution provides a higher degree of automation and is suitable for large-scale data configuration scenarios. The disadvantage is that it increases the complexity of circuit design and the cost of tool development and maintenance is high. Summary of the invention

[0005] In view of the defects existing in the above-mentioned prior art, the present invention proposes a full-chip configuration device and method based on an address self-increment mechanism, which is used to achieve high-efficiency configuration of the entire chip and reduce the complexity of hardware design within the chip, thereby increasing versatility.

[0006] The technical solution adopted by the device of the present invention is as follows:

[0007] A full-chip configuration device based on an address self-increment mechanism, the device comprising a data transmission module, an address self-increment module and a data configuration module;

[0008] The data transmission module is used to process data read and write requests and generate corresponding read and write control signals according to the requests;

[0009] The address auto-increment module is used to determine the step size of each address increase according to the bit width of the input data and the bit width of the single address configuration data, and automatically calculate and update the configuration address based on the current address;

[0010] The data configuration module is used to perform data writing or reading operations at a designated address based on the update address output by the address self-increment module and the read-write control signal output by the data transmission module.

[0011] The technical solution adopted by the method of the present invention is as follows:

[0012] A method for configuring a whole chip based on an address auto-increment mechanism, the method comprising the following steps:

[0013] Step 1, calculating an auto-increment step parameter according to the bit width of the input data and the bit width of the single address configuration data, and the address auto-increment module automatically updates the current configuration address based on the parameter;

[0014] Step 2, based on the current configuration address updated in step 1, data configuration is performed on the register array inside the chip;

[0015] Step 3, repeating the address update operation in step 1 and the data configuration operation in step 2 until the whole chip configuration is completed.

[0016] Compared with the prior art, the present invention can automatically update the configuration address of the read and write operations according to the self-increment step parameter when performing full-chip configuration of the chip, instead of directly inputting a fixed data configuration address at each data configuration, which results in redundant input operations of the address configuration information, thereby significantly improving the efficiency of the full-chip configuration of the chip through a unified configuration process and an address self-increment mechanism. By automatically updating the data configuration address, the present invention reduces the redundant input of the configuration address, optimizes the data configuration process of the chip, and enables the hardware circuit to be implemented more stably and reliably. Therefore, when performing full-chip configuration, the present invention can automatically update the configuration address according to the self-increment step parameter after each data configuration is completed, in the case of inputting the data configuration starting address, so that when performing continuous data configuration, there is no need to re-receive the configuration address, thereby achieving continuous and efficient configuration of the entire chip, and by optimizing the configuration process, the present invention also effectively reduces the complexity of the hardware design and improves the versatility of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a block diagram of a full-chip configuration device based on an address self-increment mechanism in an embodiment of the present invention;

[0018] Figure 2 is a flow chart of a full-chip configuration method based on an address auto-increment mechanism in an embodiment of the present invention;

[0019] Figure 3 is a state timing diagram of the address auto-increment module in an embodiment of the present invention;

[0020] Figure 41 is a state timing diagram of the address auto-increment module of the IIC in the specified address continuous write mode in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] This embodiment provides a full-chip configuration device based on an address self-increment mechanism, and its structural block diagram is as follows: Figure 1 As shown, it includes a data transmission module, an address self-increment module and a data configuration module. Through the communication interface (such as IIC, SPI or other bus interfaces) of the slave device (Slave), the data transmission module and the address self-increment module communicate with the upper-level master device (Master) to receive and process the data configuration information from the master device. The data configuration module is directly connected to the register array inside the chip. The data transmission module is used to process the data read and write requests from the communication interface, and generate corresponding read and write control signals according to the requests; the address self-increment module is used in the data configuration process in the chip, according to the bit width of the input data and the bit width of the single address configuration data, to determine the step size of each address increase, and automatically calculate and update the configuration address based on the current address; the data configuration module is used to perform data write or read operations at the specified address based on the update address output by the address self-increment module and the read and write control signal output by the data transmission module, and repeat the address update and data configuration process until the correct configuration of the entire chip is achieved.

[0022] Among them, the data transmission module includes three digital input signals and digital output signals. The three digital input signals are respectively a receive valid signal slave_rx_vld, a receive data signal slave_rx_dat and a send request signal slave_tx_req. The digital output signals include a write enable signal trans_wr, a write data signal trans_wdat and a read enable signal trans_rd.

[0023] The data transmission module specifically includes a data register and two D flip-flops, wherein the received valid signal slave_rx_vld is transmitted to the first D flip-flop and the data register, the first D flip-flop outputs a write enable signal trans_wr, and the received data signal slave_rx_dat is stored through the data register, indicating that data write operations are allowed; the sent request signal slave_tx_req is transmitted to the second D flip-flop, and the second D flip-flop outputs a read enable signal trans_rd, indicating that data read operations are allowed.

[0024] The address increment module includes 4 digital input signals and 1 digital output signal. The 4 digital input signals are the write enable signal trans_wr, the read enable signal trans_rd, the start address signal slave_rx_addr and the start address valid signal slave_rx_addr_vld. The digital output signal is the current configuration address addrincr_addr.

[0025] The address auto-increment module specifically includes a step register, an adder and an address register, wherein the step register stores the value of the auto-increment step parameter ADDR_NUM, where ADDR_NUM is the ratio of the bit width of the single received data to the configuration data bit width of a single address; ADDR_NUM is transmitted to the adder, added to the current configuration address addrincr_addr to obtain the auto-incremented configuration address auto_increment_addr, and then passed to the address register, which performs address management on the current configuration address addrincr_addr.

[0026] The address auto-increment module performs address management in different operating states according to the state machine trigger signal. The address operation states include: S0: standby state; S1: reset state; S2: first address update state; S3: address overflow state; S4: address increment state.

[0027] The address increment module is first in state S0 (standby state), and selects to enter state S1 (reset state) according to the reset signal, and initializes the internal address register to the default value; according to the start address valid signal slave_rx_addr_vld, the address increment module selects to enter state S2 (first address update state), and updates the current configuration address addrincr_addr to the start address slave_rx_addr as the configuration address for the first data configuration operation; then according to the write enable signal trans_wr and the read enable signal trans_rd, the overflow judgment is performed on the configuration address auto_increment_addr after the self-increment. When auto_increment_addr exceeds the maximum value allowed by the address width ADDR_WIDTH, the address increment module selects to jump to state S3 (address overflow state) to perform address reset. If the address does not overflow, it selects to jump to state S4 (address increment state) to perform address increment update as the configuration address for the next data configuration operation. After the chip is fully configured, the address increment module returns to state S0 (standby state).

[0028] The data configuration module includes 4 digital input signals and 3 digital output signals. The 4 digital input signals are the write enable signal trans_wr, the write data signal trans_wdat, the read enable signal trans_rd and the current configuration address addrincr_addr. The 3 digital output signals are the transmit valid signal config_tx_vld, the transmit data signal config_tx_dat and the receive acknowledgement signal config_rx_ack.

[0029] The data configuration module is connected to the register array inside the chip and is responsible for writing configuration data to the specified address of the array or reading data from the specified address of the array. The configuration position and working mode of the data configuration operation are determined based on the four data configuration signals: write enable signal trans_wr, write data signal trans_wdat, read enable signal trans_rd and current configuration address addrincr_addr.

[0030] This embodiment also provides a full-chip configuration method based on the address auto-increment mechanism, which specifically includes the following steps:

[0031] Step 1, according to the bit width of the input data and the bit width of the single address configuration data, the auto-increment step parameter is calculated, and the address auto-increment module automatically updates the current configuration address based on this parameter;

[0032] Step 2, based on the current configuration address updated in step 1, data configuration is performed on the register array inside the chip;

[0033] Step 3, repeating the address update operation in step 1 and the data configuration operation in step 2 until the whole chip configuration is completed.

[0034] The specific steps of step 1 include:

[0035] Step 11, the address self-increment module first enters state S1 (reset state) from state S0 (standby state) to ensure that the internal address register is initialized to the default value; after the reset is completed, according to the input starting address valid signal slave_rx_addr_vld, the address self-increment module enters state S2 (first address update state) and updates the current configuration address addrincr_addr to the starting address slave_rx_addr;

[0036] Step 12, according to the bit width of the input data and the bit width of the single address configuration data, define the bit width of the input data as 1, the bit width of the single address configuration data as n, set 1 / n as the auto-increment step parameter ADDR_NUM, and set addrincr_addr+1 / n as the configuration address auto_increment_addr after auto-increment;

[0037] Step 13, based on the write enable signal trans_wr and the read enable signal trans_rd corresponding to the starting address, the overflow judgment is performed on the configuration address auto_increment_addr after the self-increment. When the address overflows, choose to jump to state S3 (address overflow state), and the current configuration address addrincr_addr is reset to zero; otherwise, enter state S4 (address self-increment state), and update the current configuration address addrincr_addr to auto_increment_addr as the configuration address for the next data configuration operation.

[0038] The above method is applicable to communication protocols such as IIC, SPI, UART, and JTAG. Based on the commonalities of the above communication protocols in data transmission mode, communication control process, and master-slave device mode, the address auto-increment mechanism and data configuration operation are ensured to be implemented in different communication environments. This embodiment adopts the IIC communication protocol, and the full-chip configuration method flow chart provided is as follows Figure 2 As shown, the relevant parameters and indicators are exemplified as follows: the address bit width ADDR_WIDTH is 16, the bit width of the input data is 32, the bit width of the single address configuration data is 32, Master is the master device in the IIC communication, stop is the IIC data transmission stop signal input by the master device, and the IIC read and write working modes include writing to the specified address once, continuously writing to the specified address, reading the current address once, continuously reading the current address, reading the specified address once and continuously reading the specified address. Among them, the three working modes of continuously writing to the specified address, continuously reading the current address and continuously reading the specified address perform continuous configuration of data based on the address self-increment mechanism.

[0039] The specific full-chip configuration process is as follows:

[0040] First, the system starts up, and the module initialization process is triggered by the reset signal. The data transmission module, address increment module, and data configuration module reset their internal registers to ensure that the initial state is zero and ready for data configuration operations. After the reset is completed, the address increment module will update the current configuration address addrincr_addr to the starting address signal slave_rx_addr immediately based on the starting address valid signal slave_rx_addr_vld. When slave_rx_addr_vld is valid, the address increment module will immediately update the current configuration address addrincr_addr to the starting address signal slave_rx_addr. After receiving the updated current configuration address addrincr_addr, the data configuration module performs data writing or data reading according to the selected IIC working mode. The write operation is started by the write enable signal trans_wr, and the data in the write data signal trans_wdat is written to the target address. After a data write operation is completed, the data configuration module pulls up the receiving response signal config_rx_ack and transmits it to the Master through the communication interface, indicating that the data reception is completed; the read operation is started by the read enable signal trans_rd, and the data in the current configuration address addrincr_addr is obtained, and the data is transmitted to the Master through the communication interface by the send data signal config_tx_dat. After a data configuration is completed, if the stop signal transmitted by the master device is not received, the address auto-increment module determines that the step size of each address increase is 1 according to the bit width (32 bits) of the input data and the bit width (32 bits) of the single address configuration data, that is, the auto-increment step size parameter ADDR_NUM is 1, and the next auto-incremented configuration address auto_increment_addr is the starting address + 1. If the highest bit of the updated auto-incremented configuration address is 1, it means overflow occurs, and the current configuration address will be reset to 0; if no overflow occurs, the current configuration address is updated to auto_increment_addr. After the address update is completed, continue to wait for the valid write enable signal trans_wr and read enable signal trans_rd to read or write data. Similarly, the system repeats the address update and data configuration operations until all the data to be configured is written or read.

[0041] For example, the addresses to be written are 0x0003, 0x0004, 0x0012 and 0x0013, and the corresponding write data are 32'd10, 32'd20, 32'd00 and 32'd10, respectively. The two sets of data are required to be written continuously. The IIC is in the specified address continuous write working mode, and the input starting addresses are 0x0003 and 0x0012, respectively. The specific address auto-increment module working status diagram is as follows Figure 4As shown (in the figure, S0 represents the standby state, S1 represents the reset state, S2 represents the first address update state, S3 represents the address overflow state, and S4 represents the address increment state). First, the address increment module enters the state S1 from the state S0 to reset the system, and then jumps to the state S2 to receive the starting address 0x0003 sent by the master device Master. When the write enable signal trans_wr is valid, the received data 32'd10 is written into the register address 0x0003; the address increment step parameter is 1, so the configuration address after the increment is 0x0004, and the address does not overflow. The address increment module jumps to the state S4, 0x0004 is the valid current configuration address, and when the write enable signal trans_wr is valid, the received data 32'd20 is written into the register address 0x0004; at this time, the master device Master sends a stop signal, indicating that the continuous write operation is over and the next continuous write operation can be started. When the starting address valid signal slave_rx_addr_vld is valid, the address increment module continues to jump to state S2 and receives the starting address 0x0012 sent by the master device Master, and so on, until the received data 32'd10 is written to the register address 0x0013, the master device Master sends a stop signal, indicating that the data configuration process is over, and the address increment module returns to state S0.

Claims

1. A full-chip configuration device based on an address auto-increment mechanism, characterized in that: The device comprises a data transmission module, an address self-increment module and a data configuration module; The data transmission module is used to process data read and write requests and generate corresponding read and write control signals according to the requests; The address auto-increment module is used to determine the step size of each address increase according to the bit width of the input data and the bit width of the single address configuration data, and automatically calculate and update the configuration address based on the current address; The data configuration module is used to perform data writing or reading operations at a designated address based on the update address output by the address self-increment module and the read-write control signal output by the data transmission module.

2. A full-chip configuration device based on an address auto-increment mechanism according to claim 1, characterized in that: The data transmission module includes three digital input signals and digital output signals. The three digital input signals are respectively a receiving valid signal slave_rx_vld, a receiving data signal slave_rx_dat and a sending request signal slave_tx_req. The digital output signals include a write enable signal trans_wr, a write data signal trans_wdat and a read enable signal trans_rd.

3. A full-chip configuration device based on an address auto-increment mechanism according to claim 1, characterized in that: The data transmission module includes a data register and two D flip-flops, wherein the input receive valid signal slave_rx_vld is transmitted to the first D flip-flop and the data register, the first D flip-flop outputs a write enable signal trans_wr, and the input receive data signal slave_rx_dat is stored through the data register, indicating that data write operations are allowed; the input send request signal slave_tx_req is transmitted to the second D flip-flop, and the second D flip-flop outputs a read enable signal trans_rd, indicating that data read operations are allowed.

4. The full-chip configuration device based on the address auto-increment mechanism according to claim 1, characterized in that: The address increment module includes 4 digital input signals and 1 digital output signal, wherein the 4 digital input signals are a write enable signal trans_wr, a read enable signal trans_rd, a start address signal slave_rx_addr and a start address valid signal slave_rx_addr_vld, and the digital output signal is the current configuration address addrincr_addr.

5. The full-chip configuration device based on the address auto-increment mechanism according to claim 1, characterized in that: The address auto-increment module includes a step register, an adder and an address register, wherein the step register is used to store the value of the auto-increment step parameter ADDR_NUM, ADDR_NUM is the ratio of the bit width of the single received data to the configuration data bit width of a single address; the adder is used to receive the auto-increment step parameter ADDR_NUM, and add it to the current configuration address addrincr_addr to obtain the auto-incremented configuration address auto_increment_addr, and then pass it to the address register, and the address register is used to perform address management on the current configuration address addrincr_addr.

6. The full-chip configuration device based on the address auto-increment mechanism according to claim 1, characterized in that: The address auto-increment module is used to perform address management in different operation states, and the address operation states include: S0: standby state; S1: reset state; S2: first address update state; S3: address overflow state; S4: address increment state.

7. The full-chip configuration device based on the address auto-increment mechanism according to claim 1, characterized in that: The data configuration module is connected to the register array inside the chip, and includes 4 digital input signals and 3 digital output signals, wherein the 4 digital input signals are respectively a write enable signal trans_wr, a write data signal trans_wdat, a read enable signal trans_rd and a current configuration address addrincr_addr, and the 3 digital output signals are respectively a send valid signal config_tx_vld, a send data signal config_tx_dat and a receive response signal config_rx_ack.

8. A method for configuring a whole chip device based on an address auto-increment mechanism as claimed in claim 1, characterized in that: The method comprises the following steps: Step 1, calculating an auto-increment step parameter according to the bit width of the input data and the bit width of the single address configuration data, and the address auto-increment module automatically updates the current configuration address based on the parameter; Step 2, based on the current configuration address updated in step 1, data configuration is performed on the register array inside the chip; Step 3, repeating the address update operation in step 1 and the data configuration operation in step 2 until the whole chip configuration is completed.

9. The method according to claim 8, characterized in that The address self-increment module performs address management in different operating states, and its address operation states include: S0: standby state; S1: reset state; S2: first address update state; S3: address overflow state; S4: address increment state; the specific steps of step 1 include: Step 11, the address increment module first enters state S1 from state S0 to ensure that the internal address register is initialized to the default value; after the reset is completed, according to the input start address valid signal slave_rx_addr_vld, the address increment module enters state S2 and updates the current configuration address addrincr_addr to the start address slave_rx_addr; Step 12, according to the bit width of the input data and the bit width of the single address configuration data, define the bit width of the input data as 1, the bit width of the single address configuration data as n, set 1 / n as the auto-increment step parameter ADDR_NUM, and set addrincr_addr+1 / n as the configuration address auto_increment_addr after auto-increment; Step 13, based on the write enable signal trans_wr and the read enable signal trans_rd corresponding to the starting address, the overflow of the self-incremented configuration address auto_increment_addr is judged. When the address overflows, jump to state S3 and reset the current configuration address addrincr_addr to zero; otherwise, enter state S4 and update the current configuration address addrincr_addr to auto_increment_addr as the configuration address for the next data configuration operation.

10. The method according to claim 8, characterized in that The method is applicable to IIC, SPI, UART or JTAG communication protocols.

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