Memory and equipment

Abstract

The invention discloses a memory and equipment, and relates to the field of storage, and the memory comprises a first wafer and a second wafer which are stacked. The first wafer is a storage medium wafer, and a medium controller is arranged on the second wafer. The storage medium wafer comprises a plurality of areas, each area comprises a plurality of crystal grains, each crystal grain comprises a plurality of BANKs, the medium controller is connected with each BANK, and the medium controller can receive a data access instruction and access the BANKs according to the data access instruction. The memory is a wafer-level memory, and the storage medium takes the whole wafer as a substrate, so that the capacity of the memory can be greatly increased. The medium controller can directly control the BANKs and can operate a plurality of BANKs in parallel, data transmitted by the storage medium wafer and the medium controller in a transmission period can be increased, and the bit width of the memory is increased.

Description

[0001] This application is a divisional application. The application number of the original application is 202310700909.7, and the original application date is June 13, 2023. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a memory and a device. Background Art

[0003] At present, the mainstream memory is formed by cutting a single or multiple die on a wafer with a storage medium, and then packaging it with the input output (I / O) circuit through a complementary metal oxide semiconductor (CMOS) under array (CUA) architecture. In this packaging method, the die and the I / O circuit can be stacked up and down or arranged side by side. Regardless of stacking up and down or arranging side by side, there is a certain proportional relationship between the number of BANKs in the die and the size of the I / O circuit, which will limit the number of BANKs in the memory, resulting in the inability to significantly increase the memory capacity. In addition, the I / O circuit can be connected to the memory controller of the peripheral through a bus, which requires that the bit width of the memory (the bit width of the memory refers to the amount of data transmitted by the memory in one transmission cycle) will be limited by the bus, and the bit width of the memory cannot be expanded. Summary of the invention

[0004] The present application provides a memory and a device for expanding the bit width and capacity of the memory.

[0005] In a first aspect, an embodiment of the present application provides a memory, the memory comprising a stacked first wafer and a second wafer. The first wafer is a storage medium wafer, that is, a storage medium is disposed on the first wafer, a medium controller is disposed on the second wafer, and a connection is provided between the storage medium wafer and the medium controller. The storage medium wafer can store data; the medium controller can receive a data access instruction and access the storage medium according to the data access instruction.

[0006] The storage medium wafer includes multiple areas, each area includes multiple crystal grains, each crystal grain includes multiple BANKs, and each BANK is connected to the medium controller. The BANK here refers to a smaller storage unit included in the crystal grain. In different scenarios, the BANK can be replaced by different names. In the embodiment of the present application, BANK is taken as an example. The medium controller can access the BANK on the storage medium wafer according to the data access instruction.

[0007] Through the above memory, the memory is a wafer-level memory, and the storage medium is based on the entire wafer, ensuring that the capacity of the memory can be greatly increased. The control of the storage medium wafer by the media controller is based on the BANK granularity, ensuring that the memory has a higher bit width.

[0008] In a possible implementation, the media controller includes a plurality of sub-controllers, each sub-controller corresponds to an area, and the sub-controller is connected to each BANK in the corresponding area;

[0009] The sub-controller receives the data access instruction, and accesses the BANK in the corresponding area according to the data access instruction.

[0010] Through the above memory, the media controller includes multiple sub-controllers corresponding to the areas, and each sub-controller can access the BANK in the corresponding area in parallel, ensuring that the memory can efficiently process the received data access instructions, effectively improving the data access efficiency of the memory.

[0011] In a possible implementation manner, the multiple sub-controllers may not be connected to each other, or the multiple sub-controllers may be connected to each other, for example, the multiple sub-controllers communicate with each other through a NoC.

[0012] Through the above memory, multiple sub-controllers can be flexibly connected or unconnected, which is suitable for different scenarios. The connection between the multiple sub-controllers can ensure efficient information exchange between the multiple sub-controllers.

[0013] In a possible implementation, multiple sub-controllers are interconnected, that is, the multiple sub-controllers are fully connected. Any sub-controller is connected to any other sub-controller. Any sub-controller can transmit a data access instruction that the sub-controller cannot process to a sub-controller connected to the sub-controller.

[0014] Through the above memory, since the sub-controllers adopt a fully connected mode, it is ensured that a data access instruction that cannot be processed by any sub-controller can always be received by other sub-controllers that can process the data access instruction.

[0015] In a possible implementation, the sub-controller is connected to an adjacent sub-controller, and the sub-controller can transmit a data access instruction that cannot be processed by the sub-controller to the adjacent sub-controller.

[0016] Through the above-mentioned memory, there is a connection between the sub-controller and the adjacent sub-controller, the connection method is relatively simple, and by transmitting the data access instruction, the data processing instruction can eventually be received by the sub-controller that can process the data access instruction.

[0017] In a possible implementation, a plurality of sub-controllers are connected in series to form a ring-shaped circuit, and the sub-controllers may broadcast data access instructions that cannot be processed by the sub-controllers through the ring-shaped circuit.

[0018] Through the above-mentioned memory, the ring-shaped circuit makes the connection lines between multiple sub-controllers simpler without adding too many lines. The sub-controller transmits the data access instruction by broadcasting, ensuring that the other sub-controllers can receive the data access instruction.

[0019] In a possible implementation, the media controller further includes an input / output I / O module. The I / O module and a plurality of sub-controllers are connected in series to form a ring-shaped circuit. The I / O module is connected to a device outside the memory via a system bus.

[0020] The I / O module receives the data access instruction and broadcasts the data access instruction through the ring line. The sub-controller monitors the ring line and obtains the data access instruction.

[0021] Through the above-mentioned memory, the I / O module is responsible for receiving and forwarding data access instructions. The device outside the memory only needs to be connected to the I / O module, which simplifies the line between the memory and the external device. The I / O module transmits data access instructions by broadcasting, ensuring that the multiple sub-controllers can receive the data access instructions.

[0022] In a possible implementation, the subcontroller stores data address information of the corresponding area, and the data address information is used to record the data address of the corresponding area; the data address carried by the data access instruction that the subcontroller cannot process is not the data address recorded by the data address information.

[0023] Through the above memory, the sub-controller can accurately find the data access instruction that cannot be processed through the stored data address information of the corresponding area.

[0024] In a possible implementation, the memory also includes a test module, which is used to perform functional testing on the storage medium wafer and record the BANKs and the grains to which the BANKs belong in the storage medium wafer that have not passed the test. The functional test includes some or all of the following: read and write test, delay test, life test, and temperature test.

[0025] Through the above memory, the memory has a built-in test module, which can perform functional tests on the storage medium wafer to ensure that the memory can have normal functions and work normally.

[0026] In a possible implementation, the media controller can perform functional testing on the storage media wafer and record the BANKs and the grains to which the BANKs belong that have failed the test in the storage media wafer. The functional testing includes some or all of the following: read and write testing, delay testing, life testing, and temperature testing.

[0027] Through the above memory, the media controller can perform functional tests on the storage medium wafer, so that the memory can perform self-test to ensure the normal operation of the memory.

[0028] In a second aspect, a computing device is provided, the computing device comprising a processor and the memory as described in the first aspect and any possible implementation manner of the first aspect, the processor being connected to a media controller in the memory. The number of the processors may be one or more. The processor may send the data access instruction to the memory.

[0029] In a possible implementation, the processor is connected to one or more sub-controllers in the media controller. For example, there are multiple processors, and each processor is connected to a sub-controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A A schematic diagram of the structure of a wafer;

[0031] Figure 1B A flow chart for preparing a memory;

[0032] Figure 1C A schematic diagram of the connection between a memory I / O circuit, a memory controller and each BANK;

[0033] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a connection between a media controller and a storage medium in a memory provided in an embodiment of the present application;

[0035] Figure 4A A schematic diagram of the division of regions in a storage medium provided in an embodiment of the present application;

[0036] Figure 4B A schematic diagram of the connection between a sub-controller and a storage medium in a memory provided in an embodiment of the present application;

[0037] Figures 5A-5B A schematic diagram of the connection between sub-controllers provided in an embodiment of the present application;

[0038] Figures 6A-6BA schematic diagram of the connection between sub-controllers provided in an embodiment of the present application;

[0039] Figures 7A-7B A schematic diagram of the connection between sub-controllers provided in an embodiment of the present application;

[0040] Figures 8A-8B A schematic diagram of the connection between sub-controllers provided in an embodiment of the present application;

[0041] Figures 9A to 9B A schematic diagram of the connection between sub-controllers provided in an embodiment of the present application;

[0042] Fig.10 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0043] Fig.11 A schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] Before describing the memory and system provided in the embodiments of the present application, some concepts involved in the present application are described:

[0045] (1) Wafer

[0046] Wafer is the abbreviation of semiconductor crystal slice, and the shape of wafer is usually a cylindrical thin slice. Wafers are usually used to prepare computer chips, memory, solar cells and other devices. For example, integrated circuit logic on a wafer can form a computer chip with computing functions. For another example, a storage medium and input and output (I / O) circuits are set on a wafer and packaged to form a memory. For another example, a solar cell can be formed by depositing a P-type film and an N-type film on a wafer. The most common wafers are silicon wafers, gallium nitride wafers, silicon carbide wafers, etc.

[0047] In the embodiment of the present application, the memory includes a first wafer and a second wafer, the first wafer is a storage medium wafer, and the second wafer is provided with a medium controller. The storage medium wafer and the wafer provided with the medium controller are stacked to form an upper and lower stacked structure.

[0048] (2) Storage media and memory.

[0049] Storage media refers to substances or components that can be used to store binary codes "0" and "1". Storage media have two stable physical states. Through some methods (such as detecting voltage, resistance, etc.), it is possible to determine which physical state the storage medium is in, thereby determining whether the storage medium stores "0" or "1". For storage media, these two physical states can be converted to achieve the conversion from "0" to "1" or "1" to "0".

[0050] In the embodiment of the present application, the memory refers to a device capable of processing data access instructions and performing data access on the data in the memory. In other words, the memory not only has a data processing function, but also has a processing function for data access instructions.

[0051] The following is a common process for preparing memory using wafers.

[0052] Usually, a wafer is processed by photolithography, doping and other methods to form lattice-shaped grains on the wafer. Figure 1A As shown, a wafer with lattice-shaped crystal grains is formed, wherein each small square represents a crystal grain, and the crystal grain can be called a die. For memory, each crystal grain includes multiple BANKs. Each BANK can be regarded as a rectangular grid array including multiple grids. The rectangular grid array includes multiple columns (columns) and multiple rows (rows) of grids, and these grids are used to store data.

[0053] like Figure 1B As shown. After the die on the wafer is cut, the final test (FT) function is performed. The synthesized die can be used to prepare memory. The cut wafer only has the basic data storage function and cannot directly process the instructions initiated by the memory controller to realize data reading and writing. To this end, it is necessary to configure input and output (I / O) circuits for each die. After the die is connected to the I / O circuit, it is packaged together to form a memory.

[0054] like Figure 1CAs shown, the I / O circuit is connected to each BANK on the die, and the I / O circuit can read data from each BANK or write data from each BANK. The I / O circuit can be connected to an external memory controller through a bus, and can read or write data in each connected BANK under the memory controller. Due to the limitation of the bus bandwidth, the amount of data transmitted by the I / O circuit and the memory controller at one time is fixed. Taking the process of outputting data in the die to the memory controller as an example, assuming that each die includes N BANKs, the limitation of the bus bandwidth makes the amount of data transmitted by the I / O circuit and the memory controller at one time 8 bits (here, one transmission refers to the data transmission completed within one transmission cycle). If each BANK can output 8 bits of data at one time, the I / O circuit cannot transmit the data output by each BANK to the memory controller at one time, but needs to complete the N-to-1 selection operation, and can only transmit the data output by one BANK in one transmission. A memory can include one or more die. The amount of data transmitted between the memory and the memory controller at one time is called the bit width of the memory. It can be seen that the bit width of the memory is relatively fixed.

[0055] In addition, when packaging the die and the I / O circuit, a complementary metal-oxide-semiconductor (CMOS) under array (CUA) architecture can be used. This architecture requires that the size of the die be consistent with the size of the I / O circuit. Due to this limitation, there is a certain relationship between the number of BANKs in the die and the size of the I / O circuit. The size of the BANK in the die cannot be significantly increased, which also makes it impossible to effectively increase the capacity of the memory.

[0056] In an embodiment of the present application, the memory includes stacked wafers, wherein a storage medium is provided on one wafer, and a media controller is provided on another wafer. There is a connection between the storage medium and the media controller. The storage medium includes a plurality of BANKs, and each BANK in the storage medium is connected to the media controller. The media controller can directly control each BANK in the storage medium. In the memory, there is a wafer for setting the storage medium, which effectively expands the capacity of the memory. The amount of data transmitted at one time between the media controller and the storage medium is related to the number of BANKs connected to the media controller. The larger the number of BANKs connected, the larger the amount of data transmitted at one time between the media controller and the storage medium, that is, the larger the bit width of the memory.

[0057] The structure of the memory provided by the embodiment of the present application is described below in conjunction with the accompanying drawings. Figure 2As shown, a memory provided by an embodiment of the present application is a wafer-level memory. That is, the memory 10 is a memory formed by a whole wafer. In terms of the size of the memory 10, the area of ​​the memory 10 is greater than or equal to the area of ​​the wafer.

[0058] Structurally, the memory 10 includes stacked wafers. Among them, a wafer 100 is used as a substrate for a storage medium 110, and a storage medium 110 is arranged on the wafer 100, that is, a material or component for realizing a storage function is prepared on the wafer 100. The wafer 100 may also be referred to as a storage medium wafer 100. In the embodiment of the present application, the type of the storage medium 110 is not limited. For example, the storage medium 110 may be a read-only memory (ROM), a dynamic random access memory (DRAM), or a storage class memory (SCM), a static random access memory 10 (SRAM), a dual in-line memory module or a dual-line memory module (DIMM), a flash memory, a NAND flash memory, and any storage medium 110 that can be prepared with a wafer as a substrate is applicable to the embodiment of the present application.

[0059] Another wafer 200 is used as a substrate of the medium controller 210 in the memory 10, and the medium controller 210 is arranged on the wafer 200. That is, the circuit logic related to the medium controller 210 is prepared on the wafer 200. When the memory 10 is used as a memory in a computing device, the medium controller 210 can be understood as a memory controller. When the memory 10 is a non-memory type memory 10, the medium controller 210 is a controller arranged in the memory 10 and having a control function.

[0060] The media controller 210 is the control core in the memory 10. The media controller 210 receives data access instructions sent by a device (such as a processor) outside the memory 10, parses and processes the data access instructions. The media controller 210 can also control the storage medium 110 to access the data stored in the storage medium 110, that is, to complete the reading and writing of data (data is understood as the "0" and "1" mentioned in the above content).

[0061] For example, in the process of processing the data access instruction, when the media controller 210 determines that the data access instruction requests to read data, the media controller 210 may read data from the storage medium 110. For another example, in the process of processing the data access instruction, when the media controller 210 determines that the data access instruction requests to write data, the media controller 210 may write the data requested to be written by the data access instruction to the storage medium 110.

[0062] There is a connection between the storage medium wafer 100 and the media controller 210. For example, the storage medium wafer 100 and the media controller 210 can be connected through a non-bus line. The non-bus line refers to a line that is not constrained by relevant protocol standards. For the convenience of distinction, the line inside the memory 10, between the storage medium 110 and the media controller 210 is called an internal line, and the internal line can be a non-bus line. That is, the internal line is not a line under the standards such as the double data rate (DDR) bus, the open nand flash interface (ONFI), and Toggle. In this way, the data transmission between the media controller 210 and the storage medium 110 is no longer limited by the limitation of the bus, the number and bandwidth of the internal lines can be designed based on actual needs, and the media controller 210 can efficiently access the storage medium 110.

[0063] It is worth noting that among the buses in the existing memory 10, there are some buses with relatively large bandwidths, such as high bandwidth memory 10 (HBM). In the embodiment of the present application, the storage medium wafer 100 and the medium controller 210 may also use such buses with relatively large bandwidths.

[0064] Next, the structures of the storage medium 110 and the media controller 210 are described.

[0065] 1) Storage medium 110.

[0066] like Figure 3 As shown, on the storage medium wafer 100, the wafer 100 includes a dot-matrix-shaped die 120, and each die 120 includes a plurality of BANKs 130. Each BANK 130 is connected to the medium controller 210 (e.g., connected via an internal line). In other words, the medium controller 210 can directly control each BANK 130 and perform data access on each BANK 130.

[0067] In the embodiment of the present application, on the storage medium wafer 100, the die 120 is no longer provided with a separate I / O circuit, and the control of the storage medium 110 by the medium controller 210 is not based on the granularity of the die 120, but is refined to the granularity of BANK 130.

[0068] like Figure 4A As shown, in order to facilitate the media controller 210 to control the storage medium 110, the lattice-shaped grains 120 on the storage medium wafer 100 can be divided into multiple regions 140. Each region 140 includes multiple grains 120, and each region 140 corresponds to a sub-controller 220 in the media controller 210. The structure of the media controller 210 is described below.

[0069] 2) Media controller 210.

[0070] like Figure 4B As shown, the media controller 210 includes a plurality of sub-controllers 220 , each of which corresponds to an area 140 in the storage medium 110 and is used to control the BANK 130 in the corresponding area 140 to access the data in the area 140 .

[0071] For any sub-controller 220, the BANK 130 of each die 120 in the area 140 corresponding to the sub-controller 220 is connected to the sub-controller 220; or the read-write circuit of each BANK 130 in the area 140 corresponding to each sub-controller 220 is connected to the sub-controller 220. Then, the sub-controller 220 can synchronously access each BANK 130 in each die 120 in the corresponding area 140.

[0072] In the embodiment of the present application, the media controller 210 (such as each sub-controller 220) can be directly connected to the BANK 130. The media controller 210 can directly change the physical state of the BANK 130 (that is, the physical state of the part of the storage medium 110 corresponding to the BANK 130) to achieve writing or reading of "0" or "1".

[0073] Optionally, a corresponding read / write circuit is provided for each BANK 130, and the read / write circuit can read data from the grids in the BANK 130 or write data in these grids under the control of the media controller 210. The read / write circuit connects the BANK 130 and the media controller 210, and the read / write circuit can change the physical state of the BANK 130 (that is, the physical state of the part of the storage medium 110 corresponding to the BANK 130) under the instruction of the media controller 210 to achieve the writing of "0" or "1"; the read / write circuit can also detect the physical state of the BANK 130 under the instruction of the media controller 210 to achieve the reading of "0" or "1". In the scenario where the read / write circuit is provided, the read / write circuit of each BANK 130 is connected to the media controller 210 to ensure that the media controller 210 can control each BANK 130 through the read / write circuit.

[0074] As a component of the memory 10, the read / write circuit is not limited to the position of the read / write circuit inside the memory 10 in the embodiment of the present application. The read / write circuit can be located on the storage medium wafer 100, or on the wafer 200 where the medium controller 210 is located. In some scenarios, a part of the read / write circuit can be located on the storage medium wafer 100, and another part of the read / write circuit can be located on the wafer 200 where the medium controller 210 is located.

[0075] The control of the connected BANK130 by the sub-controller 220 or the media controller 210 may be associated or independent. Taking the sub-controller 220 as an example, when the sub-controller 220 controls the BANK130 in the corresponding area 140, the sub-controller 220 may synchronously write data to the BANK130 in the corresponding area 140, and may also synchronously read data from the BANK130 in the corresponding area 140. In other words, within a period of time, the sub-controller 220 performs the same operation on the BANK130 in the corresponding area 140. In this control mode, the control of the connected BANK130 by the sub-controller 220 is associated. When the sub-controller 220 controls the BANK 130 in the corresponding area 140, the sub-controller 220 can perform different operations on different BANKs 130 in the corresponding area 140. The sub-controller 220 can read data from one BANK 130 in the corresponding area 140 and write data to another BANK 130 in the corresponding area 140 at the same time. In other words, the sub-controller 220 can perform different operations on the BANKs 130 in the corresponding area 140 within a period of time. In this control mode, the sub-controller 220 controls the connected BANKs 130 independently.

[0076] The embodiments of the present application do not limit the types of the sub-controller 220 and the media controller 210. The sub-controller 220 and the media controller 210 may be application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0077] Externally, the sub-controller 220 can be connected to an external device (such as an external processor) through a system bus to receive data access instructions from the outside. The sub-controller 220 receives the data access instruction and processes the data access instruction. In the process of processing the data access instruction, the sub-controller 220 can access the BANK 130 in the corresponding area 140 according to the data access instruction.

[0078] In the embodiment of the present application, there may be no connection between the multiple sub-controllers 220, that is, there is no communication between the sub-controllers 220. Each sub-controller 220 can access each BANK 130 in the corresponding area 140, but cannot access BANK 130 in other areas 140.

[0079] Connections can also be established between the multiple sub-controllers 220, that is, the sub-controllers 220 can communicate with each other. When there are connections between the multiple sub-controllers 220, information can be exchanged between the sub-controllers 220. For example, a sub-controller 220 can transmit a data access instruction that it cannot process to the sub-controller 220 to which the sub-controller 220 is connected. For another example, a sub-controller 220 can obtain an access response of the connected sub-controller 220 to the data access instruction from the connected sub-controller 220. In an embodiment of the present application, the multiple sub-controllers 220 can be connected through an on-chip network (network on chip, NoC), or through other lines, and all lines that can connect the multiple sub-controllers 220 are applicable to the embodiment of the present application.

[0080] Optionally, for any sub-controller 220, the sub-controller 220 can be connected to a BANK 130 in an adjacent area 140 of a BANK 130 in the corresponding area 140, that is, the sub-controller 220 can access a BANK 130 in an adjacent area 140 of a BANK 130 in the corresponding area 140. The sub-controller 220 can be connected to a BANK 130 in an adjacent area 140 of a BANK 130 in the corresponding area 140 through a NoC.

[0081] Several connection modes between the multiple sub-controllers 220 on the wafer 200 provided with the medium controller 210 are listed below.

[0082] Method 1: Figure 5A As shown, the media controller 210 includes a plurality of sub-controllers 220, and there is a connection between any two sub-controllers 220. Any sub-controller 220 can pass data access instructions that it cannot process to each of the connected sub-controllers 220.

[0083] Each controller stores the data address information of the corresponding area 140. The data address information records the data address in the area 140. For any sub-controller 220, when the sub-controller 220 receives a data access instruction sent by an external device, it can first detect the data address information of the corresponding area 140 according to the data address carried by the data access instruction, and determine whether the data address carried by the data access instruction is a data address in the area 140. If the data address carried by the data access instruction is a data address in the area 140, continue to process the data access instruction. After processing the data access instruction, the sub-controller 220 can also feedback an access response to the external device. For a data access instruction requesting to read data, the access response will carry the data read by the sub-controller 220 from the corresponding area 140. For a data access instruction requesting to write data, the access response will indicate whether the data writing is successful or failed; if the data address carried by the data access instruction is not a data address within the area 140, the data access instruction is a data access instruction that the sub-controller 220 cannot process, and the sub-controller 220 can pass the data access instruction to the connected sub-controller 220.

[0084] In this connection mode, since the sub-controller 220 is connected to all sub-controllers 220 in the media controller 210 except the sub-controller 220, that is, there is always a sub-controller 220 among the sub-controllers 220 connected to the sub-controller 220 that can process the data access instruction.

[0085] After receiving the data access instruction transmitted by the sub-controller 220, any sub-controller 220 connected to the sub-controller 220 first detects the data address information of the corresponding area 140 according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is a data address within the area 140. If the data address carried by the data access instruction is a data address within the area 140, the data access instruction is processed. The sub-controller 220 connected to the sub-controller 220 can also feedback an access response to the sub-controller 220. For the description of the access response, please refer to the above content and will not be repeated here. If the data address carried by the data access instruction is not a data address within the area 140, the sub-controller 220 connected to the sub-controller 220 can discard the data access instruction.

[0086] like Figure 5B , which is a schematic diagram of a connection topology between multiple sub-controllers 220 provided in an embodiment of the present application. Figure 5B In the embodiment, the media controller 210 includes four sub-controllers 220, which are respectively referred to as sub-controller 220A, sub-controller 220B, sub-controller 220C, and sub-controller 220D for convenience of description. The regions 140 corresponding to the sub-controllers 220A, 220B, 220C, and 220D are respectively referred to as regions 140A, 140B, 140C, and 140D. The sub-controllers 220A, 220B, 220C, and 220D are connected to different processors.

[0087] Any two sub-controllers 220 are connected. For example, sub-controller 220A is connected to sub-controller 220B, sub-controller 220C, and sub-controller 220D.

[0088] When the sub-controller 220A receives a data access instruction sent by an external processor, the sub-controller 220A first detects the data address information of the area 140A according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is a data address within the area 140A. If the data address carried by the data access instruction is the data address of the area 140A, the data access instruction continues to be processed. After processing the data access instruction, the sub-controller 220A can feedback an access response to the external processor. For the description of the access response, please refer to the above content, which will not be repeated here; if the data address carried by the data access instruction is not the data address of the area 140A, the sub-controller 220A passes the data access instruction to the sub-controllers 220B, 220C, and 220D.

[0089] Taking sub-controller 220B as an example, when sub-controller 220B receives the data access instruction transmitted by sub-controller 220A, it first detects the data address information of area 140B based on the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is the data address of area 140B. If the data address carried by the data access instruction is the data address of area 140B, the data access instruction is processed. Sub-controller 220B can also feedback an access response to sub-controller 220A. For the description of the access response, please refer to the above content and will not be repeated here. If the data address carried by the data access instruction is not the data address of area 140B, sub-controller 220B can discard the data access instruction.

[0090] Method 2: Fig. 6A As shown, the media controller 210 includes a plurality of sub-controllers 220, and any sub-controller 220 is only connected to an adjacent sub-controller 220. Any sub-controller 220 can pass a data access instruction that it cannot process to an adjacent sub-controller 220.

[0091] Each controller stores the data address information of the corresponding area 140. The data address information records the data address in the area 140. For any sub-controller 220, when the sub-controller 220 receives a data access instruction initiated by an external device, it can first detect the data address information of the corresponding area 140 according to the data address carried by the data access instruction, and determine whether the data address carried by the data access instruction is a data address in the area 140. If the data address carried by the data access instruction is a data address in the area 140, the data access instruction continues to be processed. After processing the data access instruction, the sub-controller 220 can also feedback an access response to the external device. For the description of the access response, please refer to the aforementioned content, which will not be repeated here; if the data address carried by the data access instruction is not a data address in the area 140, the sub-controller 220 can pass the data access instruction to the adjacent sub-controller 220.

[0092] In this connection mode, the sub-controller 220 is only connected to the adjacent sub-controllers 220. When there are a large number of sub-controllers 220, the sub-controller 220 cannot transmit the data access instruction to all sub-controllers 220 except the sub-controller 220. If any sub-controller 220 adjacent to the sub-controller 220 cannot process the data access instruction after receiving it, it can also transmit the data access instruction to the adjacent sub-controller 220.

[0093] After receiving the data access instruction transmitted by the sub-controller 220, any sub-controller 220 adjacent to the sub-controller 220 first detects the data address information of the corresponding area 140 according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is a data address within the area 140. If the data address carried by the data access instruction is a data address within the area 140, the data access instruction is processed. The sub-controller 220 adjacent to the sub-controller 220 can also feedback an access response to the sub-controller 220. For a data access instruction requesting to read data, the access response will carry the data read from the corresponding area 140 by the sub-controller 220 adjacent to the sub-controller 220. For a data access instruction requesting to write data, the access response will indicate whether the data is written successfully or failed. If the data address carried by the data access instruction is not a data address within the area 140, the sub-controller 220 adjacent to the sub-controller 220 will continue to pass the data access instruction to the adjacent sub-controller 220.

[0094] In this way, a data access instruction that cannot be processed by a sub-controller 220 can always be transferred to a sub-controller 220 that can process the data access instruction. After the sub-controller 220 that can process the data access instruction completes processing of the data access instruction, it can transfer an access response to the sub-controller 220 that initially receives the data access instruction according to the path by which the data access instruction is transferred to the sub-controller 220, and the sub-controller 220 that initially receives the data access instruction feeds back the access response to the external device.

[0095] like Figure 6B , which is a schematic diagram of a connection topology between multiple sub-controllers 220 provided in an embodiment of the present application. Figure 6BIn the figure, the media controller 210 includes 9 sub-controllers 220, which are respectively referred to as sub-controller 220a, sub-controller 220b, sub-controller 220c, sub-controller 220d, sub-controller 220e, sub-controller 220f, sub-controller 220g, sub-controller 220h, and sub-controller 220i for convenience of description. The regions 140 corresponding to the sub-controllers 220a, sub-controller 220b, sub-controller 220c, sub-controller 220d, sub-controller 220e, sub-controller 220f, sub-controller 220g, sub-controller 220h, and sub-controller 220i are respectively referred to as region 140a, region 140b, region 140c, region 140d, region 140e, region 140f, sub-region 140g, region 140h, and region 140i. The sub-controller 220a, sub-controller 220b, sub-controller 220c, sub-controller 220d, sub-controller 220e, sub-controller 220f, sub-controller 220g, sub-controller 220h, and sub-controller 220i are respectively connected to different processors outside the memory 10.

[0096] Any sub-controller 220 has a connection line with the adjacent sub-controller 220. For example, sub-controller 220a has a connection line with the adjacent sub-controller 220b and sub-controller 220d. Sub-controller 220e has a connection line with the adjacent sub-controller 220b, sub-controller 220d, sub-controller 220f, and sub-controller 220h.

[0097] When the sub-controller 220a receives a data access instruction sent by an external processor, the sub-controller 220a first detects the data address information of the area 140a according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is a data address in the area 140a. If the data address carried by the data access instruction is the data address of the area 140a, the data access instruction continues to be processed. After processing the data access instruction, the sub-controller 220a can feedback an access response to the external processor. For the description of the access response, please refer to the above content, which will not be repeated here; if the data address carried by the data access instruction is not the data address of the area 140a, the sub-controller 220a passes the data access instruction to the adjacent sub-controllers 220b and 220d.

[0098] Taking sub-controller 220d as an example, when sub-controller 220d receives the data access instruction transmitted by sub-controller 220a, it first detects the data address information of area 140d according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is the data address of area 140d. If the data address carried by the data access instruction is the data address of area 140d, the data access instruction is processed. Sub-controller 220d can also feedback the access response to sub-controller 220a, and sub-controller 220a feeds back the feedback response to the external processor. If the data address carried by the data access instruction is not the data address of area 140d, sub-controller 220d can pass the data access instruction to adjacent sub-controllers 220e and 220g. Although sub-controller 220a is also adjacent to sub-controller 220d, since the data access instruction is received from sub-controller 220a, sub-controller 220d can no longer transmit the data access instruction to sub-controller 220a.

[0099] Taking sub-controller 220g as an example, when sub-controller 220g receives the data access instruction transmitted by sub-controller 220d, it first detects the data address information of area 140g according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is the data address of area 140g. If the data address carried by the data access instruction is the data address of area 140g, the data access instruction is processed. Sub-controller 220g can also feedback the access response to sub-controller 220d, and sub-controller 220d will feedback the access response to sub-controller 220a, and sub-controller 220a will feedback the feedback response to the external processor. If the data address carried by the data access instruction is not the data address of area 140g, sub-controller 220g can pass the data access instruction to the adjacent sub-controller 220b, sub-controller 220f, and sub-controller 220h.

[0100] Method 3: Fig. 7AAs shown, the media controller 210 includes a plurality of sub-controllers 220, and the plurality of sub-controllers 220 are connected in series through a ring line, that is, the connection lines between the plurality of sub-controllers 220 form a ring line. Any sub-controller 220 can broadcast the data access instruction that cannot be processed to other sub-controllers 220 on the ring line through the ring line. Any sub-controller 220 on the ring line monitors the data access instruction broadcasted on the ring line, and if the data address carried by the data access instruction is the data address of the corresponding area 140, the data access instruction is processed. After processing the data access instruction, the sub-controller 220 can also broadcast the access response to other sub-controllers 220 on the ring line through the ring line, and the sub-controller 220 that initially receives the data access instruction can obtain the access response.

[0101] Each controller stores the data address information of the corresponding area 140. The data address information records the data address in the area 140. For any sub-controller 220, when the sub-controller 220 receives a data access instruction initiated by an external device, it can first detect the data address information of the corresponding area 140 according to the data address carried by the data access instruction, and determine whether the data address carried by the data access instruction is a data address in the area 140. If the data address carried by the data access instruction is a data address in the area 140, continue to process the data access instruction. After processing the data access instruction, the sub-controller 220 can feedback an access response to the external processor. For the description of the access response, please refer to the aforementioned content, which will not be repeated here; if the data address carried by the data access instruction is not a data address in the area 140, the sub-controller 220 can discard the data access instruction.

[0102] In this connection mode, since the ring line connects all sub-controllers 220, the method of broadcasting the data access instruction can ensure that all sub-controllers 220 on the ring line can receive the data access instruction. In other words, the data access instruction can always be monitored by the sub-controller 220 that can process the data access instruction.

[0103] like Figure 7B , which is a schematic diagram of a connection topology between multiple sub-controllers 220 provided in an embodiment of the present application. Figure 7BIn the embodiment, the media controller 210 includes six sub-controllers 220, which are respectively referred to as sub-controller 220A, sub-controller 220B, sub-controller 220C, sub-controller 220D, sub-controller 220E, and sub-controller 220F for convenience of description. The regions 140 corresponding to the sub-controllers 220A, 220B, 220C, 220D, 220E, and 220F are respectively referred to as regions 140A, 140B, 140C, 140D, 140E, and 140F. The sub-controllers 220A, 220B, 220C, 220D, 220E, and 220F are respectively connected to different processors outside the memory 10.

[0104] The sub-controller 220A, the sub-controller 220B, the sub-controller 220C, the sub-controller 220D, the sub-controller 220E, and the sub-controller 220F are connected via a ring line.

[0105] When the sub-controller 220A receives a data access instruction sent by an external processor, the sub-controller 220A first detects the data address information of the area 140A according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is a data address within the area 140A. If the data address carried by the data access instruction is the data address of the area 140A, the data access instruction continues to be processed; if the data address carried by the data access instruction is not the data address of the area 140A, the sub-controller 220A broadcasts the data access instruction on the ring line, so that the sub-controllers 220B, 220C, 220D, 220E, and 220F can monitor the data access instruction through the information transmitted in the ring line.

[0106] Taking the sub-controller 220B as an example, when the sub-controller 220B monitors the data access instruction, it first detects the data address information of the area 140B according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is the data address of the area 140B. If the data address carried by the data access instruction is the data address of the area 140B, the data access instruction is processed. The sub-controller 220B broadcasts the access response of the data access instruction on the ring line. If the data address carried by the data access instruction is not the data address of the area 140B, the sub-controller 220B can discard the data access instruction.

[0107] Method 4: Fig. 8AAs shown, the media controller 210 includes an I / O module 230 and a plurality of sub-controllers 220. The I / O module 230 is used to communicate with an external device, receive a data access response initiated by an external device, or feed back an access response to an external device. The embodiment of the present application does not limit the number of the I / O modules 230.

[0108] The I / O module 230 and the multiple sub-controllers 220 are connected in series to form a ring, and the connection lines between the I / O module 230 and the multiple sub-controllers 220 form a ring line. The I / O module 230 can broadcast the data access instruction sent from the external device to the sub-controllers 220 on the ring line through the ring line. Any sub-controller 220 on the ring line monitors the data access instruction broadcasted on the ring line. If the data address carried by the data access instruction is the data address of the corresponding area 140, the data access instruction is processed. After processing the data access instruction, the sub-controller 220 can also broadcast an access response broadcast through the ring line. The I / O module 230 obtains the access response by monitoring the information transmitted in the ring line.

[0109] Each controller stores the data address information of the corresponding area 140. The data address information records the data address in the area 140. For any sub-controller 220, when the sub-controller 220 monitors the information transmitted in the ring line, after monitoring the data access instruction, it can first detect the data address information of the corresponding area 140 according to the data address carried by the data access instruction, and determine whether the data address carried by the data access instruction is a data address in the area 140. If the data address carried by the data access instruction is a data address in the area 140, continue to process the data access instruction; if the data address carried by the data access instruction is not a data address in the area 140, the sub-controller 220 can discard it.

[0110] In this connection mode, since the ring line connects all sub-controllers 220, the method of broadcasting the data access instruction can ensure that all sub-controllers 220 on the ring line can receive the data access instruction. In other words, the data access instruction can always be monitored by the sub-controller 220 that can process the data access instruction.

[0111] like Figure 8B , which is a schematic diagram of a connection topology between multiple sub-controllers 220 provided in an embodiment of the present application. Figure 8BIn the embodiment, the media controller 210 includes two I / O modules 230 and six sub-controllers 220. For convenience of description, the I / O modules 230 are respectively I / O modules 230A and I / O modules 230B. The six sub-controllers 220 are respectively sub-controllers 220A, sub-controllers 220B, sub-controllers 220C, sub-controllers 220D, sub-controllers 220E, and sub-controllers 220F. The regions 140 corresponding to the sub-controllers 220A, sub-controllers 220B, sub-controllers 220C, sub-controllers 220D, sub-controllers 220E, and sub-controllers 220F are respectively referred to as regions 140A, regions 140B, regions 140C, regions 140D, regions 140E, and regions 140F.

[0112] I / O module 230A, I / O module 230B, sub-controller 220A, sub-controller 220B, sub-controller 220C, sub-controller 220D, sub-controller 220E, and sub-controller 220F are connected via a ring line. I / O module 230A, I / O module 230B and external devices may be connected via a system bus.

[0113] Taking the I / O module 230A as an example, when the I / O module 230A receives a data access instruction sent by an external processor, the I / O module 230A broadcasts the data access instruction through the ring line.

[0114] Taking sub-controller A as an example, when sub-controller 220A receives a data access instruction sent by an external processor, sub-controller 220A first detects the data address information of area 140A according to the data address carried by the data access instruction, and determines whether the data address carried by the data access instruction is a data address in area 140A. If the data address carried by the data access instruction is the data address of area 140A, the data access instruction is processed continuously, and after processing, an access response is broadcast through the ring line, and I / O module 230A monitors the information in the ring line, and after obtaining the access response, the access response is transmitted to the external processor; if the data address carried by the data access instruction is not the data address of area 140A, sub-controller 220A discards the data access instruction.

[0115] Method 5: Fig. 9A As shown, the media controller 210 includes an I / O scheduling module 240 and a plurality of sub-controllers 220. The I / O scheduling module 240 is used to communicate with an external device, receive a data access response initiated by an external device, or feed back an access response to an external device.

[0116] The I / O scheduling module 240 is connected to the multiple sub-controllers 220 respectively. The I / O scheduling module 240 stores the data address information of each area 140 in the storage medium 110, and the data address information of each area 140 records the data address in the area 140. The I / O scheduling module 240 determines the sub-controller 220 that can process the data access instruction according to the data address carried by the data access instruction sent by the external device and the data address information of each area 140. The data address carried by the data access instruction is the data address of the area 140 corresponding to the sub-controller 220. After receiving the data access instruction, the sub-controller 220 can feed back an access response to the I / O scheduling module 240, and the I / O scheduling module 240 can feed back the access response to the external device that initiated the data access instruction.

[0117] In this connection mode, the I / O scheduling module 240 can obtain the data address information of each area 140, complete the scheduling of data access instructions, and feed back the received data access instructions to the sub-controller 220 that can process the data access instructions.

[0118] like Fig. 9B , which is a schematic diagram of a connection topology between multiple sub-controllers 220 provided in an embodiment of the present application. Fig. 9B In the embodiment, the media controller 210 includes two I / O scheduling modules 240 and six sub-controllers 220. For the convenience of explanation, the I / O scheduling modules 240 are respectively an I / O scheduling module 240A and an I / O scheduling module 240B. The six sub-controllers 220 are respectively referred to as sub-controller 220A, sub-controller 220B, sub-controller 220C, and sub-controller 220D. The regions 140 corresponding to the sub-controllers 220A, 220B, 220C, and 220D are respectively referred to as regions 140A, 140B, 140C, and 140D. The I / O scheduling modules 240A and 240B are respectively connected to different processors outside the memory 10.

[0119] The I / O scheduling module 240A is connected to the sub-controller 220A, the sub-controller 220B, the sub-controller 220C, and the sub-controller 220D respectively. The I / O scheduling module 240B is connected to the sub-controller 220A, the sub-controller 220B, the sub-controller 220C, and the sub-controller 220D respectively.

[0120] Taking the I / O scheduling module 240A and the sub-controller 220A as an example, when the I / O scheduling module 240A receives a data access instruction sent by an external processor, the I / O scheduling module 240A determines that the data address carried by the data access instruction is the data address of the area 140A based on the data address carried by the data access instruction and the data address information of each area 140, indicating that the sub-controller 220 that can process the data access instruction is the sub-controller 220A. The I / O scheduling module 240A sends the data access instruction to the sub-controller 220A. After receiving the data access instruction, the sub-controller 220A processes the data access instruction. After processing the data access instruction, the sub-controller 220A feeds back an access response to the I / O scheduling module 240A. The I / O scheduling module 240A feeds back the access response to the external processor.

[0121] The above description of the memory 10 focuses on the processing of data access instructions by the media controller 210 and the access to the storage medium 110. In the embodiment of the present application, the memory 10 may also have other functions. For example, the memory 10 may have a chip-level test function. That is, the memory 10 can perform functional tests on the entire storage medium wafer 100, and the content of the functional test includes but is not limited to: read and write tests, delay tests, life tests, and temperature tests.

[0122] The read and write test refers to testing whether the memory 10 can read and write normally. The delay test refers to testing whether the time consumed by the memory 10 in the read and write process is within the preset delay range. The life test indicates whether the BANK130 in the test memory 10 can reach the preset maximum number of read and write times; usually some BANK130s specifically used for life testing are reserved in the memory 10. These BANK130s used for life testing will fail after the life test because the maximum number of read and write times has been reached. The life test only detects some BANK130 in the memory 10, and does not check all BANK130 in the storage medium 110. The temperature test refers to testing whether the memory 10 can read and write normally at room temperature or within the preset operating temperature of the memory 10.

[0123] The memory 10 can perform functional testing and record the BANK 130 that failed the test and the die 120 to which the BANK 130 that failed the test belongs. The memory 10 can inform the external part of the memory 10, such as the processor, of the recorded BANK 130 that failed the FT and the die 120 to which the BANK 130 that failed the FT belongs.

[0124] Specifically, inside the memory 10, Fig.10As shown, the memory 10 also includes a test module 300, which is used to implement FT. The present application does not limit the type of the test module 300, and the test module 300 can be a processor core, which can load software to complete the functional test. The test module 300 can also be an ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. All modules that can implement FT are applicable to the embodiments of the present application.

[0125] Externally, the test module 300 can directly communicate with an external device, receive an instruction from an external device to instruct to perform a test, or notify an external device to transmit the BANK130 that failed the test and the die 120 to which the BANK130 that failed the test belongs. For example, the test device may have an independent interface facing the external device, and the test module 300 communicates with the external device through the interface. The test module 300 can also transmit information to the external device through the media controller 210. For example, the test module 300 is connected to the media controller 210, and the external device can instruct the media controller 210 to perform a functional test, and the media controller 210 can send an instruction to the test module 300 to instruct to perform a test. After receiving the instruction, the test module 300 completes the functional test, sends the BANK130 that failed the test and the die 120 to which the BANK130 that failed the test belongs to the media controller 210, and the media controller 210 notifies the external device of the BANK130 that failed the test and the die 120 to which the BANK130 that failed the test belongs.

[0126] The embodiment of the present application does not limit the deployment position and number of the test module 300. For example, the test module 300 can be deployed on the wafer 100 provided with the storage medium, or can be deployed on the wafer 200 provided with the media controller 210.

[0127] For another example, the memory 10 may include a plurality of test modules 300, each test module 300 corresponds to an area 140 in the storage medium wafer 100, and the test module 300 is used to implement a functional test for the corresponding area 140. For another example, the memory 10 may include a test module 300, and the test module 300 is used to implement a functional test for the storage medium 110.

[0128] In the above description, the test module 300 for performing functional testing is deployed separately in the memory 10 as an example. In actual applications, the test module 300 may not be deployed in the memory 10, and the test function is implemented by the medium controller 210, that is, the medium controller 210 can perform functional testing on the storage medium wafer 100. The way in which the medium controller 210 performs functional testing on the storage medium wafer 100 is similar to the way in which the test module 300 performs functional testing on the storage medium wafer 100. For details, please refer to the above description, which will not be repeated here.

[0129] like Fig.11 As shown, a computing device provided in an embodiment of the present application includes a memory 10 and a processor 20. The present application does not limit the number of processors 20. Each processor 20 can be connected to one or more sub-controllers 220 of the media controller 210 in the memory 10 through a system bus. The system bus can be a line based on the peripheral component interconnect express (PCIe), or a bus of a compute express link (CXL), a unified bus (Ubus or UB) or a cache coherent interconnect for accelerators (CCIX) protocol or other protocols. The system bus can be divided into an address bus, a data bus, a control bus, etc.

[0130] The processor 20 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or a programmable logic device (PLD). The above PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a system on chip (SoC) or any combination thereof.

[0131] Taking one of the processors 20 as an example, if there is no connection between the multiple sub-controllers 220 of the media controller 210 in the memory 10, the processor 20 can only access the data in the area 140 corresponding to the sub-controller 220 connected to the memory 10, that is, the processor 20 can only write data to the area 140 through the sub-controller 220, or read data from the area 140 through the sub-controller 220.

[0132] If multiple sub-controllers 220 of the media controller 210 in the memory 10 are connected, the processor 20 can access the data in each area 140 of the storage medium 110 in the memory 10, that is, the processor 20 can write data to any area 140 of the storage medium 110 through the connected sub-controller 220, or read data from any area 140 of the storage medium 110 through the connected sub-controller 220. The connection and interaction between the sub-controllers 220 in the memory 10 can be described above and will not be repeated here.

[0133] When the memory 10 is provided with an I / O module 230 or an I / O scheduling module 240, the processor 20 may be connected to the I / O module 230 or the I / O scheduling module 240 in the memory 10 via a system bus. The processor 20 can access data in each area 140 of the storage medium 110 in the memory 10. Specifically, the connection and interaction between the sub-controller 220, the I / O module 230 or the I / O scheduling module 240 in the memory 10 can be described above and will not be repeated here.

[0134] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A memory, characterized in that: The memory comprises a first wafer and a second wafer which are stacked; The first wafer is a storage medium wafer, the first wafer includes a plurality of crystal grains, and each crystal grain includes a plurality of BANKs; The second wafer is provided with a media controller, and the media controller is connected to each BANK on the storage medium wafer; The storage medium wafer is used to store data; The media controller is used to receive a data access instruction and access the BANK on the storage medium wafer according to the data access instruction.

2. The memory according to claim 1, wherein: The first wafer includes a plurality of regions, the media controller includes a plurality of sub-controllers, each sub-controller corresponds to one of the regions, and the sub-controller is connected to each BANK in the corresponding region; The sub-controller is used to receive the data access instruction and access the BANK in the corresponding area according to the data access instruction.

3. The memory according to claim 2, wherein: The multiple sub-controllers communicate with each other via an on-chip network NoC.

4. The memory according to claim 1 or 2, characterized in that: The multiple sub-controllers are connected to each other, and any of the sub-controllers is further used to transmit the data access instruction that cannot be processed by the sub-controller to a sub-controller connected to the sub-controller.

5. The memory according to claim 1 or 2, characterized in that: The sub-controller is connected to an adjacent sub-controller, and the sub-controller is further used to transmit the data access instruction that cannot be processed by the sub-controller to the adjacent sub-controller.

6. The memory according to claim 1 or 2, characterized in that: The multiple sub-controllers are connected in series to form a ring-shaped line, and the sub-controller is further used to broadcast data access instructions that the sub-controller cannot process through the ring-shaped line.

7. The memory according to claim 1 or 2, characterized in that: The media controller further comprises an input / output I / O module, the I / O module and the plurality of sub-controllers are connected in series to form a ring-shaped circuit, and the I / O module is connected to a device outside the memory via a system bus; The I / O module is used to: receive the data access instruction, and broadcast the data access instruction to the receiver through the ring-shaped line; The sub-controller is further used to monitor the ring line and obtain the data access instruction.

8. The memory according to any one of claims 1 to 7, characterized in that: The sub-controller stores data address information of the corresponding area, and the data address information is used to record the data address of the corresponding area; the data address carried by the data access instruction that cannot be processed by the sub-controller is not the data address recorded by the data address information.

9. The memory according to any one of claims 1 to 8, characterized in that: The memory also includes a test module, which is used to perform functional tests on the storage medium wafer and record the BANKs and the grains to which the BANKs belong that have not passed the test in the storage medium wafer. The functional tests include some or all of the following: read and write tests, delay tests, life tests, and temperature tests.

10. The memory according to any one of claims 1 to 9, characterized in that: The media controller is also used to perform functional tests on the storage medium wafer and record the BANKs and the grains to which the BANKs belong that have not passed the test in the storage medium wafer. The functional tests include some or all of the following: read and write tests, delay tests, life tests, and temperature tests.

11. A computing device, characterized in that: The computing device comprises a processor and a memory as claimed in any one of claims 1 to 11, wherein the processor is connected to a media controller in the memory; The processor is used to send the data access instruction to the memory.

12. The computing device of claim 11, wherein: The processor is connected to one or more sub-controllers in the media controller.

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