Data stream cutting device and method for physical layer

Abstract

The invention relates to a data stream cutting device of a physical layer. The data stream cutting device comprises a data register and a boundary detector, the boundary detector has the capability of detecting a boundary lock mode and a special symbol, and is used for detecting the content of the data register, and when the data register contains the boundary lock mode or the special symbol, the boundary detector detects the boundary lock mode or the special symbol. And outputting the initial address of the boundary locking mode or the special symbol detected in the data register to the offset register to update the value stored in the offset register, so that the stream divider performs data segment cutting in the data register according to the new value stored in the offset register. And the physical layer reduces the time required for correcting data cutting errors when the boundary locking mode of the host end is reduced by adding a tracking special symbol.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the invention name “Physical layer data stream cutting device and method”, the application date of April 8, 2020, and the application number of 2020102679686. Background Art

[0003] Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address to access the NOR flash memory on the address pin and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processing unit needs to write serial byte values ​​to the NAND flash memory to define the type of request command (such as read, write, erase, etc.) and the address used in this command. The address can point to a page (the smallest data block for write operations in flash memory) or a block (the smallest data block for erase operations in flash memory).

[0004] To meet the needs of high-speed communication, the physical layer of the flash memory storage device may include a serializer / deserializer (SerDes). SerDes is a pair of functional circuits used to make up for the shortcomings of limited input / output. It provides data transmission on a single wire or differential pair, so that the input and output pins and the wiring between them can be minimized. In detail, the transmitting end converts the low-speed parallel signal into a high-speed serial signal and transmits it to the receiving end through a single wire or differential pair. However, in the SerDes environment, due to frequency difference or environmental factors, the phase-locked loop (PLL) is unlocked (Lose Lock), resulting in the insertion of unnecessary bits in the original data, or the loss of some bits in the original data. Therefore, the present invention proposes a data stream cutting device and method to solve the above-mentioned problems. Summary of the invention

[0005] In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

[0006] The present invention relates to an embodiment of a data stream cutting device of a physical layer, which is installed in the physical layer and comprises: a data register and a boundary detector. The boundary detector has the ability to detect a boundary locking mode and a special symbol, and is used to detect the content of the data register, and when the data register contains a boundary locking mode or a special symbol, outputs the starting address of the boundary locking mode or the special symbol detected in the data register to an offset register to update the value stored in the offset register, so that a stream splitter cuts data segments in the data register according to the new value stored in the offset register.

[0007] The present invention further relates to an embodiment of a data stream cutting method, which is executed by a physical layer and includes: comparing each combination of n consecutive bits of data in a data register with a boundary locking pattern; comparing each combination of n consecutive bits of data in a data register with a special symbol; and when any combination of n consecutive bits of data in a data register matches the boundary locking pattern or the special symbol, changing to cutting the contents in the data register according to the boundary locking pattern or the starting address of the special symbol in the data register, so as to generate one or more fragments.

[0008] The present invention further relates to an embodiment of a data stream cutting method, which is executed by a physical layer and includes: when the decoding of the previously cut data is successful, comparing each combination of n consecutive bits of data in the data register with a boundary locking pattern; when the decoding of the previously cut data fails, comparing each combination of n consecutive bits of data in the data register with a special symbol; and when any combination of n consecutive bits of data in the data register matches the boundary locking pattern or the special symbol, changing to cutting the content in the data register according to the starting address of the boundary locking pattern or the special symbol in the data register, so as to generate one or more fragments.

[0009] One of the advantages of the above embodiment is that by adding a tracking special symbol in the physical layer, the time required to correct data segmentation errors when the host reduces the boundary locking mode is reduced.

[0010] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0012] Figure 1 FIG. 4 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

[0013] Figure 2 A schematic diagram of the connection between the flash memory interface and the storage unit.

[0014] Figure 3 The (A) portion is a schematic diagram of the original data flow.

[0015] Figure 3 (B) and (C) are partial schematic diagrams of the disturbed data flow.

[0016] Figure 4 This is the timing diagram for writing user data to the host.

[0017] Figure 5 Parts (A) and (B) are schematic diagrams of data segment cutting according to an embodiment of the present invention.

[0018] Figures 6 to 9 FIG. 4 is a block diagram of a boundary detector according to an embodiment of the present invention.

[0019] Figure 10 to Figure 11 The figure is a flow chart of a method for data stream cutting according to an embodiment of the present invention.

[0020] Explanation of symbols:

[0021] 110 Main device

[0022] 130 Controller

[0023] 131 processing units

[0024] 133 Media Access Control Layer

[0025] 135 Static Random Access Memory

[0026] 138NAND Flash Memory Controller

[0027] 139 Storage Interface

[0028] 150 Storage Devices

[0029] 151 Flash memory interface

[0030] 153#0~153#15NAND flash memory module

[0031] 170 Physical Layer

[0032] 171 Host Interface

[0033] 173 data register

[0034] 174 Boundary Detector

[0035] 175 stream splitter

[0036] 176 offset register

[0037] 177 decoder

[0038] 179 parallel interface

[0039] 310, 330, 350, 510, 530 data

[0040] 330p, 350q data bits

[0041] 410UFS burst header

[0042] 420 Host Command

[0043] 430 Confirmation Information

[0044] 450 filling yuan

[0045] 460 user data

[0046] Fn-1, Fn, Fn+1, Fn+2, Fn+3 data clips

[0047] 610-0~610-10、620-0~620-10、710-0~710-130、720-0~720-130、810-0~810-10、910-0~910-130 Comparator

[0048] 630-0~630-10、730-0~730-130、830-0~830-10、830-0~830-130 output circuit

[0049] 850, 950 multiplexer

[0050] S1010~S1070、S1110~S1170 Method Steps DETAILED DESCRIPTION

[0051] The embodiments of the present invention will be described below in conjunction with the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0052] It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and / or components, but do not exclude the addition of more technical features, values, method steps, operations, elements, components, or any combination of the above.

[0053] The words "first", "second", "third", etc. used in the present invention are used to modify the components in the claims, and are not used to indicate a priority order, a prior relationship, or that one component precedes another, or a time sequence when executing method steps. They are only used to distinguish components with the same name.

[0054] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and there may be intervening components. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components can also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.

[0055] refer to Figure 1 The electronic device includes a host side 110, a controller 130 and a storage device 150, and the controller 130 and the storage device 150 may be collectively referred to as a device side. The electronic device may be an electronic product such as a personal computer, a laptop computer, a tablet computer, a mobile phone, a digital camera, a digital video camera, etc. The interface of the host side 110 (not shown) Figure 1) and the host interface (Host Interface) 171 of the controller 130 can communicate with each other using communication protocols such as Universal Flash Storage (UFS), Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), and Peripheral Component Interconnect Express (PCI-E). The storage interface (StorageInterface) 139 of the controller 130 and the flash memory interface of the storage device 150 can communicate with each other using a double data rate (DDR) communication protocol, such as Open NAND Flash Interface (ONFI), Double Data Rate Switch (DDR Toggle) or other interface communication protocols. The controller 130 includes a processing unit 131 for receiving host commands, such as read, write, erase commands, etc., from the host end 110 through a physical layer (PHY) 170 and a media access control layer (MAC) 133. The processing unit 131 can be implemented in a variety of ways, such as using general hardware (e.g., a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and provides specified functions when executing software and / or firmware instructions. The controller 130 also includes a static random access memory (SRAM) 135 for configuring space as a data buffer to store user data to be written to the storage device 150 by the host write command, user data to be read from the storage device 150 by the host read command, and data required during the execution process, such as variables, data tables, host-to-flash (H2F Table), flash-to-host (F2H Table), etc. The controller 130 further includes a NAND Flash Controller (NFC) 138, which provides functions required in the process of accessing the storage device 150, such as a command serializer (Command Sequencer), a low density parity check (LDPC), etc.The processing unit 131 instructs the storage device 150 to perform operations such as data reading, writing, and erasing through the NFC 138 and the storage interface 139 according to the host command.

[0056] The storage device 150 includes a storage unit 153, which provides a large amount of storage space, usually hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing a large amount of user data, such as high-resolution pictures, movies, etc. The storage unit 153 includes a control circuit and a memory array. The storage cells in the memory array may include single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof. The processing unit 131 writes user data to a specified address (destination address) in the storage device 150 (specifically, the storage unit 153) through the storage interface 139, and reads user data from a specified address (source address) in the storage device 150. The storage interface 139 uses multiple electronic signals to coordinate the data and command transmission between the controller 130 and the storage device 150, including data lines, clock signals, and control signals. The data lines can be used to transmit commands, addresses, read and write data; the control signal lines can be used to transmit control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), and write enable (WE).

[0057] refer to Figure 2The flash memory interface 151 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel connecting four NAND flash memory modules, for example, channel CH#0 connects NAND flash memory modules 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory module may be packaged as an independent chip (die). The NAND flash memory controller 138 may send one of the start signals CE#0 to CE#3 through the back-end interface 139 and the flash memory interface 151 to start the NAND flash memory modules 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15, and then read user data from the started NAND flash memory modules in parallel, or write user data to the started NAND flash memory modules.

[0058] The physical layer 170 of the controller 130 can be set to an 8b / 10b, 64b / 66b or 128b / 130b serializer / deserializer (SerDes) environment. However, frequency difference or environmental factors can cause the phase-locked loop (PLL) to lose lock, causing unnecessary bits to be inserted into the original data transmitted by the host end 110, or part of the bits in the original data transmitted by the host end 110 to be lost. When the controller 130 is mounted on a mobile phone, the environmental interference is more serious. For example, the surge generated by the user operating the touch screen affects the simulation circuit (also called the analog physical layer A-PHY) in the physical layer 170, causing the phase-locked loop to lose lock more frequently. The analog physical layer includes a serializer, which is used to map each data segment into a code represented by more bits before serializing the data, such as mapping an 8, 64 or 128-bit segment into a 10, 66 or 130-bit code. For example, refer to Figure 3 In the part (A) of FIG. 1 , the host end 110 transmits data 310 to the physical layer 170 in the controller 130 through the host interface 171, including the data stream "b01100001101010000011". However, due to the unlocking of the phase-locked loop, the physical layer 170 receives the data 310. Figure 3 The error data 330 shown in the part (B) or as Figure 3 Incorrect data 350 is partially shown in (C). Figure 3 The local data stream 330 in (B) contains the bit "b11" 330p which is not present in the original data 310, and Figure 3In (C), the original bit "b00" 350q in the original data 310 is lost in the local data stream 350. Since the original data stream is composed of a series of segments of fixed size (e.g., 10, 66, 130 bits, or other number of bits), the erroneously inserted or lost bits will cause errors in subsequent data segmentation. For example, Figure 3 The original data stream 310 shown in the partial image (A) should be cut into two 10-bit segments "b0110000110" and "b1010000011". However, Figure 3 However, the local data stream 330 in (B) is cut into two erroneous 10-bit segments "b0110011001" and "b1010100000". Figure 3 The data stream 350 in the middle (C) part is cut into two erroneous 10-bit segments "b0110011010" and "b10000011xx".

[0059] In order to solve the segmentation error caused by the unlocking of the phase-locked loop as described above, in some embodiments of the 8b / 10b SerDes environment, the host end 110 may periodically transmit a boundary-lock pattern, such as the Head of Burst HOB (also known as MK0 or K.28.5 symbol) of UFS, so that the physical layer 170 can re-determine the boundary (Boundary) of each segment and perform segmentation accordingly by tracking the boundary-lock pattern of the information string transmitted by the host interface 171. In some embodiments of the 128b / 130b SerDes environment, the host end 110 may periodically transmit a boundary-lock pattern, such as the Comma Character (also known as K28.5 symbol) of PCI-E, so that the physical layer 170 can determine and segment the segment boundary. However, in order to obtain a better transmission rate, the host end 110 may reduce the number of boundary-lock pattern transmissions, which further prolongs the time it takes for the physical layer 170 to correct the data segmentation error.

[0060] To improve the shortcomings of the above-mentioned implementation, in an 8b / 10b SerDes environment, an embodiment of the present invention proposes a physical layer circuit that not only tracks the boundary locking mode in the information string transmitted from the host interface 171 during the effective packet transmission period, but also tracks special symbols in the information string transmitted from the host interface 171 during the idle period (Idle), such as the filler element (FILLER, also known as K.28.1 symbol) of UFS. Figure 4, taking the host end 110 writing user data as an example. Under normal circumstances, the host end 110 sends the SOB 410 and then sends the host write command CMD 420, so that the controller 130 can correctly cut the data stream. Then, after receiving the confirmation information (Acknowledgement ACK) 430 sent by the controller 130, the host end 110 starts to transmit the user data DAT 460. Before starting to transmit the user data, the host end 110 sends the SOB 410, so that the controller 130 can correctly cut the data stream. The host write command CMD 420 and the user data 460 can be called valid packets. Personnel in the relevant technical field understand that valid packets also include host management commands, other host input and output commands, parameters and other information that can be used by the communication protocol layer (Protocol Layer). The period of transmitting valid packets and associated necessary control symbols (such as boundary locking mode, synchronization mode SYN, etc.) is called the valid packet transmission period. The period from the sending of the host write command CMD 420 to the next SOB 410 is called the idle period t IDLE During the idle period t while waiting for the confirmation 430 from the device end IDLE , the host end 110 can continuously transmit the filler element FIL 450 to the device end. The details of the UFS burst header and filler element can be referred to Table 1:

[0061] Table 1

[0062]

[0063] In a 128b / 130b SerDes environment, the physical layer circuit not only tracks the boundary lock mode during data transmission, but also tracks a special symbol, such as the PCI-E Fast Training Sequence FTS (also known as the K28.1 symbol). The details of the PCI-E comma symbol and the Fast Training Sequence can be found in Table 2:

[0064] Table 2

[0065] coding symbol name describe K28.1 FTS Fast training serial In the ordered data set, leave L0s to L0 K28.5 COM comma For plane and link initialization and management

[0066] Those skilled in the art understand that FTS is inserted before valid data. By tracking more symbols, the physical layer 170 can correct data segmentation errors as early as possible when the host end 110 extends the period of transmitting the synchronization pattern.

[0067] refer to Figure 1The physical layer 170 includes the host interface 171 as described above, which is used to receive host commands, parameters, user data, etc. from the host end 110. Taking the 8b / 10b SerDes environment as an example, the host commands, parameters and user data transmitted by the host end 110 are encoded in units of 10 bits. The physical layer 170 also includes a data register 173, a boundary detector 174, a stream splitter 175, an offset register (Offset Register) 176 and a decoder 177. The data register 173 can store 20 bits of data received through the host interface 171. The offset register 176 records the boundary (Boundary, also known as the starting address of the cutting) of the data segment. The stream splitter (Stream Splitter) 175 cuts the data bits in the data register 173 into one or more segments according to the value of the offset register 176, and outputs them to the decoder 177. Figure 5 A and 5B respectively show the data segment segmentation when the offset register 173 records 0 and 2 according to the embodiment of the present invention. The data register 173 stores 20 bits of data 510 at time point t1, and then stores the next 20 bits of data 530 at time point t2.

[0068] refer to Figure 5 In the (A) part, for example, when the offset register 176 records 0, the stream splitter 175 may treat the 0th to 9th bits in the data 510 as the segment Fn, treat the 10th to 19th bits in the data 510 as the segment Fn+1 at the time point t1, and output the data of the two segments to the decoder 177. The stream splitter 175 may treat the 0th to 9th bits in the data 530 as the segment Fn+2, treat the 10th to 19th bits in the data 530 as the segment Fn+3 at the time point t2, and output the data of the two segments to the decoder 177.

[0069] refer to Figure 5 In the (B) part, for example, when the offset register records 2, the stream splitter 175 may treat the 2nd to 11th bits in the data 510 as a segment Fn at time point t1, and output the data of this segment to the decoder 177. In addition, the 12th to 19th bits in the data 510 are reserved for later use. At time point t2, the stream splitter 175 may combine the reserved data bits with the 0th to 1st bits in the data 530 as a segment Fn+1, treat the 2nd to 11th bits in the data 530 as a segment Fn+2, and output the data of the two segments to the decoder 177. In addition, the 12th to 19th bits in the data 530 are reserved for later use.

[0070] In response to different SerDes environment settings, decoder 177 can be an 8b / 10b converter, a 64b / 66b converter, or a 128b / 130b converter. Decoder 177 includes a mapping table for converting input data bits into codes represented by fewer bits, such as mapping input 10, 66, or 130-bit data into 8, 64, or 128-bit codes. When any input data bit cannot be converted into any code according to the mapping table, decoder 177 determines that the input data bit is wrong and can output a decoding error signal to boundary detector 174. Conversely, when the transcoding is successful, decoder 177 outputs a decoding success signal to boundary detector 174. For example, in an 8b / 10b SerDes environment, 10 bits can represent 2 10 = 1024 states, the mapping table contains only 2 8 = 256 mapping relationships. Therefore, when the decoder 177 cannot convert the input data bits into any code, it means that the original data has been changed during the transmission process.

[0071] refer to Figure 1 , the boundary detector 174 has the ability to detect the boundary lock mode (such as the burst header of UFS or the comma symbol of PCI-E) and the default special symbol (such as the filler of UFS or the FTS of PCI-E) in the data register 173. It should be noted that this default special symbol is not originally used in the specification to determine the boundary of each segment in the data stream, but has other uses. The boundary detector 174 continuously detects the content of the data register 173, and when the data register 173 contains the boundary lock mode or the default special symbol, it outputs the starting address of the detected boundary lock mode or the default special symbol in the data register 173 to the offset register 176, which is used to update the value of the offset register 176 to the detected starting address. Afterwards, the stream splitter 175 cuts the data segments in the data register 173 according to the new value stored in the offset register 176.

[0072] refer to Figure 6In some embodiments of the 8b / 10b SerDes environment, for the UFS burst header (K.28.5), the boundary detector 174 includes 11 output circuits 630-0 to 630-10, coupled to the offset register 176, and output 0 to 10 to the offset register 176 when driven. The boundary detector 174 includes 11 comparators 610-0 to 610-10, which are used to detect all possible combinations of consecutive 10 bits of data in the data register 173. For example, the comparator 610-0 detects the data D[9:0] of the 0th to 9th bits in the data register 173, the comparator 610-1 detects the data D[10:1] of the 1st to 10th bits in the data register 173, and so on. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit corresponds to the starting address of the consecutive 10 bits of data input to the comparator in the data register 173. For example, comparator 610-0 is coupled to output circuit 630-0 capable of outputting 0, comparator 610-1 is coupled to output circuit 630-1 capable of outputting 1, and so on. Each of comparators 610-0 to 610-10 compares the input continuous 10-bit data and the UFS burst header. When the input 10-bit data matches the UFS burst header, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the UFS burst header in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal. In addition, for the UFS fill element (K.28.1), the boundary detector 174 further includes 11 comparators 620-0 to 620-10 for detecting all possible combinations of continuous 10-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit matches the starting address of the continuous 10-bit data input by the comparator in the data register 173. For example, comparator 620-0 is coupled to output circuit 630-0 capable of outputting 0, comparator 620-1 is coupled to output circuit 630-1 capable of outputting 1, and so on. Each of comparators 620-0 to 620-10 compares the input continuous 10-bit data and the UFS fill element. When the input 10-bit data matches the UFS fill element, the comparator outputs a signal to drive the coupled output circuit to output a specific value (i.e., the starting address of the fill element in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal.

[0073] refer to Figure 7In some embodiments of the 128b / 130b SerDes environment, the data register 173 stores 260 bits of data. For the PCI-E comma symbol (K28.5), the boundary detector 174 includes 131 output circuits 730-0 to 730-130, coupled to the offset register 176, and output 0 to 130 to the offset register 176 when driven. The boundary detector 174 includes 131 comparators 710-0 to 710-130, which are used to detect all possible combinations of consecutive 130 bits of data in the data register 173. For example, the comparator 710-0 detects the data D[129:0] of the 0th to 129th bits in the data register 173, the comparator 710-1 detects the data D[130:1] of the 1st to 130th bits in the data register 173, and so on. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit matches the starting address of the continuous 130-bit data input to the comparator in the data register 173. For example, comparator 710-0 is coupled to output circuit 730-0 capable of outputting 0, comparator 710-1 is coupled to output circuit 730-1 capable of outputting 1, and so on. Each of comparators 710-0 to 710-130 compares the continuous 130-bit data input and the PCI-E comma symbol. When the input 130-bit data matches the PCI-E comma symbol, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the PCI-E comma symbol in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal. In addition, for PCI-E FTS (K28.1), the boundary detector 174 includes 131 comparators 720-0 to 720-130 for detecting all possible combinations of continuous 130-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit matches the starting address of the continuous 130-bit data input to the comparator in the data register 173. For example, the comparator 720-0 is coupled to the output circuit 740-0 capable of outputting 0, the comparator 720-1 is coupled to the output circuit 740-1 capable of outputting 1, and so on. Each of the comparators 720-0 to 720-130 compares the continuous 130-bit data input with the PCI-E FTS. When the input 130-bit data matches the PCI-E FTS, the comparator outputs a signal to drive the coupled output circuit to output a specific value (i.e., the starting address of the PCI-E FTS in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal.

[0074] refer to Figure 8In some embodiments of the 8b / 10b SerDes environment, the boundary detector 174 includes a multiplexer MUX 850, whose two input terminals respectively input the UFS burst header and the UFS filler. The multiplexer 850 outputs the UFS burst header to all comparators 810-0 to 810-10 according to the control signal Ct corresponding to the decoding success signal of the decoder 177, and outputs the UFS filler to all comparators 810-0 to 810-10 according to the control signal Ct' corresponding to the decoding failure signal of the decoder 177. The boundary detector 174 includes 11 output circuits 830-0 to 830-10, whose coupling relationship and functions are similar to Figure 7 Output circuits 730-0 to 730-10 are shown. The boundary detector 174 includes 11 comparators 810-0 to 810-10, which are used to detect all possible combinations of consecutive 10-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit matches the starting address of the consecutive 10-bit data input by the comparator in the data register 173. Each of the comparators 810-0 to 810-10 compares the consecutive 10-bit data input from the data register 173 with the code input from the multiplexer 850. When the two match, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the UFS burst header or UFS fill element in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal. Compared to Figure 6 , Figure 8 The circuit shown reduces the number of comparators by half.

[0075] refer to Fig. 9 In some embodiments of the 128b / 130b SerDes environment, the boundary detector 174 includes a multiplexer 950, whose two input terminals are respectively input with a PCI-E comma symbol and a PCI-E FTS. The multiplexer 950 outputs the PCI-E comma symbol to all comparators 910-0 to 910-10 according to a control signal Ct corresponding to a decoding success signal of the decoder 177, and outputs the PCI-E FTS to all comparators 910-0 to 910-10 according to a control signal Ct' corresponding to a decoding failure signal of the decoder 177. The boundary detector 174 includes 131 output circuits 930-0 to 930-130, whose coupling relationship and functions are similar to Figure 7Output circuits 730-0 to 730-130 are shown. The boundary detector 174 includes 131 comparators 910-0 to 910-130, which are used to detect all possible combinations of continuous 130 bits of data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit matches the starting address of the continuous 130 bits of data input by the comparator in the data register 173. Each of the comparators 910-0 to 910-130 compares the continuous 130 bits of data input from the data register 173 with the code input from the multiplexer 950. When the two match, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the PCI-E comma symbol or PCI-E FTS in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal. Compared to Figure 7 , Fig. 9 The circuit shown reduces the number of comparators by half.

[0076] In some embodiments, reference Fig.10 The data stream segmentation method performed by the physical layer 170 is shown.

[0077] Step S1010 : This method continuously updates the content in the data register 173 to store the data transmitted from the host end 110 .

[0078] Step S1030: After each update of the content in the data register 173, compare each possible combination of the n consecutive bits of data in the data register 137 with the boundary locking pattern.

[0079] Step S1050: After each update of the content in the data register 173, compare each possible combination of the n consecutive bits of data in the data register 137 with the default special symbol.

[0080] Step S1070: When any combination of consecutive n bits of data in the data register 137 matches the boundary locking mode or the default special symbol, the content in the data register 137 is changed to be cut according to the starting address of the boundary locking mode or the default special symbol in the data register 137 to generate one or more fragments.

[0081] In other embodiments, reference Fig.11 The data stream segmentation method performed by the physical layer 170 is shown.

[0082] Step S1110 : This method continuously updates the content in the data register 173 to store the data transmitted from the host end 110 .

[0083] Step S1130: Each time the content in the data register 173 is updated and the previously cut data is decoded successfully, compare each possible combination of the n consecutive bits of data in the data register 137 with the boundary locking pattern.

[0084] Step S1150: Each time the content in the data register 173 is updated and the decoding of the previously cut data fails, compare each possible combination of the n consecutive bits of data in the data register 137 with the default special symbol.

[0085] Step S1170: When any combination of n consecutive bits of data in the data register 137 matches the boundary locking mode or the default special symbol, the content in the data register 137 is cut according to the starting address of the boundary locking mode or the default special symbol in the data register 137 to generate one or more fragments.

[0086] exist Fig.10 or Fig.11 In some use cases of the method shown, n is 10, the physical layer 170 is set to an 8b / 10bSerDes environment, the boundary locking mode is K.28.5 symbols, and the special symbols are K.28.1 symbols transmitted by the host 110 during idle periods.

[0087] exist Fig.10 or Fig.11 In other use cases of the method shown, n is 130, the physical layer 170 is set to a 128b / 130b SerDes environment, the boundary locking mode is a K28.5 symbol, and the special symbol is a K28.1 symbol transmitted by the host 110 and inserted before the valid data.

[0088] Although the embodiments of the present invention describe 8b / 10b and 128b / 130b SerDes environments as examples, those skilled in the art may also make appropriate modifications to the apparatus and method proposed in the embodiments and apply them to other SerDes environments in data storage, such as 64b / 66b SerDes environments.

[0089] Although Figure 1 to Figure 2 , Figures 6 to 9 The components described above are included, but it does not exclude the use of more additional components without violating the spirit of the invention to achieve better technical effects. Figure 10 to Figure 11The flowchart is executed in a specified order, but without violating the spirit of the invention, a person skilled in the art can modify the order of these steps while achieving the same effect, so the present invention is not limited to the order described above. In addition, a person skilled in the art can also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereto.

[0090] Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the present invention covers obvious modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest way to include all obvious modifications and similar arrangements.

Claims

1. A data stream cutting device, installed in the physical layer, characterized in that: Include: A host interface, coupled to a host end; a data register, coupled to the host interface, for storing data received from the host end through the host interface; as well as a boundary detector coupled to the data register, for detecting the content of the data register, and when the data register contains a special symbol, outputting the starting address of the special symbol detected in the data register to the offset register to update the value stored in the offset register, so that the stream splitter performs data segment cutting in the data register according to the new value stored in the offset register, The special symbol was not originally used to determine the boundary of each segment in the data stream. The boundary detector includes a plurality of comparators for detecting all combinations of a plurality of consecutive bits of data in the data register. The special symbol is a K28.1 symbol or a K.28.1 symbol transmitted by the host end.

2. The data stream cutting device according to claim 1, characterized in that: The physical layer is set to an 8b / 10b serializer / deserializer environment, and the special symbol is a K.28.1 symbol transmitted by the host end during an idle period.

3. The data stream cutting device according to claim 2, characterized in that: The boundary detection circuit comprises: a plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value to the offset register when driven, the specific value being a starting address of a UFS fill element in the data register; and A plurality of comparators are used to detect all combinations of consecutive 10-bit data in the data register, wherein each of the comparators is coupled to a corresponding output circuit, and when it is detected that the consecutive 10-bit data input from the data register matches the K.28.1 symbol, the coupled output circuit is driven.

4. The data stream cutting device as claimed in claim 1, characterized in that: The physical layer is set to a 128b / 130b serializer / deserializer environment, and the special symbol is a K28.1 symbol transmitted from the host end and inserted before valid data.

5. The data stream cutting device according to claim 4, characterized in that: The boundary detection circuit comprises: a plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value to the offset register when driven, the specific value being a starting address of the PCI-E FTS in the data register; and A plurality of comparators are used to detect all combinations of continuous 130 bits of data in the data register, wherein each of the comparators is coupled to a corresponding output circuit, and when it is detected that the continuous 130 bits of data input from the data register match the K28.1 symbol, the coupled output circuit is driven.

6. The data stream cutting device according to claim 1, characterized in that: The physical layer is set up as a serializer / deserializer environment.

7. A data stream cutting method, performed by a physical layer, characterized in that: Include: comparing each combination of n consecutive bits of data in the data register with a special symbol, where n is a positive integer; and When any combination of n consecutive bits of data in the data register matches the special symbol, the content in the data register is cut according to the starting address of the special symbol in the data register to generate one or more fragments, The special symbol was not originally used to determine the boundary of each segment in the data stream. The special symbol is a K28.1 symbol or a K.28.1 symbol transmitted by the host end.

8. The data stream cutting method according to claim 7, characterized in that: n is 10, the physical layer is set to an 8b / 10b serializer / deserializer environment, and the special symbol is a K.28.1 symbol transmitted from the host side during an idle period.

9. The data stream cutting method according to claim 7, characterized in that: n is 130, the physical layer is set to a 128b / 130b serializer / deserializer environment, and the special symbol is a K28.1 symbol transmitted from the host end and inserted before the valid data.

10. A data stream cutting method, performed by a physical layer, characterized in that: Include: When the decoding of the previously cut data fails, comparing each combination of the consecutive n bits of data in the data register with the special symbol; and When any combination of n consecutive bits of data in the data register matches the special symbol, the content in the data register is cut according to the boundary locking mode or the starting address of the special symbol in the data register to generate one or more fragments, The special symbol was not originally used to determine the boundary of each segment in the data stream. The special symbol is a K28.1 symbol or a K.28.1 symbol transmitted by the host end.

11. The data stream cutting method according to claim 10, characterized in that: n is 10, the physical layer is set to an 8b / 10b serializer / deserializer environment, and the special symbol is a K.28.1 symbol transmitted from the host side during an idle period.

12. The data stream cutting method according to claim 10, characterized in that: n is 130, the physical layer is set to a 128b / 130b serializer / deserializer environment, and the special symbol is a K28.1 symbol transmitted from the host end and inserted before the valid data.

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