Processor system-on-chip and method used in processor system-on-chip

Abstract

The invention relates to a processor system-on-chip and a method used therein. A processor system-on-chip includes a storage device including a plurality of storage module groups, each storage module group including a plurality of storage modules, a load balancer configured to: for any one of the storage module groups, load balancer configured to load the storage module groups, and a synchronization bridge configured to synchronize the load balancer with the storage module groups; generating a memory module address signal, a memory module strobe signal, and a memory module read / write enable signal for the memory module group based on the memory address signal, the memory strobe signal, and the memory read / write enable signal from the synchronization bridge, and sending a storage module address signal, a storage module gating signal and a storage module read / write enable signal to each storage module in the storage module group through a write bus port of the storage module group, gating and combining read data of each storage module in the storage module group, and returning the data to the synchronous bridge.

Description

Technical Field

[0001] The present disclosure generally relates to the field of computers, and more particularly to a processor system on chip and a method used therein. Background Art

[0002] A Reduced Instruction Set Computer (RISC) is a processor that executes fewer types of computer instructions. The basic idea of ​​a RISC processor is to reduce the complexity of hardware design by streamlining the machine instruction system while increasing the speed of instruction execution. In a RISC processor, both simple and complex operations are completed by blocks of simple instructions. Summary of the invention

[0003] According to some embodiments of the present disclosure, a processor on-chip system includes a storage device, a load balancer, and a synchronous bridge, wherein the storage device includes multiple storage module groups, each of the multiple storage module groups includes multiple storage modules, and the load balancer is configured to: for any one of the multiple storage module groups, generate a storage module address signal, a storage module select signal, and a storage module read / write enable signal for the storage module group based on the memory address signal, the memory select signal, and the memory read / write enable signal from the synchronous bridge, send the storage module address signal, the storage module select signal, and the storage module read / write enable signal to each storage module in the storage module group via the write bus port of the storage module group, and select and merge the read data of each storage module in the storage module group and return it to the synchronous bridge.

[0004] According to some embodiments of the present disclosure, a method is provided for use in a processor system-on-chip, wherein the processor system-on-chip includes a storage device and a synchronous bridge, the storage device includes a plurality of storage module groups, each of the plurality of storage module groups includes a plurality of storage modules, the method includes: for any one of the plurality of storage module groups, based on the memory address signal, the memory select signal, and the memory read / write enable signal from the synchronous bridge, a storage module address signal, a storage module select signal, and a storage module read / write enable signal for the storage module group are generated, the storage module address signal, the storage module select signal, and the storage module read / write enable signal are sent to each storage module in the storage module group via a write bus port of the storage module group, and the read data of each storage module in the storage module group is selected and merged and then returned to the synchronous bridge. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments of the present disclosure will be illustrated by way of example and not limitation in the accompanying figures in which like reference numerals refer to similar elements.

[0006] Figure 1 FIG. 1 is a schematic diagram showing an example arrangement structure of an SRAM cell in an 8MB static random access memory (SRAM) in a RISC system on chip (SoC).

[0007] Figure 2 is a schematic diagram showing an example connection structure between an 8MB SRAM and an Advanced eXtensible Interface (AXI) bus in a RISC SoC.

[0008] Figure 3 is a schematic diagram showing an example connection structure between four 2MB SRAMs and an AXI bus in a RISC SoC.

[0009] Figure 4 is a schematic diagram showing an example connection structure between an 8MB SRAM and an AXI bus in a RISC SoC according to an embodiment of the present disclosure.

[0010] Figure 5 is a schematic diagram showing an example physical implementation layout of an SRAM module group and control logic units such as a load balancer and a synchronous bridge in a RISC SoC according to an embodiment of the present disclosure.

[0011] Figure 6 is a schematic diagram showing an example connection structure between a load balancer and any one of the SRAM module groups in a RISC SOC according to an embodiment of the present disclosure.

[0012] Figure 7 is a schematic diagram showing an example logic structure of a read logic of an SRAM module in a RISC SOC according to an embodiment of the present disclosure.

[0013] Figure 8 FIG. 4 is a schematic diagram showing example output load balancing data between a load balancer in a RISC SOC and an SRAM module group in an 8MB SRAM according to an embodiment of the present disclosure.

[0014] Fig. 9 FIG. 4 is a schematic diagram showing example input load balancing data between a load balancer in a RISC SOC and an SRAM module group in an 8MB SRAM according to an embodiment of the present disclosure.

[0015] Fig.10 A block diagram of an example computing device is shown in which a processor-on-a-chip system may be used according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] The various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of the present disclosure to other persons skilled in the art. However, it will be apparent to those skilled in the art that many alternative embodiments may be implemented using the parts of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are provided to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments may be implemented without these specific details. In other examples, known features may be omitted or simplified in order to avoid blurring the illustrative embodiments.

[0017] In addition, various operations are described as multiple discrete operations in sequence in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be interpreted as implying that these operations must be order-dependent. In particular, these operations do not need to be performed in the order presented.

[0018] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. These phrases generally do not refer to the same embodiment; however, they may refer to the same embodiment. Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrases "A or B" and "A / B" mean "(A), (B), or (A and B)."

[0019] In a RISC system on chip (SoC), a large-capacity static random access memory (SRAM) is formed by splicing multiple small-capacity SRAMs and connected to the Advanced eXtensible Interface (AXI) bus via a bridge. The RISC processor accesses the large-capacity SRAM via the AXI bus and the bridge.

[0020] Figure 1 Schematic diagram showing an example arrangement structure of SRAM cells in an 8MB SRAM in a RISC SoC. Figure 1 As shown, the 8MB SRAM is formed by splicing 256 8192x32-bit SRAM cells, which are arranged in an 8-column x 32-row matrix and each signal port of the 8MB SRAM is located on one side of the matrix (e.g., the right side), wherein 8 SRAM cells located in the same row are spliced ​​to form an 8192x256-bit SRAM module, and 32 SRAM modules are spliced ​​to form an 8MB SRAM.

[0021] Figure 2is a schematic diagram showing an example connection structure between an 8MB SRAM and an AXI bus in a RISC SoC. Figure 2 As shown, the 8MB SRAM can be connected to the AXI bus via a bridge, wherein the bridge is used to convert the AXI protocol signal into the SRAM interface protocol signal. Figure 1 In the case where the 8MB SRAM is connected to the AXI bus via a bridge, it is difficult for the RISC processor to access the 8MB SRAM at high frequency via the AXI bus and the bridge because the paths from some SRAM cells (for example, the SRAM cells in the upper left corner or the lower left corner) to the signal ports of the 8MB SRAM are too long and the RISC processor has the same timing requirements for all SRAM cells.

[0022] In order to achieve high-frequency access of the RISC processor to the 8MB SRAM, the 8MB SRAM may be divided into multiple SRAM modules (eg, four 2MB SRAM modules (2MB SRAM for short)), each 2MB SRAM being connected to the AXI bus via a dedicated bridge. Figure 3 : is a schematic diagram showing an example connection structure between four 2MB SRAMs and the AXI bus in a RISC SoC. However, the more bridges used between the 8MB SRAM and the AXI bus, the more wiring resources are needed on the RISC SoC. In a RISC SoC, too many wiring resources mean high congestion, which makes it difficult to make the overall frequency of the RISC SoC very high, and the more bridges also mean more chip logic resources (area). If a synchronous bridge is used between each 2MB SRAM and the AXI bus, not only the area is increased, but also the RISC processor may have a low access frequency to the 8MB SRAM. If an asynchronous bridge is used between each 2MB SRAM and the AXI bus, the access delay of the RISC processor to the 8MB SRAM increases by at least three clock beats, and the delay of these additional clock beats will cause the performance of the RISC processor to degrade.

[0023] In view of the above situation, a processor on-chip system according to an embodiment of the present disclosure is proposed, including a storage device, a load balancer, and a synchronous bridge, wherein the storage device includes multiple storage module groups, each storage module group includes multiple storage modules, and the load balancer is configured to: for any storage module group, generate a storage module address signal, a storage module select signal, and a storage module read / write enable signal for the storage module group based on the memory address signal, the memory select signal, and the memory read / write enable signal from the synchronous bridge, send the storage module address signal, the storage module select signal, and the storage module read / write enable signal to each storage module in the storage module group via the write bus port of the storage module group, and select and merge the read data of each storage module in the storage module group and return it to the synchronous bridge.

[0024] Below, a RISC SoC including 8MB SRAM is taken as an example to illustrate the processor system on chip according to the embodiment of the present disclosure. Figure 4 Schematic diagram showing an example connection structure between an 8MB SRAM and an AXI bus in a RISC SoC according to an embodiment of the present disclosure. Figure 4 As shown, in some embodiments, the 8MB SRAM can be connected to the AXI bus via a load balancer and a synchronous bridge, wherein the RISC processor can access the 8MB SRAM via the AXI bus, the synchronous bridge, and the load balancer, and the synchronous bridge can generate a memory address signal, a memory selection signal, and a memory read / write enable signal for the 8MB SRAM based on the read / write address signal from the AXI bus, and / or generate a memory write mask signal and a write data signal for the 8MB SRAM based on the write data signal and the write data byte selection signal from the AXI bus. It should be noted that the load balancer can be located between the 8MB SRAM and the synchronous bridge or inside the synchronous bridge, and the storage device can have a larger or smaller data capacity and can be implemented as other types of static memory.

[0025] Figure 5 1 is a schematic diagram showing an example physical implementation layout of a control logic unit such as an SRAM module group and a load balancer and a synchronous bridge in a RISC SoC according to an embodiment of the present disclosure. Figure 5As shown, in some embodiments, the 8MB SRAM may include 8 1MB SRAM module groups B0 to B7, and these SRAM module groups are arranged in a "well" shape around the load balancer. This layout can minimize the length difference of the path from the output control logic of the load balancer to the write bus port of each SRAM module group and the absolute value of each path is also minimized, and minimize the length difference of the path from the read data of each SRAM module group to the input data logic of the load balancer and the absolute value of each path is also minimized. It should be noted that, depending on the design requirements of the application scenario, the 8MB SRAM may include a greater or lesser number of SRAM module groups, and accordingly, the data capacity of each SRAM module group may be smaller or larger.

[0026] Figure 6 FIG. 2 is a schematic diagram showing an example connection structure between a load balancer and any one of the SRAM module groups in a RISC SOC according to an embodiment of the present disclosure. Figure 6 As shown, in some embodiments, any one of the SRAM module groups B0 to B7 (e.g., SRAM module group B0) may include four 8192x256-bit SRAM modules (e.g., SRAM modules U0 to U3), and the load balancer may be connected to the SRAM modules U0 to U3 in the SRAM module group B0 via a dedicated write bus port of the SRAM module group B0. Similarly, it should be noted that, depending on the design requirements of the application scenario, each SRAM module group may include a greater or lesser number of SRAM modules, and accordingly, the data capacity of each SRAM module may be smaller or larger.

[0027] In some embodiments, for any one of the SRAM module groups B0 to B7 (e.g., SRAM module group B0), the load balancer may replicate the storage module selection signal and the storage module read / write enable signal for the SRAM module group B0 to generate multiple storage module selection signal copies and multiple storage module read / write enable signal copies for each SRAM module in the SRAM module group B0, and send these signal copies to each SRAM module in the SRAM module group B0 via a dedicated write bus port of the SRAM module group B0. For example, in the case where the SRAM module group B0 includes four SRAM modules U0 to U3, the load balancer may generate a storage module address signal shared by the SRAM modules U0 to U3, four storage module selection signals for the SRAM modules U0 to U3 (at most one SRAM module is selected for each clock edge), and four storage module read / write enable signals for the SRAM modules U0 to U3 (at most one SRAM module is read / write enabled for each clock edge). That is, each SRAM module constituting the SRAM module group B0 shares a storage module address signal, but has its own independent storage module selection signal and storage module read / write enable signal. In other words, the number of copies of the storage module selection signal and the number of copies of the storage module read / write enable signal for the SRAM module group B0 can be equal to the number of SRAM modules in the SRAM module group B0. However, for area considerations, for different SRAM module groups B0 to B7, each SRAM module group can have its own, independent storage module address signal, wherein the storage module address signals for different SRAM modules have the same address data value (i.e., the load balancer can generate multiple copies of the memory address signal by copying the memory address signal from the synchronous bridge as the storage module address signals for each SRAM module group in the 8MB SRAM, and the number of the multiple copies of the memory address signal is equal to the number of SRAM module groups in the 8MB SRAM). In addition, it should be noted that, in a write operation, different SRAM module groups B0 to B7 can share a storage module write data signal and a storage module write mask signal, and each SRAM module in each SRAM module group can share a storage module write data signal and a storage module write mask signal. In this way, it is possible to avoid the problem of excessive load and insufficient timing caused by driving multiple SRAM modules with a single-bit signal, and to avoid the problem of increased area caused by copying too many signal copies (for example, storage module address signal copies and storage module write data signal copies).

[0028] Figure 7Schematic diagram showing an example logical structure of the read logic of the SRAM module in the RISC SOC according to an embodiment of the present disclosure. Figure 7 As shown, in some embodiments, any SRAM module (e.g., SRAM module U0) in any SRAM module group (e.g., SRAM module group B0) in SRAM module groups B0 to B7 may include 8 8192x32-bit SRAM cells, a multiplexer, and a trigger. For SRAM module U0, the load balancer generates a data selection signal Q_sel0 for SRAM module U0 based on the storage module selection signal for SRAM module group B0 when the storage module selection signal and the storage module read / write enable signal for SRAM module group B0 indicate that SRAM module U0 is selected and read enabled, so that the multiplexer in SRAM module U0 generates read data Q_d0 of SRAM module U0 based on the data selection signal Q_sel0 and the read data of each SRAM cell indicated by the storage module address signal for SRAM module group B0 in SRAM module U0 (i.e., 256-bit data formed by splicing 8 32-bit read data Q0 to Q7), wherein when the data selection signal Q_sel0 indicates that SRAM module U0 is selected, SRAM module U0 outputs the read data of all SRAM cells therein, otherwise it outputs all-zero data.

[0029] Figure 8 FIG. 2 is a schematic diagram showing an example output load balancing data between a load balancer in a RISC SOC and an SRAM module group in an 8MB SRAM according to an embodiment of the present disclosure. Figure 8 As shown, in some embodiments, the load balancer generates the read data of the 8MB SRAM by performing a logical OR operation on the read data Q_d0 to Q_d31 (not shown in the figure) of the SRAM modules U0 to U31 in the SRAM module groups B0 to B7, and generates a read data valid signal corresponding to the read data of the 8MB SRAM by performing a logical OR operation on the data selection signals Q_sel0 to Q_sel31 (not shown in the figure) for the SRAM modules U0 to U31 in the SRAM module groups B0 to B7.

[0030] Fig. 9 FIG. 2 is a schematic diagram showing example input load balancing data between a load balancer in a RISC SOC and an SRAM module group in an 8MB SRAM according to an embodiment of the present disclosure. Fig. 9As shown, in some embodiments, for any one of the SRAM module groups B0 to B7, in addition to generating a storage module address signal Ram_A, a storage module selection signal ram_ME, and a storage module read / write enable signal ram_WE (not shown in the figure) for the SRAM module group based on the memory address signal, the memory selection signal, and the memory read / write enable signal from the synchronous bridge, the load balancer also generates a storage module write mask signal ram_WM (not shown in the figure) and a storage module write data signal for the SRAM module group based on the memory write mask signal and the write data signal from the synchronous bridge. The storage module write data signal ram_D (not shown in the figure) is sent to each SRAM module in the SRAM module group through the dedicated write bus port of the SRAM module group, including the storage module write mask signal ram_WM and the storage module write data signal ram_D for the SRAM module group, together with the storage module address signal Ram_A, the storage module selection signal ram_ME, and the storage module read / write enable signal ram_WE, so that each SRAM module writes the corresponding bit in the storage module write data signal ram_D to the corresponding position indicated by the storage module address signal Ram_A according to the storage module write mask signal ram_WM.

[0031] It should be understood that in the processor on-chip system according to the embodiment of the present disclosure, the storage device can be a single-port storage device or a dual-port storage device, and a part of the storage module groups in the storage device can be connected to the AXI bus via a load balancer and a synchronization bridge while another part of the storage module groups can be connected to the AXI bus only via a synchronization bridge without a load balancer.

[0032] Fig.10 A block diagram of an example computing device in which a processor-on-chip system according to various embodiments of the present disclosure may be used is shown. Specifically, Fig.10 The computing device 1000 shown includes one or more processors (or processor cores) 1010, one or more memory / storage devices 1020, and one or more communication resources 1030, wherein each of these processors, memory / storage devices, and communication resources can be communicatively coupled via a bus 1040 or other interface circuits. For embodiments utilizing node virtualization (e.g., network function virtualization (NFV)), a hypervisor 1002 can be executed to provide an execution environment for one or more network slices / sub-slices to utilize the hardware resources of the computing device 1000.

[0033] The processor 1010 may include, for example, a processor 1012 and a processor 1014. The processor 1010 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof. The processor-on-chip system according to an embodiment of the present disclosure may be implemented in the processor 1012 and / or the processor 1014.

[0034] The memory / storage device 1020 may include a main memory, a disk storage device, or any suitable combination thereof. The memory / storage device 1020 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0035] The communication resources 1030 may include interconnect or network interface controllers, components, or other suitable devices to communicate with one or more peripheral devices 1004 or one or more databases 1006 or other network elements via the network 1008. For example, the communication resources 1030 may include wired communication components (e.g., for coupling via USB, Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® low energy) components, Wi-Fi® components, and other communication components.

[0036] The instructions 1050 may include software, programs, applications, applets, applications, or other executable code for causing at least any one of the processors 1010 to perform various processing procedures. The instructions 1050 may reside in whole or in part in at least one of the processor 1010 (e.g., in a cache of the processor), the memory / storage device 1020, or any suitable combination thereof. In addition, any portion of the instructions 1050 may be transmitted to the hardware resources 1000 from any combination of the peripheral device 1004 or the database 1006. Therefore, the memory of the processor 1010, the memory / storage device 1020, the peripheral device 1004, and the database 1006 are examples of computer-readable and machine-readable media.

[0037] Although certain embodiments have been illustrated and described herein for purposes of description, the embodiments illustrated and described may be replaced with a variety of alternative and / or equivalent embodiments or implementations that achieve the same purpose without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, the embodiments described herein are expressly limited only by the appended claims and their equivalents.

Claims

1. A processor system on chip, comprising a storage device, a load balancer, and a synchronization bridge, wherein: The storage device includes a plurality of storage module groups, each of the plurality of storage module groups includes a plurality of storage modules, and the load balancer is configured as follows: For any one of the multiple storage module groups, a storage module address signal, a storage module select signal, and a storage module read / write enable signal are generated for the storage module group based on the memory address signal, the memory select signal, and the memory read / write enable signal from the synchronization bridge, the storage module address signal, the storage module select signal, and the storage module read / write enable signal are sent to each storage module in the storage module group via the write bus port of the storage module group, and the read data of each storage module in the storage module group is selected and merged and then returned to the synchronization bridge.

2. The processor system on chip according to claim 1, wherein: The load balancer is further configured to: A plurality of memory address signal copies are generated by duplicating the memory address signal, and one of the plurality of memory address signal copies is used as the storage module address signal, wherein the number of the plurality of memory address signal copies is equal to the number of the plurality of storage module groups.

3. The processor system on chip according to claim 1, wherein: The load balancer is further configured to: A plurality of storage module select signal copies and a plurality of storage module read / write enable signal copies are generated by copying the storage module select signal and the storage module read / write enable signal, and the plurality of storage module select signal copies and the plurality of storage module read / write enable signal copies are respectively sent to each storage module in the storage module group via the write bus port of the storage module group, wherein at each clock edge at most one storage module in the storage module group is selected and read / write enabled.

4. The processor system on chip according to claim 3, wherein: The number of the plurality of memory module strobe signal copies and the number of the plurality of memory module read / write enable signal copies are equal to the number of memory modules in the memory module group.

5. The processor system on chip according to claim 1, wherein: The load balancer is further configured to: For any one storage module in the storage module group, when the storage module selection signal indicates that the storage module is selected and the storage module read / write enable signal indicates that the storage module is read enabled, a data selection signal for the storage module is generated based on the storage module selection signal, so that the storage module generates the read data of the storage module based on the data selection signal and the read data of each storage unit in the storage module indicated by the storage module address signal.

6. The processor system on chip according to claim 5, wherein: The load balancer is further configured to: The read data of the storage device is generated by performing a logical OR operation on the read data of each storage module in the multiple storage module groups, and a read data valid signal corresponding to the read data of the storage device is generated by performing a logical OR operation on the data selection signal for each storage module in the multiple storage module groups.

7. The processor system on chip according to claim 1, wherein: The load balancer is further configured to: A storage module write mask signal and a storage module write data signal are generated for the storage module group based on the memory write mask signal and the write data signal from the synchronous bridge, and the storage module write mask signal and the storage module write data signal are sent to each storage module in the storage module group via the write bus port of the storage module group.

8. The processor system on chip according to claim 1, wherein: The load balancer is located between the storage device and the synchronous bridge or inside the synchronous bridge.

9. The processor system on chip according to claim 1, wherein: The multiple storage module groups are arranged in a "tic-tac-toe" pattern around the load balancer.

10. The processor system on chip according to claim 1, wherein: The processor system on chip is a reduced instruction set computer processor system on chip, and its reduced instruction set computer processor accesses the storage device via an advanced extensible interface bus, the synchronous bridge, and the load balancer.

11. The processor system on chip according to claim 1, wherein: The storage device is a storage device implemented by a static random access memory.

12. A method for use in a processor system on chip, wherein: The processor system-on-chip includes a storage device and a synchronous bridge, the storage device includes a plurality of storage module groups, each of the plurality of storage module groups includes a plurality of storage modules, and the method includes: For any one of the multiple storage module groups, a storage module address signal, a storage module select signal, and a storage module read / write enable signal are generated for the storage module group based on the memory address signal, the memory select signal, and the memory read / write enable signal from the synchronization bridge, the storage module address signal, the storage module select signal, and the storage module read / write enable signal are sent to each storage module in the storage module group via the write bus port of the storage module group, and the read data of each storage module in the storage module group is selected and merged and then returned to the synchronization bridge.

13. The method according to claim 12, further comprising: A plurality of memory address signal copies are generated by duplicating the memory address signal, and one of the plurality of memory address signal copies is used as the storage module address signal, wherein the number of the plurality of memory address signal copies is equal to the number of the plurality of storage module groups.

14. The method according to claim 12, further comprising: A plurality of storage module select signal copies and a plurality of storage module read / write enable signal copies are generated by copying the storage module select signal and the storage module read / write enable signal, and the plurality of storage module select signal copies and the plurality of storage module read / write enable signal copies are respectively sent to each storage module in the storage module group via the write bus port of the storage module group, wherein at each clock edge at most one storage module in the storage module group is selected and read / write enabled.

15. The method according to claim 14, wherein: The number of the plurality of memory module strobe signal copies and the number of the plurality of memory module read / write enable signal copies are equal to the number of memory modules in the memory module group.

16. The method according to claim 12, further comprising: For any one storage module in the storage module group, when the storage module selection signal indicates that the storage module is selected and the storage module read / write enable signal indicates that the storage module is read enabled, a data selection signal for the storage module is generated based on the storage module selection signal, so that the storage module generates the read data of the storage module based on the data selection signal and the read data of each storage unit in the storage module indicated by the storage module address signal.

17. The method according to claim 16, further comprising: The read data of the storage device is generated by performing a logical OR operation on the read data of each storage module in the multiple storage module groups, and a read data valid signal corresponding to the read data of the storage device is generated by performing a logical OR operation on the data selection signal for each storage module in the multiple storage module groups.

18. The method according to claim 12, further comprising: A storage module write mask signal and a storage module write data signal are generated for the storage module group based on the memory write mask signal and the write data signal from the synchronous bridge, and the storage module write mask signal and the storage module write data signal are sent to each storage module in the storage module group via the write bus port of the storage module group.

19. The method according to claim 12, wherein: The method is performed by a load balancer located between the storage device and the synchronization bridge or located inside the synchronization bridge.

20. The method according to claim 19, wherein: The multiple storage module groups are arranged in a "tic-tac-toe" pattern around the load balancer.

21. The method according to claim 19, wherein: The processor system on chip is a reduced instruction set computer processor system on chip, and its reduced instruction set computer processor accesses the storage device via an advanced extensible interface bus, the synchronous bridge, and the load balancer.

22. The method according to claim 12, wherein: The storage device is a storage device implemented by a static random access memory.

23. A computer-readable storage medium having computer-executable instructions stored thereon, wherein: When the computer executable instructions are executed by the load balancer in a processor-on-chip system comprising a storage device, a load balancer, and a synchronization bridge, the load balancer performs the method of any one of claims 12 to 22.

24. A computer program product comprising computer executable instructions, wherein: When the computer executable instructions are executed by the load balancer in a processor-on-chip system comprising a storage device, a load balancer, and a synchronization bridge, the load balancer performs the method of any one of claims 12 to 22.

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