Chip verification method and system

Abstract

The invention provides a chip verification method and system, and the method can obtain a channel-type test case, the channel-type test case is used for verifying the function of a chip design module, the channel-type test case comprises a single-module test case and a cascade test case, the single-module test case is used for verifying a single function point module in a channel, and the cascade test case is used for verifying a single function point module in the channel. The cascade test case is used for verifying the combination of a plurality of function point modules in the path. An enabling identifier of the access type test case is read, the enabling identifier comprises a first identifier and a second identifier, the first identifier is used for representing the enabling function point module, and the second identifier is used for representing the non-enabling function point module. Generating register configuration information based on the access type test case, and running the function point module of which the enabling identifier is the first identifier based on the register configuration information to obtain a running result. According to the method, a channel type test case is developed according to a channel in a chip design module, and single-module function verification and cascade verification are achieved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a chip verification method and system. Background Art

[0002] AI chips refer to chips that have an AI computing core (Neural Processing Unit, NPU) integrated into the chip. The AI ​​computing core is a hardware concept. The AI ​​computing core is the core part of the AI ​​chip, which can accelerate the operation of the neural network model (AI model). The use of the AI ​​computing core can quickly complete the operation of the AI ​​model. The AI ​​model is a software concept. The AI ​​model can perform various complex tasks, such as image recognition, speech recognition, natural language processing, etc.

[0003] AI computing cores include matrix computing cores, vector computing cores, scalar computing cores, etc. Matrix computing cores are used to implement matrix operations, vector computing cores are used to implement vector operations, and scalar computing cores are used to implement scalar operations. Each computing core includes multiple first-level modules, and each first-level module represents a collection of a certain type of computing functions. Each first-level module also includes multiple second-level modules, and each second-level module represents a certain computing function.

[0004] When verifying the above-mentioned first-level modules, you can first perform functional verification on a single second-level module, and then cascade multiple second-level modules to verify the combined functional points. In this way, test cases need to be developed in two stages, which adds extra workload. In addition, when developing cascade test cases, it is necessary to evaluate the combination of multiple modules, which is more complex. Cascade scenario evaluation relies on human judgment, which can easily cause duplication, missing or illegal problems in test cases. If all legal cascade scenarios are not exhaustive, the completeness of the verification will be reduced. Summary of the invention

[0005] The present application provides a chip verification method and system to solve the problem of high complexity of chip verification.

[0006] In a first aspect, the present application provides a chip verification method, the method comprising:

[0007] Obtaining a path type test case, wherein the path type test case is used to verify the function of the chip design module; the path type test case includes a single module test case and a cascade test case, wherein the single module test case is used to verify a single function point module in the path, and the cascade test case is used to verify the combination of multiple function point modules in the path, wherein the path is used to characterize the data processing path of the chip design module;

[0008] Reading an enable flag of the path-type test case, wherein the enable flag is a first flag or a second flag, wherein the first flag is used to characterize an enabled function point module, and the second flag is used to characterize a disabled function point module;

[0009] Generate register configuration information based on the path-type test case, the register configuration information being configuration information required by the register when the function point module identified as the first identifier is enabled to execute the path-type test case;

[0010] The function point module whose enable identifier is the first identifier is run based on the register configuration information to obtain an operation result.

[0011] In a second aspect, the present application provides a chip verification system, including a simulation control component and a chip design module; the simulation control component is configured to:

[0012] Obtaining a path type test case, wherein the path type test case is used to verify the function of the chip design module; the path type test case includes a single module test case and a cascade test case, wherein the single module test case is used to verify a single function point module in the path, and the cascade test case is used to verify the combination of multiple function point modules in the path, wherein the path is used to characterize the data processing path of the chip design module;

[0013] Reading an enable flag of the path-type test case, wherein the enable flag is a first flag or a second flag, wherein the first flag is used to characterize an enabled function point module, and the second flag is used to characterize a disabled function point module;

[0014] Generate register configuration information based on the path-type test case, the register configuration information being configuration information required by the register when the function point module identified as the first identifier is enabled to execute the path-type test case;

[0015] The function point module whose enable identifier is the first identifier is run based on the register configuration information to obtain an operation result.

[0016] It can be seen from the above technical solutions that the present application provides a chip verification method and system, the method can obtain a path type test case, the path type test case is used to verify the function of the chip design module. The path type test case includes a single module test case and a cascade test case. The single module test case is used to verify a single function point module in the path, and the cascade test case is used to verify the combination of multiple function point modules in the path. The path is used to characterize the data processing path of the chip design module. Read the enable identifier of the path type test case, the enable identifier includes a first identifier and a second identifier, the first identifier is used to characterize the enabled function point module, and the second identifier is used to characterize the disabled function point module. Generate register configuration information based on the path type test case, the register configuration information is the configuration information required by the register when the function point module with the enable identifier as the first identifier executes the path type test case, and run the function point module with the enable identifier as the first identifier based on the register configuration information to obtain the running result. The method develops a path type test case according to the path in the chip design module, and performs single module function verification and cascade verification through the path type test case. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of a computing module in a computing core provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of a submodule 1 provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of the architecture of a chip verification system provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a pathway provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of the structure of the test case pool provided in the embodiment of the present application;

[0023] Figure 6 A schematic diagram of a simplified path01 provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of a simplified path012 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0026] AI chip refers to a chip (such as a system on a chip (SOC)) with an AI computing core (Neural Processing Unit, NPU) integrated into it, which is a dedicated processor for neural network models (AI models). AI computing core is a hardware concept. AI computing core is the core part of AI chip, which can accelerate the operation of neural network models. Using AI computing core can quickly complete the operator operation of AI model. AI model is a software concept. AI model can perform various complex tasks, such as image recognition, speech recognition, natural language processing, etc.

[0027] AI operation cores include matrix operation cores, vector operation cores, scalar operation cores, etc. Matrix operation cores are used to implement matrix operations, vector operation cores are used to implement vector operations, and scalar operation cores are used to implement scalar operations. Each operation core (zero-level module) includes an operation module for performing operation functions. The operation module includes multiple first-level modules, and each first-level module represents a collection of a certain type of operation functions. Each first-level module includes multiple second-level modules, and each second-level module represents a certain operation function.

[0028] like Figure 1 As shown in Figure 1, a single computing core has three built-in first-level modules, namely submodule 1, submodule 2 and submodule 3. Submodule 1 represents the first-level module of floating-point computing function. Figure 2 As shown, submodule 1 includes 11 secondary modules, namely module A, module B, module C, module D, module E, module F, module H, module I, module J, module K and module L, which can respectively represent floating-point number addition, subtraction, multiplication, division, remainder, absolute value, square and other operations. For example, module H can represent a floating-point number addition module, module J can represent a floating-point number multiplication module, and module L can represent a floating-point number division module.

[0029] A single computing core also includes three direct memory read access (RDMA) modules, namely RDMA0, RDMA1 and RDMA2, and one direct memory write access (WDMA) module, namely WDMA. When the computing core is running, RDMA0, RDMA1 and RDMA2 read data from the memory to the three first-level modules. The data is processed in turn by multiple second-level modules in the first-level module. The processed data is transmitted to WDMA, and WDMA writes the processed data to the memory.

[0030] When verifying the above-mentioned first-level modules, taking submodule 1 as an example, you can first perform functional verification on a single second-level module, and then cascade multiple second-level modules to verify the combined functional points. The verification engineer extracts a single functional point from the chip design document. For a second-level module, a number of single-module test cases for the second-level module will be developed, which are only used to verify the second-level module. For example, if the H module is a floating-point addition function, then a number of single-module test cases for the H module will be developed, which are only used to verify the H module, and other second-level modules will be turned off during verification. If the J module is a floating-point multiplication function, then a number of single-module test cases for the J module will be developed, which are only used to verify the J module, and other second-level modules will be turned off during verification.

[0031] After completing the functional verification of all secondary modules, cascade test cases will be developed for cascade verification of multiple secondary modules. Cascade test cases refer to combined test cases of multiple functional points. For the cascade verification of H module + J module, it is necessary to develop cascade test cases corresponding to H module + J module. H module + J module means to do floating-point addition first, and then do floating-point multiplication on the result of addition. In the process of developing cascade test cases, due to the large number of multi-module combinations and complex scenarios, verification engineers will build several cascade test cases based on experience, and will not exhaust all cascade test cases.

[0032] The disadvantage of first verifying the single module function and then cascade verification is that it requires secondary development. Test case development needs to be divided into two parts: the first is to develop single module function test cases, and the second is to develop cascade test cases, which adds extra development burden.

[0033] When developing cascade test cases, there are many cascade combinations, and modules cannot be combined arbitrarily. Each module needs to evaluate illegal cascade scenarios when combined, which increases the complexity of illegal scenario evaluation and the difficulty of developing cascade test cases.

[0034] In actual application scenarios, the cascade test cases do not cover enough scenarios. In actual projects, in order to save time, verification engineers will match several main cascade test cases based on experience, and consider the verification to be passed after connecting several typical paths. For example, Figure 2 As shown, the two typical paths are (A+B+C+H+J) and (C+D+E+H+J+K+L). In the verification process, only the above two typical paths need to be verified. The above implementation method does not enumerate all legal cascade scenarios, resulting in many cascade scenarios not being verified, reducing the completeness of the verification.

[0035] Since there are many cascade scenarios for module evaluation and the test case construction rules are unclear, relying on manual judgment one by one can easily lead to problems such as duplication, missing, and illegality of test cases.

[0036] Therefore, some embodiments of the present application provide a chip verification system, such as Figure 3 As shown, it is a schematic diagram of the architecture of the chip verification system provided by the embodiment of the present application. The chip verification system includes a memory management component, a simulation control component, a test case pool, a reference model component, a data packet transceiver, a comparison component and a simulation report component. The components are interconnected in the verification system. In order to realize chip verification, the chip design module to be verified, i.e., the register transfer level (RTL) module, is integrated in the verification system. The RTL module is connected to the components in the verification system by electrical signals, and an electrical signal level control and data interaction channel are created so that the RTL module can be correctly and effectively verified in the chip verification system.

[0037] The test case pool is used to store path-type test cases, and the path-type test cases are used to verify the execution function of the RTL module. In the embodiment of the present application, a test case pool can be created, the paths are divided according to the data processing paths of the RTL module, and the path-type test cases are constructed according to the paths, and the constructed path-type test cases are stored in the test case pool for subsequent simulation tests.

[0038] Paths are used to characterize the data processing path of RTL modules. Specifically, a path is composed of different function point modules in the RTL module, and data is processed in a certain order between these function point modules. That is, a path includes a series of function point modules in the complete path from data input to data output.

[0039] In some embodiments, after dividing the paths according to the data processing paths of the RTL modules, a cascaded legality analysis can be performed for each path to detect which function point modules in the path can be enabled and which function point modules cannot be enabled, thereby exhaustively enumerating all possible legal module combinations based on the legality analysis results, and the legal module combination includes one or more function point modules in the path. Finally, a path-type test case corresponding to each legal module combination is constructed and stored in a test case pool for subsequent simulation testing.

[0040] It should be noted that the exhaustive process can be performed manually or using programming tools. For example, a Python script can be written to automatically exhaust all legal scenarios by channel.

[0041] In some embodiments, illegal modules, critical restriction modules and freely enabled modules in the path can be detected. The illegal module is a functional point module that is not allowed to be enabled in the path, the critical restriction module is a functional point module that must be enabled in the path, and the freely enabled module is a functional point module that can be freely enabled or disabled.

[0042] If the path does not contain a critical restriction module, a legal module combination is generated according to the free enabling modules, and the legal module combination includes one or more free enabling modules.

[0043] If the path contains a critical restriction module, a legal module combination is generated according to the critical restriction module and the free enabling module, and the legal module combination includes the critical restriction module and one or more free enabling modules.

[0044] For example, the cascaded legality analysis is performed on each path, and the legality analysis results are as follows: Figure 4 As shown in the figure, the function point module marked with "×" is an illegal module, and the module is not allowed to be enabled in the current path. The module marked with "★" indicates a key restriction module, which must be enabled in the current path. Other unmarked modules are freely enabled modules, which can be freely enabled or disabled.

[0045] Taking path0 as an example, the legality of path0 requires that the H module and J module are not enabled, and there are no restrictions on other modules. Because the function of the H module is to perform addition operations on the two-way data of the 0th and 1st paths, path0 does not have the data of the 1st path (the data of path1), so the H module in path0 cannot be enabled. Similarly, the function of the J module is to perform multiplication operations on the two-way data of the 0th and 1st paths, requiring two-way input, and path0 does not have the data of the 2nd path (the data of path2), so the J module in path0 cannot be enabled. Based on the cascade legality analysis, the legal module combination generated for path0 can be a combination of any modules except the H module and the J module, such as (A+D), (A+F), (A+I), (D+F)(A+D+F), (A+D+F+I+K+L), etc., but there cannot be module combinations related to the H module and the J module such as (A+H) and (F+J).

[0046] Similarly, taking path02 as an example, the legality of path02 requires that the J module must be enabled, the H module is not enabled, and there are no restrictions on other modules. Because path02 requires that both the 0th and 2nd paths are connected to the data stream, and the 1st path cannot have data stream access, the J module must be enabled. Since the 1st path has no input, the H module cannot be enabled. Based on the cascade legality analysis, the legal module combination generated for path02 can be a combination of any modules that include the J module but do not include the H module, such as (J), (A+J), (A+C+J), (F+C+J+L), etc., but there cannot be a module combination that enables the H module such as (H+J) and (C+H+J), nor a module combination that does not enable the J module such as (A+C).

[0047] Figure 4 The cascade legality analysis of other paths in the path can refer to the above steps and will not be listed here. It should be noted that the cascade legality analysis of the path can be determined according to the actual situation of the chip. For example, in the actual scenario, there may be a requirement that module A and module D cannot be enabled at the same time. In this case, the legal module combination of path0 is not allowed to have (A+D), and legal module combinations such as (A+F) and (D+F) are allowed. Or there is a linkage relationship between a register of module A and a register of module C, etc. In the legal module combination of path02, module A and module C need to appear at the same time.

[0048] It can be understood that according to the development of the path type test case, the path type test case includes a single module test case and a cascade test case. The single module test case is used to verify a single function point module in the path, such as the above legal module combination: (J). The cascade test case is used to verify the combination of multiple function point modules in the path, such as the above legal module combination: (A+C+J). This allows the development of test cases to be completed in one step.

[0049] In some embodiments, for ease of maintenance and management, a unique test case name is created for each path-type test case of a legal module combination. A test case name template may be obtained, and the path-type test case of the legal module combination may be named according to the test case name template to obtain a test case name, so as to facilitate searching for the corresponding path-type test case by the test case name.

[0050] In some embodiments, for a path, a path list of the path can be created in the test case pool, and the test case name corresponding to the path can be stored in the path list. That is, a special list is established for each path in the test case pool, and the test case name related to the path is stored in the list for easy subsequent search and use.

[0051] For example, Figure 2 Taking the first-level module submodule 1 as an example, the submodule 1 is divided into paths, and the following is obtained: Figure 4 The 7 paths shown are path0, path1, path2, path01, path02, path12 and path012. A corresponding path list can be created for each of the 7 paths, as shown in the figure. Figure 5 The test case name corresponding to each path is stored in the corresponding path list.

[0052] Taking path2 as an example, the path list corresponding to path2 is Figure 5 float_path2_list in float_path2_list is used to store the test case names of path2. The legal module combinations of path2 include (C), (C+K), (C+L), (L), etc. The corresponding test case names can be CRdmaFloatPath2(CEn+JDis+KDis+LDis)Wdma, CRdmaFloatPath2(CEn+JDis+KEn+LDis)Wdma, CRdmaFloatPath2(CEn+JDis+KDis+LEn)Wdma, CRdmaFloat Path2(CDis+JDis+KDis+LEn)Wdma, etc. Store the above test case names in float_path2_list.

[0053] It should be noted that the above test case name is only an example. Other test case name templates can be set based on actual conditions. For example, the legal module combination: (C), the corresponding test case name can also be CRdmaFloatPath2(CEnJDisKDisLDis)Wdma.

[0054] In some embodiments, the step of constructing a path-type test case corresponding to a legal module combination includes limiting the enable register and other registers to construct random constraints. Limiting the enable register means limiting whether a certain function point module is enabled. Constructing random constraints for other registers means setting specific constraints, which are used to indicate what mode or range the value of a register in a certain function point module should conform to, including that the value of the register must be within a certain valid range, the values ​​between registers need to satisfy a certain logical relationship, the value of the register must conform to a specific encoding or mode, etc.

[0055] The function point modules in the path can be traversed, and the enabling identifier of the function point module belonging to the legal module combination is set as the first identifier, and specific constraints are set for the function point module whose enabling identifier is set to the first identifier, and the first identifier is used to characterize the enabled function point module. The enabling identifier of the function point module that does not belong to the legal module combination is set to the second identifier, and the second identifier is used to characterize the disabled function point module. Finally, the specific implementation file of the path type test case is set, and the specific implementation file is added to the test case pool.

[0056] For example, the first identifier is 1, and the second identifier is 0. For the test case CRdmaFloatPath2(CEn+JDis+KDis+LEn)Wdma, multiple registers are set, namely C_en, C_others, J_en, K_en, L_en and L_others. Configure C_en=1 (indicating that the C module is enabled), C_others=specific constraints (indicating specific constraints of the C module), J_en=0 (indicating that the J module is not enabled), K_en=0 (indicating that the K module is not enabled), L_en=1 (indicating that the L module is enabled), L_others=specific constraints (indicating specific constraints of the L module), and thus, the development of this path type test case is completed.

[0057] It should be noted that the path test case development process can be automated by writing scripts. Using scripts can quickly generate test cases, reduce human errors, and improve efficiency. The embodiment of the present application does not limit the tool for developing test cases, and the tool or language can be selected according to the actual situation.

[0058] It can be understood that the above test case pool stores a path list, the names of all path-type test cases and the specific implementations of the path-type test cases, and all chip verification function points are stored and maintained in the test case pool.

[0059] Based on the above test case pool, the simulation control component is used to control the start and end of the simulation, load path-type test cases from the test case pool, randomize the register information in the path-type test cases under constraints, configure the function registers to the RTL module, configure the function registers to the reference model component, configure the function registers to the comparison component, initialize the data and write it to the memory management component.

[0060] The process of executing chip verification in the verification system is executed by the simulation control component, and the simulation control component can obtain the path type test case from the test case pool. Read the enable flag of the path type test case, and the enable flag is the first flag or the second flag. Then read the specific constraint conditions corresponding to the function point module whose enable flag is set to the first flag in the path type test case. Then generate register configuration information according to the specific constraint conditions. The register configuration information is the configuration information required for the register when the function point module whose enable flag is the first flag executes the path type test case. Finally, configure the register configuration information to the RTL module, so that the function point module whose enable flag is the first flag in the RTL module executes the corresponding operation function to obtain the operation result.

[0061] The data packet transceiver is used to read or write data from the memory management component, and pack or unpack the data into data packets according to a specific bus protocol (such as AXI, AHB, APB, etc.), and then transmit the data packets to the RTL module through electrical signals.

[0062] The memory management component is used to manage memory space and implement unified memory management of the verification system. It can interact with multiple components in the verification system and perform corresponding operations, including initializing data in the specified memory area, reading and writing data, and other operations.

[0063] The reference model component is a functional module with the execution function of the RTL module, and is used to simulate the function of the RTL module. The simulation report component configures the generated register configuration information to the reference model component, so that the reference model component runs based on the register configuration information to obtain a reference result.

[0064] The comparison component is used to receive the register configuration information sent by the simulation control component, obtain the address information of the running results written by the RTL module to the memory management component according to the register configuration information, and then read the running results from the corresponding address of the memory management component, compare the running results of the RTL module with the reference results of the reference model to obtain the comparison results, and write the comparison results into the simulation log file.

[0065] The simulation report component is used to retrieve the simulation log file, read and analyze the comparison results in the simulation log file, generate and output the verification simulation report according to the comparison results, and output the verification simulation report. For example, if the comparison results include keywords such as error (ERR OR) and failure (FAIL), a verification simulation report representing simulation failure is generated, otherwise a verification simulation report representing simulation success is generated.

[0066] In this embodiment, a development plan for pathway-type test cases and a construction plan for a test case pool are provided to achieve standardization and normalization of test case development. The construction of all pathway-type test cases can be completed with only one development, and the pathway-type test cases include single module function test cases and cascade test cases. And there is no need to evaluate all illegal cascade scenarios for each functional point module one by one, only the legal scenarios of each pathway need to be evaluated, reducing the evaluation workload. After completing the pathway-level joint law scenario analysis, all legal test case combinations can be exhaustively enumerated to improve the completeness of the verification. The rules of this test case are clear, divided by pathway, and then all test cases are exhaustively implemented. The standardized process reduces the probability of test case errors.

[0067] The verification system provided by this application is described below with reference to specific embodiments.

[0068] Embodiment 1: Figure 4 Take path2 shown as an example to develop a path type test case and perform simulation.

[0069] according to Figure 1 The hardware architecture shown divides submodule 1 into 7 paths, namely: path0, path1, path2, path01, path02, path12 and path012.

[0070] For path2, create a text file in the test case pool, i.e. Figure 5 The float_path2_list shown is used to save the names of all path-type test cases of path2.

[0071] Perform cascaded legality analysis on path2. The results of path2 legality analysis are: J module is an illegal module and cannot be enabled. C module, K module and L module are freely enabled modules and can be enabled or disabled. Because J module is a floating-point multiplication operation, if J is enabled, there must be two inputs, but currently there is only one input for path2.

[0072] Based on the results of the legality analysis, all legal module combinations of path2 are exhausted, and a test case name is set for each legal module combination, resulting in 7 legal module combinations, namely: (C), (K), (L), (C+K), (C+L), (K+L), (C+K+L)), and the corresponding test case names are: CRdmaFloatPath2(CEn+JDis+KDis+LDis)Wdma, CRdmaFloatPath2(CDis+JDis+KEn+LDis)Wdma, CRdmaFloatPath2( CDis+JDis+KDis+LEn)Wdma、CRdmaFloatPath2(CEn+JDis+KEn+LDis)Wdma、CRdmaFloatPath2(CEn+JDis+KDis+LEn)Wdma、CRdmaFloatPath2(CDis+JDis+KEn+LEn)Wdma、CRdmaFloatPath2(CEn+JDis+KEn+LEn)Wdma, add the above 7 test case names to float_path2_list.

[0073] Develop the path-type test cases corresponding to the 7 legal module combinations in float_path2_list one by one, and store the path-type test cases in the test case pool. For example, for the CRdmaFloatPath2(CEn+JDis+KDis+LEn)Wdma test case, set multiple registers, namely C_en, C_others, J_en, K_en, L_en and L_others. Configure C_en=1 (indicating that the C module is enabled), C_others=specific constraints (indicating specific constraints of the C module), J_en=0 (indicating that the J module is not enabled), K_en=0 (indicating that the K module is not enabled), L_en=1 (indicating that the L module is enabled), and L_others=specific constraints (indicating specific constraints of the L module). Set the specific implementation file of the CRdmaFloatPath2(CEn+JDis+KDis+LEn)Wdma test case and add the specific implementation file to the test case pool.

[0074] After the path test case is stored, start the simulation and specify the execution of the path test case: CRdmaFloatPath2(CEn+JDis+KDis+LEn)Wdma through the command line. The simulation control component loads the specific implementation file (code implementation) of CRdmaFloatPath2(CEn+JDis+KDis+LEn)Wdma from the test case pool, and performs constrained randomization on the limited registers to generate a set of register configuration information.

[0075] The simulation control component calls the memory management component to initialize the data value of the memory area, and configures the above register configuration information to the RTL module so that the RTL module enables the C module and the L module, reads data from the memory area of ​​the memory management component according to the register configuration information, performs corresponding operations on the data through the C module and the L module, and writes the operation results into the memory area of ​​the memory management component.

[0076] The simulation control component waits for the task completion signal of the RTL module, and in response to the task completion signal, sends the above-mentioned register configuration information to the reference model component. The reference model component reads data from the memory area of ​​the memory management component based on the register configuration information, performs corresponding operations on the data, and writes the operation results to the memory area inside the reference model component.

[0077] The simulation control component sends the above register configuration information to the comparison component. The comparison component reads the operation results of the RTL module and the operation results of the reference model component from the memory management component and the reference model component respectively, compares them, and writes the comparison results into the simulation log file.

[0078] After the simulation is completed, the simulation report component analyzes the simulation log file. If error keywords such as ERROR and FAIL are detected, a verification simulation report representing the failure of the simulation is output. Otherwise, a verification simulation report representing the success of the simulation is output.

[0079] Embodiment 2: Figure 4 Take path01 as an example to develop a path test case and perform simulation. Figure 6 The figure shows the simplified module structure of path01.

[0080] according to Figure 1 The hardware architecture shown divides submodule 1 into 7 paths, namely: path0, path1, path2, path01, path02, pathl2 and path012.

[0081] For path01, create a text file in the test case pool, i.e. Figure 5 The float_path01_list shown is used to save the names of all path-type test cases of path01.

[0082] Perform cascaded legality analysis on path01. The results of path01 legality analysis are as follows: H module is a key restriction module and must be enabled, J module is an illegal module and cannot be enabled, and other modules can be enabled or disabled freely. Because there are two inputs, H module must be enabled, and J module cannot be enabled. If J is enabled, there must be input from path2.

[0083] Based on the results of the legality analysis, all legal module combinations of path01 are exhausted, and a test case name is set for each legal module combination, resulting in 8 legal module combinations, namely: (H), (E+H), (F+H), (H+I), (E+F+H), (E+H+I), (F+H+I), (E+F+H+I)), and the corresponding test case names are: CRdmaFloatPath01(EDis+FDis+HEn+IDis+JDis)Wdma, CRdmaFloatPath01(EEn+FDis+HEn+IDis+JDis)Wdma, CRdmaFloatPath01(EDis+FEn+HEn+IDis+J Dis)Wdma, CRdmaFloatPath01(EDis+FDis+HEn+IEn+JDis)Wdma, CRdmaFloatPath01(EEn+FEn+HEn+IDis+JDis)Wdma, CRdmaFloatPath01(EEn+FDis+HEn+IEn +JDis)Wdma, CRdmaFloatPath01(EDis+FEn+HEn+IEn+JDis)Wdma, CRdmaFloatPath01(EEn+FEn+HEn+IEn+JDis)Wdma, add the above 8 test case names to float_path01_list.

[0084] Develop the path-type test cases corresponding to the 8 legal module combinations in float_path01_list one by one, and store the path-type test cases in the test case pool. For example, for the CRdmaFloatPath01(EEn+FDis+HEn+IDis+JDis)Wdma test case, set multiple registers, namely E_en=1, E_others, F_en=0, H_en=1, H_others, I_en and J_en. Configure E_en=1 (indicating that the E module is enabled), E_others=specific constraints (indicating specific constraints of the E module), F_en=0 (indicating that the F module is not enabled), H_en=1 (indicating that the H module is enabled), H_others=specific constraints (indicating specific constraints of the H module), I_en=0 (indicating that the I module is not enabled), and J_en=0 (indicating that the J module is not enabled). And set the specific implementation file of the CRdmaFloatPath01(EEn+FDis+HEn+IDis+JDis)Wdma test case, and add the specific implementation file to the test case pool.

[0085] After the path test case is stored, start the simulation and specify the execution of the path test case: CRdmaFloatPath01(EEn+FDis+HEn+IDis+JDis)Wdma through the command line. The simulation control component loads the specific implementation file of CRdmaFloatPath01(EEn+FDis+HEn+IDis+JDis)Wdma from the test case pool, and performs constrained randomization on the limited registers to generate a set of register configuration information.

[0086] The simulation control component calls the memory management component to initialize the data value of the memory area, and configures the above register configuration information to the RTL module so that the RTL module enables the E module and the H module, reads data from the memory area of ​​the memory management component according to the register configuration information, performs corresponding operations on the data through the E module and the H module, and writes the operation results into the memory area of ​​the memory management component.

[0087] The simulation control component waits for the task completion signal of the RTL module, and in response to the task completion signal, sends the above-mentioned register configuration information to the reference model component. The reference model component reads data from the memory area of ​​the memory management component based on the register configuration information, performs corresponding operations on the data, and writes the operation results to the memory area inside the reference model component.

[0088] The simulation control component sends the above register configuration information to the comparison component. The comparison component reads the operation results of the RTL module and the operation results of the reference model component from the memory management component and the reference model component respectively, compares them, and writes the comparison results into the simulation log file.

[0089] After the simulation is completed, the simulation report component analyzes the simulation log file. If error keywords such as ERROR and FAIL are detected, a verification simulation report representing the failure of the simulation is output. Otherwise, a verification simulation report representing the success of the simulation is output.

[0090] Embodiment 3: Figure 4 Take path012 as an example to develop a path test case and perform simulation. Figure 7 As shown, the simplified module structure of path012 is shown.

[0091] according to Figure 1 The hardware architecture shown divides submodule 1 into 7 paths, namely: path0, path1, path2, path01, path02, path12 and path012.

[0092] For path012, create a text file in the test case pool, namely Figure 5 The float_path012_list shown is used to save the names of all path-type test cases of path012.

[0093] Perform cascaded legality analysis on path012. The results of the legality analysis of path012 are as follows: H module and J module are key limiting modules and must be enabled. Other modules can be enabled or disabled freely. Because there are 3 inputs, H module must be enabled and J module must be enabled.

[0094] Based on the results of the legality analysis, all legal module combinations of path012 are exhausted, and a test case name is set for each legal module combination, and two legal module combinations are obtained, namely: (H+J) and (H+I+J). The corresponding test case names are: CRdmaFloatPath012(HEn+IDis+JEn)Wdma and CRdmaFloatPath012(HEn+IEn+JEn)Wdma. Add the above two test case names to float_path012_list.

[0095] Develop the path-type test cases corresponding to the two legal module combinations in float_path012_list one by one, and store the path-type test cases in the test case pool. For example, for the CRdmaFloatPath012(HEn+IEn+JEn)Wdma test case, set multiple registers, namely H_en, H_others, I_en, I_others, J_en and J_others. Configure H_en=1 (indicating that the H module is enabled), H_others=specific constraints (indicating the specific constraints of the H module), I_en=1 (indicating that the I module is enabled), I_others=specific constraints (indicating the specific constraints of the I module), J_en=0 (indicating that the J module is enabled), J_others=specific constraints (indicating the specific constraints of the J module). And set the specific implementation file of the CRdmaFloatPath012(HEn+IEn+JEn)Wdma test case, and add the specific implementation file to the test case pool.

[0096] After the path test case is stored, start the simulation and specify the execution of the path test case: CRdmaFloatPath012(HEn+IEn+JEn)Wdma through the command line. The simulation control component loads the specific implementation file of CRdmaFloatPath012(HEn+IEn+JEn)Wdma from the test case pool, and performs constrained randomization on the limited registers to generate a set of register configuration information.

[0097] The simulation control component calls the memory management component to initialize the data value of the memory area, and configures the above register configuration information to the RTL module, so that the RTL module enables the H module, I module and J module, reads data from the memory area of ​​the memory management component according to the register configuration information, performs corresponding operations on the data through the H module, I module and J module, and writes the operation results into the memory area of ​​the memory management component.

[0098] The simulation control component waits for the task completion signal of the RTL module, and in response to the task completion signal, sends the above-mentioned register configuration information to the reference model component. The reference model component reads data from the memory area of ​​the memory management component based on the register configuration information, performs corresponding operations on the data, and writes the operation results to the memory area inside the reference model component.

[0099] The simulation control component sends the above register configuration information to the comparison component. The comparison component reads the operation results of the RTL module and the operation results of the reference model component from the memory management component and the reference model component respectively, compares them, and writes the comparison results into the simulation log file.

[0100] After the simulation is completed, the simulation report component analyzes the simulation log file. If error keywords such as ERROR and FAIL are detected, a verification simulation report representing the failure of the simulation is output. Otherwise, a verification simulation report representing the success of the simulation is output.

[0101] Based on the above chip verification system. Some embodiments of the present application also provide a chip verification method, which is applied to the chip verification system described in the above embodiment. The method comprises the following steps:

[0102] Get the path type test case. Among them, the path type test case is used to verify the function of the RTL module. The path type test case includes single module test case and cascade test case. The single module test case is used to verify a single function point module in the path, and the cascade test case is used to verify the combination of multiple function point modules in the path. The path is used to characterize the data processing path of the RTL module.

[0103] The enable flag of the path type test case is read, where the enable flag is a first flag or a second flag, the first flag is used to characterize an enabled function point module, and the second flag is used to characterize a disabled function point module.

[0104] Register configuration information is generated based on the path type test case, where the register configuration information is configuration information required by the register when the function point module with the first identifier is enabled to execute the path type test case.

[0105] The function point module whose enable identifier is the first identifier is run based on the register configuration information to obtain an operation result.

[0106] The same and similar parts between the various embodiments in this specification can be referenced to each other and will not be described again here.

[0107] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A chip verification method, characterized in that: The method comprises: Obtaining a path type test case, wherein the path type test case is used to verify the function of the chip design module, the path type test case includes a single module test case and a cascade test case, the single module test case is used to verify a single function point module in the path, the cascade test case is used to verify the combination of multiple function point modules in the path, and the path is used to characterize the data processing path of the chip design module; Reading an enable flag of the path-type test case, wherein the enable flag is a first flag or a second flag, wherein the first flag is used to characterize an enabled function point module, and the second flag is used to characterize a disabled function point module; Generate register configuration information based on the path-type test case, the register configuration information being configuration information required by the register when the function point module identified as the first identifier is enabled to execute the path-type test case; The function point module whose enable identifier is the first identifier is run based on the register configuration information to obtain an operation result.

2. The chip verification method according to claim 1, characterized in that: The method further comprises: Create a test case pool; Dividing the pathways according to the data processing paths of the chip design modules; Construct a pathway-type test case according to the pathway; The pathway test case is stored in the test case pool.

3. The chip verification method according to claim 2, characterized in that: The step of constructing a path-type test case according to the path in the chip design module also includes: Detecting illegal modules and freely enabled modules in the path, wherein the illegal modules are function point modules that are not allowed to be enabled in the path, and the freely enabled modules are function point modules that can be enabled or disabled; According to the free enabling module, generating a legal module combination, the legal module combination including one or more of the free enabling modules; Construct a pathway-type test case corresponding to the legal module combination.

4. The chip verification method according to claim 2, characterized in that: The step of constructing a path-type test case according to the path in the chip design module also includes: Detecting a key restriction module and a freely enabled module in the path, wherein the key restriction module is a function point module that must be enabled in the path, and the freely enabled module is a function point module that can be enabled or disabled; According to the key restriction module and the free enabling module, generating a legal module combination, the legal module combination including the key restriction module and one or more free enabling modules; Construct a pathway-type test case corresponding to the legal module combination.

5. The chip verification method according to claim 3 or 4, characterized in that: The method further comprises: Get the test case name template; According to the test case name template, the path-type test case of the legal module combination is named to obtain a test case name.

6. The chip verification method according to claim 5, characterized in that: The method further comprises: Creating a path list of the paths in the test case pool; The test case name corresponding to the path is stored in the path list.

7. The chip verification method according to claim 3 or 4, characterized in that: The step of constructing a path-type test case corresponding to the legal module combination also includes: Traversing the function point modules in the path; Setting the enabling identifier of the function point module belonging to the legal module combination as the first identifier, and setting a specific constraint condition for the function point module whose enabling identifier is set to the first identifier; The enabling identifier of the function point module that does not belong to the legal module combination is set as the second identifier.

8. The chip verification method according to claim 7, characterized in that: The step of generating register configuration information based on the path type test case also includes: Reading the specific constraint condition corresponding to the function point module whose enabling identifier is set to the first identifier in the path type test case; Register configuration information is generated according to the specific constraint conditions.

9. The chip verification method according to claim 1, characterized in that: The method further comprises: Running a reference model component based on the register configuration information to obtain a reference result, wherein the reference model component is a functional module having an execution function of a chip design module; Comparing the operation result with the reference result to obtain a comparison result; Generate a verification simulation report according to the comparison result; The verification simulation report is output.

10. A chip verification system, characterized in that: It includes a simulation control component and a chip design module; the simulation control component is configured as follows: Obtaining a path type test case, wherein the path type test case is used to verify the function of the chip design module, the path type test case includes a single module test case and a cascade test case, the single module test case is used to verify a single function point module in the path, the cascade test case is used to verify the combination of multiple function point modules in the path, and the path is used to characterize the data processing path of the chip design module; Reading an enable flag of the path-type test case, wherein the enable flag is a first flag or a second flag, wherein the first flag is used to characterize an enabled function point module, and the second flag is used to characterize a disabled function point module; Generate register configuration information based on the path-type test case, the register configuration information being configuration information required by the register when the function point module identified as the first identifier is enabled to execute the path-type test case; The function point module whose enable identifier is the first identifier is run based on the register configuration information to obtain an operation result.

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