Chip based on IP core and implementation method thereof

Abstract

The invention discloses a chip based on an IP core and an implementation method thereof, at least one IP core and a variable delay line connected with an interface of the IP core are integrated in the chip, and the variable delay line is used for repairing time sequence deviation of the interface of the IP core. Compared with the prior art, the method has the advantages that the variable delay line is added to the IP interface, the delay of the IP interface can be effectively adjusted to offset the problem of inaccurate time sequence of an IP library file, so that time sequence violation is repaired, and the reliability of designing a chip based on an IP core is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip based on an IP core and an implementation method thereof. Background Art

[0002] IP refers to intellectual property cores or knowledge modules, which are some commonly used modules that have been verified in integrated circuits. Although process improvements have continued to reduce the cost of a single transistor, the increase in design complexity has also caused the design cost of integrated circuits to rise sharply. Process improvements have led to an increasing number of transistors in integrated circuits of the same size, and more and more functions. Now a chip usually contains several different functional modules, and it will cost a lot of money and time to develop these modules from scratch. Therefore, in order to improve chip performance at advanced process nodes, more and more chip design companies use IP.

[0003] In order to protect intellectual property rights, the internal structure of IP is not open to users. In order for IP to work properly in the chip, IP design manufacturers will provide users with IP library files for timing analysis. The risks are: 1) the accuracy and completeness of the library file information bring usage risks; 2) the deviations in the analysis of noise, interference and other aspects of IP and the overall design bring usage risks. The above risks may cause the IP interface timing analyzed by the library file to differ from the actual timing, thus causing timing problems, affecting chip performance, and even causing severe failures. The timing problems caused by inaccurate IP interface timing are as follows: (1) IP interface has setup time violation or hold time violation; (2) the offset between IP bus interfaces is too large; (3) the sampling window is tight and the clock does not appear in the center of the sampling window.

[0004] The occurrence of setup time violation or hold time violation means that the chip cannot work properly and the tape-out fails, which will bring huge losses to the design company. Although the sampling window is tight and the clock does not appear in the center of the sampling window, it will significantly reduce the chip's anti-interference ability, thereby increasing the risk of timing violation.

[0005] The best way to solve the above problems is to ask the IP design manufacturer for the detailed internal structure of the IP instead of just the library file. With the internal structure of the IP, you can perform a complete timing analysis on the entire chip including the IP, minimizing the risk of timing violations.

[0006] However, it is not feasible for IP users to ask IP design manufacturers for the complete internal structure of IP, because this will touch the core of intellectual property. The internal structure of IP covers the core technology and confidential information of the design manufacturer. Providing it in full to IP users may lead to intellectual property leakage. IP design manufacturers have invested a lot of resources and time to develop and optimize these IPs, and these IPs are their core competitiveness. Therefore, although obtaining the complete internal structure of IP is very helpful for timing analysis and performance optimization, IP design manufacturers usually do not provide these details publicly for the sake of intellectual property protection and commercial confidentiality. If only the library files provided by the IP design manufacturer are used for timing analysis, once the IP interface timing is inaccurate, it is very likely to cause timing violations, resulting in the chip not being able to work properly.

[0007] Therefore, in view of the defects of the prior art, it is necessary to propose a technical solution to solve the technical problems existing in the prior art. Summary of the invention

[0008] In view of this, it is indeed necessary to provide a chip based on an IP core and an implementation method thereof that can repair the timing deviation caused by the IP interface, so as to effectively solve the timing problems caused by inaccurate IP interface timing and improve the reliability of the chip designed based on the IP core.

[0009] In order to solve the technical problems existing in the prior art, the technical solution of the present invention is as follows:

[0010] A chip based on an IP core integrates at least one IP core and a variable delay line connected to an interface of the IP core. The variable delay line is used to repair the timing deviation of the IP core interface.

[0011] As a further improvement, the variable delay line is composed of multiple delay units, and each delay unit is used to delay for a preset time.

[0012] As a further improvement, the delay unit is composed of a number of logic gate circuits, at least an enable terminal and a mode_select terminal are set, wherein the mode_select terminal is used to configure the delay mode to fast_mode or slow_mode, and the enable terminal is used to control whether the delay unit is cascaded.

[0013] As a further improvement, the delay unit is composed of a buffer, two inverters and six NAND gates.

[0014] As a further improvement, the chip is further provided with a configuration register, and the configuration register is used to configure the mode of the variable delay line.

[0015] As a further improvement, the variable delay line is provided with 20 levels of delay units.

[0016] The present invention also discloses a method for implementing a chip based on an IP core, comprising the following steps:

[0017] Step S1: During the chip design phase, at least one IP core is integrated inside the chip, and variable delay lines are connected to the interfaces of the IP core;

[0018] Step S2: After the chip is taped out, the IP function test is performed, wherein the correctness of the IP function is ensured by configuring a variable delay line.

[0019] As a further improvement, in step S2, when performing IP function testing, a string of test characters is written to the register connected to the IP interface. If the output of the IP is inconsistent with the predicted characters, it indicates that the IP interface has a timing violation due to inaccurate timing. The variable delay line is adjusted to increase or decrease the IP interface delay until the characters output by the IP are consistent with the predicted characters.

[0020] As a further improvement, in step S1, during the chip design phase, the number of stages of the variable delay line is adjusted to an intermediate position.

[0021] As a further improvement, the variable delay line is composed of multiple delay units, each delay unit is used to delay for a preset time;

[0022] The delay unit is composed of a number of logic gate circuits, and at least an enable terminal and a mode_select terminal are set, wherein the mode_select terminal is used to configure the delay mode to fast_mode or slow_mode, and the enable terminal is used to control whether the delay unit is cascaded.

[0023] Compared with the prior art, the present invention can effectively adjust the delay of the IP interface to offset the problem of inaccurate timing by adding a variable delay line to the IP interface, thereby repairing the timing violation and improving the reliability of the chip designed based on the IP core. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure of the chip based on IP core of the present invention.

[0025] Figure 2 It is a schematic diagram of the structure of the variable delay line of the present invention.

[0026] Figure 3 It is a schematic diagram of the structure of the delay unit in the present invention.

[0027] Figure 4 It is a timing diagram between IP and register in the present invention.

[0028] Figure 5 Schematic diagram of path delay that meets the timing requirements in the present invention.

[0029] Figure 6 It is a schematic diagram of timing violation caused by inaccurate timing of IP interface in the present invention.

[0030] Figure 7 A schematic diagram of adjusting the path delay of an IP interface to repair a timing violation in the present invention.

[0031] Figure 8 This is a connection diagram between the IP bus interface and the on-chip registers and variable delay lines in the present invention.

[0032] Fig. 9 Schematic diagram of the sampling window on the bus interface in the present invention.

[0033] Fig.10 Schematic diagram of the sampling window when the IP interface timing is inaccurate in the present invention.

[0034] Fig.11 It is a schematic diagram of using a variable delay line to restore the sampling window in the present invention.

[0035] Fig.12 It is a schematic diagram of the clock edge in the center of the sampling window in the present invention.

[0036] Fig.13 It is a schematic diagram of the variable delay line in the present invention to recover the clock edge position.

[0037] Fig.14 It is a schematic diagram of adjusting the variable delay line to repair the timing violation in the present invention.

[0038] Fig.15 The figure is a flowchart of actual chip testing using the method of the present invention.

[0039] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0040] The technical solution provided by the present invention will be further described below in conjunction with the accompanying drawings.

[0041] IP refers to intellectual property cores or knowledge modules, which are some commonly used modules that have been verified in integrated circuits. Using IP in chip design can shorten the design cycle, reduce design costs, and improve product competitiveness. IP users perform timing analysis based on the IP library files provided by IP design manufacturers so that the IP can work normally in the chip. There are major risks in integrating IP into chips: 1) usage risks due to the accuracy and completeness of library file information; 2) usage risks due to some deviations in the analysis of noise, interference, etc. between IP and the overall design. Therefore, a method is needed to dynamically adjust the IP interface delay after the chip is put into production, perform error correction and timing compensation, so as to improve the stability and availability of IP.

[0042] In order to solve the above technical problems, the present invention provides a chip based on IP core, see Figure 1 , shown is a schematic diagram of the structure of the chip based on the IP core of the present invention, the chip integrates at least one IP core and a variable delay line connected to the interface of the IP core, and the variable delay line is used to repair the timing deviation of the IP core interface.

[0043] In the above technical solution, a variable delay line VDL is added at the IP interface to dynamically adjust the delay, aiming to fix the timing problem caused by inaccurate IP interface timing and improve the reliability of IP. When the IP interface timing is inaccurate and the IP interface delay is increased or decreased compared to the IP library file, causing a timing violation, the delay of the IP interface is adjusted to offset the timing inaccuracy, thereby fixing the timing violation.

[0044] In a preferred embodiment, see Figure 2 , shown is a schematic diagram of the structure of the variable delay line of the present invention, the variable delay line (VDL) is composed of a multi-stage delay unit (DLY), each delay unit is used to delay a preset time.

[0045] See also Figure 3 , shown is a schematic diagram of the structure of the delay unit in the present invention, the delay unit is composed of a number of logic gate circuits, at least an enable terminal and a mode_select terminal are set, wherein the mode_select terminal is used to configure the delay mode to fast_mode or slow_mode, and the enable terminal is used to control whether the delay unit is cascaded.

[0046] Enable and mode_select are used to control whether the delay unit is enabled and to select the delay mode. The delay unit consists of a buffer, two inverters and six NAND gates. The delay mode of the delay unit at this level is selected by the mode_select signal: when mode_select is set to 1, the delay mode is slow_mode, and the delay time is longer; when mode_select is set to 0, the delay mode is fast_mode, and the delay time is shorter. The delayed signal will be passed to the next level of delay unit. The signal enable determines whether the delay block at this level accepts the output feedback signal of the next level: when enable is set to 1, the output pin waits for the output signal feedback of the next level, and continues to feed back the feedback signal to the previous level of delay unit; when enable is set to 0, the delay unit at this level does not receive the output signal feedback of the next level, and the output pin directly feeds back the input signal to the previous level of delay unit. The final delayed signal will return to the output of the first delay unit.

[0047] Through the mode_select signal and the enable signal, the variable delay line can control the delay mode of the unipolar delay unit and the number of enabled delay units, thereby controlling the total delay size of the delay line in disguise.

[0048] Generally speaking, the larger the total delay of the variable delay line and the more delay unit levels, the larger the adjustment range and better adjustment accuracy can be obtained. However, due to the limitation of chip area, it is impossible to increase the number of variable delay lines indefinitely. Therefore, in order to obtain a significant adjustment effect, the total delay of the variable delay line should be at least in the same order of magnitude as the clock cycle of the IP. On this basis, the more delay unit levels in the variable delay line, the better.

[0049] As a further improvement, the chip is further provided with a configuration register, and the configuration register is used to configure the mode of the variable delay line.

[0050] In an application example of the present invention: assuming that the clock cycle of the IP is 1.5ns, the variable delay line contains 20 levels of variable delay units, and the slow mode delay of each level of delay unit is 0.1ns, that is, the adjustment range of the variable delay line for the IP interface delay is 0-2ns.

[0051] By adopting the above technical solution of the present invention, the variable delay line can effectively repair the IP interface timing violation. As pointed out in the background technology, the timing problems caused by the inaccurate IP interface timing are as follows:

[0052] 1. A setup time violation or a hold time violation occurs on the IP interface.

[0053] 2. The offset between IP bus interfaces is too large and the sampling window is tight.

[0054] 3. The clock does not appear in the center of the sampling window.

[0055] Now let's analyze the repair effect of using variable delay lines on these three timing problems one by one.

[0056] 1. The IP interface has a setup time violation or a hold time violation:

[0057] See also Figure 4 , which is a timing diagram between IP and register in the present invention. When the timing of IP interface is inaccurate, the timing path of IP interface is likely to violate the setup time or hold time constraint. The specific analysis is as follows: Figure 4 The timing diagram of the interconnection between the IP interface and the on-chip registers and variable delay line VDL is shown. Assume that the clock period T p The delay from the clock source to the clock pin of the register in the IP is T launch The delay from the register clock pin in the IP to the register output is T ck2q , the delay from the register output to the IP output is T in The delay from the IP output to the chip register is T out The time from the clock source to the register on the chip is T capture , the register setup time is T setup , keep time T hold .

[0058] Therefore, the setup time requirement is:

[0059] T launch +T ck2q +T in +T out <T p +T capture -T setup

[0060] That is, T out :

[0061] T out <T p +T capture -T setup -T ck2q -T in -T launch The hold time requirement is:

[0062] T capture +T hold <T launch +T ck2q +T in +T out

[0063] That is, T out :

[0064] T capture +T hold -T ck2q -T in -T launch <T out

[0065] Where T ck2q , T in , T launch It constitutes the IP interface delay, which is provided by the IP library file of the IP design manufacturer. To simplify the formula:

[0066] T ip =T ck2q +T in +T launch

[0067] T α =T p +T capture -T setup

[0068] T β =T capture +T hold

[0069] Thus:

[0070] T β -T ip <T out <T α -T ip

[0071] This will delay the path between the IP output and the on-chip register T out Under the influence of PVT (process, voltage, temperature), T out Not a fixed value.

[0072] like Figure 5 , which is a schematic diagram of the path delay that meets the timing requirements in the present invention. Assuming that the delay provided by the IP library is used for timing analysis during the chip design phase, T out The constraints are always satisfied.

[0073] like Figure 6 , which is a schematic diagram showing a timing violation caused by inaccurate IP interface timing in the present invention. If the IP interface timing is inaccurate, the actual IP delay is reduced by T compared to the delay provided by the IP library. Δ , so that the constraint range is offset, T out If the constraints are exceeded, a hold time violation occurs.

[0074] like Figure 7 , which is a schematic diagram of adjusting the path delay of the IP interface to repair the timing delay in the present invention. At this time, a variable delay line is added between the IP output port and the register to increase T VDL The delay of the offending IP interface is adjusted to compensate for T Δ Fix the timing violation by correcting the offset caused by

[0075] The above introduction uses the IP interface as the transmitting register and the on-chip register as the capturing register as an example, and analyzes in detail the impact of inaccurate IP library delay on timing, and demonstrates that when the IP interface timing is inaccurate, adjusting the IP interface path delay can repair the timing violation. When the on-chip register is used as the transmitting register and the register in the IP is used as the capturing register, dynamically adjusting the IP interface path delay can still repair the timing violation. The specific analysis is the same as above and will not be repeated here.

[0076] 2. The offset between IP bus interfaces is too large and the sampling window is tight:

[0077] See also Figure 8 , which shows the connection diagram of the IP bus interface, the register on the chip, and the variable delay line in the present invention. On the IP bus interface, data needs to be sampled under the same clock signal, which requires that the clock signal must meet the timing constraints of all interfaces on the IP bus. In other words, the clock can only be sampled when all signals on the bus interface are stable. The time range in which the clock signal can correctly sample data is called the sampling window.

[0078] See also Fig. 9 , which is a schematic diagram of the sampling window on the bus interface in the present invention. Assuming that there are eight interfaces D[0] to D[7] on the bus, the data on the eight interfaces are stabilized after different delays. The shaded part in the figure represents the sampling window formed by the time range in which the eight data are simultaneously stable. The effective edge of the clock can only appear within the sampling window. When the effective edge of the clock appears outside the sampling window, it means that a timing violation has occurred, that is, the clock signal fails to correctly sample the data within the predetermined time range, resulting in data transmission errors.

[0079] The arrival time of the clock signal is not always constant due to process, voltage and temperature (PVT) variations and clock jitter. These factors cause the clock signal to fluctuate so that it does not always appear at the same moment. Therefore, a smaller sampling window increases the risk of timing violations because any slight deviation of the clock signal may cause it to fall outside the sampling window.

[0080] The size of the sampling window depends largely on the skew between the IP bus interfaces. Skew refers to the difference in time when data is received by different interfaces. If the skew between the IP bus interfaces is large, it will reduce the sampling window and make the system more prone to timing violations. In order to expand the sampling window and reduce the possibility of timing violations, the skew between the IP bus interfaces should be minimized.

[0081] By minimizing the skew between IP bus interfaces, the sampling window can be significantly expanded, thereby improving the system's tolerance to PVT changes and clock jitter. This will help ensure that data can be reliably sampled on the IP bus, improving overall system stability and performance.

[0082] See also Fig.10 , which is a schematic diagram of a sampling window when the timing of the IP interface is inaccurate in the present invention, wherein, Fig.10 (a) is a schematic diagram of the sampling window in the chip design stage. Fig.10 (b) is a schematic diagram of the sampling window when the IP interface timing is inaccurate in actual situations. During the chip design phase, the offset between the IP bus interfaces is adjusted to 0 according to the timing provided by the IP library, and a sampling window as large as possible is obtained. Assume that due to the influence of the inaccurate IP interface timing, the actual delay of each IP interface increases by T △ (T △ It can be positive or negative). At this time, the offset between IP bus interfaces increases, the sampling window decreases, and the system's anti-interference ability deteriorates.

[0083] See also Fig.11 , which is a schematic diagram of using a variable delay line to restore the sampling window in the present invention, adjusting the variable delay line on each IP interface, and adding a T VDL Compensation T △ (T VDL =-T △ ), offset the sampling window change caused by the inaccurate IP interface timing, and restore the sampling window.

[0084] 3. The clock does not appear in the center of the sampling window:

[0085] When sampling data, the effective edge of the clock signal should be at the center of the sampling window to ensure that the data can be accurately sampled within a stable and generous time period. Fig.12 , shown is a schematic diagram of the clock edge in the center of the sampling window in the present invention. The clock is sampled at the center of the sampling window, and has the largest margin before and after the clock edge, and has a higher tolerance for inevitable signal noise and jitter, thereby improving the stability and reliability of data transmission.

[0086] See also Fig.13, which is a schematic diagram of the variable delay line recovering the clock edge position in the present invention. Assuming that due to the influence of the inaccurate timing of the IP interface, the actual delay of each IP interface is increased by T △ At this time, the clock edge deviates from the center of the sampling window, and the margin behind the clock edge is reduced, increasing the risk of timing violation. By adjusting the variable delay line on all IP interfaces and adding a TVDL compensation T△ (TVDL = -T△), the clock signal is realigned to the center of the sampling window.

[0087] After analysis, it can be seen that the variable delay line can repair the three timing problems caused by inaccurate IP interface timing. When the chip is actually working, it does not care about which timing problem occurs, but focuses on whether the chip function is implemented normally. Therefore, when using the variable delay line to repair the timing problem, the focus is on whether the inaccurate IP interface timing affects the IP function.

[0088] To this end, the present invention also proposes a chip implementation method based on an IP core, comprising the following steps:

[0089] Step S1: During the chip design phase, at least one IP core is integrated inside the chip, and variable delay lines are connected to the interfaces of the IP core;

[0090] Step S2: After the chip is taped out, the IP function test is performed, wherein the correctness of the IP function is ensured by configuring a variable delay line.

[0091] During the chip design phase, the level of the variable delay line is adjusted to the middle position, which is equivalent to adding half of the maximum delay of the variable line to the IP interface. At the same time, the chip designer will eliminate timing violations on this basis to reduce the risk of timing violations. When the chip is taped out, when the IP function test is performed, a string of test characters is written to the register connected to the IP interface, and the output characters when the IP function is correct are predicted. Under the premise of excluding other errors, if the output of the IP is inconsistent with the predicted characters, it indicates that the IP interface has a timing violation due to inaccurate timing. At this time, it is necessary to adjust the variable delay line forward and backward to increase or decrease the IP interface delay until the characters output by the IP are consistent with the predicted characters. At this time, it can be considered that the variable delay line has repaired the timing violation of the IP interface due to inaccurate timing.

[0092] See also Fig.14, shown is a schematic diagram of adjusting the variable delay line to repair the timing violation in the present invention, showing the process of adjusting the variable delay line to repair the timing violation, wherein the number of boxes in the VDL represents the level of the variable delay line, and the larger the level, the larger the delay of the variable delay line. Before the test, all the levels of the variable delay lines are in the middle position. A string of test characters "1101101" is input into the register connected to the IP, and it is predicted that if the IP function is correct, the Q port will also output "1101101". The test results show that the output results of Q[0] and Q[7] do not match the predicted results. At this time, it can be considered that the interface timing of D[0] and D[7] of the IP is inaccurate, resulting in the data not being sampled correctly. The variable delay lines connected to D[0] and D[7] are adjusted forward and backward to compensate for the inaccurate interface timing until the output results of Q[0] and Q[7] match the predicted results.

[0093] In addition to timing violations causing incorrect IP functions, inaccurate IP interface timing may also cause two timing problems: the sampling window is too small and the clock is not in the center of the sampling window. These two timing problems will not directly cause timing violations when the chip is working normally, but will increase the risk of timing violations when the chip is in an extreme working environment.

[0094] In order to simulate the complex working environment of the chip, it is necessary to select multiple chip test environments to cover its working conditions as comprehensively as possible, including extreme low temperature, high temperature, low pressure and high pressure environments. Use the above test method to adjust the variable delay line in these test environments to ensure that the IP function is correct and there are no timing violations on the interface. When the chip does not have timing violations on the IP interface under the most complete test environment possible, it can be considered that the risk of timing violations caused by inaccurate IP interface timing has been eliminated. The actual test flow chart is as follows: Fig.15 shown.

[0095] By adjusting the variable delay line to ensure that the IP interface does not have timing violations under all test conditions, it can be considered that the variable delay line has successfully repaired the timing violations caused by inaccurate IP interface timing and eliminated the risk of timing violations. This means that the delay line effectively compensates for the timing deviation, allowing the chip to operate stably in various working environments and improving the reliability of the IP.

[0096] The above embodiments are only used to help understand the method and core idea of ​​the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0097] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip based on IP core, characterized in that: The chip integrates at least one IP core and a variable delay line connected to the interface of the IP core, and the variable delay line is used to repair the timing deviation of the IP core interface.

2. The IP core-based chip according to claim 1, characterized in that: The variable delay line is composed of multiple delay units, and each delay unit is used to delay for a preset time.

3. The IP core-based chip according to claim 2, characterized in that: The delay unit is composed of a number of logic gate circuits, and at least an enable terminal and a mode_select terminal are set, wherein the mode_select terminal is used to configure the delay mode to fast_mode or slow_mode, and the enable terminal is used to control whether the delay unit is cascaded.

4. The IP core-based chip according to claim 3, characterized in that: The delay unit is composed of a buffer, two inverters and six NAND gates.

5. The IP core-based chip according to claim 2, characterized in that: The chip also sets a configuration register, and the configuration register is used to configure the mode of the variable delay line.

6. The IP core-based chip according to claim 1, characterized in that: The variable delay line is provided with 20 levels of delay units.

7. A method for implementing a chip based on an IP core, characterized in that: The following steps are involved: Step S1: During the chip design phase, at least one IP core is integrated inside the chip, and variable delay lines are connected to the interfaces of the IP core; Step S2: After the chip is taped out, the IP function test is performed, wherein the correctness of the IP function is ensured by configuring a variable delay line.

8. The method for implementing a chip based on an IP core according to claim 7, characterized in that: In step S2, when performing IP function testing, a string of test characters is written to the register connected to the IP interface. If the output of the IP is inconsistent with the predicted characters, it indicates that the IP interface has a timing violation due to inaccurate timing. The variable delay line is adjusted to increase or decrease the IP interface delay until the characters output by the IP are consistent with the predicted characters.

9. The method for implementing a chip based on an IP core according to claim 7, characterized in that: In step S1, during the chip design phase, the level of the variable delay line is adjusted to an intermediate position.

10. The method for implementing a chip based on an IP core according to claim 7, characterized in that: The variable delay line is composed of multiple delay units, each delay unit is used to delay for a preset time; The delay unit is composed of a number of logic gate circuits, and at least an enable terminal and a mode_select terminal are set, wherein the mode_select terminal is used to configure the delay mode to fast_mode or slow_mode, and the enable terminal is used to control whether the delay unit is cascaded.

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