Power amplifier design method, power amplifier, terminal and storage medium

Abstract

The invention relates to a power amplifier design method and a power amplifier. The power amplifier design method comprises the following steps: performing Load Pull simulation on a target power amplifier to obtain input impedance and output impedance of a transistor; designing a bias circuit; respectively designing an input matching network and an output matching network according to the input impedance and the output impedance of the transistor; simulating and optimizing the input matching network and the output matching network by using a small signal S parameter to obtain an optimized input matching network and an optimized output matching network; and respectively substituting the optimized input matching network and the optimized output matching network into the input end and the output end of a transistor to obtain the circuit structure of the target power amplifier. According to the method, an ideal large signal simulation result of the power amplifier can be obtained by optimizing the input matching network and the output matching network through the small signal S parameter, and the design working efficiency of the power amplifier is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a power amplifier design method, a power amplifier, a terminal and a storage medium. Background Art

[0002] In recent years, MMIC technology based on GaN HEMT process has developed rapidly, and MMIC technology has been widely used in active phased array radar components. In active phased array radar, power amplifier is its basic component. With the advancement of technology, people's requirements for power and efficiency of power amplifiers are constantly increasing. Therefore, the development of microwave RF power amplifiers with high output power and high efficiency has become one of the core technologies of modern microwave circuit design.

[0003] ADS software provides a powerful tool for RF microwave circuit design. Currently, the use of ADS software to design MMIC chips through harmonic balance simulation optimization has replaced the design and calculation work done manually, greatly improving the efficiency of chip design. However, as the area of ​​power amplifier chips continues to increase, the output power continues to increase, and the frequency band gradually becomes wider, the time required for harmonic balance simulation will continue to increase. Therefore, the method of optimizing power amplifier chip performance through harmonic balance simulation can no longer meet the design requirements, and a more time-saving power amplifier design optimization method is urgently needed. Summary of the invention

[0004] Based on this, in view of the problem that the current method of optimizing power amplifier chip performance through harmonic balance simulation is difficult to meet design requirements, the purpose of the present invention is to provide a power amplifier design method, a power amplifier, a terminal and a storage medium. The power amplifier design method extracts the optimal input and output impedance of the transistor through LoadPull simulation, and then obtains the optimal input and output matching network of the transistor through small signal S parameter simulation optimization, thereby getting rid of the harmonic balance simulation optimization method, thereby improving the design work efficiency.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] The present invention provides a method for designing a power amplifier, which comprises the following steps:

[0007] S1. Perform a Load Pull simulation on the target power amplifier to obtain the optimal input impedance and optimal output impedance of the transistor;

[0008] S2. Design bias circuit;

[0009] S3. Design an input matching network and an output matching network according to the optimal input impedance and the optimal output impedance of the transistor;

[0010] S4. Optimize the input matching network and the output matching network by using small signal S parameter simulation to obtain an optimized input matching network and an optimized output matching network;

[0011] S5. The optimized input matching network and the optimized output matching network are respectively introduced into the input end and the output end of the transistor to obtain the circuit structure of the target power amplifier.

[0012] Preferably, in step S1, the target frequency of the target power amplifier is Ku band, the transistor adopts a field effect transistor of 0.15 μm GaN HEMT process, and the DC operating point of the transistor is V ds =28V, V gs =-2.4V.

[0013] Preferably, in step S2, the designing of the bias circuit includes the following steps: according to the DC operating point requirement of the transistor, the D terminal of the transistor is connected to a 28V power supply, the G terminal is connected to a -2.4V power supply, a DC_Block ideal DC blocking capacitor is added between the DC and AC paths of the transistor to block the DC power supply network, and a DC_Feed ideal choke inductor is added to the DC path of the transistor, thereby obtaining a bias circuit.

[0014] Preferably, in step S3, DA_SmithChartMatch in ADS software is used to design the input matching network and the output matching network.

[0015] Preferably, in step S3, designing the input matching network and the output matching network respectively according to the optimal input impedance and the optimal output impedance of the transistor obtained in step S1 includes: setting the load impedance of the input matching circuit to the optimal input impedance of the transistor obtained in step S1, and setting the source impedance of the output matching circuit to the optimal output impedance of the transistor obtained in step S1, to obtain the input matching network and the output matching network.

[0016] Preferably, in step S4, the use of small signal S parameter simulation to optimize the input matching network and the output matching network designed in step S3 includes:

[0017] The impedance in the Term component is set to the optimal input impedance and the optimal output impedance of the transistor, and a transistor input impedance Term component and a transistor output impedance Term component whose impedance changes with frequency are obtained. The transistor input impedance Term component and the transistor output impedance Term component are used to optimize the input matching network and the output matching network obtained in step S3, respectively, to obtain an optimized input matching network and an optimized output matching network.

[0018] Preferably, in step S5, after obtaining the circuit structure of the target power amplifier, the design method further comprises: performing simulation verification on the target power amplifier.

[0019] The present invention provides a power amplifier, which is designed by using the power amplifier design method as described above.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention extracts the optimal input impedance and output impedance of the transistor through LoadPull simulation, and then obtains the optimal input matching network and output matching network of the transistor through small-signal S parameter simulation optimization, gets rid of the harmonic balance simulation optimization method, and obtains the ideal power amplifier large-signal simulation result only through small-signal S parameter optimization of the input matching network and the output matching network, thereby greatly improving the design efficiency of the power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a flow chart of a method for designing a power amplifier in an embodiment of the present invention;

[0023] Figure 2 The optimal input and load impedance points of the transistor at each frequency point in the embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of a bias circuit in an embodiment of the present invention;

[0025] Figure 4 Input a matching circle diagram in an embodiment of the present invention;

[0026] Figure 5 Outputting a matching circle diagram in an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of setting the transistor input and output impedance Term component in an embodiment of the present invention;

[0028] Figure 7 An input matching network optimization schematic diagram in an embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of the output matching network optimization in an embodiment of the present invention;

[0030] Fig. 9 is a circuit structure diagram of a power amplifier in an embodiment of the present invention;

[0031] Fig.10 for Fig. 9 The saturated output power and efficiency curves obtained by simulation;

[0032] Fig.114 is a graph showing the saturated output power and efficiency obtained through harmonic balance simulation in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] For ease of understanding of the present invention, the present invention will be described more fully below in conjunction with specific embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0035] In view of the problem that the current method of optimizing the performance of a power amplifier chip through harmonic balance simulation is difficult to meet design requirements, this embodiment provides a power amplifier design method.

[0036] Reference Figure 1 The purpose of the present invention is to provide a power amplifier design method comprising the following steps:

[0037] S1. Perform a Load Pull simulation on the target power amplifier to obtain the optimal input impedance and optimal output impedance of the transistor.

[0038] The target frequency of the power amplifier designed in this embodiment is the Ku band, and the transistor adopts a field effect transistor of 0.15um GaN HEMT process, and its DC operating point is V ds =28V, V gs = -2.4V. Using LoadPull simulation in ADS software, the optimal input and load impedance points of transistors at each frequency are obtained by comprehensively considering the maximum power and maximum efficiency, such as Figure 2 shown.

[0039] From the simulation results, the input impedance and output impedance of the transistor at each frequency point in the 14-18 GHz frequency band are shown in Table 1.

[0040] Table 1 Input impedance and output impedance of transistor at various frequencies

[0041] Input impedance(Ohm) Output Impedance(Ohm) 14GHz 2.98-j*4.82 25.612-j*44.793 15GHz 2.85-j*4.25 24.050-j*42.061 16GHz 2.73-j*3.69 22.492-j*39.547 17GHz 2.52-j*3.14 18.342-j*37.790 18GHz 2.45-j*2.65 17.013-j*35.741

[0042] S2. Design bias circuit.

[0043] According to the DC operating point requirements of the transistor, the D end of the transistor model is connected to a 28V power supply, and the G end is connected to a -2.4V power supply. At the same time, an ideal DC blocking capacitor DC_Block is added between the DC and AC paths of the transistor to block the DC power supply network, and an ideal choke inductor DC_Feed is added to the DC path of the transistor to prevent high-frequency signals from entering the DC power supply network and affecting signal transmission. Figure 3 The bias circuit is shown.

[0044] S3. Design the input matching network and the output matching network according to the optimal input impedance and the optimal output impedance of the transistor respectively.

[0045] Use DA_SmithChartMatch in ADS software to design input matching network and output matching network.

[0046] Take the matching at 16GHz as an example: In order to match the conjugate impedance of the optimal source impedance to 50Ohm, the load impedance of the input matching circuit is set to the input impedance of the transistor 2.73-j*3.69Ohm, and the following is obtained: Figure 4 Similarly, in order to match the conjugate impedance of the optimal load impedance to 50Ohm, the source impedance of the output matching circuit is set to the output impedance of the transistor 22.492-j*39.547Ohm, and the following is obtained: Figure 5 The output shown matches the circle graph.

[0047] S4. Optimize the input matching network and the output matching network using small signal S parameter simulation to obtain an optimized input matching network and an optimized output matching network.

[0048] First, set the impedance in the Term component to the optimal input impedance and optimal output impedance of the transistor. By using the DAC control and the MDF file containing the input and output impedance, different impedance values ​​can be assigned to different frequency points. Finally, set the Z in the Term component to a reference to the DAC to obtain the transistor input impedance Term component and transistor output impedance Term component whose impedance changes with frequency. The settings are as follows Figure 6 shown.

[0049] Substitute the input matching network obtained in step S3 into Figure 7 As shown in the input matching network optimization schematic diagram, the optimization targets are set to "dB(S(1,1)<-25", "dB(S(2,2)<-25", "dB(S(2,1)>-0.02", and the optimized output matching network is obtained; similarly, the output matching network obtained in step S3 is brought into Figure 8As shown in the output matching network optimization schematic diagram, the optimization targets are set to "dB(S(1,1)<-25", "dB(S(2,2)<-25", and "dB(S(2,1)>-0.02" to obtain the optimized output matching network.

[0050] S5. The optimized input matching network and the optimized output matching network are respectively introduced into the input end and the output end of the transistor to obtain the circuit structure of the target power amplifier.

[0051] Bring the optimized input matching network and the optimized output matching network to the input and output ends of the transistor respectively, and we can get the following: Fig. 9 The circuit schematic diagram of the input and output matching network power amplifier after small signal S parameter optimization is shown in the figure. The simulation results are shown in Fig.10 shown.

[0052] Since the traditional method for optimizing the large signal simulation results of power amplifiers requires setting the results of harmonic balance simulation as the optimization target, for comparison, the input matching network and output matching network generated by the Smith chart tool in step S3 are added to the input and output ends of the transistor respectively, and then combined with the harmonic balance simulation to obtain Fig.11 The saturated output power and efficiency curves are shown.

[0053] Depend on Fig.11 From the curve, we can see that the matching network generated by the Smith chart tool only has a good matching result for the 16GHz frequency point, and the efficiency of other frequency points has not reached the optimal level. In order to achieve a higher efficiency at each frequency point in the band, further optimization is required. Fig.10 and Fig.11 By comparing the simulation results, it can be seen that the typical output power of the power amplifier designed in this embodiment is increased by 0.5dB in the 14-18GHz frequency band, and the efficiency is increased by up to 13%. The simulation results show that the power amplifier designed in this embodiment does not need to be optimized through harmonic balance simulation, and more ideal saturated output power and efficiency results can be obtained only through small signal S parameter simulation of the matching network. Compared with the small signal S parameter simulation of this embodiment, the traditional harmonic balance simulation takes longer, and as the scale and bandwidth of the power amplifier increase, the harmonic balance simulation speed also decreases. Therefore, the input and output networks can be optimized through small signal S parameter simulation to reduce the time required for simulation.

[0054] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for designing a power amplifier, characterized in that: It includes the following steps: S1. Perform a Load Pull simulation on the target power amplifier to obtain the optimal input impedance and optimal output impedance of the transistor; S2. Design bias circuit; S3. Designing an input matching network and an output matching network according to the optimal input impedance and the optimal output impedance of the transistor; S4. Optimize the input matching network and the output matching network by using small signal S parameter simulation to obtain an optimized input matching network and an optimized output matching network; S5. The optimized input matching network and the optimized output matching network are respectively introduced into the input end and the output end of the transistor to obtain the circuit structure of the target power amplifier.

2. The power amplifier design method according to claim 1, characterized in that: In step S1, the target frequency of the target power amplifier is Ku band, the transistor adopts a field effect transistor of 0.15 μm GaN HEMT process, and the DC operating point of the transistor is V ds =28V, V gs =-2.4V.

3. The power amplifier design method according to claim 2, characterized in that: In step S2, the design of the bias circuit includes the following steps: according to the DC operating point requirements of the transistor, the D terminal of the transistor is connected to a 28V power supply, the G terminal is connected to a -2.4V power supply, a DC_Block ideal DC blocking capacitor is added between the DC and AC paths of the transistor to block the DC power supply network, and a DC_Feed ideal choke inductor is added to the DC path of the transistor, thereby obtaining a bias circuit.

4. The power amplifier design method according to claim 1, characterized in that: In step S3, DA_SmithChartMatch in ADS software is used to design input matching network and output matching network.

5. The power amplifier design method according to claim 1, characterized in that: In step S3, designing the input matching network and the output matching network respectively according to the optimal input impedance and the optimal output impedance of the transistor obtained in step S1 includes: setting the load impedance of the input matching circuit to the optimal input impedance of the transistor obtained in step S1, and setting the source impedance of the output matching circuit to the optimal output impedance of the transistor obtained in step S1, to obtain the input matching network and the output matching network.

6. The power amplifier design method according to claim 1, characterized in that: In step S4, the input matching network and the output matching network designed in step S3 are optimized by using small signal S parameter simulation, including: The impedance in the Term component is set to the optimal input impedance and the optimal output impedance of the transistor, and a transistor input impedance Term component and a transistor output impedance Term component whose impedance changes with frequency are obtained. The transistor input impedance Term component and the transistor output impedance Term component are used to optimize the input matching network and the output matching network obtained in step S3, respectively, to obtain an optimized input matching network and an optimized output matching network.

7. The power amplifier design method according to claim 1, characterized in that: In step S5, after obtaining the circuit structure of the target power amplifier, the design method further includes: performing simulation verification on the target power amplifier.

8. A power amplifier, characterized in that: The power amplifier is designed by the power amplifier design method as described in any one of claims 1 to 7.

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