Wafer defect detection method and system for IGP processing unit, and storage medium

Abstract

The invention discloses a wafer defect detection method and system for an IGP processing unit, and a storage medium. The detection method comprises the following steps: acquiring a wafer image; the method comprises the following steps: constructing a multi-dimensional and multi-level low-magnification imaging feature recognition network, extracting different-dimensional features of an image by using a deep convolutional neural network formed by convolution kernels, introducing a feature pyramid structure, and realizing fusion and extraction of multi-level features through a top-down path and transverse connection in combination with features of different levels. Further processing the high-dimensional features extracted by the convolutional neural network model by adopting a multi-granularity scanning structure through a deep forest model to complete multi-dimensional and multi-level extraction of wafer defect features; and training the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, and carrying out wafer defect detection. By introducing structures such as a feature pyramid and a depth forest, a multi-dimensional and multi-level low-magnification imaging feature recognition network is constructed, and the wafer defect recognition capability is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of machine vision, and the present invention relates to a wafer defect detection method, system and storage medium for an IGP processing unit. Background Art

[0002] Semiconductor wafers are the basic materials for manufacturing chips and have a direct impact on the performance and quality of chip products. In recent years, countries around the world have increased their efforts in the research and development and production of chip products, which has also led to the expansion of production of many wafer fabs, and the continuous investment and expansion of micro-silicon processes and micro-nano manufacturing. However, wafers are easily affected by manufacturing technology, production line dynamics and environmental factors during processing, which leads to crystal defects, reduces the yield rate of wafer output, causes manufacturing cost losses of downstream chips, and affects the performance of chips. Therefore, defect detection of wafer products is becoming increasingly important. Traditional wafer defect detection algorithms mainly analyze the difference area between the image to be detected and the reference image. Although this method can achieve the purpose of wafer defect detection to a certain extent, it is often difficult to directly obtain accurate defect images. At the same time, the extracted local features cannot effectively represent different types of defects in specific problems, and the detection accuracy is low and the robustness is weak. In addition, the entire recognition model needs to be redesigned according to new problems. Technologies such as deep learning are increasingly widely used in the field of defect detection, but the existing deep learning algorithms have low detection accuracy and weak robustness. Summary of the invention

[0003] The purpose of the present invention is to provide a wafer defect detection method, system and storage medium for an IGP processing unit. By introducing structures such as feature pyramids and deep forests, a multi-dimensional and multi-level low-magnification imaging feature recognition network is constructed, thereby improving the model's ability to recognize wafer defects.

[0004] The technical solution to achieve the purpose of the present invention is: A wafer defect detection method for an IGP processing unit comprises the following steps: S01: Acquire wafer image; S02: Construct a multi-dimensional and multi-level low-magnification imaging feature recognition network, use a deep convolutional neural network composed of convolution kernels to extract features of different dimensions of the image, introduce a feature pyramid structure, combine features of different levels through top-down paths and lateral connections, and realize the fusion and extraction of multi-level features. On this basis, through the deep forest model and a multi-granularity scanning structure, further process the high-dimensional features extracted by the convolutional neural network model to complete the multi-dimensional and multi-level extraction of wafer defect features; S03: training the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, and using the trained multi-dimensional and multi-level low-magnification imaging feature recognition network to perform wafer defect detection.

[0005] In the preferred technical solution, the backbone network of the multi-dimensional and multi-level low-magnification imaging feature recognition network is a Darknet-53 network. After the image data is input into the Darknet-53 network, it first passes through two convolutional layers, and then the data is processed by five convolutional groups in sequence. A convolutional layer is used between every two convolutional groups to complete the downsampling operation and extract image feature data. Introducing the feature pyramid structure, we obtain the output feature maps of the last three convolution groups in the Darknet-53 network, and obtain three feature maps of different sizes. We pass the feature map of the deep network through a 1×1 convolution layer to make it the same size as the feature map of the shallow network. Figure 1 Finally, the output feature maps of the three network layers are converted to the same size, and then stacked and fused for feature pyramid processing.

[0006] In the preferred technical solution, a multi-granularity cascade forest algorithm is used after feature pyramid processing. First, a multi-granularity scan is performed, and the input feature data is scanned using feature windows of different sizes to generate a multi-scale enhancement vector. Then, in the cascade forest execution stage, the generated multi-scale enhancement vector is trained layer by layer to predict the wafer defect category distribution, and the generated category distribution vector is connected with the original vector and input to the next cascade layer through the cascade channel.

[0007] In the preferred technical solution, a model joint training method based on multi-level pre-training and terminal fine training is used to train the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, including: The first level of pre-training is performed on the industrial defect dataset to enable the model to learn some common features of defects in the real world; The second level of pre-training is performed on a public wafer defect dataset, so that the model can learn the subdivided features of wafer defects based on the general defect features; Part of the structure of the pre-trained network model is migrated to the new network structure through the transfer learning algorithm; Perform terminal fine training on other parts of the network except the migration parameters.

[0008] In the preferred technical solution, the training parameters of the first two convolution groups in the Daranet-53 network are migrated.

[0009] In the preferred technical solution, the transfer learning algorithm is:

[0010] in, Represents the final model training parameters, are the model parameters obtained through pre-training, , are the starting layer and the ending layer of the migration part, respectively. These are the parameters in the network that need further training except the migration part.

[0011] The present invention also discloses a wafer defect detection system for an IGP processing unit, comprising: Wafer image acquisition module, acquiring wafer images; A multi-dimensional and multi-level low-magnification imaging feature recognition network construction module is used to build a multi-dimensional and multi-level low-magnification imaging feature recognition network. A deep convolutional neural network composed of convolution kernels is used to extract features of different dimensions of the image. A feature pyramid structure is introduced to combine features of different levels through top-down paths and lateral connections to achieve the fusion and extraction of multi-level features. On this basis, a deep forest model is used with a multi-granularity scanning structure to further process the high-dimensional features extracted by the convolutional neural network model to complete the multi-dimensional and multi-level extraction of wafer defect features. The training detection module trains the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, and uses the trained multi-dimensional and multi-level low-magnification imaging feature recognition network to perform wafer defect detection.

[0012] In the preferred technical solution, the backbone network of the multi-dimensional and multi-level low-magnification imaging feature recognition network is a Darknet-53 network. After the image data is input into the Darknet-53 network, it first passes through two convolutional layers, and then the data is processed by five convolutional groups in sequence. A convolutional layer is used between every two convolutional groups to complete the downsampling operation and extract image feature data. Introducing the feature pyramid structure, we obtain the output feature maps of the last three convolution groups in the Darknet-53 network, and obtain three feature maps of different sizes. We pass the feature map of the deep network through a 1×1 convolution layer to make it the same size as the feature map of the shallow network. Figure 1 Finally, the output feature maps of the three network layers are converted to the same size, and then stacked and fused for feature pyramid processing.

[0013] The present invention further discloses an IGP processing unit, which integrates an NPU neural network processing unit, an ARM architecture CPU, a high-speed storage device, and multiple data transmission interfaces. The NPU neural network processing unit is embedded with any of the above-mentioned wafer defect detection methods for the IGP processing unit.

[0014] The present invention also discloses a computer storage medium on which a computer program is stored. When the computer program is executed, the above-mentioned wafer defect detection method for an IGP processing unit is implemented.

[0015] Compared with the prior art, the present invention has the following significant advantages: By adopting deep learning technology and introducing structures such as feature pyramids and deep forests, a multi-dimensional and multi-level low-magnification imaging feature recognition network is constructed. Based on the transfer learning algorithm, a multi-level pre-training + terminal fine training mode is adopted to improve the model's ability to recognize wafer defects, thereby achieving the purpose of improving the accuracy of wafer defect detection for IGP processing units. It has broad application market space and economic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the Draknet-53 convolutional neural network structure; Figure 2 Schematic diagram of module-N and residual structure; Figure 3 This is a schematic diagram of the Darknet-53 network structure after the introduction of the feature pyramid; Figure 4 Schematic diagram of feature pyramid processing image; Figure 5 It is a schematic diagram of the multi-granularity cascade forest structure; Figure 6 A schematic diagram of the transfer learning structure of the wafer defect detection network for the IGP processing unit; Figure 7 A diagram of the training structure. DETAILED DESCRIPTION

[0017] The principle of the present invention is: by introducing structures such as feature pyramids and deep forests, a multi-dimensional and multi-level low-magnification imaging feature recognition network is constructed, and on the basis of the transfer learning algorithm, a multi-level pre-training + terminal fine training mode is adopted to improve the model's recognition ability of wafer defects, thereby achieving the purpose of improving the accuracy of wafer defect detection for IGP processing units.

[0018] Embodiment 1:

[0019] A wafer defect detection method for an IGP processing unit comprises the following steps: S01: Acquire wafer image; S02: Construct a multi-dimensional and multi-level low-magnification imaging feature recognition network, use a deep convolutional neural network composed of convolution kernels to extract features of different dimensions of the image, introduce a feature pyramid structure, combine features of different levels through top-down paths and lateral connections, and realize the fusion and extraction of multi-level features. On this basis, through the deep forest model and a multi-granularity scanning structure, further process the high-dimensional features extracted by the convolutional neural network model to complete the multi-dimensional and multi-level extraction of wafer defect features; S03: training the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, and using the trained multi-dimensional and multi-level low-magnification imaging feature recognition network to perform wafer defect detection.

[0020] In a preferred embodiment, the backbone network of the multi-dimensional and multi-level low-magnification imaging feature recognition network is a Darknet-53 network. After the image data is input into the Darknet-53 network, it first passes through two convolutional layers, and then the data is processed by five convolutional groups in sequence. A convolutional layer is used between every two convolutional groups to complete the downsampling operation and extract image feature data. Introducing the feature pyramid structure, we obtain the output feature maps of the last three convolution groups in the Darknet-53 network, and obtain three feature maps of different sizes. We pass the feature map of the deep network through a 1×1 convolution layer to make it the same size as the feature map of the shallow network. Figure 1 Finally, the output feature maps of the three network layers are converted to the same size, and then stacked and fused for feature pyramid processing.

[0021] In a preferred embodiment, a multi-granularity cascade forest algorithm is used after feature pyramid processing. First, a multi-granularity scan is performed, and the input feature data is scanned using feature windows of different sizes to generate a multi-scale enhancement vector. Then, in the cascade forest execution stage, the generated multi-scale enhancement vector is trained layer by layer to predict the wafer defect category distribution, and the generated category distribution vector is connected with the original vector and input to the next cascade layer through the cascade channel.

[0022] In a preferred embodiment, a model joint training method based on multi-level pre-training and terminal fine training is used to train the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, including: The first level of pre-training is performed on the industrial defect dataset to enable the model to learn some common features of defects in the real world; The second level of pre-training is performed on a public wafer defect dataset, so that the model can learn the subdivided features of wafer defects based on the general defect features; Part of the structure of the pre-trained network model is migrated to the new network structure through the transfer learning algorithm; Perform terminal fine training on other parts of the network except the migration parameters.

[0023] In a preferred embodiment, the training parameters of the first two convolution groups in the Daranet-53 network are migrated.

[0024] In a preferred embodiment, the transfer learning algorithm is:

[0025] in, represents the final model training parameters, are the model parameters obtained through pre-training, , are the starting layer and the ending layer of the migration part, respectively. These are the parameters in the network that need further training except the migration part.

[0026] In another embodiment, a computer storage medium stores a computer program, and when the computer program is executed, the above-mentioned wafer defect detection method for an IGP processing unit is implemented. The above-mentioned wafer defect detection method for an IGP processing unit is adopted and will not be described in detail here.

[0027] In another embodiment, a wafer defect detection system for an IGP processing unit includes: Wafer image acquisition module, acquiring wafer images; A multi-dimensional and multi-level low-magnification imaging feature recognition network construction module is used to build a multi-dimensional and multi-level low-magnification imaging feature recognition network. A deep convolutional neural network composed of convolution kernels is used to extract features of different dimensions of the image. A feature pyramid structure is introduced to combine features of different levels through top-down paths and lateral connections to achieve the fusion and extraction of multi-level features. On this basis, a deep forest model is used with a multi-granularity scanning structure to further process the high-dimensional features extracted by the convolutional neural network model to complete the multi-dimensional and multi-level extraction of wafer defect features. The training detection module trains the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, and uses the trained multi-dimensional and multi-level low-magnification imaging feature recognition network to perform wafer defect detection.

[0028] Specifically, the workflow of the wafer defect detection system for the IGP processing unit is described below by taking a preferred embodiment as an example: Step 1: Construct a multi-dimensional and multi-level low-magnification imaging feature recognition network.

[0029] Wafer defects are diverse and complex. They are usually small in size and have various shapes, including but not limited to particle defects, scratch defects, bubble defects, cracks and fractures, and lattice defects. Wafer defects can lead to reduced chip yield and performance, causing huge losses to companies. Due to the diversity and complexity of defects, the detection of wafer defects has become a difficult problem that needs to be overcome.

[0030] The present invention is based on deep learning technology to construct a multi-dimensional and multi-level low-magnification imaging feature recognition network. First, a deep convolutional neural network composed of convolution kernels is used to complete the universal extraction of features of different dimensions of the image. On this basis, a deep forest model is used to further process the high-dimensional features extracted by the convolutional neural network model using a multi-granularity scanning structure. Then, a feature pyramid is introduced to achieve the fusion and extraction of multi-level features through top-down paths and lateral connections, combined with features of different levels, thereby completing the multi-dimensional and multi-level extraction of wafer defect features.

[0031] Step 11: Construction of the convolutional neural network backbone.

[0032] The present invention uses the Draknet-53 convolutional neural network as the backbone network for wafer defect detection. Draknet-53 achieves efficient feature extraction by replacing the pooling layer with a deep residual structure and a convolutional layer. The network structure is as follows: Figure 1 As shown. The main part of the Draknet-53 network is 5 convolution groups ( Figure 1 Each group contains a different number of convolutional modules, which have similar structures and are set as "module-N", where N is the number of channels per layer. The structure of module-N is as follows: Figure 2 As shown in Figure 1, each module is composed of convolution kernels of size 1×1 and 3×3, so the structure of each module can be expressed as shown in formula (1).

[0033] (1) At the same time, Darknet-53 uses a lot of residual structures, such as Figure 2 As shown, assume that the input data is , the output after processing by the convolutional layer is , and the residual structure superimposes the input data on the output of the neural network to obtain the output result , as shown in formula (2), it can effectively solve the problem of gradient vanishing or gradient exploding that occurs when the number of layers of the neural network model increases.

[0034] (2) according to Figure 1The Darknet-53 network structure shown in the figure, after the image data is input into the network, it first passes through two 3×3 convolutional layers, and the step size of the second convolutional layer is 2. Then the data is processed by 5 convolutional groups in sequence. A convolutional layer with a step size of 2 and a convolution kernel size of 3×3 is set between every two convolutional groups to complete the downsampling operation and finally obtain the extracted image feature data.

[0035] Step 12: Introduce feature pyramid network.

[0036] Due to the diversity and complexity of wafer defects, the detection model must be able to detect multiple defects. In the feature maps output by each layer of the actual convolutional neural network, the features detected by convolutional layers of different depths are different. The feature maps output by the shallow network have undergone fewer convolution operations and retain more small-size detail information, while the feature maps output by the deep network have undergone more layers of convolution operations and contain image information with a wider field of view. Feature Pyramid Networks (FPN) can effectively solve the multi-scale problem in target detection and greatly improve the detection performance of small targets by simply changing the network connection.

[0037] Therefore, in order to fully utilize the feature data output by different network layers, the present invention introduces a feature pyramid structure to enhance the effect of wafer defect detection. The network structure after introducing the feature pyramid is as follows: Figure 3 As shown in the figure, the feature pyramid is divided into two parts. First, the output feature maps of the last three convolution groups in the Darknet-53 network are obtained. Due to the different depths of the network, the sizes of the three feature maps obtained at this time are different. The feature map of the shallow network is larger, and the feature map of the deep network is smaller. In order to integrate and utilize the feature data of different network depths, the feature map of the deep network is passed through a 1×1 convolution layer to make its size the same as the shallow network feature map. Figure 1 Finally, the output feature maps of the three network layers are converted to the same size so that subsequent stacking and fusion can be performed. The schematic diagram of feature pyramid processing of the image is as follows: Figure 4 shown.

[0038] Step 13: Introduce the multi-grained cascade forest (GCForest) algorithm.

[0039] The image feature data extracted by Darknet-53 and feature pyramid has high dimensionality, and it is difficult to achieve higher accuracy by directly classifying and predicting it. The multi-granularity cascade forest algorithm is used to identify and process high-dimensional feature information. Its structure is as follows Figure 5As shown, a multi-granularity cascade forest algorithm is introduced to further enhance the ability of wafer defect detection for IGP processing units.

[0040] The multi-granularity cascade forest algorithm generates multi-scale feature vectors through multi-dimensional scanning. It can adaptively determine the number of cascade layers and decide the model complexity by itself. The algorithm itself has fewer hyperparameters. The multi-granularity cascade forest algorithm consists of two parts. The first part is the multi-granularity scanning structure, which scans the feature data through a sliding window to generate a set of multi-size feature vectors. The second part is the cascade forest structure, which generates the corresponding class distribution according to each input instance. The structure of the multi-granularity cascade forest is as follows: Figure 5 As shown, where M is the number of layers of the cascade forest.

[0041] When the multi-granularity cascade forest algorithm works, it first performs multi-granularity scanning, and can use feature windows of different sizes to scan the input feature data to generate multi-scale enhancement vectors; then in the cascade forest execution phase, the generated multi-scale enhancement vectors are trained layer by layer to predict the wafer defect category distribution, and the generated category distribution vector is connected with the original vector and input to the next cascade layer through the cascade channel. During the training process of the cascade forest, when the recognition performance of the verification set converges, the model adaptively terminates the training. Therefore, the cascade forest can adaptively determine the model complexity.

[0042] Step 2: Model joint training method based on multi-level pre-training and terminal fine training.

[0043] In reality, since wafer defect samples are difficult to collect, the data required for model training is difficult to meet the demand, which limits the accuracy of various wafer defect detection algorithms. To overcome this problem, the present invention uses a joint training method of multi-level pre-training and terminal fine training to greatly improve the accuracy of model detection.

[0044] Step 21: Multi-level pre-training Due to the insufficient number of wafer defect samples, the present invention draws on the idea of ​​transfer learning and performs pre-training with the help of an industrial defect training data set that has a certain similarity with wafer defects.

[0045] The first level of pre-training is carried out on large-scale industrial defect datasets such as DAGM2007, magnetic tile defects, and NEU surface defect database. Through this level of pre-training, the model can learn some common features of defects in the real world.

[0046] The second level of pre-training is performed on public wafer defect datasets such as WM-811K and MixedWM38. These datasets contain various types of wafer defect image data. Therefore, through this level of training, the model can learn more detailed features of wafer defects based on general defect features. After the above two levels of training, a pre-trained model for wafer defects can be obtained.

[0047] Step 22: Transfer learning and terminal fine-tuning Transfer learning is based on the idea of ​​model parameter sharing. By migrating the pre-trained network model in a large-scale data set, better representation learning capabilities can be obtained. Since the wafer defect data set is small and difficult to obtain, there is a problem of class imbalance. The transfer learning algorithm can effectively extract the deep feature information of small sample data and identify its type by learning the model and weight parameters that perform well on large-scale data sets.

[0048] The basic idea of ​​transfer learning can be expressed by formula (3), that is, part of the structure of the pre-trained network model is transferred to the new network structure, where Represents the final model training parameters, are the model parameters obtained through pre-training, , are the starting layer and the ending layer of the migration part, respectively. Parameters in the network that need further training except the migration part: (3) In the present invention, the training parameters of the first two convolution groups in the Daranet-53 network are migrated, such as Figure 6 shown.

[0049] In order to make the wafer defect detection network more closely fit the actual characterization of the wafer, the present invention collects various defect samples during the wafer production process, builds a small sample data set of wafer defects, and enhances the data set by various methods such as rotation, offset, and scaling. The terminal fine training is performed on the other parts of the network except the migration parameters, further improving the accuracy of the network for wafer defect detection and achieving better training results. The final training structure diagram of the present invention is as follows: Figure 7 shown.

[0050] In another embodiment, a wafer defect detection IGP (Integrated Graphics Processor) processing module integrates an NPU neural network processing unit, an ARM architecture CPU, a high-speed storage device, and a variety of data transmission interfaces, supports different interface protocols such as PCI, GPIO, and AGP, and can be embedded in a variety of wafer detection equipment motherboards, with an adaptation rate of more than 98%. By embedding the neural network algorithm proposed in the present invention, the wafer surface feature recognition index reaches more than 0.65, the wafer defect missed detection rate is reduced to 7.5%, the wafer defect detection accuracy mAP for the IGP processing unit is increased to 96.6%, and the recognition time for the wafer standard image is shortened to 0.94s, the detection efficiency is increased by 1.8 times, and the detection resolution of wafer defects can reach 100 nanometers. At the same time, in order to verify the effectiveness of the present invention, we selected the commonly used detection algorithms SSD and YOLOv3, based on the same hardware platform, to process the same wafer image, and the obtained detection effect is shown in Table 1.

[0051] It can be seen that the present invention has obvious advantages in detection accuracy, missed detection rate, etc., which shows that the present invention has good accuracy when facing wafer defect detection.

[0052] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principles of the present invention shall be equivalent replacement modes and shall be included in the protection scope of the present invention.

Claims

1. A wafer defect detection method for an IGP processing unit, characterized in that: The following steps are involved: S01: Acquire wafer image; S02: Construct a multi-dimensional and multi-level low-magnification imaging feature recognition network, use a deep convolutional neural network composed of convolution kernels to extract features of different dimensions of the image, introduce a feature pyramid structure, combine features of different levels through top-down paths and lateral connections, and realize the fusion and extraction of multi-level features. On this basis, through the deep forest model and a multi-granularity scanning structure, further process the high-dimensional features extracted by the convolutional neural network model to complete the multi-dimensional and multi-level extraction of wafer defect features; S03: training the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, and using the trained multi-dimensional and multi-level low-magnification imaging feature recognition network to perform wafer defect detection.

2. The wafer defect detection method for an IGP processing unit according to claim 1, characterized in that: The backbone network of the multi-dimensional and multi-level low-magnification imaging feature recognition network is a Darknet-53 network. After the image data is input into the Darknet-53 network, it first passes through two convolutional layers, and then the data is processed by five convolutional groups in sequence. A convolutional layer is used between every two convolutional groups to complete the downsampling operation and extract image feature data. The feature pyramid structure is introduced to obtain the output feature maps of the last three convolution groups in the Darknet-53 network, and three feature maps of different sizes are obtained. The feature map of the deep network passes through a 1×1 convolution layer to make its size consistent with the feature map of the shallow network. Finally, the output feature maps of these three network layers are converted to the same size, and then stacked and fused for feature pyramid processing.

3. The wafer defect detection method for an IGP processing unit according to claim 2, characterized in that: After feature pyramid processing, a multi-granularity cascade forest algorithm is used. First, multi-granularity scanning is performed, and the input feature data is scanned using feature windows of different sizes to generate multi-scale enhanced vectors. Then, in the cascade forest execution stage, the generated multi-scale enhanced vectors are trained layer by layer to predict the wafer defect category distribution, and the generated category distribution vector is connected with the original vector and input into the next cascade layer through the cascade channel.

4. The wafer defect detection method for an IGP processing unit according to claim 1, characterized in that: The model joint training method based on multi-level pre-training and terminal fine training is used to train the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, including: The first level of pre-training is performed on the industrial defect dataset to enable the model to learn some common features of defects in the real world; The second level of pre-training is performed on a public wafer defect dataset, so that the model can learn the subdivided features of wafer defects based on the general defect features; Part of the structure of the pre-trained network model is migrated to the new network structure through the transfer learning algorithm; Perform terminal fine training on other parts of the network except the migration parameters.

5. The wafer defect detection method for an IGP processing unit according to claim 4, characterized in that: Migrate the training parameters of the first two convolutional groups in the Daranet-53 network.

6. The wafer defect detection method for an IGP processing unit according to claim 4, characterized in that: The transfer learning algorithm is: ， in, Represents the final model training parameters, are the model parameters obtained through pre-training, , are the starting layer and the ending layer of the migration part, respectively. These are the parameters in the network that need further training except the migration part.

7. A wafer defect detection system for an IGP processing unit, characterized in that: include: Wafer image acquisition module, acquiring wafer images; A multi-dimensional and multi-level low-magnification imaging feature recognition network construction module is used to build a multi-dimensional and multi-level low-magnification imaging feature recognition network. A deep convolutional neural network composed of convolution kernels is used to extract features of different dimensions of the image. A feature pyramid structure is introduced to combine features of different levels through top-down paths and lateral connections to achieve the fusion and extraction of multi-level features. On this basis, a deep forest model is used with a multi-granularity scanning structure to further process the high-dimensional features extracted by the convolutional neural network model to complete the multi-dimensional and multi-level extraction of wafer defect features. The training detection module trains the constructed multi-dimensional and multi-level low-magnification imaging feature recognition network, and uses the trained multi-dimensional and multi-level low-magnification imaging feature recognition network to perform wafer defect detection.

8. The wafer defect detection system for an IGP processing unit according to claim 7, characterized in that: The backbone network of the multi-dimensional and multi-level low-magnification imaging feature recognition network is a Darknet-53 network. After the image data is input into the Darknet-53 network, it first passes through two convolutional layers, and then the data is processed by five convolutional groups in sequence. A convolutional layer is used between every two convolutional groups to complete the downsampling operation and extract image feature data. The feature pyramid structure is introduced to obtain the output feature maps of the last three convolution groups in the Darknet-53 network, and three feature maps of different sizes are obtained. The feature map of the deep network passes through a 1×1 convolution layer to make its size consistent with the feature map of the shallow network. Finally, the output feature maps of these three network layers are converted to the same size, and then stacked and fused for feature pyramid processing.

9. An IGP processing unit, integrating an NPU neural network processing unit, an ARM architecture CPU, a high-speed storage device, and multiple data transmission interfaces, characterized in that: The NPU neural network processing unit is embedded with the wafer defect detection method for the IGP processing unit as described in any one of claims 1-6.

10. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the wafer defect detection method for an IGP processing unit according to any one of claims 1 to 6 is implemented.

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