Array substrate, flexible display panel and electronic equipment

Abstract

The invention relates to an array substrate, a flexible display panel and electronic equipment, and the array substrate comprises a first pixel circuit which is used for driving a first pixel unit of a preset line to emit light; the second pixel circuit is used for driving the second pixel units of the preset row to emit light; the first scanning driving circuit is used for outputting a scanning signal to the first pixel circuit; the second scanning driving circuit is used for being coupled with a clock signal line, and the second scanning driving circuit is used for outputting a scanning signal to the second pixel circuit; one end of the gating circuit is coupled with the first scanning driving circuit, the other end of the gating circuit is used for being coupled with a clock signal line, and the gating circuit is used for gating the first scanning driving circuit and the clock signal line. The first scanning driving circuit and the second scanning driving circuit share one group of clock signal lines, so that the number of circuits for generating clock signals is reduced, and the complexity of the circuit structure of the array substrate is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a flexible display panel and an electronic device. Background Art

[0002] At present, with the development of flexible display panels, more and more electronic devices have folding functions and are favored by users. However, since different partitions of the display panel need to be turned on and off in different folding states, the circuit structure of the array substrate in the display panel is complicated. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides an array substrate, a display panel and an electronic device.

[0004] According to a first aspect of the present disclosure, an array substrate is provided, the array substrate comprising:

[0005] A first pixel circuit, wherein the first pixel circuit is used to drive a first pixel unit of a preset row to emit light;

[0006] a second pixel circuit, the second pixel circuit being used to drive the second pixel unit of the preset row to emit light;

[0007] a first scan driving circuit, the first scan driving circuit being used to output a scan signal to the first pixel circuit;

[0008] a second scanning driving circuit, the second scanning driving circuit being used to couple with the clock signal line, and the second scanning driving circuit being used to output a scanning signal to the second pixel circuit;

[0009] A gating circuit, one end of which is coupled to the first scan driving circuit, and the other end of which is used to couple to the clock signal line, and the gating circuit is used to select the first scan driving circuit and the clock signal line.

[0010] In some embodiments of the present disclosure, the gating circuit includes at least one first transistor, a first end of the first transistor is coupled to the first scan drive circuit, a second end of the first transistor is coupled to the clock signal line, and a gate of the first transistor is used to couple to an enable signal line.

[0011] In some embodiments of the present disclosure, the clock signal line includes a first clock signal line and a second clock signal line; the first scan drive circuit includes:

[0012] an output circuit, the output circuit being coupled to the second clock signal line through the gating circuit, the output circuit being used to output a scanning signal;

[0013] A control circuit, the control circuit is coupled to the output circuit, the control circuit is coupled to both the first clock signal line and the second clock signal line through the gating circuit, and the control circuit is used to control the opening and closing of the output circuit;

[0014] A storage circuit is coupled to both the output circuit and the control circuit, and is used to keep the voltage of the output circuit unchanged when the control circuit is disconnected from the output circuit.

[0015] In some embodiments of the present disclosure, the number of the first transistors is two, one of the first transistors is coupled between the first clock signal line and the control circuit, and the gate is coupled to the enable signal line; the first end of the other first transistor is coupled to the second clock signal line, the second end is coupled to both the output circuit and the control circuit, and the gate is coupled to the enable signal line.

[0016] In some embodiments of the present disclosure, the output circuit includes:

[0017] a second transistor, wherein a first terminal of the second transistor is used to be coupled to a high-level power line;

[0018] a third transistor, a first end of the third transistor being coupled to the second end of the second transistor, and a second end of the third transistor being coupled to the second clock signal line through the gating circuit;

[0019] The gates of the second transistor and the third transistor are both coupled to the control circuit.

[0020] In some embodiments of the present disclosure, the storage circuit includes:

[0021] A first storage capacitor, wherein the first storage capacitor is coupled between the first terminal and the gate of the second transistor;

[0022] A second storage capacitor is coupled between the first terminal and the gate of the third transistor.

[0023] In some embodiments of the present disclosure, the control circuit includes:

[0024] a fourth transistor, wherein a first end of the fourth transistor is used to couple with an input signal line, a second end of the fourth transistor is coupled with a gate of the third transistor to form a first node, and the gate of the fourth transistor is coupled with the first clock signal line through the gating circuit;

[0025] a fifth transistor, a first terminal of the fifth transistor being coupled to the first node, and a gate of the fifth transistor being coupled to the second clock signal line through the gating circuit;

[0026] a sixth transistor, wherein a first terminal of the sixth transistor is coupled to a second terminal of the fifth transistor, a second terminal of the sixth transistor is used to be coupled to the high-level power line, and a gate of the sixth transistor is coupled to a gate of the second transistor to form a second node;

[0027] a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the second node, a second terminal of the seventh transistor is coupled to the first clock signal line through the gating circuit, and a gate of the seventh transistor is coupled to the first node;

[0028] An eighth transistor, wherein a first end of the eighth transistor is used to couple to a low-level power supply line, a second end of the eighth transistor is coupled to the second node, and a gate of the eighth transistor is coupled to the first clock signal line through the gating circuit.

[0029] In some embodiments of the present disclosure, the first scan driving circuit further includes:

[0030] A voltage stabilizing circuit is coupled between the output circuit and the control circuit, and is used for stabilizing the voltage outputted from the control circuit to the output circuit.

[0031] In some embodiments of the present disclosure, the voltage stabilizing circuit includes:

[0032] A ninth transistor, wherein the ninth transistor is coupled between the first node and the gate of the third transistor, and the gate of the ninth transistor is used to be coupled to the low-level power line.

[0033] According to a second aspect of the present disclosure, a flexible display panel is provided, comprising the array substrate as described above, wherein the flexible display panel comprises a first partition and a second partition, the first pixel circuit is located in the first partition, the second pixel circuit is located in the second partition, and the first partition and the second partition can be folded relative to each other.

[0034] In some embodiments of the present disclosure, the second partition includes a first sub-region and a second sub-region, and the first sub-region and the second sub-region are capable of being folded relative to each other.

[0035] According to a third aspect of the present disclosure, an electronic device is provided, comprising the flexible display panel as described above.

[0036] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0037] The array substrate includes a first pixel circuit, a second pixel circuit, a first scan driving circuit, a second scan driving circuit and a gating circuit, wherein the first scan driving circuit is used to output a scan signal to the first pixel circuit, the second scan driving circuit is used to output a scan signal to the second pixel circuit, and the gating circuit is used to gating the first scan driving circuit and a clock signal line. Since the first scan driving circuit and the second scan driving circuit share a group of clock signal lines, the number of circuits generating clock signals is reduced, thereby reducing the complexity of the circuit structure in the array substrate.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0040] Figure 1-1 It is a schematic diagram of the structure of a double-folding screen electronic device;

[0041] Figure 1-2 It is a structural schematic diagram of an array substrate of a double-folding screen electronic device;

[0042] Figure 2-1 It is a schematic diagram of the structure of a three-fold screen electronic device;

[0043] Figure 2-2 It is a structural schematic diagram of an array substrate of a three-fold screen electronic device;

[0044] Figure 3 is a structural schematic diagram of an array substrate;

[0045] Figure 4 is a structural schematic diagram of an array substrate provided by an exemplary embodiment of the present disclosure;

[0046] Figure 5 is a structural schematic diagram of an array substrate provided by another exemplary embodiment of the present disclosure;

[0047] Figure 6 is a structural schematic diagram of an array substrate provided by another exemplary embodiment of the present disclosure;

[0048] Figure 7 is a structural schematic diagram of an array substrate provided by another exemplary embodiment of the present disclosure;

[0049] Figure 8 is a structural schematic diagram of an array substrate provided by another exemplary embodiment of the present disclosure;

[0050] Fig. 9is a working timing diagram of an array substrate gate driving circuit provided by an exemplary embodiment of the present disclosure;

[0051] Fig.10 is a system block diagram of an electronic device provided by an exemplary embodiment of the present disclosure.

[0052] In the figure:

[0053] 1-first partition; 2-second partition; 10-first scan drive circuit; 11-output circuit; 12-control circuit; 13-storage circuit; 14-voltage stabilizing circuit; 20-second scan drive circuit; 30-selection circuit; Q1-first output transistor; Q2-second output transistor; Q3-first control transistor; Q4-second control transistor; Q5-third control transistor; Q6-fourth control transistor; Q7-fifth control transistor; Q8-voltage stabilizing transistor; Tx1-first transistor; Tx2-first transistor; T2-second transistor; T3-third transistor; T4-fourth transistor; T5-fifth transistor; T6-sixth transistor; T7-seventh transistor; T8-eighth transistor; T9-first transistor Nine transistors; C1-first storage capacitor; C2-second storage capacitor; CK-clock signal line; CK1-first clock signal line; CK2-second clock signal line; CK3-third clock signal line; CK4-fourth clock signal line; En-enable signal line; VGH-high level power line; VGL-low level power line; SCAN(n-1)-input signal line; SCAN(n)-scan signal line; N1-first node; N2-second node; 400-electronic device; 402-processing component; 404-memory; 406-power supply component; 408-multimedia component; 410-audio component; 412-input and output interface; 414-sensor component; 416-communication component; 420-processor. DETAILED DESCRIPTION

[0054] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0055] In the related art, for a double-folding screen electronic device, such as Figure 1-1 and Figure 1-2As shown, the electronic device includes a flexible display panel. The flexible display panel includes a first partition 1 and a second partition 2, the first partition 1 and the second partition 2 can be folded relative to each other and the second partition 2 cannot be folded, thereby forming a double-folding screen electronic device. When the electronic device is in an unfolded state, the first pixel unit in the first partition 1 displays half of the picture, and the second pixel unit in the second partition 2 displays half of the picture. When the electronic device is in a folded state, the first partition 1 is closed and the second partition 2 displays the entire picture. That is, the second partition 2 is a constantly lit partition, which is always in a lit state when displaying the picture. The first pixel circuit and the second pixel circuit in the first partition 1 and the second partition 2 both include multiple rows, and each row of pixel circuits in each partition corresponds to an array substrate gate drive circuit (GateDriven on Array, GOA), which is used to output a scan signal to the pixel circuit (the figure shows an array substrate gate drive circuit corresponding to a row of pixel circuits). The array substrate gate drive circuit can be located in the first partition 1 or the second partition 2, or in the frame of the flexible display panel. When driving a first pixel circuit of a row, the first scan drive circuit 10 of the array substrate gate drive circuit in the first partition 1 outputs a scan signal through the first clock signal line CK1 and the second clock signal line CK2. When driving a second pixel circuit of a row, the second scan drive circuit 20 of the array substrate gate drive circuit in the second partition 2 outputs a scan signal through the third clock signal line CK3 and the fourth clock signal line CK4. Since the array substrate uses four clock signal lines to operate the first scan drive circuit 10 and the second scan drive circuit 20, the circuit structure of the array substrate is complicated.

[0056] For tri-fold screen electronic devices, such as Figure 2-1 and Figure 2-2 As shown, similar to the double-folding screen electronic device, the first partition 1 and the second partition 2 can be folded relative to each other. Different from the double-folding screen electronic device, the second partition 2 is a foldable structure, thus forming a three-fold screen electronic device. When the electronic device is in the unfolded state, the first partition 1 displays 2 / 3 of the screen, and the second partition 2 displays 1 / 3 of the screen. When the electronic device is in the folded state, the first partition 1 is closed, and the second partition 2 displays the entire screen. The coupling method of the first scanning drive circuit 10 and the second scanning drive circuit 20 of the three-fold screen electronic device and the clock signal line is the same as that of the double-folding screen electronic device, which will not be repeated here.

[0057] For double-folding screen and triple-folding screen electronic devices, when the electronic device is in the unfolded state, the first clock signal in the first clock signal line CK1 is the same as the third clock signal of the third clock signal line CK3, and the second clock signal in the second clock signal line CK2 is the same as the fourth clock signal of the fourth clock signal line CK4. When the electronic device is in the folded state, the first clock signal line CK1 and the second clock signal line CK2 stop outputting the first clock signal and the second clock signal, so that the first scan drive circuit 10 stops outputting the scan signal to the first pixel circuit. Since the first clock signal and the second clock signal use a set of timing control, and the third clock signal and the fourth clock signal use a set of timing control, the array substrate gate drive circuit requires a total of two sets of timing control.

[0058] For electronic devices with four-fold screens, five-fold screens, and even N-fold screens, the number of required clock signal lines increases as the number of partitions increases, greatly increasing the complexity of the circuit structure of the array substrate. For example, for electronic devices with four-fold screens and five-fold screens, there are two first partitions 1, and a total of six clock signal lines are required to drive a row of array substrate gate drive circuits. For electronic devices with N-1 fold screens and N fold screens, there are (N-1) / 2 first partitions 1, and a total of N+1 clock signal lines are required to drive a row of array substrate gate drive circuits. Wherein N is a positive odd number.

[0059] Since each clock signal is outputted through a display driver IC (DDIC) in the flexible display panel, an increase in the number of clock signals results in an increase in the number of pins of the required display driver IC.

[0060] In related technologies, such as Figure 3As shown, the first scan drive circuit 10 of the array substrate gate drive circuit includes a first output transistor Q1, a second output transistor Q2, a first control transistor Q3, a second control transistor Q4, a third control transistor Q5, a fourth control transistor Q6, a fifth control transistor Q7, a voltage regulator transistor Q8, a first storage capacitor C1 and a second storage capacitor C2. The first output transistor Q1 is coupled between the high-level power line VGH and the second output transistor Q2. The other end of the second output transistor Q2 is coupled to the second clock signal line CK2. The coupling end of the first output transistor Q1 and the second output transistor Q2 serves as the output end of the first scan drive circuit 10, and the signal line where the output end is located is the scan signal line SCAN (n) of the first scan drive circuit 10, which is used to output the scan signal. The first control transistor Q3 is coupled between the input signal line SCAN (n-1) and the gate of the second output transistor Q2, and the gate is coupled to the first clock signal line CK1. The second control transistor Q4 is coupled between the gate of the second output transistor Q2 and the third control transistor Q5, and the gate is coupled to the second clock signal line CK2. The other end of the third control transistor Q5 is coupled to the high-level power line VGH, and the gate is coupled to the gate of the first output transistor Q1. The fourth control transistor Q6 is coupled between the gate of the first output transistor Q1 and the first clock signal line CK1, and the gate is coupled to the gate of the second output transistor Q2. The fifth control transistor Q7 is coupled between the low-level power line VGL and the gate of the first output transistor Q1, and the gate is coupled to the first clock signal line CK1. One end of the voltage regulator transistor Q8 is coupled to the gate of the second output transistor Q2, and the other end is coupled to both the first control transistor Q3 and the second control transistor Q4, and the gate is coupled to the low-level power line. The first scan drive circuit 10 outputs a scan signal to the first pixel circuit of the preset row through the output end according to the input signal of the input signal line SCAN (n-1), the first clock signal of the first clock signal line CK1, and the second clock signal of the second clock signal line CK2. The circuit structure of the second scan drive circuit 20 is the same as that of the first scan drive circuit 10, which will not be repeated here.

[0061] Taking the double-fold screen and the triple-fold screen as an example, the difference between the second scan drive circuit 20 and the first scan drive circuit 10 is as follows: the second output transistor Q2 is coupled to the fourth clock signal line CK4 instead of the second clock signal line CK2. The gate of the first control transistor Q3 is coupled to the third clock signal line CK3 instead of the first clock signal line CK1. The gate of the second control transistor Q4 is coupled to the fourth clock signal line CK4 instead of the second clock signal line CK2. The fourth control transistor Q6 is coupled to the third clock signal line CK3 instead of the first clock signal line CK1. The gate of the fifth control transistor Q7 is coupled to the third clock signal line CK3 instead of the first clock signal line CK1. Since the first scan drive circuit 10 and the second scan drive circuit 20 require a total of four clock signals to operate, the circuit structure in the array substrate is complicated.

[0062] Based on this, the present disclosure provides an array substrate, wherein the first scan drive circuit is coupled to the clock signal line through a gating circuit. The second scan drive circuit is directly coupled to the clock signal line. When the electronic device is in an unfolded state, the gating circuit connects the first scan drive circuit to the clock signal line to output a scan signal to the first pixel circuit. When the electronic device is in a folded state, the gating circuit disconnects the first scan drive circuit from the clock signal line to stop outputting a scan signal to the first pixel circuit. By adding a gating circuit to control the on-off between the first scan drive circuit and the clock signal line, the first scan drive circuit and the second scan drive circuit share a set of clock signal lines without affecting the display of the picture. Since the number of circuits generating clock signals is reduced, the complexity of the circuit structure in the array substrate is reduced.

[0063] like Figure 4As shown, an exemplary embodiment of the present disclosure provides an array substrate, including a first pixel circuit, a second pixel circuit, a first scan driving circuit 10, a second scan driving circuit 20 and a gating circuit 30. The first pixel circuit is used to drive the first pixel unit of a preset row to emit light. The second pixel circuit is used to drive the second pixel unit of a preset row to emit light. The first scan driving circuit 10 is coupled to the first pixel circuit and is used to output a scan signal to the first pixel circuit. The second scan driving circuit 20 is coupled to the second pixel circuit and is used to couple with the clock signal line CK and output a scan signal to the second pixel circuit. One end of the gating circuit 30 is coupled to the first scan driving circuit 10, the other end is used to couple with the clock signal line CK, and the control end is used to couple with the enable signal line En, and is used to gating the first scan driving circuit 10 and the clock signal line CK according to the enable signal of the enable signal line En. When the coupled first scan driving circuit 10 needs to output a scan signal, the enable signal is in an enable state, and the gating circuit 30 is turned on. When the coupled first scan driving circuit 10 needs to stop outputting a scan signal, the enable signal is in a disable state, and the gating circuit 30 is turned off. The first pixel circuit and the second pixel circuit may be located in different partitions. One first pixel circuit corresponds to at least one first pixel unit. One second pixel circuit corresponds to at least one second pixel unit. For the first scan drive circuit 10 and the second scan drive circuit 20 with different structures, the number of clock signal lines CK is different. When the number of partitions where the first pixel circuit is located is multiple, the number of the first scan drive circuit 10 and the gating circuit 30 is the same as the number of the partitions where the first pixel circuit is located.

[0064] In the gate driving circuit provided in this embodiment, the array substrate includes a first pixel circuit, a second pixel circuit, a first scanning driving circuit, a second scanning driving circuit and a gating circuit, wherein the first scanning driving circuit is used to output a scanning signal to the first pixel circuit, the second scanning driving circuit is used to output a scanning signal to the second pixel circuit, and the gating circuit is used to gating the first scanning driving circuit and the clock signal line. Since the first scanning driving circuit and the second scanning driving circuit share a group of clock signal lines, the number of circuits generating clock signals is reduced, thereby reducing the complexity of the circuit structure in the array substrate.

[0065] Exemplarily, when the number of clock signal lines CK is one, although adding the enable signal line En will not reduce the total number of signal lines, since the enable signal in the enable signal line En is generated according to the folding state of the electronic device, the circuit structure for generating the enable signal is simpler than the circuit structure for generating the clock signal. When the number of clock signal lines CK is two, two circuits for generating clock signals can be reduced. When the number of clock signal lines CK is M, M circuits for generating clock signals can be reduced. Wherein, M is a positive integer greater than 1.

[0066] In one embodiment, the gating circuit 30 includes at least one first transistor. The first end of the first transistor is coupled to the first scan driving circuit 10, the second end is coupled to the clock signal line CK, and the gate is used to couple to the enable signal line En. The number of the first transistors is the same as the number of the clock signal lines CK.

[0067] In this embodiment, the first transistor is used as the gating circuit, the control of the gating circuit is simple, and the complexity of the gating circuit is reduced.

[0068] In one embodiment, if Figure 5 As shown, the clock signal line CK includes a first clock signal line CK1 and a second clock signal line CK2. The first scan driving circuit 10 includes an output circuit 11, a control circuit 12 and a storage circuit 13. The output circuit 11 of the first scan driving circuit 10 is coupled to the second clock signal line CK2 through a gate circuit 30, and is used to output a scan signal. The control circuit 12 of the first scan driving circuit 10 is coupled to the output circuit 11, and is coupled to both the first clock signal line CK1 and the second clock signal line CK2 through the gate circuit 30, and is used to control the opening and closing of the output circuit 11. The storage circuit 13 of the first scan driving circuit 10 is coupled to the output circuit 11 and the control circuit 12, and is used to keep the voltage of the output circuit 11 unchanged when the control circuit 12 is disconnected from the output circuit 11. The second scan driving circuit 20 includes an output circuit 11, a control circuit 12 and a storage circuit 13. The output circuit 11 of the second scan driving circuit 20 is directly coupled to the second clock signal line CK2, and the control circuit 12 of the second scan driving circuit 20 is directly coupled to the first clock signal line CK1 and the second clock signal line CK2.

[0069] In this embodiment, the output circuit is controlled by the control circuit, and the output circuit can output the required scanning signal to drive the first pixel circuit. The voltage of the output circuit is stabilized by the voltage stabilizing circuit to keep the voltage of the output circuit unchanged when the control circuit is disconnected from the output circuit. The output circuit is coupled to the second clock signal line through the gating circuit, and the control circuit is coupled to the first clock signal line and the second clock signal line through the gating circuit, so that the gating circuit can control whether the output circuit outputs the scanning signal to the corresponding pixel circuit. The first clock signal line and the second clock signal line are connected or disconnected with the control circuit and the output circuit through the gating circuit to stop outputting the scanning signal when the corresponding pixel circuit does not need to display, thereby reducing the power consumption of the array substrate.

[0070] In one embodiment, if Figure 6As shown, the output circuit 11 includes a second transistor T2 and a third transistor T3. The first end of the second transistor T2 is used to couple with the high-level power line VGH. The first end of the third transistor T3 is coupled with the second end of the second transistor T2 as the output end of the first scanning circuit 10, and the signal line where the output end is located is the scanning signal line SCAN (n), which is used to output the scanning signal, and the second end of the third transistor T3 is coupled with the second clock signal line CK2 through the gating circuit 30. The gates of the second transistor T2 and the third transistor T3 are both coupled with the control circuit 12.

[0071] In this embodiment, the output circuit is formed by the second transistor and the third transistor, and a high level or a second clock signal is output in different situations to drive the pixel circuit, thereby displaying a picture.

[0072] In one embodiment, the control circuit 12 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The first end of the fourth transistor T4 is used to couple with the input signal line SCAN (n-1), the second end is coupled with the gate of the third transistor T3 to form a first node N1, and the gate is coupled with the first clock signal line CK1 through the gating circuit 30. The first end of the fifth transistor T5 is coupled with the first node N1, and the gate is coupled with the second clock signal line CK2 through the gating circuit 30. The first end of the sixth transistor T6 is coupled with the second end of the fifth transistor T5, the second end is used to couple with the high level power line VGH, and the gate is coupled with the gate of the second transistor T2 to form a second node N2. The first end of the seventh transistor T7 is coupled with the second node N2, the second end is coupled with the first clock signal line CK1 through the gating circuit 30, and the gate is coupled with the first node N1. The first end of the eighth transistor T8 is used to couple with the low level power line VGL, the second end is coupled with the second node N2, and the gate is coupled with the first clock signal line CK1 through the gating circuit 30. The input signal line SCAN(n-1) can be the scanning signal line SCAN(n) of the first scanning driving circuit 10 of the previous row.

[0073] In this embodiment, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are used as the control circuit to control the second transistor and the third transistor in the output circuit to output the scanning signal, thereby driving the pixel circuit of the preset row to operate and display the picture.

[0074] In one embodiment, the storage circuit 13 includes a first storage capacitor C1 and a second storage capacitor C2. The first storage capacitor C1 is coupled between the first terminal and the gate of the second transistor T2. The second storage capacitor C2 is coupled between the first terminal and the gate of the third transistor T3.

[0075] In this embodiment, the first storage capacitor can keep the voltage of the first end and the gate of the second transistor unchanged when the control circuit is disconnected from the output circuit. The second storage capacitor can keep the voltage of the first end and the gate of the third transistor unchanged when the control circuit is disconnected from the output circuit. By using the first storage capacitor and the second storage capacitor as the storage circuit, the scanning signal of the output end can be maintained, thereby improving the reliability of the operation of the array substrate.

[0076] In one embodiment, if Figure 7 As shown, the first scan driving circuit 10 further includes a voltage stabilizing circuit 14. The voltage stabilizing circuit 14 is coupled between the output circuit 11 and the control circuit 12, and is used to stabilize the voltage outputted from the control circuit 12 to the output circuit 11.

[0077] In this embodiment, the voltage at the control end of the output circuit can be stabilized by the voltage stabilizing circuit, thereby preventing the output circuit from being mistakenly turned on or off, thereby improving the reliability of the operation of the array substrate.

[0078] In one embodiment, if Figure 8 As shown, the voltage stabilizing circuit 14 includes a ninth transistor T9. The ninth transistor T9 is coupled between the first node N1 and the gate of the third transistor T3, and the gate is used to be coupled to the low level power line VGL.

[0079] In this embodiment, the gate voltage of the third transistor can be stabilized by the ninth transistor, so that the third transistor can be prevented from being turned on or off by mistake, thereby improving the reliability of the operation of the array substrate.

[0080] In one embodiment, if Figure 6 and Figure 8As shown, the number of first transistors is two. A first transistor Tx1 is coupled between the first clock signal line CK1 and the control circuit 12, and the gate is coupled to the enable signal line En. The first end of another first transistor Tx2 is coupled to the second clock signal line CK2, the second end is coupled to both the output circuit 11 and the control circuit 12, and the gate is coupled to the enable signal line En. Exemplarily, the first end of the first transistor Tx1 is coupled to the first clock signal line CK1, the second end is coupled to the gate of the fourth transistor T4, the second end of the seventh transistor T7 and the gate of the eighth transistor T8, and the gate is coupled to the enable signal line En. The first end of the first transistor Tx2 is coupled to the second clock signal line CK2, the second end is coupled to the second end of the third transistor T3 and the gate of the fifth transistor T5, and the gate is coupled to the enable signal line En. The enable signal in the enable signal line En is used to turn on and off the first transistor Tx1 and the first transistor Tx2, that is, to control the gating circuit 30 to be turned on and off. When the electronic device is in the unfolded state, the enable signal in the enable signal line En turns on the first transistor Tx1 and the first transistor Tx2, that is, turns on the gating circuit 30. When the electronic device is in the folded state, the enable signal in the enable signal line En turns off the first transistor Tx1 and the first transistor Tx2, that is, turns off the gating circuit 30. For N-1 folding screen and N folding screen electronic devices, the number of enable signal lines En is (N-1) / 2, and N is a positive odd number.

[0081] In this embodiment, the number of the first transistors is two, and only one enable signal is needed to control the opening and closing of the gating circuit, thereby reducing the complexity of the array substrate circuit.

[0082] Exemplarily, the first transistor Tx1, the first transistor Tx2, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 may be N-type transistors or P-type transistors. The first end of each transistor may be a source or a drain, and the second end may be a drain or a source.

[0083] It is understandable that the first scan driving circuit 10 and the second scan driving circuit 20 in the present disclosure are not limited to the above-mentioned circuit structure, but can also be other circuit structures capable of outputting scan signals, and the selection circuit 30 only needs to be coupled between the first scan driving circuit 10 and the clock signal line CK.

[0084] The working principle of the array substrate is described in detail below, taking a double-folding screen electronic device and a triple-folding screen electronic device as examples. Figure 4As shown, the array substrate includes a first pixel circuit, a second pixel circuit, a first scan drive circuit 10, a second scan drive circuit 20 and a gating circuit 30. The first scan drive circuit 10 is coupled to the clock signal line CK through the gating circuit 30. The second scan drive circuit 20 is directly coupled to the clock signal line CK. When the electronic device is in the unfolded state, the gating circuit 30 is turned on. The first scan drive circuit 10 outputs a scan signal to the first pixel circuit. The second scan drive circuit 20 outputs a scan signal to the second pixel circuit. The scan signal is output by the first scan drive circuit 10 and the second scan drive circuit 20 in each row so that the first pixel circuit and the second pixel circuit display a picture. When the electronic device is in the folded state, the gating circuit 30 is turned off. The first scan drive circuit 10 stops outputting a scan signal to the first pixel circuit. The second scan drive circuit 20 outputs a scan signal to the second pixel circuit. Since the first scan drive circuit 10 in each row stops outputting a scan signal, and the second scan drive circuit 20 in each row outputs a scan signal, only the second pixel circuit displays a picture.

[0085] The working principle of the first scanning driving circuit 10 opened by the gating circuit 30 is described in detail below. Figure 8 and Fig. 9 As shown, the clock signal line CK includes a first clock signal line CK1 and a second clock signal line CK2, and the first scan driving circuit 10 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first storage capacitor C1 and a second storage capacitor C2. The first end of the second transistor T2 is coupled to the high-level power line VGH. The first end of the third transistor T3 is coupled to the second end of the second transistor T2 to output the scan signal, and the second end is coupled to the second clock signal line CK2 through the first transistor Tx2. The first end of the fourth transistor T4 is coupled to the input signal line SCAN (n-1), and the second end is coupled to the gate of the third transistor T3 to form a first node N1, and the gate is coupled to the first clock signal line CK1 through the first transistor Tx1. The first end of the fifth transistor T5 is coupled to the first node N1, and the gate is coupled to the second clock signal line CK2 through the first transistor Tx2. The first end of the sixth transistor T6 is coupled to the second end of the fifth transistor T5, the second end is coupled to the high level power line VGH, and the gate is coupled to the gate of the second transistor T2 to form a second node N2. The first end of the seventh transistor T7 is coupled to the second node N2, the second end is coupled to the first clock signal line CK1 through the first transistor Tx1, and the gate is coupled to the first node N1. The first end of the eighth transistor T8 is coupled to the low level power line VGL, the second end is coupled to the second node N2, and the gate is coupled to the first clock signal line CK1 through the first transistor Tx1. SCAN(n-1)is the input voltage of the input signal line SCAN(n-1), V CK1 is the first clock voltage of the first clock signal line CK1, V CK2 is the second clock voltage of the second clock signal line CK2, V SCAN(n) is the scan voltage of the scan signal line SCAN(n).

[0086] Taking each transistor as a P-type transistor as an example, the operation of the first scan driving circuit 10 includes three stages from t1 to t3.

[0087] Phase t1: Input voltage V of input signal line SCAN(n-1) SCAN(n-1) and the first clock voltage V of the first clock signal line CK1 CK1 is low level, the second clock voltage V CK2 is high level. Since the first clock voltage V CK1 The fourth transistor T4 and the eighth transistor T8 are turned on, and the voltages of the first node N1 and the second node N2 are at a low level. The second transistor T2 and the sixth transistor T6 are turned on because the second node N2 is at a low level. The third transistor T3 and the seventh transistor T7 are turned on because the first node N1 is at a low level. Since the second transistor T2 and the third transistor T3 are turned on, the scanning voltage V SCAN(n) is high level. Since the second clock voltage V CK2 is high level, and the fifth transistor T5 is turned off.

[0088] Phase t2: At the beginning, the input voltage V of the input signal line SCAN(n-1) SCAN(n-1) , the first clock voltage V of the first clock signal line CK1 CK1 and the second clock voltage V of the second clock signal line CK2 CK2 is high level. Since the first clock voltage V CK1 = is high level, the fourth transistor T4 and the eighth transistor T8 are turned off. Due to the holding effect of the second storage capacitor C2, the voltage of the first node N1 is low level, and the third transistor T3 and the seventh transistor T7 are turned on. The first clock voltage V CK1 The voltage of the second node N2 is adjusted to a high level through the seventh transistor T7, and the second transistor T2 and the sixth transistor T6 are turned off. CK2 is high level, and the fifth transistor T5 is turned off. Since the third transistor T3 is turned on, the scanning voltage V SCAN(n) is high level.

[0089] During the intermediate process, the second clock voltage V CK2 is low level, the input voltage V of the input signal line SCAN(n-1) SCAN(n-1) and the first clock voltage V of the first clock signal line CK1 CK1 is high level. Since the first clock voltage V CK1 = is high level, the fourth transistor T4 and the eighth transistor T8 are turned off. Due to the holding effect of the second storage capacitor C2, the voltage of the first node N1 is low level, and the third transistor T3 and the seventh transistor T7 are turned on. The first clock voltage V CK1 The voltage of the second node N2 is maintained at a high level by the seventh transistor T7, and the second transistor T2 and the sixth transistor T6 are turned off. CK2 is low level, and the fifth transistor T5 is turned on. Since the third transistor T3 is turned on, the scanning voltage V SCAN(n) becomes a low level.

[0090] During the end process, the input voltage V of the input signal line SCAN(n-1) SCAN(n-1) , the first clock voltage V of the first clock signal line CK1 CK1 and the second clock voltage V of the second clock signal line CK2 CK2 is high level. Since the first clock voltage V CK1 = is high level, the fourth transistor T4 and the eighth transistor T8 are turned off. Due to the holding effect of the second storage capacitor C2, the voltage of the first node N1 is low level, and the third transistor T3 and the seventh transistor T7 are turned on. The first clock voltage V CK1 The voltage of the second node N2 is maintained at a high level by the seventh transistor T7, and the second transistor T2 and the sixth transistor T6 are turned off. CK2 is high level, and the fifth transistor T5 is turned off. Since the third transistor T3 is turned on, the scanning voltage V SCAN(n) becomes high level.

[0091] Phase t3: During the start process, the input voltage V of the input signal line SCAN(n-1) SCAN(n-1) and the second clock voltage V of the second clock signal line CK2 CK2 is high level, the first clock voltage V CK1 is low level. Since the first clock voltage V CK1The fourth transistor T4 and the eighth transistor T8 are turned on, the voltage of the first node N1 is high, and the voltage of the second node N2 is low. The second transistor T2 and the sixth transistor T6 are turned on because the second node N2 is low. The third transistor T3 and the seventh transistor T7 are turned off because the first node N1 is high. Since the second transistor T2 is turned on, the scanning voltage V SCAN(n) Maintained at a high level. Since the second clock voltage V CK2 is high level, and the fifth transistor T5 is turned off.

[0092] In the first intermediate process, the input voltage V of the input signal line SCAN(n-1) SCAN(n-1) , the first clock voltage V of the first clock signal line CK1 CK1 and the second clock voltage V of the second clock signal line CK2 CK2 is high level. Since the first clock voltage V CK1 The fourth transistor T4 and the eighth transistor T8 are turned off. Due to the holding effect of the second storage capacitor C2, the voltage of the first node N1 is high, and the third transistor T3 and the seventh transistor T7 are turned off. Due to the holding effect of the first storage capacitor C1, the voltage of the second node N2 is low, and the second transistor T2 and the sixth transistor T6 are turned on because the second node N2 is low. Since the second transistor T2 is turned on, the scanning voltage V SCAN(n) Maintained at a high level. Since the second clock voltage V CK2 is high level, and the fifth transistor T5 is turned off.

[0093] In the second intermediate process, the second clock voltage V CK2 is low level, the input voltage V of the input signal line SCAN(n-1) SCAN(n-1) and the first clock voltage V of the first clock signal line CK1 CK1 is high level. Since the first clock voltage V CK1 = is high, the fourth transistor T4 and the eighth transistor T8 are turned off. Due to the holding effect of the first storage capacitor C1, the voltage of the second node N2 is low, and the second transistor T2 and the sixth transistor T6 are turned on because the second node N2 is low. CK2 is low level, the fifth transistor T5 is turned on, and the voltage of the first node N1 is high level. Since the voltage of the first node N1 is high level, the third transistor T3 and the seventh transistor T7 are turned off. Since the second transistor T2 is turned on, the scanning voltage V SCAN(n) Keep it at high level.

[0094] During the end process, the input voltage V of the input signal line SCAN(n-1) SCAN(n-1) , the first clock voltage V of the first clock signal line CK1 CK1 and the second clock voltage V of the second clock signal line CK2 CK2 is high level. Since the first clock voltage V CK1 =The voltage of the second node N2 is at a low level due to the holding effect of the first storage capacitor C1, and the second transistor T2 and the sixth transistor T6 are turned on because the second node N2 is at a low level. The voltage of the first node N1 is at a high level due to the holding effect of the second storage capacitor C2, and the third transistor T3 and the seventh transistor T7 are turned off. CK2 is high level, and the fifth transistor T5 is turned off. Since the second transistor T2 is turned on, the scanning voltage V SCAN(n) Keep it at high level.

[0095] An exemplary embodiment of the present disclosure provides a flexible display panel, comprising the array substrate as described above. The flexible display panel comprises a first partition 1 and a second partition 2, wherein a first pixel circuit is located in the first partition 1, and a second pixel circuit is located in the second partition 2, and the first partition 1 and the second partition 2 can be folded relative to each other.

[0096] In one embodiment, the second partition 2 includes a first sub-area and a second sub-area, and the first sub-area and the second sub-area can be folded relative to each other. It can be understood that the second display screen can also include a third sub-area, a fourth sub-area, and the like.

[0097] In an exemplary embodiment, an electronic device is provided, and the electronic device is, for example, a mobile phone, a laptop computer, a tablet computer, a wearable device, etc.

[0098] refer to Fig.10 As shown, electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0099] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0100] The memory 404 is configured to store various types of data to support operations on the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, videos, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0101] The power supply component 406 provides power to the various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0102] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera module and / or a rear camera module. When the electronic device 400 is in an operating mode, such as a shooting mode or a video mode, the front camera module and / or the rear camera module may receive external multimedia data. Each front camera module and the rear camera module may be a fixed optical lens system or have a focal length and optical zoom capability. Among them, the screen includes a flexible display panel as described above. Through the gating circuit in the flexible display panel, the number of circuits that generate clock signals is reduced, thereby reducing the complexity of the circuit structure in the array substrate and reducing the border of the flexible display panel.

[0103] The audio component 410 is configured to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), and when the electronic device 400 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 404 or sent via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0104] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0105] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of components, such as the display and keypad of the electronic device 400, and the sensor assembly 414 can also detect the position change of the electronic device 400 or a component of the electronic device 400, the presence or absence of user contact with the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and the temperature change of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0106] The communication component 416 is configured to facilitate wired or wireless communication between the electronic device 400 and other terminals. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0107] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0108] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0109] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0110] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises: A first pixel circuit, wherein the first pixel circuit is used to drive a first pixel unit of a preset row to emit light; a second pixel circuit, the second pixel circuit being used to drive the second pixel unit of the preset row to emit light; a first scan driving circuit, the first scan driving circuit being used to output a scan signal to the first pixel circuit; a second scanning driving circuit, the second scanning driving circuit being used to couple with the clock signal line, and the second scanning driving circuit being used to output a scanning signal to the second pixel circuit; A gating circuit, one end of which is coupled to the first scan driving circuit, and the other end of which is used to couple to the clock signal line, and the gating circuit is used to select the first scan driving circuit and the clock signal line.

2. The array substrate according to claim 1, characterized in that: The gating circuit includes at least one first transistor, a first end of the first transistor is coupled to the first scan driving circuit, a second end of the first transistor is coupled to the clock signal line, and a gate of the first transistor is used to couple to an enable signal line.

3. The array substrate according to claim 2, characterized in that: The clock signal line includes a first clock signal line and a second clock signal line; the first scan drive circuit includes: an output circuit, the output circuit being coupled to the second clock signal line through the gating circuit, the output circuit being used to output a scanning signal; A control circuit, the control circuit is coupled to the output circuit, the control circuit is coupled to both the first clock signal line and the second clock signal line through the gating circuit, and the control circuit is used to control the opening and closing of the output circuit; A storage circuit is coupled to both the output circuit and the control circuit, and is used to keep the voltage of the output circuit unchanged when the control circuit is disconnected from the output circuit.

4. The array substrate according to claim 3, characterized in that: There are two first transistors, one of which is coupled between the first clock signal line and the control circuit, and its gate is coupled to the enable signal line; the first end of the other first transistor is coupled to the second clock signal line, the second end is coupled to both the output circuit and the control circuit, and its gate is coupled to the enable signal line.

5. The array substrate according to claim 3, characterized in that: The output circuit comprises: a second transistor, wherein a first terminal of the second transistor is used to be coupled to a high-level power line; a third transistor, a first end of the third transistor being coupled to the second end of the second transistor, and a second end of the third transistor being coupled to the second clock signal line through the gating circuit; The gates of the second transistor and the third transistor are both coupled to the control circuit.

6. The array substrate according to claim 5, characterized in that: The storage circuit comprises: A first storage capacitor, wherein the first storage capacitor is coupled between the first terminal and the gate of the second transistor; A second storage capacitor is coupled between the first terminal and the gate of the third transistor.

7. The array substrate according to claim 5, characterized in that: The control circuit comprises: a fourth transistor, wherein a first end of the fourth transistor is used to couple with an input signal line, a second end of the fourth transistor is coupled with a gate of the third transistor to form a first node, and the gate of the fourth transistor is coupled with the first clock signal line through the gating circuit; a fifth transistor, a first terminal of the fifth transistor being coupled to the first node, and a gate of the fifth transistor being coupled to the second clock signal line through the gating circuit; a sixth transistor, wherein a first terminal of the sixth transistor is coupled to a second terminal of the fifth transistor, a second terminal of the sixth transistor is used to be coupled to the high-level power line, and a gate of the sixth transistor is coupled to a gate of the second transistor to form a second node; a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the second node, a second terminal of the seventh transistor is coupled to the first clock signal line through the gating circuit, and a gate of the seventh transistor is coupled to the first node; An eighth transistor, wherein a first end of the eighth transistor is used to couple to a low-level power supply line, a second end of the eighth transistor is coupled to the second node, and a gate of the eighth transistor is coupled to the first clock signal line through the gating circuit.

8. The array substrate according to claim 7, characterized in that: The first scanning driving circuit further includes: A voltage stabilizing circuit is coupled between the output circuit and the control circuit, and is used for stabilizing the voltage outputted from the control circuit to the output circuit.

9. The array substrate according to claim 8, characterized in that: The voltage stabilizing circuit comprises: A ninth transistor, wherein the ninth transistor is coupled between the first node and the gate of the third transistor, and the gate of the ninth transistor is used to be coupled to the low-level power line.

10. A flexible display panel, characterized in that: Comprising the array substrate as described in any one of claims 1 to 9, the flexible display panel comprises a first partition and a second partition, the first pixel circuit is located in the first partition, the second pixel circuit is located in the second partition, and the first partition and the second partition can be folded relative to each other.

11. The flexible display panel according to claim 10, characterized in that: The second partition includes a first sub-region and a second sub-region, and the first sub-region and the second sub-region are capable of being folded relative to each other.

12. An electronic device, characterized in that: Comprising the flexible display panel as claimed in claim 10 or 11.

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