Data transmission circuit, compensation method and storage device

Abstract

The embodiment of the invention provides a data transmission circuit, a compensation method and a storage device. The data transmission circuit comprises a receiving circuit, a sampling circuit and a compensation circuit. The receiving circuit is configured to receive input data, compare a voltage difference between the input data and a reference voltage, and output a first signal and a first differential signal which are mutually differential. The sampling circuit is configured to sample a first signal and a first differential signal in response to a sampling clock, and output a sampled signal. The compensation circuit is connected with the receiving circuit and is configured to perform mismatch compensation on the receiving circuit based on device mismatch of the receiving circuit.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a data transmission circuit, a compensation method, and a storage device. Background Art

[0002] Memory devices are one of the most widely used semiconductor devices. Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device can store one of two states, which are usually represented by logic 1 or logic 0. In other devices, more than two states can be stored. In order to access the stored information, the components of the device can read or sense at least one stored state in the memory device. In order to store information, the components of the device can write or program the state in the memory device.

[0003] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods of time even in the absence of external power. Volatile memory devices (e.g., DRAM) may lose their stored state over time unless they are periodically refreshed by an external power source. Summary of the invention

[0004] The embodiments of the present disclosure provide a data transmission circuit, a compensation method, and a storage device, which are at least beneficial to improving the quality of a sampling signal output by a sampling circuit.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a data transmission circuit, including: a receiving circuit, configured to receive input data and compare the voltage difference between the input data and a reference voltage, and output a first signal and a first differential signal that are differential with each other; a sampling circuit, configured to sample the first signal and the first differential signal in response to a sampling clock, and output a sampling signal; a compensation circuit, connected to the receiving circuit, and configured to perform mismatch compensation on the receiving circuit based on device mismatch of the receiving circuit.

[0006] In some embodiments, the receiving circuit includes: a first amplifier circuit, configured to compare and amplify the voltage difference between the input data and the reference voltage, and output a second signal and a second differential signal that are differential with each other; a second amplifier circuit, configured to compare and amplify the voltage difference between the second signal and the second differential signal, and output the first signal and the first differential signal; the compensation circuit is configured to perform mismatch compensation on the receiving circuit based at least on a first device mismatch of the first amplifier circuit or a second device mismatch of the second amplifier circuit.

[0007] In some embodiments, the compensation circuit is connected to a node outputting the second signal and / or the second differential signal; the compensation circuit is configured to provide a compensation current to the node outputting the second signal and / or the second differential signal based at least on the first device mismatch.

[0008] In some embodiments, the compensation circuit is further configured to provide a compensation current to a node outputting the second signal and / or the second differential signal based on the second device mismatch.

[0009] In some embodiments, the compensation circuit is configured to provide a compensation current to the receiving circuit for mismatch compensation, and further to make the magnitude of the compensation current for mismatch compensation of the receiving circuit adjustable in response to a control signal.

[0010] In some embodiments, the compensation circuit includes: at least two sub-compensation circuits connected in parallel, each of the sub-compensation circuits determining whether to connect the receiving circuit in response to a corresponding control code; wherein all the control codes constitute a control signal, and each of the sub-compensation circuits is configured to provide a compensation current to the receiving circuit.

[0011] In some embodiments, the control signal is provided by a mode register.

[0012] In some embodiments, the sub-compensation circuit includes: a switch and a current source connected in series between an operating power supply and the receiving circuit; wherein the switch is turned on or off in response to the control code.

[0013] In some embodiments, the current source is further configured to adjust the magnitude of the compensation current provided to the receiving circuit in response to a preset level, and the magnitude of the preset level is adjustable.

[0014] In some embodiments, the sub-compensation circuit includes: a voltage generating circuit configured to, in response to a selection signal, generate a voltage having the preset level corresponding to the selection signal.

[0015] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a compensation method, which can be applied to the data transmission circuit provided by any of the above embodiments, including: testing the receiving circuit to obtain test results, the test results are used to characterize the device mismatch situation and target compensation amount of the receiving circuit, and the target compensation amount corresponds to the device mismatch situation; based on the test results, using the target compensation amount to perform mismatch compensation on the receiving circuit.

[0016] In some embodiments, the testing of the receiving circuit includes: during the testing phase, adjusting the magnitude of the compensation current provided by the compensation circuit to the receiving circuit to obtain the quality of the sampling signal output by the receiving circuit under different compensation current conditions; and taking the compensation current corresponding to the sampling signal with the best quality among all the sampling signals as the target compensation amount.

[0017] In some embodiments, the receiving circuit includes: a first amplifier circuit, configured to compare the voltage difference between the input data and the reference voltage, and output a second signal and a second differential signal that are differential with each other; a second amplifier circuit, configured to compare the voltage difference between the second signal and the second differential signal, and output the first signal and the first differential signal; adjusting the magnitude of the compensation current provided by the compensation circuit to the receiving circuit includes: compensating the first amplifier circuit and adjusting the magnitude of the compensation current provided to the first amplifier circuit; based on the test result, using the target compensation amount to perform mismatch compensation on the receiving circuit includes: using the target compensation amount to compensate the first amplifier circuit.

[0018] In some embodiments, the compensation circuit is further configured to respond to a control signal and a preset level so that the size of the compensation current provided to the receiving circuit is adjustable; the adjustment of the size of the compensation current provided by the compensation circuit to the receiving circuit includes: using different control signals and / or different preset levels to test the receiving circuit, obtaining the control signal corresponding to the target compensation amount as a target control signal, and obtaining the preset level corresponding to the target compensation amount as a target level; the compensation circuit provides a corresponding compensation current to the receiving circuit in response to the target control signal and the target level.

[0019] According to some embodiments of the present disclosure, the embodiments of the present disclosure further provide a storage device on the other hand, including the data transmission circuit provided by any of the above embodiments.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] In the technical solution provided by the embodiment of the present disclosure, at least based on the device mismatch of the receiving circuit, the mismatch compensation of the receiving circuit can be performed, that is, a compensation mechanism for offsetting the mismatch of the input common mode level is added to the receiving circuit, so that the receiving circuit is in a relatively balanced working state, thereby accelerating the sampling speed of the sampling circuit, improving the sampling working current of the sampling circuit, shortening the sampling time, increasing the area of ​​the digital eye diagram corresponding to the sampling signal, increasing the eye height of the digital eye diagram, and reducing the bit error rate of the sampling circuit, so as to improve the transmission capacity of the received input data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A block diagram of a data transmission circuit provided by an embodiment of the present disclosure;

[0024] Figure 2 is another block diagram of a data transmission circuit;

[0025] Figure 3 for Figure 2 A schematic diagram of a circuit structure of the first amplifier circuit;

[0026] Figure 4 for Figure 2 A schematic diagram of a circuit structure of the second amplifier circuit;

[0027] Figure 5 is another block diagram of a data transmission circuit;

[0028] Figure 6 is another block diagram of a data transmission circuit;

[0029] Figure 7 is another block diagram of a data transmission circuit;

[0030] Figure 8 A schematic diagram of a compensation circuit;

[0031] Fig. 9 A schematic diagram of a circuit structure of a sub-compensation circuit;

[0032] Fig.10Another circuit structure diagram of the compensation circuit;

[0033] Fig.11 A circuit structure schematic diagram of a voltage generating circuit;

[0034] Fig.12 A circuit structure diagram of a receiving circuit;

[0035] Fig.13 is another circuit structure schematic diagram of a receiving circuit;

[0036] Fig.14 for Figure 1 A schematic diagram of a circuit structure of a sampling circuit;

[0037] Fig.15 is another block diagram of a data transmission circuit;

[0038] Fig.16 A schematic diagram of a data receiving circuit in a storage device;

[0039] Fig.17 A flowchart of a compensation method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The circuit structure of the data transmission circuit in the storage device can be equivalent to a cascade circuit of a receiving circuit and a sampling circuit. Among them, the receiving circuit can be a differential circuit, so that the single-ended input signal can be transmitted through the differential circuit, thereby realizing the conversion of the single-ended input signal to the differential signal. The sampling circuit samples the differential signal output by the receiving circuit and outputs a sampling signal, and the sampling signal is used to characterize the received single-ended input signal, thereby realizing the purpose of transmitting the single-ended input signal via the data transmission circuit. However, there is a phenomenon that the sampling time of the sampling circuit is long, the sensitivity needs to be improved, the bit error rate of the sampling circuit is high, and the eye height of the digital eye diagram corresponding to the sampling signal is low.

[0041] The analysis found that for the receiving circuit, the common mode level in the differential signal output by the receiving circuit is affected by the input common mode level, thus affecting the working state of the sampling circuit. On the one hand, the communication channel for the single-ended input signal to be transmitted to the receiving circuit is relatively long, and the loss of the communication channel will affect the quality of the single-ended input signal, and this impact will only be applied to one input end of the receiving circuit. The reference voltage received by the other input end is generally not affected by the loss of the communication channel, which leads to a natural mismatch in the input common mode level between the single-ended input signal received by the receiving circuit and the reference level. On the other hand, affected by process deviations, it is difficult for the devices of the half circuit receiving the single-ended input signal and the half circuit receiving the reference voltage in the receiving circuit to be completely symmetrical, such as the channel size of the device is difficult to be completely symmetrical, which leads to device mismatch (also known as misalignment) in the receiving circuit itself.

[0042] Among them, the size of the device mismatch can be characterized by the equivalent input offset voltage Vos. The receiving circuit is a differential input differential output circuit, and its equivalent input offset voltage Vos is defined as: the voltage that needs to be added to the input end when the output voltage is the reference value is the offset voltage. For the receiving circuit, the reference value is the differential output voltage of 0 (VOD = VO1-VO2 = 0), and the differential voltage that needs to be applied to the differential input end at this time is the equivalent input offset voltage of the receiving circuit (VID = VIN1-VIN2).

[0043] For the receiving circuit, the polarity and amplitude of the equivalent input offset voltage are uncertain. Accordingly, the output signal of the receiving circuit fluctuates with the fluctuation of the equivalent input offset voltage, which causes the input voltage of the sampling circuit to change, and the sampling time of the sampling circuit is affected. For example, the more serious the device mismatch, the greater the equivalent input offset voltage, the more serious the fluctuation of the output signal of the corresponding receiving circuit, the worse the sampling sensitivity of the sampling circuit, the longer the sampling time, the higher the bit error rate, and the worse the eye diagram quality of the sampling circuit.

[0044] The disclosed embodiment provides a data transmission circuit, which can at least perform mismatch compensation on a receiving circuit based on the device mismatch of the receiving circuit, that is, a compensation mechanism for offsetting the mismatch of the input common mode level is added to the receiving circuit, so that the receiving circuit is in a relatively balanced working state, thereby accelerating the sampling speed of the sampling circuit, improving the sampling working current of the sampling circuit, shortening the sampling time, increasing the area of ​​the digital eye diagram corresponding to the sampling signal, increasing the eye height of the digital eye diagram, and reducing the bit error rate of the sampling circuit, so as to improve the transmission capability of the received input data.

[0045] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0046] Figure 1 A block diagram of a data transmission circuit provided in an embodiment of the present disclosure.

[0047] refer to Figure 1 The data transmission circuit provided by the embodiment of the present disclosure includes a receiving circuit 101, a sampling circuit 102 and a compensation circuit 103.

[0048] The receiving circuit 101 is configured to receive input data IN, compare the voltage difference between the input data IN and a reference voltage VREF, and output a first differential signal OUT1 and a first differential signal OUT1B which are differential with each other.

[0049] The sampling circuit 102 is configured to sample the first signal OUT1 and the first differential signal OUT1B in response to a sampling clock CLK, and output a sampled signal OUTS.

[0050] The compensation circuit 103 is connected to the receiving circuit 101 . The compensation circuit 103 is configured to perform mismatch compensation on the receiving circuit 101 based on device mismatch of the receiving circuit 101 .

[0051] Since the compensation circuit 103 performs mismatch compensation on the receiving circuit 101 to compensate for the influence of the device mismatch of the receiving circuit 101 on the input common mode level, the quality of the first signal OUT1 and the first differential signal OUT1B output by the receiving circuit 101 is improved, and the sampling sensitivity of the sampling circuit 102 is improved, the sampling bit error rate of the sampling circuit 102 is reduced, and the eye diagram quality corresponding to the sampling circuit 102 is improved.

[0052] The data transmission circuit can be applied to a memory, and the memory can be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In some embodiments, the data transmission circuit can be applied to an SDRAM (Synchronous Dynamic Random Access Memory), and the SDRAM can be a DDR (Double Data Rate) SDRAM, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0053] The data transmission circuit provided by the embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0054] The receiving circuit 101 is a differential circuit, that is, it compares the received input data IN with the reference voltage VREF to output the first signal OUT1 and the first differential signal OUT1B which are differential signals. In this way, even if the input data IN is affected by channel attenuation in the path of being transmitted to the receiving circuit 101 via the communication channel, the swing of the output first signal OUT1 and the first differential signal OUT1B can still be amplified by the receiving circuit 101.

[0055] The compensation circuit 103 may perform mismatch compensation on the receiving circuit 101 by providing a compensation current to the receiving circuit 101 .

[0056] The principle of compensation circuit 103 compensating receiving circuit 101 may be as follows:

[0057] Entering the test phase, in the test phase, the compensation circuit 103 compensates the receiving circuit 101 to different degrees, for example, the compensation circuit 103 provides different compensation currents to the receiving circuit 101, and obtains corresponding test results respectively, and the test results are used to characterize the quality of the sampling signal output by the sampling circuit 102. The best test result is selected from the multiple test results, and the best test result characterizes that the quality of the sampling signal is the best, and the compensation amount of the receiving circuit 101 by the compensation circuit 103 under the best test result is obtained as the target compensation amount, for example, the target compensation amount can be a target compensation current.

[0058] When entering the normal working stage, the compensation circuit 103 compensates the receiving circuit 101 with the target compensation current.

[0059] Figure 2 Another block diagram of a data transmission circuit.

[0060] refer to Figure 2 , the receiving circuit 101 may include a first amplifier circuit 111 and a second amplifier circuit 121. The first amplifier circuit 111 is configured to compare and amplify the voltage difference between the input data IN and the reference voltage VREF, and output a second differential signal OUT2 and a second differential signal OUT2B that are differential with each other. The second amplifier circuit 121 is configured to compare and amplify the voltage difference between the second signal OUT2 and the second differential signal OUT2B, and output a first signal OUT1 and a first differential signal OUT1B.

[0061] Among them, the first amplifier circuit 111 and the second amplifier circuit 121 are both differential circuits, and the receiving circuit 101 includes a two-stage amplifier circuit, which is beneficial to further reduce the impact of channel loss on the input data IN, and improve the swing of the first signal OUT1 and the first differential signal OUT1B, so that the first signal OUT1 and the first differential signal OUT1B are full-swing signals.

[0062] Continue to refer Figure 2 The compensation circuit 103 is configured to perform mismatch compensation on the receiving circuit 101 based on at least a first device mismatch of the first amplifying circuit 111 or a second device mismatch of the second amplifying circuit 121 .

[0063] Figure 3 for Figure 2 It should be noted that the embodiment of the present disclosure does not limit the specific circuit structure of the first amplifier circuit, and any first amplifier circuit 111 that can generate a second differential signal OUT2 and a second differential signal OUT2B based on input data IN and reference voltage VREF can be applied to the embodiment of the present disclosure.

[0064] The equalizer circuit 11 can compensate the input data IN in a continuous time to compensate for the frequency loss of the input data IN. The first amplifier circuit 111 can be a continuous time linear equalizer (CTLE, Continuous Time Linear Equalizer), where continuous time linear equalization refers to compensating for a lossy signal (i.e., input data IN) in a continuous time.

[0065] refer to Figure 3, the first amplifier circuit 121 may include: a first NMOS tube MN1 and a first resistor R1, one end of the first resistor R1 is connected to the working power supply VDD, and the other end is connected to the drain of the first NMOS tube MN1, the gate of the first NMOS tube MN1 receives the reference voltage VREF, and the source is grounded via the first current source I1. A second NMOS tube MN2 and a second resistor R2, one end of the second resistor R2 is connected to the working power supply VDD, and the other end is connected to the drain of the second NMOS tube MN2, the gate of the second NMOS tube MN2 receives the input data IN, and the source is grounded via the second current source I2. A third resistor R3 and a capacitor C are connected in parallel between the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2. Among them, the drain of the first NMOS tube MN1 provides the second signal OUT2, and the drain of the second NMOS tube MN2 provides the second differential signal OUT2B. It should be noted that, unless otherwise specified, GND is used to represent ground in the drawings provided in the embodiments of the present disclosure.

[0066] Among them, the third resistor R3 and the capacitor C are connected in parallel, which can give the high-frequency circuit a zero point at high frequency, so that the spectrum diagram corresponding to the first amplifier circuit 111 shows a boost effect at high frequency, thereby improving the high-frequency gain and offsetting the frequency loss introduced in the received input data channel.

[0067] Figure 4 for Figure 2 It should be noted that the embodiments of the present disclosure do not limit the specific circuit structure of the second amplifier circuit, and any second amplifier circuit based on the second signal and the second differential signal to generate a first signal and a first differential signal that are differential with each other can be applied to the embodiments of the present disclosure.

[0068] The second amplifier circuit 121 may be a variable gain amplifier (VGA). For example, the second amplifier circuit 121 may be a current mode based gain amplifier, and the low frequency gain may be changed by changing the magnitude of the bias current.

[0069] refer to Figure 4The second amplifier circuit 121 may include: a third NMOS transistor MN3 and a fourth resistor R4, one end of the fourth resistor R4 is connected to the working power supply VDD, and the other end is connected to the drain of the third NMOS transistor MN3, the gate of the third NMOS transistor MN3 receives the second differential signal OUT2B, and the source is grounded via the third current source I3. A fourth NMOS transistor MN4 and a fifth resistor R5, one end of the fifth resistor R5 is connected to the working power supply VDD, and the other end is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor MN4 receives the second signal OUT2, and the source is grounded via the third current source I3. The drain of the third NMOS transistor MN3 provides the first signal OUT1, and the drain of the fourth NMOS transistor MN4 provides the first differential signal OUT1B.

[0070] The magnitude of the third current source I3 may be constant or adjustable. For example, the third current source I3 may be composed of an NMOS tube controlled by a bias voltage.

[0071] Continue to refer Figure 2 Since the first amplifier circuit 111 and the second amplifier circuit 121 are both differential circuits, affected by process deviations, the first amplifier circuit 111 usually has a first device mismatch, and the second amplifier circuit 121 usually has a second device mismatch.

[0072] The first device mismatch refers to the mismatch between the device of the half circuit receiving the input data IN and the device of the half circuit receiving the reference voltage VREF. The first device mismatch will accordingly affect the equivalent input offset voltage of the first amplifier circuit 111, thereby affecting the quality of the output second signal OUT2 and the second differential signal OUT2B.

[0073] For example, combined with reference Figure 2 and Figure 3 The device of the half circuit receiving the input data IN includes the second NMOS transistor MN2 and the second resistor R2, and the device of the half circuit receiving the reference voltage VREF includes the first NMOS transistor MN1 and the first resistor R1. The first device mismatch may include the mismatch caused by the inconsistency between the channel size of the first NMOS transistor MN1 and the channel size of the second NMOS transistor MN1, and the mismatch caused by the inconsistency between the size of the first resistor R1 and the size of the second resistor R2.

[0074] The second device mismatch refers to the mismatch between the device of the half circuit receiving the second signal OUT2 and the device of the half circuit receiving the second differential signal OUT2B. The second device mismatch will accordingly affect the equivalent input offset voltage of the second amplifier circuit 121, thereby affecting the quality of the output first signal OUT1 and the first differential signal OUT1B.

[0075] Combined with reference Figure 2and Figure 4 , the device of the half circuit receiving the second differential signal OUT2B includes the third NMOS transistor MN3 and the fourth resistor R4, and the device of the half circuit receiving the second signal includes the fourth NMOS transistor MN4 and the fifth resistor R5. The second device mismatch may include the mismatch caused by the inconsistency between the channel size of the third NMOS transistor MN3 and the channel size of the fourth NMOS transistor MN4, and the mismatch caused by the inconsistency between the size of the fourth resistor R4 and the size of the fifth resistor R5.

[0076] Figure 5 Another block diagram of a data transmission circuit.

[0077] refer to Figure 5 The compensation circuit 103 may be connected to the node outputting the second signal OUT2 and / or the second differential signal OUT2B. The compensation circuit 103 is configured to provide a compensation current to the node outputting the second signal OUT2 and / or the second differential signal OUT2B based on at least the first device mismatch.

[0078] The compensation circuit 103 performs mismatch compensation on the first amplifying circuit 111 , and can improve the signal quality from a relatively front position of the data transmission path, which is beneficial to further improve the quality of the sampling signal finally outputted.

[0079] The node where the first amplifier circuit 111 outputs the second signal is defined as a first node n1 , and the node where the first amplifier circuit 111 outputs the second differential signal is defined as a second node n2 .

[0080] It should be noted that for the sake of illustration, Figure 5 In the embodiment, the compensation circuit 103 is connected to both the first node n1 and the second node n2. However, in practice, the compensation circuit 103 may be connected to only the first node n1, only the second node n2, or both the first node n1 and the second node n2.

[0081] Among them, "A and / or B" in the embodiments of the present disclosure means that there can be three different situations, which can be A, can be B, or can be A or B.

[0082] In a specific example, the compensation circuit 103 provides a compensation current to the first node n1 and / or the second node n2 based on the first device mismatch. Specifically, the principle of compensation by the compensation circuit 103 may be as follows:

[0083] Entering the test phase, in the test phase, the compensation circuit 103 performs different degrees of compensation on the first amplifier circuit 111. For example, the compensation circuit 103 provides compensation currents of different magnitudes to the first amplifier circuit 111, and obtains corresponding test results respectively, and the test results are used to characterize the quality of the second signal OUT2 and the second differential signal OUT2B. The best test result is selected from the multiple test results, and the best test result characterizes that the quality of the second signal OUT2 and the second differential signal OUT2B is the best, and the compensation degree of the compensation circuit 103 for the first amplifier circuit 111 under the best test result is obtained as the target compensation amount, for example, the target compensation amount can be a target compensation current.

[0084] When entering the normal working stage, the compensation circuit 103 uses the target compensation current to compensate the first amplifying circuit 111 .

[0085] Continue to refer Figure 5 In some embodiments, the compensation circuit 103 may also be configured to provide a target compensation current to a node outputting the second signal OUT2 and / or the second differential signal OUT2B based on the first device mismatch and the second device mismatch.

[0086] That is to say, considering the overall device mismatch between the first amplifier circuit 111 and the second amplifier circuit 121, the mismatch compensation is performed on the first amplifier circuit 111. In this way, there is no need to set up a compensation circuit connected to the second amplifier circuit 121, which is beneficial to reducing the circuit complexity of the data transmission circuit.

[0087] Specifically, the compensation circuit 103 performs compensation in the following manner:

[0088] Entering the test phase, in the test phase, the compensation circuit 103 performs different degrees of compensation on the first amplifier circuit 111. For example, the compensation circuit 103 provides different compensation currents to the first amplifier circuit 111, and obtains corresponding test results respectively. The test results are used to characterize the quality of the sampling signal OUTS. The best test result is selected from the multiple test results. The best test result characterizes that the quality of the sampling signal OUTS is the best, and the compensation amount of the first amplifier circuit 111 by the compensation circuit 103 under the best test result is obtained as the target compensation amount.

[0089] When entering the normal working stage, the compensation circuit 103 compensates the first amplifying circuit 111 with the target compensation amount.

[0090] Figure 6 Another block diagram of a data transmission circuit.

[0091] refer to Figure 6The compensation circuit 103 may also be connected to the node outputting the first signal OUT1 and / or the first differential signal OUT1B. The compensation circuit 103 is configured to provide a compensation current to the node outputting the first signal OUT1 and / or the first differential signal OUT1B based on at least the second device mismatch.

[0092] The node at which the second amplifier circuit 121 outputs the first signal is defined as a third node n3 , and the node at which the second amplifier circuit 121 outputs the first differential signal is defined as a fourth node n4 .

[0093] It should be noted that for the sake of illustration, Figure 6 In the embodiment, the compensation circuit 103 is connected to both the third node n3 and the fourth node n4. However, in practice, the compensation circuit 103 may be connected to only the third node n3, only the fourth node n4, or both the third node n3 and the fourth node n4.

[0094] In a specific example, the compensation circuit 103 provides a compensation current to the third node n3 and / or the fourth node n4 based on the second device mismatch. Specifically, the principle of compensation by the compensation circuit 103 may be as follows:

[0095] Entering the test phase, in the test phase, a test input signal is provided to the second amplifier circuit 121, that is, the signal received by the second amplifier circuit 121 is not from the first amplifier circuit 111, and the compensation circuit 103 performs different degrees of compensation on the second amplifier circuit 121, for example, the compensation circuit 103 provides different magnitudes of compensation current to the second amplifier circuit 121, and obtains corresponding test results respectively, and the test results are used to characterize the quality of the sampling signal output by the second amplifier circuit 121. The best test result is selected from the multiple test results, and the best test result characterizes that the quality of the sampling signal is the best, and the compensation degree of the second amplifier circuit 121 by the compensation circuit 103 under the best test result is obtained as the target compensation amount.

[0096] When entering the normal working stage, the compensation circuit 103 compensates the second amplifying circuit 121 with the target compensation amount.

[0097] Continue to refer Figure 6 The compensation circuit 103 may also be configured to provide a compensation current to a node outputting the first signal OUT1 and / or the first differential signal OUT1B based on the first device mismatch and the second device mismatch. Specifically, the principle of compensation by the compensation circuit 103 may be as follows:

[0098] Entering the test phase, in the test phase, an input test signal is provided to the first amplifier circuit 111, the signal received by the second amplifier circuit 121 comes from the first amplifier circuit 111, and the compensation circuit 103 compensates the second amplifier circuit 121 to different degrees, for example, the compensation circuit 103 provides compensation currents of different magnitudes to the second amplifier circuit 121, and obtains corresponding test results respectively, and the test results are used to characterize the quality of the sampling signal OUTS output by the second amplifier circuit 121. The best test result is selected from multiple test results, and the best test result characterizes that the quality of the sampling signal OUTS is the best, and the compensation degree of the second amplifier circuit 121 by the compensation circuit 103 under the best test result is obtained as the target compensation amount.

[0099] When entering the normal working stage, the compensation circuit 103 compensates the second amplifying circuit 121 with the target compensation amount.

[0100] That is to say, considering the overall device mismatch between the first amplifier circuit 111 and the second amplifier circuit 121, the mismatch compensation is performed on the second amplifier circuit 121. In this way, there is no need to set up a compensation circuit connected to the first amplifier circuit, which is beneficial to reducing the circuit complexity of the data transmission circuit.

[0101] Figure 7 Another block diagram of a data transmission circuit.

[0102] refer to Figure 7 The compensation circuit 103 may be configured to provide a compensation current to the receiving circuit 101 for mismatch compensation, and further to make the size of the compensation current for mismatch compensation of the receiving circuit 101 adjustable in response to the control signal SG.

[0103] Figure 8 A structural diagram of a compensation circuit.

[0104] refer to Figure 8 The compensation circuit 103 may include at least two parallel sub-compensation circuits 113, each of which determines whether to connect to the receiving circuit 101 in response to a corresponding control code; wherein all control codes constitute a control signal SG (reference Figure 7 ), each sub-compensation circuit 113 is configured to provide a compensation current to the receiving circuit 101 when connected to the receiving circuit 101.

[0105] in, Figure 8 In the example, the number of sub-compensation circuits 113 is n, and different control codes are respectively identified as S1 . . . Sn, where n is a natural number greater than or equal to 2.

[0106] The more sub-compensation circuits 113 connected to the receiving circuit 101, the greater the compensation current for mismatch compensation to the receiving circuit 101. Therefore, by adjusting the number of sub-compensation circuits 113 connected to the receiving circuit 101, the compensation current can be adjusted.

[0107] Fig. 9 It should be noted that the embodiments of the present disclosure do not limit the specific circuit structure of the sub-compensation circuit, and any specific circuit structure that can realize the functions required by the sub-compensation circuit can be applied to the embodiments of the present disclosure.

[0108] refer to Fig. 9 The sub-compensation circuit 113 may include a circuit connected in series with the working power supply VDD and the receiving circuit 101 (reference Figure 8 ) between a switch SW and a current source I0; wherein the switch SW is turned on or off in response to a control code.

[0109] The switch SW may be connected between the current source I0 and the receiving circuit 101, and the current source I0 is connected between the switch SW and the working power supply VDD. Alternatively, the current source I0 may be connected between the switch SW and the receiving circuit 101, and the switch SW is connected between the current source I0 and the working power supply VDD.

[0110] If the switch SW is turned on in response to the control code, the corresponding sub-compensation circuit 112 is connected to the receiving circuit 101. If the switch SW is turned off in response to the control code, the corresponding sub-compensation circuit 112 is not connected to the receiving circuit 101.

[0111] The switch SW may be formed by a MOS transistor. In some examples, the switch SW is formed by an NMOS transistor, and when the control code is logic "1", the switch SW is turned on, and when the control code is logic "0", the switch SW is turned off.

[0112] In some other examples, the switch SW may also be formed by a PMOS tube.

[0113] Continue to refer Fig. 9 , the current source I0 may also be configured to adjust the magnitude of the compensation current provided to the receiving circuit 101 in response to a preset level Bias. The magnitude of the preset level Bias is adjustable. In this way, not only the magnitude of the compensation current provided to the receiving circuit 101 can be adjusted by adjusting the number of sub-compensation circuits 112 connected to the receiving circuit 101, but also the magnitude of the compensation current provided by each sub-compensation circuit 113 to the receiving circuit 101 can be adjusted, so that the method of adjusting the compensation current is more flexible and the accuracy of adjusting the compensation current is higher.

[0114] It should be noted that, in some other examples, the preset level Bias received by the current source I0 may also be a fixed value, and accordingly, the compensation current provided by the current source I0 to the receiving circuit 101 is a fixed value.

[0115] Fig.10 This is another circuit diagram of the compensation circuit. Fig.10 In some examples, the switch SW and the current source I0 may both be formed by PMOS tubes.

[0116] Continue to refer Fig. 9 The compensation circuit 103 may further include a voltage generating circuit 123. The voltage generating circuit 123 is configured to generate a preset level Bias corresponding to the selection signal Sel in response to the selection signal Sel.

[0117] Each sub-compensation circuit 113 may correspond to a respective independent voltage generating circuit 123 .

[0118] In some examples, in order to further reduce circuit complexity, different sub-compensation circuits 113 may share a voltage generation circuit 123, wherein the voltage generation circuit 123 may have an output terminal for outputting a preset level Bias, and the preset level Bias is provided to different sub-compensation circuits 113. The voltage generation circuit 123 may also have multiple output terminals for outputting multiple preset levels Bias of different magnitudes, and each preset level Bias is provided to different sub-compensation circuits 113.

[0119] Fig.11 It should be noted that the embodiments of the present disclosure do not limit the specific circuit structure of the voltage generating circuit, and any circuit structure that can output a corresponding preset level based on a selection signal can be applied to the embodiments of the present disclosure.

[0120] refer to Fig.11 The voltage generating circuit 123 may include: a resistor voltage divider circuit 1231, having different voltage divider nodes, and the levels of signals at each voltage divider node are different from each other; a selector 1232, connecting multiple voltage divider nodes, and configured to select the signal of one of the voltage divider nodes as a preset level in response to a selection signal.

[0121] The resistor voltage divider circuit 1231 may include a plurality of resistors R connected in series between a working power supply VDD and a ground terminal GND, and the resistance value of each resistor R may be the same, at least partially the same, or different from each other.

[0122] The selection signal Sel may be provided by a mode register, and the control signal SG may also be provided by a mode register.

[0123] Specifically, based on the device mismatch, different control signals SG and / or different preset levels Bias are used to test the receiving circuit 101, and the control signal SG corresponding to the target compensation amount is obtained as the target control signal, and the preset level Bias corresponding to the target compensation amount is obtained as the target level; the compensation circuit 103 responds to the target control signal and the target level and provides a corresponding compensation current to the receiving circuit 101.

[0124] It should be noted that, for explanations of the target compensation amount, reference may be made to the corresponding descriptions above, which will not be repeated here.

[0125] The target control signal is stored in the mode register. When the compensation circuit performs mismatch compensation, the mode register provides the stored target control signal to the compensation circuit 103 as a control signal received by the compensation circuit 103 .

[0126] The selection signal Sel corresponding to the target level may also be stored in the mode register.

[0127] Fig.12 A circuit structure diagram of a receiving circuit.

[0128] refer to Fig.12 , the compensation circuit 103 can be connected to the node where the first amplifier circuit 111 outputs the second signal OUT2. It can be understood that the compensation circuit 103 can also be connected to the node where the first amplifier circuit 111 outputs the second differential signal OUT2B. Alternatively, a part of the sub-compensation circuits 113 in the compensation circuit 103 are connected to the node where the first amplifier circuit 111 outputs the second signal OUT, and the remaining part of the sub-compensation circuits 113 are connected to the node where the first amplifier circuit 111 outputs the second differential signal OUT2B.

[0129] For the detailed structural description of the compensation circuit 103 and the first amplifier circuit 111 , please refer to the above corresponding description, which will not be repeated here.

[0130] Fig.13 Another circuit structure diagram of the receiving circuit.

[0131] refer to Fig.13 , the compensation circuit 103 can be connected to the node where the second amplifier circuit 121 outputs the first signal OUT1. It can be understood that the compensation circuit 103 can also be connected to the node where the second amplifier circuit 121 outputs the first differential signal OUT1B. Alternatively, a portion of the sub-compensation circuits 113 in the compensation circuit 103 are connected to the node where the second amplifier circuit 121 outputs the first signal OUT1, and the remaining portion of the sub-compensation circuits 113 are connected to the node where the second amplifier circuit 121 outputs the first differential signal OUT1B.

[0132] For the detailed circuit structure description of the compensation circuit 103 and the second amplifier circuit 121 , please refer to the above corresponding description, which will not be repeated here.

[0133] In addition, it should be noted that the above description is based on an example in which the receiving circuit 101 includes a cascaded first amplifier circuit 111 and a second amplifier circuit 121. In the embodiment of the present disclosure, the receiving circuit may also be composed of a single-stage amplifier circuit.

[0134] The sampling circuit may be a sense amplifier (SA). The sampling signal OUTS may include a differential sub-sampling signal and a differential sub-sampling signal.

[0135] Fig.14 for Figure 1 It should be noted that the embodiments of the present disclosure do not limit the specific circuit structure of the sampling circuit, and any level that can sample the first signal and the first differential signal and output the sampling signal can be applied to the embodiments of the present disclosure.

[0136] refer to Fig.14, the sampling circuit 103 may include: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7. The gate of the fifth NMOS transistor MN5 receives the first signal OUT1, the source of the fifth NMOS transistor MN5 is connected to the source of the sixth NMOS transistor MN6 and the drain of the seventh NMOS transistor MN7, the gate of the seventh NMOS transistor MN7 receives the sampling clock CLK, the source of the seventh NMOS transistor MN7 is connected to the ground terminal, and the gate of the sixth NMOS transistor MN6 receives the first differential signal OUT1B. The eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the first PMOS transistor MP1, and the second PMOS transistor MP2. The source of the eighth NMOS transistor MN8 is connected to the drain of the fifth NMOS transistor MN5, the drain of the eighth NMOS transistor MN8 is connected to the drain of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2, and the gate of the first PMOS transistor MP1 is connected to the gate of the eighth NMOS transistor MN8. The gate of the ninth NMOS tube MN9 is connected to the gate of the second PMOS tube, the drain of the ninth NMOS tube MN9 is connected to the drain of the second PMOS tube MP2 and the gate of the first PMOS tube MP1, and the source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are both connected to the working power supply VDD. The third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5. The source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are both connected to the working power supply VDD, the gate of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4 and the gate of the fifth PMOS tube MP5 all receive the sampling clock CLK, the drain of the third PMOS tube MP3 is connected to the drain of the second PMOS tube MP2, the drain of the fourth PMOS tube MP4 is connected to the drain of the first PMOS tube MP1, the source of the fifth PMOS tube MP5 is connected to the drain of the fifth NMOS tube MN5, and the drain of the fifth PMOS tube MP5 is connected to the drain of the sixth NMOS tube MN6.

[0137] The sampling signal includes a sampling sub-signal OUTS_P and a differential sampling sub-signal OUTS_N which are a differential pair, wherein the sampling sub-signal OUTS_P is provided by the drain of the second PMOS transistor MP2, and the differential sampling sub-signal OUTS_N is provided by the drain of the first PMOS transistor MP1.

[0138] Fig.15 Another block diagram of a data transmission circuit.

[0139] refer to Fig.15 The data transmission circuit may further include an adder (summer) 104, and the adder 104 is connected to the receiving circuit 101. The adder 104 is used to improve the problem of inter-symbol interference.

[0140] In some examples, the adder 104 can improve the problem of inter-symbol interference based on the principle of decision feedback equalization (DFE).

[0141] In the technical solution of the data transmission circuit provided in the above embodiment, the receiving circuit 101 is connected to the compensation circuit 103 for compensating for offset, which weakens or offsets the offset of the input common mode level of the receiving circuit 101, so as to reduce the equivalent input offset voltage of the receiving circuit 101, thereby reducing the adverse effect of the equivalent input offset voltage on the first signal OUT1 and the first differential signal OUT1B output by the receiving circuit 101, so that the receiving circuit 101 works in a relatively balanced working state, that is, the equivalent input offset voltage of the receiving circuit 101 is close to 0. In this way, it is beneficial to improve the quality of the first signal OUT1 and the first differential signal OUT1B received by the sampling circuit, thereby improving the sensitivity of the sampling circuit 102, reducing the bit error rate of sampling, and increasing the eye height of the digital eye diagram corresponding to the sampling signal OUTS.

[0142] Accordingly, the present disclosure also provides a storage device, including the data transmission circuit provided in the above embodiment. The storage device provided in the present disclosure will be described in detail below. It should be noted that the description in the above embodiment is also applicable to the embodiment of the storage device.

[0143] The storage device may be a DRAM or an SRAM. The DRAM may be an SDRAM, and the SDRAM may be a DDR SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6. In some embodiments, the storage device may be a memory chip, and the memory chip may be a DRAM chip or an SRAM chip. In addition, the input data may be DQ input data.

[0144] The storage device may include a plurality of data transmission circuits, each of which receives input data and a corresponding sampling clock, and the sampling clocks received by each of which have different phases.

[0145] A plurality of data transmission circuits constitute a data receiving circuit of the storage device. Fig.16 A schematic diagram of a data receiving circuit in a storage device.

[0146] refer to Fig.16, taking the data receiving circuit of the storage device including 4 data transmission circuits as an example. Each data transmission circuit may include a first amplifier circuit 111 and a second amplifier circuit 121, and also includes a sampling circuit 102 and a compensation circuit 103. Among them, the sampling clocks of each data transmission circuit are CLK_0°, CLK_90°, CLK_180° and CLK_270°, respectively, and the corresponding output sampling signals are OUTS_0°, OUTS_90°, OUTS_180° and OUTS_270°, respectively. Different data transmission circuits can share the first amplifier circuit 111, and two data transmission circuits with adjacent sampling clock phases can also share the second amplifier circuit 121.

[0147] It is understandable that the embodiments of the present disclosure do not limit the specific architectures of different data transmission circuits, and different data transmission circuits may also have first amplifier circuits independent of each other or second amplifier circuits independent of each other.

[0148] Accordingly, the embodiment of the present disclosure also provides a compensation method that can be applied to the data transmission circuit provided in the above embodiment. The compensation method provided in the embodiment of the present disclosure will be described in detail below. It should be noted that the description in the above embodiment is also applicable to the embodiment of the compensation method.

[0149] Fig.17 A flowchart of a compensation method provided in an embodiment of the present disclosure.

[0150] refer to Fig.17 , perform step S1, test the receiving circuit, and obtain the test result, the test result is used to characterize the device mismatch condition and the target compensation amount of the receiving circuit, and the target compensation amount corresponds to the device mismatch condition.

[0151] Continue to refer Fig.17 , proceed to step S2, based on the test result, use the target compensation amount to perform mismatch compensation on the receiving circuit.

[0152] In some examples, testing the receiving circuit includes: during the testing phase, adjusting the magnitude of the compensation current provided by the compensation circuit to the receiving circuit to obtain the quality of the sampling signal output by the receiving circuit under different compensation current conditions; and taking the compensation current corresponding to the sampling signal with the best quality among all the sampling signals as the target compensation amount.

[0153] like Figure 2 As shown, the receiving circuit 101 includes: a first amplifier circuit 111, configured to compare the voltage difference between the input data IN and the reference voltage VREF, and output a second signal and a second differential signal that are differential to each other; a second amplifier circuit 121, configured to compare the voltage difference between the second signal and the second differential signal, and output the first signal and the first differential signal.

[0154] In some examples, the magnitude of the compensation current provided by the compensation circuit 103 to the receiving circuit 101 is adjusted, including: compensating the first amplifier circuit 111 and adjusting the magnitude of the compensation current provided to the first amplifier circuit 111; based on the test results, the mismatch compensation of the receiving circuit is performed using a target compensation amount, including: compensating the first amplifier circuit 111 using the target compensation amount.

[0155] The test result may be the quality of the sampled signal, and accordingly, the test result is related to the overall device mismatch between the first amplifier circuit 111 and the second amplifier circuit 121. In this way, the first amplifier circuit 111 may be compensated based on the overall device mismatch.

[0156] The test result may also be the quality of the second signal OUT2 and the second differential signal OUT2B. Accordingly, the test result is related to the device mismatch of the first amplifier circuit 111. In this way, the first amplifier circuit 111 may be compensated based on the device mismatch of the first amplifier circuit 111.

[0157] In other examples, the size of the compensation current provided by the compensation circuit 103 to the receiving circuit 101 is adjusted, including: compensating the first amplifier circuit 111 and adjusting the size of the compensation current provided to the first amplifier circuit 111; based on the test results, the target compensation amount is used to perform mismatch compensation on the receiving circuit, including: using the target compensation amount to compensate the first amplifier circuit 111.

[0158] In some examples, adjusting the magnitude of the compensation current provided by the compensation circuit 103 to the receiving circuit 101 includes: compensating the second amplifying circuit 121 and adjusting the magnitude of the compensation current provided to the second amplifying circuit 121; and based on the test result, using the target compensation amount to perform mismatch compensation on the receiving circuit includes: using the target compensation amount to compensate the second amplifying circuit 121. The test result includes the quality of the sampled signal.

[0159] In the test phase, a test input signal can be provided to the second amplifier circuit 121 alone, and accordingly, the test result is related to the device mismatch of the second amplifier circuit 121. In this way, the second amplifier circuit 121 can be compensated based on the device mismatch of the second amplifier circuit 121.

[0160] During the test phase, the output of the first amplifier circuit 111 may also be provided to the second amplifier circuit 121. Accordingly, the test result is related to the overall device mismatch between the first amplifier circuit 111 and the second amplifier circuit 121. In this way, the second amplifier circuit 121 may be compensated based on the overall device mismatch.

[0161] In addition, combined with reference Figures 7 to 10 The compensation circuit 103 can also be configured to respond to the control signal and the preset level so that the size of the compensation current provided to the receiving circuit 101 is adjustable; adjusting the size of the compensation current provided by the compensation circuit 103 to the receiving circuit 101 includes: using different control signals SG and / or different preset levels Bias to test the receiving circuit 101, obtaining the control signal SG corresponding to the target compensation amount as the target control signal, and obtaining the preset level Bias corresponding to the target compensation amount as the target level; the compensation circuit 103 responds to the target control signal and the target level, and provides the corresponding compensation current to the receiving circuit 101.

[0162] For detailed description of the control signal SG and the preset level Bias, reference may be made to the corresponding description of the aforementioned embodiment, which will not be repeated here.

[0163] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A data transmission circuit, characterized in that: include: A receiving circuit is configured to receive input data and compare a voltage difference between the input data and a reference voltage, and output a first signal and a first differential signal that are differential with each other; a sampling circuit configured to sample the first signal and the first differential signal in response to a sampling clock and output a sampled signal; The compensation circuit is connected to the receiving circuit and is configured to perform mismatch compensation on the receiving circuit based on device mismatch of the receiving circuit.

2. The data transmission circuit according to claim 1, characterized in that: The receiving circuit comprises: A first amplifier circuit is configured to compare and amplify a voltage difference between the input data and the reference voltage, and output a second signal that is differential with respect to each other and a second differential signal; a second amplifying circuit configured to compare and amplify a voltage difference between the second signal and the second differential signal, and output the first signal and the first differential signal; The compensation circuit is configured to perform mismatch compensation on the receiving circuit based on at least a first device mismatch of the first amplifying circuit or a second device mismatch of the second amplifying circuit.

3. The data transmission circuit according to claim 2, characterized in that: The compensation circuit is connected to a node outputting the second signal and / or the second differential signal; the compensation circuit is configured to provide a compensation current to the node outputting the second signal and / or the second differential signal based at least on the first device mismatch.

4. The data transmission circuit according to claim 3, characterized in that: The compensation circuit is further configured to provide a compensation current to a node outputting the second signal and / or the second differential signal based on the second device mismatch.

5. The data transmission circuit according to claim 1, characterized in that: The compensation circuit is configured to provide a compensation current to the receiving circuit for mismatch compensation, and further to make the magnitude of the compensation current for mismatch compensation of the receiving circuit adjustable in response to a control signal.

6. The data transmission circuit according to claim 1, characterized in that: The compensation circuit comprises: at least two parallel sub-compensation circuits, each of the sub-compensation circuits determining whether to connect to the receiving circuit in response to a corresponding control code; Wherein, all the control codes constitute a control signal, and each of the sub-compensation circuits is configured to provide a compensation current to the receiving circuit.

7. The data transmission circuit according to claim 6, characterized in that: The control signal is provided by a mode register.

8. The data transmission circuit according to claim 6, characterized in that: The sub-compensation circuit comprises: A switch and a current source connected in series between a working power supply and the receiving circuit; The switch is turned on or off in response to the control code.

9. The data transmission circuit according to claim 8, characterized in that: The current source is further configured to adjust the magnitude of the compensation current provided to the receiving circuit in response to a preset level, and the magnitude of the preset level is adjustable.

10. The data transmission circuit according to claim 9, characterized in that: The sub-compensation circuit comprises: The voltage generating circuit is configured to generate a voltage having the preset level corresponding to the selection signal in response to the selection signal.

11. A compensation method applied to the data transmission circuit according to any one of claims 1 to 10, characterized in that: include: Testing the receiving circuit to obtain a test result, wherein the test result is used to characterize a device mismatch condition and a target compensation amount of the receiving circuit, wherein the target compensation amount corresponds to the device mismatch condition; Based on the test result, mismatch compensation is performed on the receiving circuit using the target compensation amount.

12. The compensation method according to claim 11, characterized in that: The testing of the receiving circuit comprises: In the testing phase, the magnitude of the compensation current provided by the compensation circuit to the receiving circuit is adjusted to obtain the quality of the sampling signal output by the receiving circuit under different compensation current conditions; The compensation current corresponding to the sampling signal with the best quality among all the sampling signals is used as the target compensation amount.

13. The compensation method according to claim 12, characterized in that: The receiving circuit comprises: A first amplifier circuit is configured to compare a voltage difference between the input data and the reference voltage, and output a second signal and a second differential signal that are differential with each other; a second amplifying circuit configured to compare a voltage difference between the second signal and the second differential signal, and output the first signal and the first differential signal; The adjusting the magnitude of the compensation current provided by the compensation circuit to the receiving circuit includes: The first amplifying circuit is compensated, and the magnitude of the compensation current provided to the first amplifying circuit is adjusted; and based on the test result, the mismatch compensation of the receiving circuit is performed using the target compensation amount, including: The first amplifier circuit is compensated using the target compensation amount.

14. The compensation method according to claim 13, characterized in that: The compensation circuit is further configured to, in response to a control signal and a preset level, make the magnitude of the compensation current provided to the receiving circuit adjustable; the adjusting the magnitude of the compensation current provided by the compensation circuit to the receiving circuit comprises: Using different control signals and / or different preset levels to test the receiving circuit, obtaining the control signal corresponding to the target compensation amount as a target control signal, and obtaining the preset level corresponding to the target compensation amount as a target level; The compensation circuit provides a corresponding compensation current to the receiving circuit in response to the target control signal and the target level.

15. A storage device, characterized in that: include: The data transmission circuit according to any one of claims 1 to 10.

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