A power selection circuit and memory

Abstract

The present disclosure provides a power selection circuit and memory, relating to the field of integrated circuit technology, comprising: a first control circuit configured to receive a power selection signal in a first voltage domain, and generate and output a first control signal in a second voltage domain based on the power selection signal; a second control circuit configured to receive the power selection signal, and generate and output a second control signal in a third voltage domain based on the power selection signal; a power selection output circuit coupled to the first control circuit and the second control circuit, with a first end connected to the first power signal and a second end connected to the second power signal; the power selection output circuit configured to control a path between its first end and its output end based on the first control signal, and to control a path between its second end and its output end based on the first control signal and the second control signal. The present disclosure can solve the problem of a short circuit between two power signals in a power selection circuit during a specific power-on process.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a power selection circuit and a memory. Background Art

[0002] A power selection circuit is used in DRAM chips within integrated circuits to selectively power dummy word lines. Under normal operating conditions, the power selection circuit selectively provides either VKK power or VPP power to the dummy word lines. Before all power signals stabilize upon power-up, the output of the level shifter within the power selection circuit floats, causing the circuit to lose its power selection function. Under the influence of a small disturbance voltage, the circuit can short-circuit the VKK and VPP power supplies, reducing the reliability of the power selection circuit. Summary of the Invention

[0003] The embodiments of the present disclosure provide a power selection circuit and a memory, which can solve the problem of short circuit between two power supplies in the power selection circuit during a specific power-on process, thereby improving the power selection reliability of the power selection circuit.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] An embodiment of the present disclosure provides a power selection circuit, comprising: a first control circuit configured to receive a power selection signal in a first voltage domain, and generate and output a first control signal in a second voltage domain according to the power selection signal;

[0006] a second control circuit configured to receive the power selection signal, and generate and output a second control signal in a third voltage domain according to the power selection signal;

[0007] a power selection output circuit coupled to the first control circuit and the second control circuit, with a first terminal connected to a first power signal and a second terminal connected to a second power signal; the power selection output circuit being configured to control a path between the first terminal and an output terminal thereof according to the first control signal, and to control a path between the second terminal and an output terminal thereof according to the first control signal and the second control signal;

[0008] The high level voltage value of the second voltage domain is equal to the voltage value of the first power signal, and the low level voltage value of the third voltage domain is equal to the voltage value of the second power signal.

[0009] In the above scheme, the power supply selection output circuit is configured to open the path between its first end and its output end and close the path between its second end and its output end when the first control signal is at a low level; and to open the path between its second end and its output end and close the path between its first end and its output end when both the first control signal and the second control signal are at a high level.

[0010] In the above scheme, the level of the first control signal and the level of the second control signal are the same as the level of the power selection signal; the power selection output circuit is configured to open the path between its first end and its output end and close the path between its second end and its output end when the first control signal and the second control signal are both at a low level; and to open the path between its second end and its output end and close the path between its first end and its output end when the first control signal and the second control signal are both at a high level.

[0011] In the above scheme, the power selection output circuit includes: a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the threshold voltage of the first NMOS transistor is greater than the threshold voltage of the second NMOS transistor; the first PMOS transistor, whose first end serves as the first end of the power selection output circuit, whose control end is connected to the output end of the first control circuit for receiving the first control signal, and whose second end is connected to the first end of the first NMOS transistor; the first NMOS transistor, whose control end is connected to the output end of the first control circuit for receiving the first control signal, and whose second end is connected to the first end of the second NMOS transistor, and whose first end is connected to the second end of the first transistor serves as the output end of the power selection output circuit; the second end of the second NMOS transistor, whose second end serves as the second end of the power selection output circuit, and whose control end is connected to the second end of the second control circuit for receiving the second control signal.

[0012] In the above solution, the power selection output circuit includes: a second PMOS transistor, a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the second PMOS transistor has a first end serving as the first end of the power selection output circuit, a control end connected to the output end of the first control circuit for receiving the first control signal, and a second end connected to the first end of the third PMOS transistor; the third PMOS transistor has a control end connected to the output end of the second control circuit for receiving the second control signal, a second end connected to the first end of the second PMOS transistor, and a second end connected to the first end of the third NMOS transistor serves as the output end of the power selection output circuit; the third NMOS transistor has a second end connected to the first end of the fourth NMOS transistor; the fourth NMOS transistor has a second end serving as the second end of the power selection output circuit, and a control end connected to the second end of the second control circuit for receiving the second control signal.

[0013] In the above scheme, the first control circuit receives a local power signal provided by a local power generation circuit, and in response to the local power signal at a high level, converts the power selection signal into the first control signal in a second voltage domain for output; a first voltage value of the high level of the first voltage domain is lower than a second voltage value of the high level of the second voltage domain, and a voltage value of the local power signal is between the first voltage value and the second voltage value.

[0014] In the above scheme, the first control circuit includes: a first level conversion circuit and a first drive circuit; the first level conversion circuit, whose input end receives the power selection signal, and whose output end is connected to the input end of the first drive circuit, whose first power supply end receives the first power signal, and is connected to the local power generation circuit; under the control of the local power supply signal, the first control circuit converts the power selection signal into a control voltage at the same level as the power selection signal, and provides it to the first drive circuit; the first drive circuit, whose output end serves as the output end of the first control circuit, outputs a high-level first control signal according to the high-level control voltage, and outputs a low-level first control signal according to the low-level control voltage.

[0015] In the above solution, the first level conversion circuit includes: a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a first inverter; the fourth PMOS transistor has a first end receiving a first power supply signal, a control end connected to the second end of the fifth PMOS transistor, and a second end connected to the first end of the fifth NMOS transistor and the control end of the fifth PMOS transistor; the fifth NMOS transistor has a second end connected to the first end of the sixth NMOS transistor, and a control end receiving the local power supply signal; the sixth NMOS transistor has a second end connected to ground, and a control end connected to the power supply selection signal and the input end of the first inverter, respectively. The fifth PMOS transistor has a first end receiving a first power supply signal, and a second end connected to the first end of the seventh NMOS transistor and the control end of the fourth PMOS transistor; the seventh NMOS transistor has a first end connected to the input end of the first drive circuit, a second end connected to the first end of the eighth NMOS transistor, and a control end receiving the local power supply signal; the eighth NMOS transistor has a second end grounded, and a control end connected to the output end of the first inverter; the first drive circuit includes: a second inverter and a third inverter; the second inverter has a first end serving as the input end of the first drive circuit, a second end connected to the first end of the third inverter, and a second end of the third inverter serving as the output end of the first drive circuit.

[0016] In the above scheme, the local power supply generating circuit includes: a third control circuit and a fourth control circuit; the third control circuit, whose input end receives a reference power supply signal, whose first power supply end receives a first power supply signal, and whose output end is connected to the input end of the fourth control circuit, is configured to output a reference voltage to the fourth control circuit according to the reference power supply signal; the fourth control circuit, whose first power supply end receives the first power supply signal, and whose output end serves as the output end of the local power supply generating circuit, is configured to output the local power supply signal according to the reference voltage.

[0017] In the above solution, the third control circuit includes: a first operational amplifier, a sixth PMOS transistor, a first resistor, and a second resistor; the fourth control circuit includes: a second operational amplifier, a seventh PMOS transistor, a third resistor, and a fourth resistor; the first operational amplifier, whose inverting input terminal serves as the input terminal of the third control circuit, whose non-inverting input terminal is connected to the second terminal of the first resistor, and whose output terminal is connected to the control terminal of the sixth PMOS transistor; the sixth PMOS transistor, whose first terminal serves as the first power supply terminal of the third control circuit, and whose second terminal is connected to the first terminal of the first resistor and the inverting input terminal of the second operational amplifier; the first resistor, whose second terminal is connected to the first terminal of the second resistor, and whose second terminal is grounded; the second operational amplifier, whose non-inverting input terminal is connected to the second terminal of the third resistor, and whose output terminal is connected to the control terminal of the seventh PMOS transistor; the seventh PMOS transistor, whose first terminal serves as the first power supply terminal of the fourth control circuit, and whose second terminal serves as the output terminal of the local power generation circuit; the third resistor, whose first terminal is connected to the second terminal of the seventh PMOS transistor, and whose second terminal is connected to the first terminal of the fourth resistor, and whose second terminal is grounded.

[0018] In the above scheme, the second control circuit includes: a second level conversion circuit and a second drive circuit; the second level conversion circuit, whose input end serves as the input end of the second control circuit, whose first power supply end receives the third power supply signal, whose second power supply end receives the second power supply signal, and whose output end is connected to the input end of the second drive circuit, is used to output the third power supply to the second drive circuit when the power supply selection signal is at a high level, and output the second power supply signal to the second drive circuit when the power supply selection signal is at a low level; the second drive circuit, whose second end serves as the output end of the second control circuit, outputs the second control signal at a high level in the third voltage domain according to the third power supply, and outputs the second control signal at a low level in the third voltage domain according to the second power supply signal; the third voltage value of the low level of the first voltage domain is higher than the fourth voltage value of the low level of the third voltage domain.

[0019] In the above solution, the second level conversion circuit includes: a fourth inverter, a fifth inverter, an eighth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a ninth PMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor; the fourth inverter has an input end serving as the input end of the second level conversion circuit, and an output end thereof is connected to the input end of the fifth inverter and the control ends of the eighth PMOS transistor and the ninth NMOS transistor, respectively; the fifth inverter has an output end connected to the control ends of the ninth PMOS transistor and the eleventh NMOS transistor; the eighth PMOS transistor has a first end receiving a third power supply signal, and a second end thereof is connected to the control ends of the ninth PMOS transistor and the eleventh NMOS transistor; the first terminal of the ninth NMOS transistor; the first terminal of the ninth NMOS transistor serving as the output terminal of the second level shifting circuit and connected to the control terminal of the twelfth NMOS transistor, and the second terminal of the ninth NMOS transistor being connected to the first terminal of the tenth NMOS transistor; the second terminal of the tenth NMOS transistor receiving the second power supply signal, and the control terminal of the tenth NMOS transistor being connected to the second terminal of the ninth PMOS transistor; the first terminal of the ninth PMOS transistor receiving the third power supply signal, and the second terminal of the ninth PMOS transistor being connected to the first terminal of the eleventh NMOS transistor; the second terminal of the eleventh NMOS transistor being connected to the first terminal of the twelfth NMOS transistor; the second terminal of the twelfth NMOS transistor receiving the second power supply signal;

[0020] The second drive circuit includes: a tenth PMOS transistor, a thirteenth NMOS transistor, an eleventh PMOS transistor and a fourteenth NMOS transistor; the tenth PMOS transistor has a first end connected to the third power supply signal, a second end connected to the first end of the thirteenth NMOS transistor, and a control end connected to the control end of the thirteenth NMOS transistor as an input end of the second drive circuit; the thirteenth NMOS transistor has a second end connected to the second power supply signal, a first end connected to the second end of the tenth PMOS transistor and then connected to the control ends of the eleventh PMOS transistor and the fourteenth NMOS transistor; the eleventh PMOS transistor has a first end connected to the third power supply signal, a second end connected to the first end of the fourteenth NMOS transistor; the fourteenth NMOS transistor has a second end connected to the second power supply signal, and a first end connected to the second end of the eleventh PMOS transistor as an output end of the second drive circuit.

[0021] An embodiment of the present disclosure further provides a memory, which includes the power selection circuit as described above.

[0022] It can be seen that the embodiment of the present disclosure provides a power selection circuit, including: a first control circuit, configured to receive a power selection signal in a first voltage domain, and generate and output a first control signal in a second voltage domain according to the power selection signal; a second control circuit, configured to receive the power selection signal, and generate and output a second control signal in a third voltage domain according to the power selection signal; a power selection output circuit, coupled to the first control circuit and the second control circuit, with its first end connected to the first power signal and its second end connected to the second power signal; the power selection output circuit is configured to control the path between its first end and its output end according to the first control signal, and to control the path between its second end and its output end according to the first control signal and the second control signal; wherein the voltage value of the high level of the second voltage domain is equal to the voltage value of the first power signal, and the voltage value of the low level of the third voltage domain is equal to the voltage value of the second power signal. In this way, since the power selection output circuit controls the output of the first power signal according to the first control signal and controls the output of the second power signal according to the second control signal, the first control signal and the second control signal are both formed according to the power selection signal and have nothing to do with whether all the power signals are stable upon power-on. As a result, the power selection circuit ensures the power selection function even before all the power signals are stable upon power-on, thereby solving the problem of a short circuit between the two power supply circuits during a specific power-on process of the power selection circuit and improving the power selection reliability of the power selection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 1 ;

[0024] Figure 2 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 2 ;

[0025] Figure 3 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 3 ;

[0026] Figure 4 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 4 ;

[0027] Figure 5 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 5 ;

[0028] Figure 6 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 6 ;

[0029] Figure 7A schematic structural diagram of a first level conversion circuit provided in an embodiment of the present disclosure;

[0030] Figure 8 A power supply trend diagram in the related art provided by the embodiment of the present disclosure;

[0031] Figure 9 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 7 ;

[0032] Figure 10 A schematic diagram of the structure of a reference power supply circuit provided in an embodiment of the present disclosure;

[0033] Figure 11 A schematic structural diagram of a local power generation circuit provided in an embodiment of the present disclosure;

[0034] Figure 12 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 8 ;

[0035] Figure 13 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 9 ;

[0036] Figure 14 An optional structural diagram of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0038] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0039] If similar descriptions of "first / second" appear in the invention document, the following explanation is added. In the following description, the terms "first\second\third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0041] In related technologies, memories have multiple voltage domains, and power supply circuits are required to perform level conversion between different voltage domains. When the voltage difference between two voltage domains is too large, a control power signal (a voltage signal between the two voltage domains) is required to perform control conversion. However, this control power signal can only be generated after all power signals are stable at power-up. If power-up is unstable, the control power signal output after level conversion is 0, causing the output to float, potentially shorting the power supply circuit used for level conversion.

[0042] See also Figure 1 , Figure 1 A schematic diagram of the structure of the power selection circuit provided in the embodiment of the present disclosure Figure 1 .

[0043] Combine Figure 1 A power selection circuit 90 includes: a first control circuit 20 configured to receive a power selection signal 10 in a first voltage domain and generate and output a first control signal in a second voltage domain based on the power selection signal 10; a second control circuit 30 configured to receive the power selection signal 10 and generate and output a second control signal in a third voltage domain based on the power selection signal 10; a power selection output circuit 40 coupled to the first control circuit 20 and the second control circuit 30, with a first end connected to the first power signal and a second end connected to the second power signal; the power selection output circuit 40 is configured to control a path between the first end and an output end thereof based on the first control signal, and to control a path between the second end and an output end thereof based on the first control signal and the second control signal; wherein a high level voltage value of the second voltage domain is equal to a voltage value of the first power signal, and a low level voltage value of the third voltage domain is equal to a voltage value of the second power signal.

[0044] The first control circuit 20 and the second control circuit 30 both have level conversion functions. The first control circuit 20 can convert the power selection signal 10 in the first voltage domain into a first control signal in the second voltage domain. The second control circuit 30 can convert the power selection signal 10 in the first voltage domain into a second control signal in the third voltage domain. The power selection output circuit 40 can select to output either the first power signal or the second power signal to the dummy word line based on the first control signal and the second control signal.

[0045] In the embodiment of the present disclosure, the first control signal and the second control signal are both generated according to the power selection signal 10. The power selection output circuit 40 can control the path between its first end and its output end according to the first control signal, and control the path between its second end and its output end according to the second control signal of the first control signal, without having to wait for all power signals to be stable after power-on to control the output power by controlling the power signal. This eliminates the defect in the related art that all power signals need to be stable after power-on before the output power can be controlled by a stable control power signal. Furthermore, before all power signals are stable after power-on, the power selection output circuit can also select to output the first power signal or the second power signal according to the first control signal and the second control signal, thereby solving the problem of short circuit between the two power signals during a specific power-on process and improving the power selection reliability of the power selection circuit.

[0046] Combine Figure 1 The power supply selection output circuit 40 is configured to open the path between its first end and its output end and close the path between its second end and its output end when the first control signal is at a low level; and to open the path between its second end and its output end and close the path between its first end and its output end when both the first control signal and the second control signal are at a high level.

[0047] Combine Figure 1 Before all power signals of the memory device stabilize upon power-up, the level-converted output control power signal is 0, causing the output to float. At this point, the first control signal is a low-level voltage. When the first control signal is a low-level voltage, the power selection output circuit 40 only outputs the first power signal, thereby resolving the issue of a short circuit between the first and second power signals during a specific power-up process and improving the power selection reliability of the power selection circuit.

[0048] Combine Figure 1 , the levels of the first control signal and the second control signal are the same as the level of the power selection signal; the power selection output circuit 40 is configured to, when the first control signal and the second control signal are both at a low level, open the path between the first end and the output end thereof, and close the path between the second end and the output end thereof; when the first control signal and the second control signal are both at a high level, open the path between the second end and the output end thereof, and close the path between the first end and the output end thereof.

[0049] Combine Figure 1Before all power signals of the memory device stabilize upon power-up, the level-converted output control power signal is 0, causing the output to float. At this point, the first control signal is at a low voltage level. Furthermore, when the power selection signal is at a low voltage level, the second control signal is also at a low voltage level. Therefore, when both the first and second control signals are at low voltage levels, the power selection output circuit 40 only outputs the first power signal. This eliminates the problem of a short circuit between the first and second power signals during a specific power-up process and improves the power selection reliability of the power selection circuit.

[0050] Combine Figure 2 The power selection output circuit 40 includes: a first PMOS transistor P1, a first NMOS transistor N1, and a second NMOS transistor N2; the threshold voltage of the first NMOS transistor N1 is greater than the threshold voltage of the second NMOS transistor N2; the first PMOS transistor P1, whose first end serves as the first end of the power selection output circuit, whose control end is connected to the output end of the first control circuit for receiving the first control signal, and whose second end is connected to the first end of the first NMOS transistor N1; the first NMOS transistor N1, whose control end is connected to the output end of the first control circuit for receiving the first control signal, and whose second end is connected to the first end of the second NMOS transistor N2, whose first end and the second end of the first transistor are connected to serve as the output end of the power selection output circuit; the second end of the second NMOS transistor N2, whose second end serves as the second end of the power selection output circuit, and whose control end is connected to the second end of the second control circuit for receiving the second control signal.

[0051] Combine Figure 2 The first NMOS transistor N1 uses an NMOS transistor with a thick gate oxide. NMOS transistors with thick gate oxides can be used in voltage domains with higher-level power supplies. Here, because the first terminal of the first NMOS transistor N1 is connected to the first power supply signal (VPP power supply), the maximum power level of the VPP power supply can reach 3V. Therefore, an NMOS transistor with a thick gate oxide is required to prevent breakdown by the VPP power supply.

[0052] Combine Figure 2Before all the power supply signals of the memory are stable after power-on, the control power supply signal output after level conversion is 0, causing the output to float. At this time, the first control signal is a low-level voltage. When the first control signal is a low-level voltage, the control end of the first PMOS transistor P1 and the control end of the first NMOS transistor N1 both receive the low-level first control signal. The first PMOS transistor P1 is turned on under the first control signal of the low-level voltage, that is, the path between the first power supply signal and the output end of the power selection output circuit is turned on, and the first power supply signal is output. The first NMOS transistor N1 will not be turned on under the first control signal of the low-level voltage, and the path between the second power supply signal and the output end of the power selection output circuit is not turned on, and the second power supply signal will not be output. Therefore, the problem of short circuit between the first power supply signal and the second power supply signal during a specific power-on process is solved, and the power selection reliability of the power selection circuit is improved.

[0053] Combine Figure 3 The power selection output circuit may further include: a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, and a fifteenth NMOS transistor N15; the threshold voltage of the thirteenth PMOS transistor P13 is greater than the threshold voltage of the twelfth PMOS transistor P12; the first end of the twelfth PMOS transistor P12 serves as the first end of the power selection output circuit 40, the control end of the twelfth PMOS transistor P12 is connected to the output end of the first control circuit 20 for receiving the first control signal, and the second end of the twelfth PMOS transistor P12 is connected to the first end of the thirteenth PMOS transistor P13; the control end of the thirteenth PMOS transistor P13 is connected to the output end of the second control circuit 30 for receiving the second control signal, the second end of the thirteenth PMOS transistor P13 is connected to the first end of the fifteenth NMOS transistor N15, and the second end of the thirteenth NMOS transistor N15 is connected to the first end of the fifteenth NMOS transistor N15 to serve as the output end of the power selection output circuit 40; the second end of the fifteenth NMOS transistor N15 serves as the second end of the power selection output circuit 40, and the control end of the fifteenth NMOS transistor N15 is connected to the second end of the second control circuit 30 for receiving the second control signal.

[0054] Combine Figure 3 The thirteenth PMOS transistor P13 uses a PMOS transistor with a thick gate oxide. A PMOS transistor with a thick gate oxide can be used in a voltage domain with a higher power level. Here, because the first terminal of the thirteenth PMOS transistor P13 is connected to the first power signal (VPP power supply), the maximum power level of the VPP power supply can reach 13V. Therefore, a PMOS transistor with a thick gate oxide is required to prevent breakdown by the VPP power supply.

[0055] Combine Figure 3Before all power supply signals of the memory device stabilize upon power-up, the control power supply signal output after level conversion is 0, causing the output to float. At this time, the first control signal is at a low voltage level. The control terminal of the twelfth PMOS transistor P12 receives the first control signal at a low voltage level. Furthermore, when the power selection signal is at a low voltage level, the second control signal is also at a low voltage level. The control terminal of the thirteenth PMOS transistor P13 receives the second control signal at a low voltage level. The twelfth PMOS transistor P12 conducts under the first control signal at a low voltage level, thereby connecting the first power supply signal to the output terminal of the power selection output circuit 40 and outputting the first power supply signal. The thirteenth PMOS transistor P13 does not conduct under the tenth control signal at a low voltage level, thereby disconnecting the second power supply signal from the output terminal of the power selection output circuit 40 and preventing the second power supply signal from being output. Therefore, when both the first and second control signals are at low voltage levels, the power selection output circuit 40 only outputs the first power supply signal, thereby resolving the issue of a short circuit between the first and second power supply signals during a specific power-up process and improving the power selection reliability of the power selection circuit.

[0056] Combine Figure 4 The power selection output circuit includes: a second PMOS transistor P2, a third PMOS transistor P3, a third NMOS transistor N3, and a fourth NMOS transistor N4; the threshold voltage of the third PMOS transistor P3 is greater than the threshold voltage of the second PMOS transistor P2; the second PMOS transistor P2 has a first end serving as the first end of the power selection output circuit, a control end connected to the output end of the first control circuit for receiving the first control signal, and a second end connected to the first end of the third PMOS transistor P3; the third PMOS transistor P3 has a control end connected to the output end of the second control circuit for receiving the second control signal, a second end connected to the first end of the second PMOS transistor P2, and a second end connected to the first end of the third NMOS transistor N3 serving as the output end of the power selection output circuit 40; the third NMOS transistor N3 has a second end connected to the first end of the fourth NMOS transistor N4; the fourth NMOS transistor N4 has a second end serving as the second end of the power selection output circuit 40, and a control end connected to the second end of the second control circuit for receiving the second control signal.

[0057] Combine Figure 4Before all the power signals of the memory are powered on and stabilized, the control power signal output after level conversion is 0, causing the output to float. At this time, the first control signal is a low-level voltage. The control end of the second PMOS transistor receives the first control signal of the low-level voltage, and the control end of the third NMOS transistor N3 receives the first control signal of the low-level voltage. And when the power selection signal is low, the second control signal is also low. The control end of the third PMOS transistor P3 receives the second control signal of the low-level voltage, and the control end of the fourth NMOS transistor N4 receives the first control signal of the low-level voltage. The second PMOS transistor P2 is turned on under the first control signal of the low-level voltage, and the third PMOS transistor P3 is turned on under the second control signal of the low-level voltage, that is, the path between the first power signal and the output end of the power selection output circuit 40 is connected, and the first power signal is output. The third NMOS transistor N3 and the fourth NMOS transistor N4 will not be turned on under the control signal of a low-level voltage, and thus the path between the second power supply signal and the output end of the power supply selection output circuit will not be conductive, and the second power supply signal will not be output. Therefore, when the first control signal and the second control signal are both low-level voltages, the power supply selection output circuit 40 only outputs the first power supply signal, thereby solving the problem of short circuit between the first power supply signal and the second power supply signal during a specific power-on process, and improving the power supply selection reliability of the power supply selection circuit.

[0058] Combine Figure 5 , the first control circuit 20 receives the local power signal provided by the local power generating circuit 211, and in response to the local power signal at a high level, converts the power selection signal into the first control signal in the second voltage domain for output; the first voltage value of the high level of the first voltage domain is lower than the second voltage value of the high level of the second voltage domain, and the voltage value of the local power signal is between the first voltage value and the second voltage value.

[0059] Combine Figure 5 , the first control circuit 20 can convert the power selection signal into a high-level first control signal under the action of a high-level local power signal. Moreover, the output of the first control circuit 20 is floating under the action of a low-level local power signal, and may form a low-level first control signal under the action of a small disturbance voltage. The power selection output circuit 40 can control the path between its first end and its output end according to the level of the first control signal, without having to wait for all power signals to be stable after power-on to control the output power through a stable control power signal. This eliminates the defect in the related art that all power signals need to be stable after power-on before the output power can be controlled through a stable control power signal, solves the problem of short circuit between two power signals during a specific power-on process, and improves the power selection reliability of the power selection circuit.

[0060] Please combine Figure 6 The first control circuit 20 includes: a first level conversion circuit 21 and a first drive circuit 22; the first level conversion circuit 21, whose input end receives the power selection signal, and whose output end is connected to the input end of the first drive circuit 22, whose first power end receives the first power signal, and is connected to the local power generation circuit 211; under the control of the local power signal, it converts the power selection signal into a control voltage at the same level as the power selection signal, and provides it to the first drive circuit 22; the first drive circuit 22, whose output end serves as the output end of the first control circuit 20, outputs a high-level first control signal according to the high-level control voltage, and outputs a low-level first control signal according to the low-level control voltage.

[0061] Combine Figure 6 When the power selection signal 10 is at a high level, the control voltage is also at a high level. When the power selection signal 10 is at a low level, the control voltage is also at a low level. The first drive circuit 22 can output a high-level or low-level first control signal under the action of control voltages of different levels. In addition, because the power selection output circuit 40 can control whether to output the first power signal according to the level of the first control signal, there is no need to wait for all power signals to be stable after power-on before controlling the output power through a stable control power signal. This eliminates the defect in the related art that all power signals must be stable after power-on before controlling the output power through a stable control power signal. This solves the problem of short circuit between two power signals during a specific power-on process, and improves the power selection reliability of the power selection circuit.

[0062] Combine Figure 7The first level conversion circuit 21 includes: a fourth PMOS transistor P4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a fifth PMOS transistor P5, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a first inverter INV1; the fourth PMOS transistor P4 has a first end receiving a first power supply signal, a control end thereof connected to a second end of the fifth PMOS transistor P5, and a second end thereof connected to a first end of the fifth NMOS transistor N5 and a control end of the fifth PMOS transistor P5; the fifth NMOS transistor N5 has a second end connected to a first end of the sixth NMOS transistor N6, and a control end thereof receiving the local power supply signal. signal; the sixth NMOS transistor N6, a second end of which is grounded, and a control end of which is respectively connected to the power selection signal and the input end of the first inverter INV1; the fifth PMOS transistor P5, a first end of which receives the first power signal, and a second end of which is connected to the first end of the sixth-seventh NMOS transistor N7 and the control end of the fourth PMOS transistor P4; the seventh NMOS transistor N7, a first end of which is connected to the input end of the first driving circuit, a second end of which is connected to the first end of the eighth NMOS transistor N8, and a control end of which receives the local power signal; the eighth NMOS transistor N8, a second end of which is grounded, and a control end of which is connected to the output end of the first inverter INV1.

[0063] Combine Figure 9 The first driving circuit 22 includes: a second inverter INV2 and a third inverter INV3; the first end of the second inverter INV2 serves as the input end of the first driving circuit, and the second end of the second inverter INV2 is connected to the first end of the third inverter INV3, and the second end of the third inverter INV3 serves as the output end of the first driving circuit.

[0064] Combine Figure 7 , the fourth PMOS transistor P4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the fifth PMOS transistor P5, the seventh NMOS transistor N7, the eighth NMOS transistor N8 and the first inverter INV1 form a level converter. Among them, the level converter is a voltage conversion device. The level converter converts the signal from the original voltage domain to another voltage domain, and the logic high and low of the signal remain unchanged. Exemplarily, when the IN of the level converter is high, the OUT of the level converter is pulled high. When the IN of the level converter is low, the OUT of the level converter 21 is pulled low. Combined Figure 9 The second inverter INV2 and the third inverter INV3 can invert the phase of the input signal by 180 degrees. This circuit is used in analog circuits, such as audio amplifiers, clock oscillators, etc.

[0065] Combine Figure 8 In the related art, the power supplies in the memory may include: VDD, VPP and VKK. VDD is an external power supply, which is the power supply for the entire memory. VKK and VPP are the power supplies inside the memory. In one case, the VDD power supply starts to supply power before the VPP power supply reaches the predetermined voltage value. At time point A, the VDD level rises to the threshold voltage (Vth) of the VKK power supply branch in the power selection circuit, and the path from the output end of the power selection circuit to the VKK power supply is turned on, thereby providing VKK power to the virtual word line. Between time point A and time point B, the VPP power supply did not reach the predetermined voltage value, please continue to combine Figure 7 and Figure 9 , the local power signal received by the level converter is 0, and the fifth NMOS transistor N5 and the seventh NMOS transistor N7 of the level converter are grounded and blocked. At this time, the output of the level converter is floating, and the power selection circuit can turn on the path of the VPP power supply under the action of a small disturbance voltage, and then provide VPP power and VKK power to the virtual word line at the same time, so that the VPP power supply and the VKK power supply are short-circuited. At time point B, the VPP power supply reaches a predetermined voltage value, and starts to provide a high-level local power signal to the level converter. The output of the level converter is not floating under the action of the local power signal, and the power selection circuit can selectively provide VPP power or VKK power to the virtual word line under the action of the VDD power supply voltage. Combined with Figure 8 Furthermore, in the related art, there is a problem of short circuit between the VKK power supply and the VPP power supply during a specific power-on process between time point A and time point B, which reduces the power selection reliability of the power selection circuit.

[0066] Combine Figure 7In the disclosed embodiment, when the power select signal 10 provides a low-level voltage to the control terminal of the sixth NMOS transistor N6 in the level shifter, the sixth NMOS transistor N6 will not conduct, and consequently, the fourth PMOS transistor P4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 will not be grounded. The low-level voltage is converted by the first inverter INV1 to a high-level voltage and transmitted to the control terminal of the eighth NMOS transistor N8, turning on the eighth NMOS transistor N8. Consequently, the fifth PMOS transistor P5, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are grounded. The voltage at the first terminal of the seventh NMOS transistor N7 decreases, and the seventh NMOS transistor N7 transmits a low-level voltage to the control terminal of the fourth PMOS transistor P4, turning on the fourth PMOS transistor P4. The first power signal VPP, connected to the first terminal of the fourth PMOS transistor P4, is transmitted to the control terminal of the fifth PMOS transistor P5 via the second terminal of the fourth PMOS transistor P4. Since the voltage of the first power signal VPP is greater than the threshold voltage of the fifth PMOS transistor P5, the fifth PMOS transistor P5 is disconnected. After the fifth PMOS transistor P5 is disconnected, it cannot output the first power supply VPP voltage connected to its first end, and the output voltage provided to the first driving circuit is a low-level voltage. At this time, the first control signal is also a low-level voltage. Figure 9 Because the power selection output circuit 40 can control the output of the first power signal based on the level of the first control signal, the problem of the power selection circuit causing the first power signal and the second power signal to short-circuit under the influence of a small disturbance voltage is eliminated. This ensures that the output of the first power signal is controlled by the power selection signal 10.

[0067] Combine Figure 7 , when the power selection signal 10 provides a high-level voltage to the control end of the sixth NMOS transistor N6 in the level converter, the sixth NMOS transistor N6 is turned on, and then the fourth PMOS transistor P4, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are grounded. The high-level voltage is converted by the first inverter INV1 to form a low-level voltage and transmitted to the control end of the eighth NMOS transistor N8, and the eighth NMOS transistor N8 will not be turned on. Then the fifth PMOS transistor P5, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 will not be grounded. After the sixth NMOS transistor N6 is grounded, the voltage at the first end of the fifth NMOS transistor N5 is reduced, and a low-level voltage is transmitted to the control end of the fifth PMOS transistor P5, and the fifth PMOS transistor P5 is turned on. The first power signal connected to the first end of the fifth PMOS transistor P5 is output through the second end. Since the first power signal VPP is a high-level voltage, the first control signal output by the first drive circuit is also a high-level voltage. Combined Figure 9Because the power selection output circuit 40 can control the output of the first power signal based on the level of the first control signal, the problem of the power selection circuit causing the first power signal and the second power signal to short-circuit under the influence of a small disturbance voltage is eliminated. This ensures that the output of the first power signal is controlled by the power selection signal 10.

[0068] Combine Figure 10 The local power generation circuit 211 includes: a third control circuit 2111 and a fourth control circuit 2112; the third control circuit 2111, whose input end receives a reference power signal, whose first power end receives a first power signal, and whose output end is connected to the input end of the fourth control circuit 2112, is configured to output a reference voltage to the fourth control circuit 2112 according to the reference power signal; the fourth control circuit 2112, whose first power end receives the first power signal, and whose output end serves as the output end of the local power generation circuit 211, is configured to output the local power signal according to the reference voltage.

[0069] In this application example, please continue to combine Figure 11 The reference power signal can be provided by a reference power circuit. The reference power circuit can output a reference power signal with a voltage of 0 before the first power signal reaches a predetermined voltage value, and can output a high-level reference power signal after the first power signal reaches a predetermined voltage value. Figure 10 , the local power generation circuit 211 outputs a high-level local power signal under the action of a high-level reference power signal, and the local power generation circuit 211 outputs a low-level local power signal under the action of a low-level reference power signal. Figure 10 , the first control circuit 20 can convert the power selection signal into a high-level first control signal under the action of a high-level local power signal. The output of the first control circuit 20 is floating under the action of a low-level local power signal, and may then form a low-level first control signal under the action of a small disturbance voltage. However, in this solution, the power selection output circuit 40 can control the path between its first end and its output end according to the level of the first control signal, without having to wait for all power signals to stabilize after power-on to control the output power through a stable control power signal. Furthermore, the problem of short circuit between the two power signals during a specific power-on process is solved, and the power selection reliability of the power selection circuit is improved.

[0070] Combine Figure 11The reference power supply circuit includes: a sixth inverter INV6, a level shifter, a twentieth NMOS transistor N20, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a third operational amplifier AMP3, transistors B1, B2, and B3, coils R1, and R2. The sixth inverter INV6 has an input connected to the TM_VBGR_DIS signal and an output connected to the input of the level shifter. The level shifter has an output connected to the first terminal of the twentieth NMOS transistor N20 and the control terminal of the third operational amplifier AMP3, and its control terminal is connected to the POR_VPPEX_B signal. The twentieth NMOS transistor N20 has a control terminal connected to the POR_VPPEX signal and a second terminal grounded. The POR_VPPEX_B signal and the POR_VPPEX signal have opposite voltage levels. Before the first power signal reaches a predetermined voltage, the POR_VPPEX_B signal is low, and the POR_VPPEX signal is high. When the first power signal reaches a predetermined voltage, the POR_VPPEX_B signal goes high and the POR_VPPEX signal goes low. A third operational amplifier AMP3 has its non-inverting input connected to the second terminal of the sixteenth PMOS transistor P16 and the first terminal of the transistor B1, respectively. Its inverting input is connected to the second terminal of the seventeenth PMOS transistor P17 and the first terminal of the coil R1, respectively. Its output is connected to the control terminals of the sixteenth and seventeenth PMOS transistors P16 and P17, respectively, and the control terminal of the eighteenth PMOS transistor P18, respectively. The first terminal of the eighteenth PMOS transistor P18 is connected to the first power signal, the first terminal of the seventeenth PMOS transistor P17 is connected to the first power signal, and the second terminal is connected to the first terminal of the coil R1. The first terminal of the eighteenth PMOS transistor P18 is connected to the first power signal, the second terminal is connected to the first terminal of the coil R2, and serves as the output terminal of the reference power circuit, outputting the reference power signal. The control terminal and the second terminal of the transistor B1 are grounded. The second terminal of the coil R1 is connected to the first terminal of the transistor B2, and the control terminal and the second terminal of the transistor B2 are grounded. The second end of coil R2 is connected to the first end of transistor B3. The control end and the second end of transistor B3 are grounded. Transistor B1 is smaller than transistors B2 and B3. The threshold voltages of the sixteenth PMOS transistor P16, the seventeenth PMOS transistor P17, and the eighteenth PMOS transistor P18 are all the same.

[0071] Combine Figure 11, wherein the level converter includes: a fourteenth PMOS transistor P14, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, a fifteenth PMOS transistor P15, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19 and a seventh inverter INV7. The fourteenth PMOS transistor P14 has a first terminal receiving the first power supply signal, a control terminal thereof connected to the second terminal of the fifteenth PMOS transistor P15, and a second terminal thereof connected to the first terminal of the sixteenth NMOS transistor N16 and the control terminal of the fifteenth PMOS transistor P15; the sixteenth NMOS transistor N16 has a second terminal connected to the first terminal of the seventeenth NMOS transistor N17, and a control terminal thereof receiving the POR_VPPEX_B signal; the seventeenth NMOS transistor N17 has a second terminal grounded, and a control terminal thereof is connected to the power supply selection signal I0 and the seventh inverter I respectively. The input end of NV7 is connected; the fifteenth PMOS transistor P15, the first end of which receives the first power supply signal, and the second end of which is connected to the first end of the eighteenth NMOS transistor N18 and the control end of the fourteenth PMOS transistor P14; the eighteenth NMOS transistor N18, the first end of which serves as the output end of the level converter, the second end of which is connected to the first end of the nineteenth NMOS transistor N19, and the control end of which receives the POR_VPPEX_B signal; the nineteenth NMOS transistor N19, the second end of which is grounded, and the control end of which is connected to the output end of the seventh inverter INV7.

[0072] Combine Figure 11 Before the first power signal reaches a predetermined voltage value, the POR_VPPEX_B signal is low and the POR_VPPEX signal is high. When the POR_VPPEX_B signal is low, the control terminals of the sixteenth NMOS transistor N16 and the eighteenth NMOS transistor N18 within the level converter are both low and non-conductive, resulting in a low output voltage. The POR_VPPEX signal at the control terminal of the twentieth NMOS transistor N20 is high, and the twentieth NMOS transistor N20 is grounded. After the twentieth NMOS transistor N20 is grounded, the control terminal voltage of the third operational amplifier AMP3 is also low. When the control terminal of the third operational amplifier AMP3 is low, the third operational amplifier AMP3 outputs a high voltage. After receiving the high voltage output by the third operational amplifier AMP3, the control terminal of the eighteenth PMOS transistor P18 is non-conductive, resulting in a reference power signal outputted from the output terminal of the reference power circuit being 0. When the reference power signal is 0, the local power generation circuit outputs a low local power signal.

[0073] Combine Figure 11When the first power supply signal reaches a predetermined voltage, the POR_VPPEX_B signal is high and the POR_VPPEX signal is low. When the POR_VPPEX_B signal is high, the control terminals of the sixteenth and eighteenth NMOS transistors N16 and N18 within the level shifter are both high, and both are grounded, allowing the level shifter to operate normally. Because the TM_VBGR_DIS signal is low, the TM_VBGR_DIS signal, after processing by the sixth inverter, inputs a high-level voltage to the level shifter. After processing the high-level voltage, the output voltage of the level shifter is also high, and the control terminal voltage of the third operational amplifier AMP3 is high. The POR_VPPEX signal at the control terminal of the twentieth NMOS transistor N20 is low, disconnecting the twentieth NMOS transistor N20. When the control terminal voltage of the third operational amplifier AMP3 is high, the output voltage of the third operational amplifier AMP3 is controlled by the voltages at its non-inverting and inverting input terminals. At this time, the non-inverting input terminal of the third operational amplifier AMP3 is powered by the second terminal of the sixteenth PMOS transistor P16, and the inverting input terminal is powered by the second terminal of the seventeenth PMOS transistor P17. The third operational amplifier AMP3 is now dual-powered, and the voltage at its output terminal is low. The control terminal of the eighteenth PMOS transistor P18 is turned on after receiving the low-level voltage output by the third operational amplifier AMP3. Because the VPP voltage at the first terminal of the eighteenth PMOS transistor P18 is higher, the output terminal of the reference power circuit outputs a high-level reference power signal. In response to the high-level reference power signal, the local power generation circuit outputs a high-level local power signal.

[0074] Combine Figure 12The third control circuit includes: a first operational amplifier AMP1, a sixth PMOS transistor P6, a first resistor R1 and a second resistor R2; the fourth control circuit includes: a second operational amplifier AMP2, a seventh PMOS transistor P7, a third resistor R3 and a fourth resistor R4; the first operational amplifier AMP1, its inverting input terminal serves as the input terminal of the third control circuit, its non-inverting input terminal is connected to the second terminal of the first resistor R1, and its output terminal is connected to the control terminal of the sixth PMOS transistor P6; the sixth PMOS transistor P6, its first terminal serves as the first power supply terminal of the third control circuit, and its second terminal is connected to the first terminal of the first resistor R1 and the second terminal an inverting input terminal of the operational amplifier AMP2; a second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded; a non-inverting input terminal of the second operational amplifier AMP2 is connected to the second end of the third resistor R3, and an output terminal of the second operational amplifier AMP2 is connected to the control terminal of the seventh PMOS transistor P7; a first end of the seventh PMOS transistor P7 serves as the first power supply terminal of the fourth control circuit, and a second end of the seventh PMOS transistor P7 serves as the output terminal of the local power generation circuit; a first end of the third resistor R3 is connected to the second end of the seventh PMOS transistor P7, and a second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded.

[0075] Combine Figure 12 After the first power supply signal reaches a predetermined voltage value, the reference power supply signal is amplified by the first operational amplifier AMP1 and transmitted to the sixth PMOS transistor P6. Under the action of the received voltage signal, the sixth PMOS transistor P6 outputs a stable reference voltage. The reference voltage is amplified by the second operational amplifier AMP2 and transmitted to the seventh PMOS transistor P7. Under the action of the received voltage signal, the seventh PMOS transistor P7 outputs a high-level local power supply signal through the second terminal. Figure 10At this time, the first control signal output by the first control circuit has the same level as the power selection signal. In addition, because before the first power signal reaches the predetermined voltage value, the output of the first control circuit 20 is floating under the action of the low-level local power signal, and thus a low-level first control signal may be formed under the action of a small disturbance voltage. Regardless of whether the first control signal is high or low, the power selection output circuit 40 can control whether the path between its first end and its output end is conductive according to the level of the first control signal, without waiting for all power signals to be stable after power-on to control the output power through a stable control power signal. This eliminates the defect in the related art that all power signals need to be stable after power-on before the output power can be controlled through a stable control power signal. This solves the problem of short circuit between two power signals during a specific power-on process, and improves the power selection reliability of the power selection circuit.

[0076] Combine Figure 13 The second control circuit 30 includes: a second level conversion circuit 31 and a second drive circuit 32; the second level conversion circuit 31, whose input end serves as the input end of the second control circuit 30, whose first power supply end receives the third power supply signal, whose second power supply end receives the second power supply signal, and whose output end is connected to the input end of the second drive circuit 32, is used to output the third power supply to the second drive circuit 32 when the power supply selection signal 10 is at a high level, and output the second power supply signal to the second drive circuit 32 when the power supply selection signal 10 is at a low level; the second drive circuit 32, whose second end serves as the output end of the second control circuit 30, outputs the second control signal at a high level in the third voltage domain according to the third power supply, and outputs the second control signal at a low level in the third voltage domain according to the second power supply signal; the third voltage value of the low level of the first voltage domain is higher than the fourth voltage value of the low level of the third voltage domain.

[0077] Combine Figure 13 Since the second drive circuit 32 can output a high-level second control signal based on the third power signal and a low-level second control signal based on the second power signal, the power selection output circuit 40 can selectively output the second power signal based on the level of the second control signal, without waiting for all power signals to be powered up. This eliminates the problem of the power selection circuit short-circuiting the first and second power signals due to a small disturbance voltage. This ensures that the output of the second power signal is controlled by the power selection signal 10.

[0078] Combine Figure 9The second level conversion circuit 31 includes: a fourth inverter INV4, a fifth inverter INV5, an eighth PMOS transistor P8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, a ninth PMOS transistor P9, an eleventh NMOS transistor N11, and a twelfth NMOS transistor N12; the fourth inverter INV4 has an input end serving as an input end of the second level conversion circuit, and an output end thereof is connected to the input end of the fifth inverter INV5 and the control ends of the eighth PMOS transistor P8 and the ninth NMOS transistor N9, respectively; the fifth inverter INV5 has an output end connected to the control ends of the ninth PMOS transistor P9 and the eleventh NMOS transistor N11; the eighth PMOS transistor P8 has a first end receiving a third power supply signal, a second end thereof connected to the first end of the ninth NMOS transistor N9; a first end of the ninth NMOS transistor N9 serving as the output end of the second level shifting circuit and connected to the control end of the twelfth NMOS transistor N12, and a second end thereof connected to the first end of the tenth NMOS transistor N10; a second end of the tenth NMOS transistor N10 receiving the second power supply signal, and a control end thereof connected to the second end of the ninth PMOS transistor P9; a first end of the ninth PMOS transistor P9 receiving the third power supply signal, and a second end thereof connected to the first end of the eleventh NMOS transistor N11; a second end of the eleventh NMOS transistor N11 connected to the first end of the twelfth NMOS transistor N12; a second end of the twelfth NMOS transistor N12 receiving the second power supply signal;

[0079] Combine Figure 9When the power selection signal 10 provides a high-level voltage to the fourth inverter INV4, the fourth inverter INV4 outputs a low-level voltage. The fifth inverter INV5 converts the received low-level voltage into a high-level voltage for output. At this time, the control terminal of the ninth PMOS transistor P9 receives a low-level voltage, and the ninth PMOS transistor P9 turns on and outputs the third power supply signal VDD voltage at its first terminal. When the power selection signal 10 provides a low-level voltage to the fourth inverter INV4, the fourth inverter INV4 outputs a high-level voltage. The fifth inverter INV5 converts the received high-level voltage into a low-level voltage for output. At this time, the control terminal of the ninth PMOS transistor P9 receives a high-level voltage and turns off. The control terminal of the ninth NMOS transistor N9 receives a high-level voltage and turns on. The control terminal of the ninth PMOS transistor P9 receives a low-level voltage and turns on, and transmits the third power supply VDD voltage at its first terminal to the control terminal of the tenth NMOS transistor N10 through its second terminal. Because the third power supply VDD voltage is higher, the tenth NMOS transistor N10 turns on. After the tenth NMOS transistor N10 is turned on, the voltage of the second power supply signal VKK at the second terminal of the ninth NMOS transistor N9 can be output via the first terminal of the eighth NMOS transistor N8. In this embodiment, the first terminal of the ninth NMOS transistor N9 can output the VDD power supply or the VKK power supply based on the voltage level provided by the power selection signal 10. The VDD power supply and the VKK power supply are then used to control the second drive circuit to output a high-level or low-level second control signal. The power selection output circuit can select whether to output the VKK power supply based on the second control signal at different levels. This ensures that the VKK power supply circuit is enabled or disabled under the control of the power selection signal 10, thereby improving the stability of the power selection function of the power selection circuit.

[0080] The second drive circuit includes: a tenth PMOS transistor P10, a thirteenth NMOS transistor N13, an eleventh PMOS transistor P11, and a fourteenth NMOS transistor N14; the tenth PMOS transistor P10 has a first end connected to the third power supply signal, a second end connected to the first end of the thirteenth NMOS transistor N13, and a control end connected to the control end of the thirteenth NMOS transistor N13 as an input end of the second drive circuit; the thirteenth NMOS transistor N13 has a second end connected to the second power supply signal, a first end connected to the second end of the tenth PMOS transistor P10, and then connected to the control ends of the eleventh PMOS transistor P11 and the fourteenth NMOS transistor N14; the eleventh PMOS transistor P11 has a first end connected to the third power supply signal, and a second end connected to the first end of the fourteenth NMOS transistor N14; the fourteenth NMOS transistor N14 has a second end connected to the second power supply signal, and a first end connected to the second end of the eleventh PMOS transistor P11 as an output end of the second drive circuit.

[0081] Combine Figure 9 When the power selection signal 10 provides a high voltage, the second level shifter circuit 31 provides the third power signal VDD to the control terminal of the tenth PMOS transistor P10 and the control terminal of the thirteenth NMOS transistor N13. Because the VDD power supply voltage is high, the thirteenth NMOS transistor N13 turns on and provides the VKK power supply voltage at its second terminal to the control terminals of the eleventh PMOS transistor P11 and the fourteenth NMOS transistor N14. Because the VKK power supply voltage is low, the eleventh PMOS transistor P11 turns on and outputs the third power supply signal VDD at its first terminal as the second control signal. When the power selection signal 10 provides a low voltage, the second level shifter circuit 31 provides the second power signal VKK to the control terminals of the tenth PMOS transistor P10 and the control terminals of the thirteenth NMOS transistor N13. Because the VKK power supply voltage is low, the tenth PMOS transistor P10 turns on and provides the third power supply signal VDD at its first terminal to the control terminals of the eleventh PMOS transistor P11 and the fourteenth NMOS transistor N14. Because the third power signal VDD has a higher voltage, the fourteenth NMOS transistor N14 turns on and outputs the second power signal VKK at its second terminal as the second control signal. The power selection output circuit 40 can select whether to output the second power signal based on the level of the second control signal. This ensures that the activation or deactivation of the second power signal (VKK power circuit) is controlled by the power selection signal 10, improving the reliability of the power selection function of the power selection circuit.

[0082] Figure 14 An optional structural diagram of a memory provided in an embodiment of the present disclosure, such as Figure 14 As shown, the memory 100 includes the power selection circuit 90 provided in the above embodiment.

[0083] In some embodiments of the present disclosure, reference Figure 14 , the memory 100 is a dynamic random access memory (DRAM).

[0084] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0085] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0086] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A power selection circuit, characterized in that: include: a first control circuit configured to receive a power selection signal in a first voltage domain, and generate and output a first control signal in a second voltage domain according to the power selection signal; a second control circuit configured to receive the power selection signal, and generate and output a second control signal in a third voltage domain according to the power selection signal; a power selection output circuit coupled to the first control circuit and the second control circuit, with a first terminal connected to a first power signal and a second terminal connected to a second power signal; the power selection output circuit being configured to control a path between the first terminal and an output terminal thereof according to the first control signal, and to control a path between the second terminal and an output terminal thereof according to the first control signal and the second control signal; The high level voltage value of the second voltage domain is equal to the voltage value of the first power signal, and the low level voltage value of the third voltage domain is equal to the voltage value of the second power signal.

2. The power selection circuit according to claim 1, wherein: The power supply selection output circuit is configured to open the path between its first end and its output end and close the path between its second end and its output end when the first control signal is at a low level; and to open the path between its second end and its output end and close the path between its first end and its output end when both the first control signal and the second control signal are at a high level.

3. The power selection circuit according to claim 1, wherein: The levels of the first control signal and the second control signal are both the same as the level of the power selection signal; the power selection output circuit is configured to open the path between its first end and its output end and close the path between its second end and its output end when the first control signal and the second control signal are both at a low level; and to open the path between its second end and its output end and close the path between its first end and its output end when the first control signal and the second control signal are both at a high level.

4. The power selection circuit according to claim 2, wherein: The power selection output circuit includes: a first PMOS transistor, a first NMOS transistor and a second NMOS transistor; the threshold voltage of the first NMOS transistor is greater than the threshold voltage of the second NMOS transistor; The first PMOS transistor has a first end serving as the first end of the power selection output circuit, a control end connected to the output end of the first control circuit for receiving the first control signal, and a second end connected to the first end of the first NMOS transistor; The first NMOS transistor has a control end connected to the output end of the first control circuit and is used to receive the first control signal, a second end connected to the first end of the second NMOS transistor, and a first end connected to the second end of the first NMOS transistor to serve as the output end of the power selection output circuit; The second NMOS transistor has a second end serving as the second end of the power selection output circuit, and a control end connected to the second end of the second control circuit for receiving the second control signal.

5. The power selection circuit according to claim 3, wherein: The power selection output circuit includes: a second PMOS transistor, a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The second PMOS transistor has a first end serving as the first end of the power selection output circuit, a control end connected to the output end of the first control circuit for receiving the first control signal, and a second end connected to the first end of the third PMOS transistor; the third PMOS transistor, having a control end connected to the output end of the second control circuit and configured to receive the second control signal, a second end connected to the first end of the second PMOS transistor, and a second end connected to the first end of the third NMOS transistor to serve as the output end of the power selection output circuit; The second end of the third NMOS transistor is connected to the first end of the fourth NMOS transistor; The fourth NMOS transistor has a second end serving as the second end of the power selection output circuit, and a control end connected to the second end of the second control circuit for receiving the second control signal.

6. The power selection circuit according to any one of claims 1 to 5, characterized in that: The first control circuit receives a local power signal provided by a local power generation circuit, and in response to the local power signal at a high level, converts the power selection signal into the first control signal in a second voltage domain for output; a first voltage value of the high level of the first voltage domain is lower than a second voltage value of the high level of the second voltage domain, and a voltage value of the local power signal is between the first voltage value and the second voltage value.

7. The power selection circuit according to claim 6, wherein: The first control circuit includes: a first level conversion circuit and a first driving circuit; The first level conversion circuit has an input terminal receiving the power selection signal, an output terminal connected to the input terminal of the first driving circuit, a first power terminal receiving the first power signal, and is connected to the local power generation circuit; under the control of the local power signal, the first level conversion circuit converts the power selection signal into a control voltage at the same level as the power selection signal, and provides the control voltage to the first driving circuit; The output end of the first driving circuit serves as the output end of the first control circuit, and outputs the first control signal of a high level according to the high level control voltage, and outputs the first control signal of a low level according to the low level control voltage.

8. The power selection circuit according to claim 7, characterized in that: The first level conversion circuit includes: a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a first inverter; the fourth PMOS transistor, having a first end receiving the first power signal, a control end connected to the second end of the fifth PMOS transistor, and a second end connected to the first end of the fifth NMOS transistor and the control end of the fifth PMOS transistor; The fifth NMOS transistor has a second terminal connected to the first terminal of the sixth NMOS transistor, and a control terminal receiving the local power signal; The sixth NMOS transistor has a second terminal connected to the ground, and a control terminal connected to the power selection signal and the input terminal of the first inverter respectively; the fifth PMOS transistor, a first end of which receives a first power signal, and a second end of which is connected to the first end of the seventh NMOS transistor and the control end of the fourth PMOS transistor; The seventh NMOS transistor has a first end connected to the input end of the first driving circuit, a second end connected to the first end of the eighth NMOS transistor, and a control end receiving the local power signal; The eighth NMOS transistor has a second terminal connected to the ground and a control terminal connected to the output terminal of the first inverter; The first driving circuit includes: a second inverter and a third inverter; The second inverter has a first end serving as an input end of the first driving circuit, a second end connected to a first end of the third inverter, and a second end of the third inverter serving as an output end of the first driving circuit.

9. The power selection circuit according to claim 6, wherein: The local power generation circuit includes: a third control circuit and a fourth control circuit; The third control circuit has an input terminal receiving a reference power signal, a first power terminal receiving a first power signal, an output terminal connected to the input terminal of the fourth control circuit, and is configured to output a reference voltage to the fourth control circuit according to the reference power signal; The fourth control circuit has a first power supply terminal receiving the first power supply signal and an output terminal serving as an output terminal of the local power supply generating circuit, and is configured to output the local power supply signal according to the reference voltage.

10. The power selection circuit according to claim 9, wherein: The third control circuit includes: a first operational amplifier, a sixth PMOS transistor, a first resistor, and a second resistor; the fourth control circuit includes: a second operational amplifier, a seventh PMOS transistor, a third resistor, and a fourth resistor; the first operational amplifier, having an inverting input terminal serving as an input terminal of the third control circuit, a non-inverting input terminal connected to the second terminal of the first resistor, and an output terminal connected to the control terminal of the sixth PMOS transistor; the sixth PMOS transistor, a first end of which serves as a first power supply end of the third control circuit, and a second end of which is connected to the first end of the first resistor and the inverting input end of the second operational amplifier; The first resistor has a second end connected to the first end of the second resistor, and the second end of the second resistor is grounded; the second operational amplifier, having a non-inverting input terminal connected to the second end of the third resistor, and an output terminal connected to the control terminal of the seventh PMOS transistor; The seventh PMOS transistor has a first terminal serving as the first power supply terminal of the fourth control circuit and a second terminal serving as the output terminal of the local power generation circuit; The third resistor has a first end connected to the second end of the seventh PMOS transistor, a second end connected to the first end of the fourth resistor, and a second end of the fourth resistor is grounded.

11. The power selection circuit according to any one of claims 1 to 5, characterized in that: The second control circuit includes: a second level conversion circuit and a second driving circuit; The second level conversion circuit has an input end serving as an input end of the second control circuit, a first power supply end receiving a third power supply signal, a second power supply end receiving the second power supply signal, and an output end connected to the input end of the second drive circuit, and is configured to output the third power supply to the second drive circuit when the power supply selection signal is at a high level, and output the second power supply signal to the second drive circuit when the power supply selection signal is at a low level; The second end of the second driving circuit serves as the output end of the second control circuit, which outputs the second control signal at a high level in the third voltage domain according to the third power supply, and outputs the second control signal at a low level in the third voltage domain according to the second power supply signal; the third voltage value of the low level of the first voltage domain is higher than the fourth voltage value of the low level of the third voltage domain.

12. The power selection circuit according to claim 11, wherein: The second level conversion circuit includes: a fourth inverter, a fifth inverter, an eighth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a ninth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; The fourth inverter has an input end serving as an input end of the second level conversion circuit, and an output end connected to the input end of the fifth inverter and the control ends of the eighth PMOS transistor and the ninth NMOS transistor, respectively; The fifth inverter has an output end connected to the control ends of the ninth PMOS transistor and the eleventh NMOS transistor; the eighth PMOS transistor, a first terminal of which receives the third power signal, and a second terminal of which is connected to the first terminal of the ninth NMOS transistor; The ninth NMOS transistor has a first end serving as the output end of the second level conversion circuit and connected to the control end of the twelfth NMOS transistor, and a second end connected to the first end of the tenth NMOS transistor; The tenth NMOS transistor has a second terminal receiving a second power signal and a control terminal connected to the second terminal of the ninth PMOS transistor; The ninth PMOS transistor has a first end receiving a third power supply signal, and a second end connected to the first end of the eleventh NMOS transistor; The eleventh NMOS transistor has a second terminal connected to the first terminal of the twelfth NMOS transistor; The twelfth NMOS transistor has a second terminal receiving a second power signal; The second driving circuit includes: a tenth PMOS transistor, a thirteenth NMOS transistor, an eleventh PMOS transistor and a fourteenth NMOS transistor; the tenth PMOS transistor, having a first end connected to the third power supply signal, a second end connected to the first end of the thirteenth NMOS transistor, and a control end connected to the control end of the thirteenth NMOS transistor as an input end of the second driving circuit; The thirteenth NMOS transistor has a second end connected to the second power signal, a first end connected to the second end of the tenth PMOS transistor, and then connected to the control ends of the eleventh PMOS transistor and the fourteenth NMOS transistor; The eleventh PMOS transistor has a first terminal connected to the third power signal, and a second terminal connected to the first terminal of the fourteenth NMOS transistor; The fourteenth NMOS transistor has a second end connected to the second power supply signal, and a first end connected to the second end of the eleventh PMOS transistor as an output end of the second driving circuit.

13. A memory, characterized in that: The memory includes the power selection circuit according to any one of claims 1 to 12.

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