Semiconductor device and counting method

Abstract

The invention provides a semiconductor device capable of improving processing capability and a counting method. According to one embodiment, a semiconductor device includes an oscillator (201) that outputs a first signal (OSC), and a counter (202) that counts the number of cycles of the first signal (OSC). The counter (202) sets the count value CNT of the number of cycles of the first signal to N before the oscillator (201) outputs the Nth (N is an integer of 2 or more) cycle of the first signal.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-104387 (filing date: June 26, 2023), and this application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device having a counter and a counting method. Background Art

[0004] There is known a semiconductor device having a counter for counting the number of periods of a periodic signal. Summary of the invention

[0005] According to one embodiment of the present invention, a semiconductor device and a counting method capable of improving processing capability are provided.

[0006] The semiconductor device of the embodiment includes an oscillator that outputs a first signal and a counter that counts the number of cycles of the first signal. The counter sets the count value of the number of cycles of the first signal to N before the oscillator outputs the Nth (N is an integer greater than or equal to 2) cycle of the first signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing an example of the overall configuration of a memory system including the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a block diagram showing an example of the configuration of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a circuit diagram of a memory cell array included in the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a block diagram showing an example of the configuration of an input circuit included in the semiconductor device according to the first embodiment.

[0011] Figure 5 This is a diagram showing an example of a circuit configuration of an input circuit included in the semiconductor device according to the first embodiment.

[0012] Figure 6 1 is a diagram showing the amplitude waveforms of the signals DQS and bDQS and the signal DQ in the semiconductor device according to the first embodiment.

[0013] Figure 7 This is a diagram showing an example of the overall configuration of a replica circuit included in the semiconductor device according to the first embodiment.

[0014] Figure 8 This is a circuit diagram showing an example of the configuration of a counter included in the semiconductor device according to the first embodiment.

[0015] Fig. 9 This is a table showing a specific example of address information of the count value CNT<15:0> of the status register of the semiconductor device according to the first embodiment.

[0016] Fig.10 This is a diagram showing an example of a command sequence for a counting operation of the semiconductor device according to the first embodiment.

[0017] Fig.11 It is a diagram showing a comparative example of counting operation.

[0018] Fig.12 This is a diagram showing a specific example of the count value CNT of the counting operation of the counter included in the semiconductor device according to the first embodiment.

[0019] Fig.13 This is a flowchart showing an example of the flow of the counting operation of the semiconductor device according to the first embodiment.

[0020] Fig.14 This is a block diagram showing an example of the configuration of a semiconductor device according to a modification of the first embodiment.

[0021] Fig.15 This is a diagram showing an example of a command sequence of command and address input when the first mode is selected in the semiconductor device according to the modification example of the first embodiment.

[0022] Fig.16 This is a diagram showing an example of a command sequence of a feature acquisition operation (GetFeature operation) when the first mode is selected in the semiconductor device according to the modification example of the first embodiment.

[0023] Fig.17 This is a diagram showing an example of a command sequence of a counting operation when the first mode is selected in the semiconductor device according to the modification example of the first embodiment.

[0024] Fig.18 This is a circuit diagram showing an example of the configuration of a counter included in the semiconductor device according to the second embodiment.

[0025] Fig.19 This is a diagram showing an example of a command sequence for a counting operation of the semiconductor device according to the second embodiment.

[0026] Fig. 20 This is a flowchart showing an example of the flow of the counting operation of the semiconductor device according to the second embodiment.

[0027] Fig.21 This is a circuit diagram showing an example of the configuration of a counter included in the semiconductor device according to the third embodiment.

[0028] Fig. 22 This is a diagram showing a specific example of each signal of the counter included in the semiconductor device according to the third embodiment.

[0029] Fig.23 This is a flowchart showing an example of the flow of the counting operation of the semiconductor device according to the third embodiment.

[0030] Fig.24 This is a circuit diagram showing an example of the configuration of a counter included in the semiconductor device according to the fourth embodiment.

[0031] Fig.25 It is a diagram showing a specific example of the signal OSC and the signal OSC_CLK2 and the count value CNT of the counter included in the semiconductor device according to the fourth embodiment.

[0032] Fig.26 This is a diagram showing an example of a command sequence for a counting operation of the semiconductor device according to the fourth embodiment.

[0033] Fig. 27 This is a flowchart showing an example of the flow of the counting operation of the semiconductor device according to the fourth embodiment.

[0034] Fig.28 This is a diagram showing an example of the overall configuration of a replica circuit included in a semiconductor device according to a variation of the fourth embodiment.

[0035] Fig.29 This is a circuit diagram showing an example of the configuration of a counter included in a semiconductor device according to a modification of the fourth embodiment.

[0036] Fig.30 This is a diagram showing an example of a command sequence for a counting operation of a semiconductor device according to a modification of the fourth embodiment.

[0037] Fig.31 This is a flowchart showing an example of the flow of the counting operation of the semiconductor device according to the modification of the fourth embodiment.

[0038] Fig.32 This is a block diagram showing an example of the overall configuration of a semiconductor device according to a first example of the fifth embodiment.

[0039] Fig.33 This is a block diagram showing an example of the overall configuration of a semiconductor device according to a second example of the fifth embodiment.

[0040] Fig.34This is a block diagram showing an example of connection between an oscillator and input / output ports included in the semiconductor device of the second example of the fifth embodiment.

[0041] Fig.35 This is a flowchart showing an example of the flow of the counting operation of the semiconductor device according to the second example of the fifth embodiment. DETAILED DESCRIPTION

[0042] Hereinafter, the embodiments are described with reference to the accompanying drawings. Each embodiment illustrates a device or method for embodying the technical idea of ​​the invention. The accompanying drawings are schematic or conceptual drawings, and the dimensions and proportions of each drawing may not be the same as the actual ones. All descriptions of a certain embodiment are also suitable as descriptions of other embodiments unless explicitly stated or obviously excluded. The technical idea of ​​the present invention is not specified by the shape, structure, configuration, etc. of the constituent elements.

[0043] In addition, in the following description, the same symbols are marked for components having substantially the same function and configuration. The numbers after the characters constituting the reference symbols are referenced by the reference symbols containing the same characters, and are used to distinguish between components having the same configuration. In the case where it is not necessary to distinguish between the components indicated by the reference symbols containing the same characters, these components are respectively referenced by reference symbols containing only characters.

[0044] 1. First Implementation Method

[0045] First, as a first embodiment, a case where the semiconductor device is a NAND (Not and) type flash memory will be described. The semiconductor device is not limited to a NAND type flash memory. Any semiconductor device having an oscillator and a counter may be used.

[0046] 1.1 Composition

[0047] 1.1.1 Memory System Configuration

[0048] First, refer to Figure 1 , an example of the structure of a memory system 1 including a semiconductor device is described. Figure 1 1 is a block diagram showing an example of the overall configuration of the memory system 1. Figure 1 In the example of FIG. 1 , a part of the connection between the components is indicated by an arrow line, but the connection between the components is not limited to this.

[0049] like Figure 1 As shown, the memory system 1 is, for example, a SSD (Solid State Drive). The memory system 1 is connected to a host device (not shown). For example, the host device controls the memory system 1.

[0050] The memory system 1 includes a nonvolatile memory 10 and a memory controller 20 .

[0051] The nonvolatile memory 10 is a nonvolatile storage medium and stores data received from the memory controller 20 in a nonvolatile manner.

[0052] The memory controller 20 is, for example, a SoC (System On a Chip). The memory controller 20 commands the nonvolatile memory 10 to read, write, and erase based on a request (command) from a host device. The memory controller 20 also manages the memory space of the nonvolatile memory 10.

[0053] Next, an example of the internal structure of the nonvolatile memory 10 is described. The nonvolatile memory 10 includes a plurality of memory chips 11. The plurality of memory chips 11 can operate independently. Each memory chip 11 is connected to the memory controller 20 via a NAND bus. In addition, the number of memory chips 11 included in the nonvolatile memory 10 may be one.

[0054] The memory chip 11 is, for example, a semiconductor device equipped with a NAND flash memory. The memory chip 11 stores data in a nonvolatile manner. Alternatively, the memory chip 11 may be another nonvolatile memory.

[0055] The memory chip 11 transmits and receives, for example, an 8-bit signal DQ<7:0> and signals DQS and bDQS with the memory controller 20 (more specifically, the memory interface circuit 27) via the NAND bus. Hereinafter, without limiting any one of the signals DQ<7:0>, it is simply referred to as "signal DQ". The signal DQ is, for example, data, address, instruction, or status information. When the signal DQ is data, the signals DQS and bDQS are selection signals (clock signals) for inputting and outputting the signal DQ. The signal bDQS is an inversion signal of the signal DQS.

[0056] In this embodiment, when data is transmitted from the memory controller 20 to the memory chip 11, the transmission of data (signal DQ) and the transmission of the strobe signal (signals DQS and bDQS) are performed asynchronously. Hereinafter, this data input interface standard is referred to as "Unmatched DQS".

[0057] The memory chip 11 receives various control signals from the memory controller 20 via the NAND bus. The details of the control signals will be described later.

[0058] In addition, the memory chip 11 sends a ready / busy signal bRB to the memory controller 20 via the NAND bus. The ready / busy signal bRB is a signal indicating a state in which the memory chip 11 can receive instructions from the memory controller 20 or a state in which it cannot receive instructions. The ready state is a state in which the memory chip 11 can receive instructions from the memory controller 20. The busy state is a state in which the memory chip 11 cannot receive instructions from the memory controller 20. For example, the ready / busy signal bRB is set to a "low (L)" level when the memory chip 11 is in a busy state.

[0059] Next, an example of the internal structure of the memory controller 20 is described. The memory controller 20 includes a host interface circuit (host I / F) 21, a CPU (Central Processing Unit) 22, a ROM (Read only Memory) 23, a RAM (Random Access Memory) 24, a buffer memory 25, an ECC (Error Checking and Correcting) circuit 26, and a memory interface circuit (memory I / F) 27. These circuits are connected to each other through, for example, an internal bus of the memory controller 20. In addition, each function of the host interface circuit 21, the ECC circuit 26, and the memory interface circuit 27 can be realized by a dedicated circuit, or can be realized by causing the CPU 22 to execute firmware.

[0060] The host interface circuit 21 is an interface circuit connected to the host device. The host interface circuit 21 controls the communication between the host device and the memory controller 20. The host interface circuit 21 sends the request and data received from the host device to the CPU 22 and the buffer memory 25 respectively. In addition, the host interface circuit 21 sends the data in the buffer memory 25 to the host device based on the control of the CPU 22.

[0061] The CPU 22 is a processor. The CPU 22 controls the entire operation of the memory controller 20. For example, the CPU 22 instructs the nonvolatile memory 10 (memory chip 11) to write, read, and erase based on a request from a host device. In addition, the CPU 22 manages the memory area of ​​the nonvolatile memory 10.

[0062] CPU22 performs, for example, command write training on the nonvolatile memory 10 (memory chip 11). Write training is an action for the purpose of adjusting the timing between signal DQ and signals DQS and bDQS. For example, CPU22 causes the memory chip 11 to perform a write action of write training data and a read action of the data. At this time, CPU22 changes the delay time of signal DQ relative to signals DQS and bDQS while sending signals DQS and bDQS as well as signal DQ to the memory chip 11. In addition, CPU22 sets the condition with the highest consistency between the write data and the read data (the delay time of signal DQ relative to signals DQS and bDQS) as the data sending condition. In the following, the delay time of signal DQ relative to signals DQS and bDQS is recorded as time tDQS2DQ.

[0063] For example, in the memory chip 11, the transmission path to the latch circuit for extracting the signal DQ is different between the signals DQS and bDQS and the signal DQ. Therefore, the optimal value of the time tDQS2DQ varies due to changes in the voltage or temperature in the memory chip 11. To cope with this, the CPU 22 appropriately performs write training at an arbitrary timing.

[0064] In addition, CPU22, for example, periodically performs a counting operation of a clock signal (signal OSC described later) generated by an oscillator in the memory chip 11. The clock signal is a pseudo signal of the signal DQS generated in the memory chip 11. In the counting operation, the number of cycles (number of clocks) of the clock signal is counted. CPU22 controls the execution time of the counting operation (hereinafter also referred to as "counting execution time"). The number of cycles (number of counts) of the clock signal in the memory chip 11 changes, like the change in time tDQS2DQ, depending on changes in voltage or temperature in the memory chip 11. Based on the change in the number of cycles, CPU22 predicts the change in time tDQS2DQ and determines whether write training is performed.

[0065] ROM23 is a non-volatile memory. For example, ROM23 is an EEPROM. TM (Electrically ErasableProgrammableRead-OnlyMemory: Electrically ErasableProgrammableRead-OnlyMemory) The ROM 23 is a non-transitory storage medium that stores firmware and programs, etc. For example, the CPU 22 expands the firmware downloaded from the ROM 23 in the RAM 24 .

[0066] RAM 24 is a volatile memory. RAM 24 is a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). RAM 24 can be used as a work area of ​​CPU 22. For example, RAM 24 stores firmware for managing non-volatile memory 10 or various management tables. For example, the result of a counting operation is stored in RAM 24.

[0067] The buffer memory 25 is a volatile memory. The buffer memory 25 is a DRAM or an SRAM, etc. The buffer memory 25 temporarily stores data read from the nonvolatile memory 10 by the memory controller 20 or data received from a host device.

[0068] The ECC circuit 26 is a circuit that performs ECC processing. The ECC processing includes data encoding processing and decoding processing. For example, when the ECC circuit 26 writes data, it performs data encoding processing and generates an error correction code (parity check). In addition, the ECC circuit 26 provides parity check for the data. In addition, when the ECC circuit 26 reads data, it performs decoding processing. In other words, the ECC circuit 26 uses parity check to perform data error correction processing.

[0069] The memory interface circuit 27 controls the communication between the memory controller 20 and the nonvolatile memory 10. The memory interface circuit 27 may have a plurality of channels CH (CH0, CH1, ...). A plurality of memory chips 11 may be connected to each channel CH via a NAND bus. The memory interface circuit 27 sends a signal DQ, a signal DQS and a bDQS, and various control signals to the memory chip 11. In addition, the memory interface circuit 27 receives a signal DQ, a signal DQS and a bDQS, and a ready / busy signal bRB from the memory chip 11.

[0070] 1.1.2 Composition of memory chips

[0071] Next, refer to Figure 2 , an example of the structure of the memory chip 11 is described. Figure 2 1 is a block diagram showing an example of the structure of the memory chip 11 (semiconductor device). Figure 2 In the example of FIG. 1 , a part of the connection between the components is indicated by an arrow line, but the connection between the components is not limited to this.

[0072] like Figure 2As shown, the memory chip (NAND flash memory) 11 includes an input-output circuit 101, a replica circuit 102, a logic control circuit 103, an address register 104, an instruction register 105, a status register 106, a sequencer 107, a ready / busy circuit 108, a voltage generating circuit 109, a memory cell array 120, a row decoder 121, a sense amplifier 122, a data register 123 and a column decoder 124.

[0073] The input / output circuit 101 is a circuit for inputting and outputting the signal DQ, the signal DQS, and the signal bDQS with the memory controller 20. The input / output circuit 101 is connected to the memory controller 20 via a plurality of pads PD (external connection terminals) corresponding to the signal DQ<7:0> and the signal DQS and the signal bDQS. In addition, the input / output circuit 101 is connected to the logic control circuit 103, the address register 104, the instruction register 105, the status register 106, and the data register 123.

[0074] The input-output circuit 101 includes an input circuit 131 and an output circuit 132 .

[0075] The input circuit 131 is a circuit that receives the signal DQ from the memory controller 20. When the signal DQ is data DAT, the input circuit 131 extracts the signal DQ based on the signals DQS and bDQS. Furthermore, the input circuit 131 sends the data DAT to the data register 123. When the signal DQ is address ADD, the input circuit 131 extracts the signal DQ based on the write enable signal bWE described later. Furthermore, the input circuit 131 sends the address ADD to the address register 104. When the signal DQ is command CMD, the input circuit 131 extracts the signal DQ based on the write enable signal bWE. Furthermore, the input circuit 131 sends the command CMD to the command register 105.

[0076] The output circuit 132 is a circuit that sends a signal DQ to the memory controller 20. The output circuit 132 sends the signal DQ together with the signals DQS and bDQS to the memory controller 20. The output circuit 132 sends the data DAT or the status information STS read from the memory cell array 120 to the memory controller 20 as the signal DQ.

[0077] The replica circuit 102 is a circuit that generates a clock signal (signal OSC described later) corresponding to the signal DQS and counts the number of cycles (clock count) of the clock signal. The replica circuit 102 includes a feedback oscillator for generating a clock signal. The feedback path of the oscillator has the same structure as the transmission path of the signal DQS in the input circuit 131. Therefore, the replica circuit 102 can also be referred to as a "DQS oscillator". The replica circuit 102 is connected to the state register 106 and the sequencer 107. The replica circuit 102 sends the count result of the counting operation to the state register 106.

[0078] The logic control circuit 103 is a circuit for performing logic control of the memory chip 11. The logic control circuit 103 is connected to the memory controller 20 via a plurality of pads PD corresponding to respective control signals. In addition, the logic control circuit 103 is connected to the input / output circuit 101 and the sequencer 107. The logic control circuit 103 controls the input / output circuit 101 and the sequencer 107 based on various control signals.

[0079] For example, the logic control circuit 103 receives the chip enable signal bCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal bWE, and the read enable signals RE and bRE as control signals.

[0080] The chip enable signal bCE is a signal for enabling the memory chip 11. The chip enable signal bCE is asserted at, for example, a low ("L") level.

[0081] The command latch enable signal CLE is a signal indicating that the signal DQ is a command. The command latch enable signal CLE is asserted at a high ("H") level, for example.

[0082] Address latch enable signal ALE is a signal indicating that signal DQ is an address. Address latch enable signal ALE is asserted at, for example, "H" level.

[0083] The write enable signal bWE is a signal used to extract the signal DQ when the signal DQ is a command CMD or an address ADD. The write enable signal bWE is established at the timing of extracting the command CMD or the address ADD in the memory chip 11, for example, at an "L" level. Therefore, each time the write enable signal bWE is toggled, the command CMD or the address ADD is extracted to the memory chip 11.

[0084] The write enable signals RE and bRE are signals for causing the memory controller 20 to read data from the memory chip 11. The read enable signal bRE is an inverted signal of the read enable signal RE. The read enable signals RE and bRE are established at, for example, an "L" level. For example, when the memory chip 11 outputs data, it generates signals DQS and bDQS based on the read enable signals RE and bRE.

[0085] The address register 104 is a register for temporarily storing the address ADD. The address register 104 is connected to the input / output circuit 101, the sequencer 107, the row decoder 121, and the column decoder 124. The address ADD includes a row address RAD and a column address CAD. The address register 104 sends the row address RAD to the row decoder 121. In addition, the address register 104 sends the column address CAD to the column decoder 124.

[0086] The command register 105 is a register for temporarily storing the command CMD. The command register 105 is connected to the input / output circuit 101 and the sequencer 107. The command register 105 sends the command CMD to the sequencer 107.

[0087] The status register 106 is a register that temporarily stores the status information STS. The status register 106 is connected to the input / output circuit 101, the replica circuit 102, and the sequencer 107. For example, the status information STS includes information related to the results of the write operation, the read operation, and the erase operation. In addition, the status information STS includes information related to the result of the counting operation of the replica circuit 102. The status information STS is sent to the memory controller 20 as a signal DQ.

[0088] The sequencer 107 is a circuit that controls the entire operation of the memory chip 11. The sequencer 107 is connected to the replica circuit 102, the logic control circuit 103, the address register 104, the command register 105, the status register 106, the ready / busy circuit 108, the voltage generating circuit 109, the row decoder 121, and the sense amplifier 122. The sequencer 107 controls the replica circuit 102, the status register 106, the ready / busy circuit 108, the voltage generating circuit 109, the row decoder 121, and the sense amplifier 122. The sequencer 107 performs a write operation, a read operation, and an erase operation based on the command CMD. The sequencer 107 performs write training. In addition, the sequencer 107 controls the counting operation of the replica circuit 102.

[0089] The ready / busy circuit 108 is a circuit for generating a ready / busy signal bRB. The ready / busy circuit 108 is connected to the sequencer 107. The ready / busy circuit 108 generates the ready / busy signal bRB based on the control of the sequencer 107. The ready / busy circuit 108 sends the ready / busy signal bRB to the memory controller 20.

[0090] The voltage generating circuit 109 generates various voltages used for programming, reading, and erasing operations based on the control of the sequencer 107. The voltage generating circuit 109 supplies various voltages to the memory cell array 120, the row decoder 121, the sense amplifier 122, and the like.

[0091] The memory cell array 120 is a collection of a plurality of memory cell transistors (also referred to as "memory cells") arranged in a row. The memory cell array 120 includes a plurality of blocks BLK. The block BLK is, for example, a collection of a plurality of memory cell transistors whose data are erased at once. Figure 2 In the example of FIG. 1 , the memory cell array 120 includes four blocks BLK0 , BLK1 , BLK2 , and BLK3 . The number of blocks BLK in the memory cell array 120 is arbitrary.

[0092] The row decoder 121 is a decoding circuit for the row address RAD. The row decoder 121 is connected to the address register 104, the sequencer 107, the voltage generating circuit 109, and the memory cell array 120. The row decoder 121 selects any block BLK based on the decoding result of the row address RAD. The row decoder 121 applies a voltage to the row-direction wiring (the word line and the selection gate line described later) of the selected block BLK.

[0093] The sense amplifier 122 is a circuit for writing and reading data DAT. The sense amplifier 122 is connected to the sequencer 107, the voltage generating circuit 109, the memory cell array 120, and the data register 123. The sense amplifier 122 reads data DAT from the memory cell array 120 during a read operation. In addition, the sense amplifier 122 supplies a voltage corresponding to the write data DAT to the memory cell array 120 during a write operation.

[0094] The data register 123 is a register for temporarily storing data DAT. The data register 123 is connected to the input / output circuit 101, the sequencer 107, the sense amplifier 122, and the column decoder 124. The data register 123 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0095] The column decoder 124 is a circuit that decodes the column address CAD. The column decoder 124 is connected to the address register 104, the sequencer 107, and the data register 123. The column decoder 124 receives the column address CAD from the address register 104. The column decoder 124 selects a latch circuit in the data register 123 based on the decoding result of the column address CAD.

[0096] 1.1.3 Circuit structure of memory cell array

[0097] Next, refer to Figure 3, an example of the circuit structure of the memory cell array 120 is described. Figure 3 is a circuit diagram of the memory cell array 120. In addition, Figure 3 The example shows the circuit configuration of one block BLK.

[0098] like Figure 3 As shown, the block BLK includes a plurality of string units SU. The string unit SU is, for example, a collection of a plurality of NAND strings NS selected together in a write operation or a read operation. Figure 3 In the example of , the block BLK includes four string units SU0 to SU3. The number of string units SU included in the block BLK is arbitrary.

[0099] Next, the internal structure of the string unit SU is described. The string unit SU includes multiple NAND strings NS. The NAND string NS is a collection of multiple memory cell transistors connected in series. For example, n+1 (n is an integer greater than 1) NAND strings NS in the string unit SU are respectively connected to n+1 bit lines BL0 to BLn.

[0100] Next, the internal structure of the NAND string NS will be described. Each NAND string NS includes a plurality of memory cell transistors MC and selection transistors ST1 and ST2. Figure 3 In the example shown, the NAND string NS includes eight memory cell transistors MC0 to MC7. The number of memory cell transistors MC in the NAND string NS is arbitrary.

[0101] The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge accumulation layer. The memory cell transistor MC can be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type. The MONOS type charge accumulation layer uses an insulating layer. The FG type charge accumulation layer uses a conductive layer.

[0102] The selection transistors ST1 and ST2 are used to select the string unit SU in various operations. The number of the selection transistors ST1 and ST2 is arbitrary. It is sufficient that the NAND string NS includes at least one selection transistor ST1 and ST2.

[0103] The memory cell transistors MS in each NAND string NS and the current paths of the selection transistors ST1 and ST2 are connected in series. More specifically, the current paths of the selection transistor ST2, the memory cell transistors MC0 to MC7, and the selection transistor ST1 are connected in series in sequence. The drain of the selection transistor ST1 is connected to any bit line BL. The source of the selection transistor ST2 is connected to the source line SL.

[0104] The control gates of multiple memory cell transistors MC0 to MC7 in the same block BLK are respectively connected to word lines WL0 to WL7. More specifically, for example, block BLK includes four string units SU0 to SU3. In addition, each string unit SU0 to SU3 includes multiple memory cell transistors MC0. The control gates of these multiple memory cell transistors MC0 in block BLK are connected to one word line WL0. The same is true for memory cell transistors M1 to MC7.

[0105] The gates of the selection transistors ST1 in the string unit SU are connected in common to one selection gate line SGD. More specifically, the string unit SU0 includes a plurality of selection transistors ST1. The gates of the plurality of selection transistors ST1 in the string unit SU0 are connected in common to the selection gate line SGD0. Similarly, the gates of the plurality of selection transistors ST1 in the string unit SU1 are connected in common to the selection gate line SGD1. The gates of the plurality of selection transistors ST1 in the string unit SU2 are connected in common to the selection gate line SGD2. The gates of the plurality of selection transistors ST1 in the string unit SU3 are connected in common to the selection gate line SGD3.

[0106] The gates of multiple selection transistors ST2 in the same block BLK are connected to one selection gate line SGS. More specifically, for example, block BLK includes four string units SU0 to SU3. And, each of the string units SU0 to SU3 includes multiple selection transistors ST2. The gates of these multiple selection transistors ST2 in block BLK are connected to one selection gate line SGS. In addition, similar to the selection gate line SGD, a selection gate line SGS that is different for each string SU can also be set.

[0107] The word lines WL0 ˜ WL7 , the selection gate lines SGD0 ˜ SGD3 , and the selection gate line SGS are respectively connected to the row decoder 121 .

[0108] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. The same column address CAD is assigned to a plurality of NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 122 .

[0109] The source line SL is shared by, for example, a plurality of blocks BLK.

[0110] In one string unit SU, a collection of multiple memory cell transistors MC connected to one word line WL is referred to as a "unit group CU". For example, when the memory cell transistor MC stores 1 bit of data, the storage capacity of the unit group CU is defined as "1 page of data". Based on the number of bits of data stored in the memory cell transistor MC, the unit group CU may have a storage capacity of more than 2 pages of data.

[0111] 1.1.4 Input circuit configuration

[0112] 1.1.4.1 Input circuit configuration

[0113] Next, refer to Figure 4 , an example of the configuration of the input circuit 131 is described. Figure 4 1 is a block diagram showing an example of the configuration of the input circuit 131. Figure 4 The example of FIG. 1 shows a case where the input signal DQ is data DAT, that is, a configuration in which the signal DQ is extracted based on the signals DQS and bDQS.

[0114] like Figure 4 As shown, the input circuit 131 includes an input receiver (IREC: Input RECeiver) 141 , a delay circuit 142 and a latch circuit 143 .

[0115] The input receiver 141 is a receiving circuit for the signals DQS and bDQS. The two input terminals of the input receiver 141 are respectively connected to the pad PD to which the signal DQS is input and the pad PD to which the signal bDQS is input. In addition, the output terminal of the input receiver 141 is connected to the delay circuit 142. For example, the input receiver 141 outputs an inversion signal synchronized with the signals DQS and bDQS. The output signal of the input receiver 141 is input to the delay circuit 142.

[0116] The delay circuit 142 is a circuit that delays the signal received from the input receiver 141. The delay circuit 142 is connected to the latch circuit 143. In addition, the delay circuit 142 can be omitted. In addition, a driver or the like for the purpose of signal transmission can also be set in the wiring path between the input receiver 141 and the latch circuit 143. The output signal of the input receiver 141 is delayed by the delay circuit 142 and the wiring delay of the wiring path connecting the input receiver 141 and the latch circuit 143, and is input to the latch circuit 143. The signals input to the latch circuit 143 are recorded as signals CK and bCK. The signal CK is a selection signal that delays the signal DQS. The signal bCK is an inversion signal of the signal CK. The delay time of the signals CK and bCK relative to the signals DQS and bDQS is equivalent to the time tDQS2DQ. That is, the signals DQS and bDQS after the delay time tDQS2DQ are input to the latch circuit 143.

[0117] The latch circuit 143 is a circuit for extracting the signal DQ based on the signals CK and bCK (the signals DQS and bDQS after the delay time tDQS2DQ). <0> ~DQ <7> For example, the latch circuit 143 extracts the data of the odd bits of each signal DQ based on the signal CK, and extracts the data of the even bits of each signal DQ based on the signal bCK. For example, the latch circuit 143 may include a plurality of LTSAs (Latch-Type voltage Sense Amplifiers) corresponding to each signal DQ, and may also include a plurality of DTSAs (Double-Tail latch-type voltage Sense Amplifiers). The latch circuit 143 outputs the data corresponding to the signal DQ. <0> ~DQ <7> The signal DQ_INT <0> ~DQ_INT <7> .

[0118] The latch circuit 143 is arranged relatively close to the pad PD of the input signal DQ. By being arranged relatively close, the wiring length connecting the pad PD and the latch circuit 143 can be relatively shortened. In addition, the number of circuits provided in the path connecting the pad PD of the input signal DQ and the latch circuit 143 is less than the number of circuits (including the input receiver 141 and the delay circuit 142) provided in the path connecting the pad PD of the input signal DQS and the latch circuit 143. Thus, the fluctuation and time difference of the signal DQ in the latch circuit 143 can be reduced. In addition, for the purpose of correcting signal degradation, a CTLE (Continuous Time Linear Equalizer) or the like can also be configured between the pad PD and the latch circuit 143. CTLE is a circuit that compensates for insertion loss and reduces fluctuations.

[0119] 1.1.4.2 Circuit structure of input circuit

[0120] Next, refer to Figure 5 , an example of the circuit configuration of the input circuit 131 is described. Figure 5 1 is a diagram showing an example of the circuit configuration of the input circuit 131. Figure 5 In the example of FIG. 1 , the delay circuit 142 and the signal DQ are omitted for simplicity of description. <1> ~DQ <6> Each of the latch circuits 143. In addition, Figure 5 In the example, signal bCK is omitted.

[0121] like Figure 5As shown, the input receiver 141 includes a comparator 151. The comparator 151 includes a first input terminal to which a signal DQS is input, a second input terminal to which a signal bDQS is input, and an output terminal. The first input terminal is connected to the pad PD to which the signal DQS is input. The second input terminal is connected to the pad PD to which the signal bDQS is input. For example, the comparator 151 outputs an inversion signal synchronized with the signals DQS and bDQS. The output terminal is connected to the latch circuit 143 via drivers 152 and 153. For example, the driver 152 is a CML (Current Mode Logic) circuit that amplifies the amplitude of the signal output by the comparator 151. In addition, for example, the driver 153 is a C2C (Cml ToCmos: Current Mode Logic to Complementary Metal Oxide Semiconductor) circuit that converts the signal amplified by the driver 152 into a CMOS level.

[0122] The latch circuit 143 includes a plurality of comparators 154 corresponding to the respective signals DQ. In addition, a plurality of comparators 154 may be provided for one signal DQ. For example, a comparator 154 that operates based on the signal CK and a comparator 154 that operates based on the signal bCK may be provided for one signal DQ.

[0123] The comparator 154 includes a first input terminal, a second input terminal, a clock signal input terminal, and an output terminal. The first input terminal is connected to a pad PD to which a corresponding signal DQ is input. A reference voltage VREF is input to the second input terminal, for example. The reference voltage VREF is a reference voltage for determining the logic level of the signal DQ. A signal CK is input to the clock signal input terminal, for example. The clock signal input terminal is connected to the driver 153. The wiring delay generated in the wiring path connecting the output terminal of the comparator 151 and the clock signal input terminal of the comparator 154 is equivalent to the time tDQS2DQ. The signal DQ_INT is output from the output terminal of the comparator 154. Figure 5 In the example, when the signal CK is at a high (“H”) level, the comparator 154 outputs the result of comparing the signal DQ with the reference voltage VREF. For example, when the voltage of the signal DQ is higher than the reference voltage VREF, the comparator 154 outputs the signal DQ_INT at a low (“L”) level.

[0124] A comparator 154 is provided for each signal DQ. Therefore, for each comparator 154, the wiring path (wiring length) connecting the output terminal of the comparator 151 and the clock signal input terminal of the comparator 154 is different. Therefore, for each signal DQ, the amount of wiring delay generated in the wiring path is different. In other words, the time tDQS2DQ may be different for each signal DQ. For example, in write training, the optimal time tDQS2DQ can be set according to each signal DQ.

[0125] 1.1.4.3 Input Timing of Signals DQS, bDQS, and DQ

[0126] Next, refer to Figure 6 , an example of the input timing of the signals DQS, bDQS, and the signal DQ is described. Figure 6 The diagram shows the amplitude waveforms of the signals DQS and bDQS, and the signal DQ. Figure 6 The example shows the amplitude waveforms of the signals DQS and bDQS and the signal DQ in the pad PD, and the amplitude waveforms of the signals CK and bCK (delayed signals DQS and bDQS) and the signal DQ in the latch circuit 143.

[0127] like Figure 6 As shown, in this embodiment, data (signal DQ) and selection signals (signals DQS and bDQS) are input asynchronously to the memory chip 11. That is, the input timing of the signals DQS and bDQS in the pad PD is not synchronized with the input timing of the signal DQ. The time difference between the signals DQS and bDQS and the signal DQ is the time tDQS2DQ.

[0128] The latch circuit 143 is arranged relatively close to the pad PD corresponding to the signal DQ. Therefore, the latch circuit 143 receives the signal DQ from the pad PD in a state with relatively less delay. In addition, the latch circuit 143 receives the signals CK and bCK that delay the signals DQS and bDQS. In the latch circuit 143, the input timing of the signals CK and bCK is synchronized with the input timing of the signal DQ. Thus, the latch circuit 143 can extract the signal DQ based on the signals CK and bCK. In the write training, the timing of the signal DQ is optimized in such a way that the delay time of the signals CK and bCK corresponding to the signals DQS and bDQS becomes the time tDQS2DQ.

[0129] 1.1.5 Construction of the replica circuit

[0130] 1.1.5.1 Overall structure of the replica circuit

[0131] First, refer to Figure 7 , an example of the overall structure of the replica circuit 102 is described. Figure 7 1 is a diagram showing an example of the overall configuration of the replica circuit 102 .

[0132] like Figure 7 As shown, the replica circuit 102 includes an oscillator 201 and a counter 202 .

[0133] In this embodiment, the replica circuit 102 includes a signal corresponding to the signal DQ <0> ~DQ <7> The case of a set of one oscillator 201 and a counter 202 corresponding to any one time tDQS2DQ will be described below. In addition, the replica circuit 102 may include a plurality of sets of oscillators 201 and counters 202 corresponding to a plurality of signals DQ.

[0134] When the replica circuit 102 includes a set of an oscillator 201 and a counter 202, the set of the oscillator 201 and the counter 202 may correspond to the signal DQ of the comparator 154 whose wiring length between the comparator 151 input to the input receiver 141 and the comparator 154 of the latch circuit 143 is the longest (wiring delay is the longest). Alternatively, the set of the oscillator 201 and the counter 202 may correspond to the signal DQ input to the comparator 154 whose wiring length is the average length, or to the signal DQ input to the comparator 154 whose wiring length is the shortest. In other words, the set of the oscillator 201 and the counter 202 may correspond to the signal DQ with the longest time tDQS2DQ, may correspond to the signal DQ with the average time tDQS2DQ, or may correspond to the signal DQ with the shortest time tDQS2DQ.

[0135] The oscillator 201 is a feedback type oscillator circuit. The oscillator 201 outputs a signal OSC. The signal OSC is a clock signal. The oscillator 201 includes a comparator 203 and drivers 204 and 205 .

[0136] The comparator 203 has, for example, the same configuration as the comparator 151 of the input receiver 141. The output terminal of the comparator 203 is connected to the first input terminal and the second input terminal of the comparator 203. That is, the output signal is fed back. The comparator 203 inverts the logic level of the signal input to the first input terminal and outputs the signal. Therefore, the output signal of the oscillator 201 oscillates. For example, if the comparator 203 inputs a signal of "L" level to the first input terminal (output signal of the comparator 203), a signal of "H" level is output.

[0137] The wiring path (feedback path) connecting the output terminal of the comparator 203 with the first input terminal and the second input terminal has the same characteristics as that of the circuit to be used. Figure 5The wiring path connecting the output terminal of the comparator 151 of the input receiver 141 and the clock signal input terminal of the comparator 154 of the latch circuit 143 described above has the same structure and wiring length. For example, in the wiring path connecting the output terminal of the comparator 203 with the first input terminal and the second input terminal, drivers 204 and 205 are provided in the same manner as the input circuit 131. For example, the driver 204 is a CML circuit having the same structure as the driver 152. For example, the driver 205 is a C2C circuit having the same structure as the driver 153. In the wiring path connecting the output terminal of the comparator 203 with the first input terminal and the second input terminal, a wiring delay of the time tDQS2DQ is generated in the same manner as the input circuit 131. Therefore, the logic level of the output signal of the comparator 203 is inverted every time tDQS2DQ. Therefore, the time of one cycle (one period) of the signal OSC is twice the time tDQS2DQ, that is, 2×(tDQS2DQ).

[0138] The signal OSC output from the oscillator 201 is input to the counter 202. The counter 202 counts the number of cycles of the signal OSC. The counter 202 outputs a count value CNT as a counting result. For example, the count value CNT may be a 16-bit signal. In this case, the counter 202 outputs a 16-bit count value CNT<15:0>. The replica circuit 102 sends the count value CNT<15:0> to the status register 106. In addition, the number of bits of the count value CNT is arbitrary.

[0139] 1.1.5.2 Counter Configuration

[0140] Next, refer to Figure 8 , an example of the structure of the counter 202 is described. Figure 8 2 is a circuit diagram showing an example of the configuration of the counter 202 .

[0141] like Figure 8 As shown, the counter 202 of this embodiment counts the number of cycles at the falling edge of the signal OSC, that is, at the timing when the signal changes from the "H" level to the "L" level. The counter 202 adds +1 to the number of cycles and outputs the result as the count value CNT<15:0>.

[0142] The counter 202 includes an inverter 211, an AND circuit 212, a plurality of flip-flops 213, and an adder 214. For example, when the count value CNT is a 16-bit signal, the counter 202 includes 16 flip-flops 213. <0> ~CNT <15> In the case of the flip-flop 213, they are recorded as flip-flops 213_0 to 213_15.

[0143] The inverter 211 inverts the signal OSC and outputs it. The input terminal of the inverter 211 is connected to the oscillator 201 . The signal OSC is input to the input terminal of the inverter 211 . The output terminal of the inverter 211 is connected to the first input terminal of the AND circuit 212 .

[0144] The start signal EN is input to the second input terminal of the AND circuit 212. The start signal EN is a start signal for the oscillator 201 and the counter 202. For example, while the start signal EN is at the "H" level, the oscillator 201 outputs the signal OSC. In addition, the counter 202 performs a counting operation. The start signal EN is supplied, for example, from the sequencer 107. The output terminal of the AND circuit 212 is connected to the clock signal input terminal of the flip-flop 213_0. The AND circuit 212 performs a logical product (AND) operation on the inversion signal of the signal OSC and the start signal EN, and outputs the result as the signal OSC_CLK. The signal OSC_CLK is a clock signal that inverts the signal OSC when the start signal EN is at the "H" level. For example, when the start signal EN is at the "H" level and the inversion signal of the signal OSC is at the "H" level (that is, the signal OSC is at the "L" level), the signal OSC_CLK is set to the "H" level.

[0145] The flip-flop 213 is a D flip-flop provided in plurality according to the number of bits of the count value CNT, and includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0146] The flip-flop 213 extracts (stores) the data input from the data input terminal D at the rising edge of the clock signal input to the clock signal input terminal, that is, at the timing of shifting from the "L" level to the "H" level. Thus, the output data is updated. The data input terminal D of the flip-flop 213 is connected to the inverting output terminal Qn of the flip-flop 213. Therefore, the flip-flop 213 inverts the signal output from the output terminal Q and the inverting output terminal Qn at the rising edge of the clock signal input to the clock signal input terminal. The reset signal RST is input to the reset signal input terminal R of the flip-flop 213. If the reset signal RST of the "H" level is input to the reset signal input terminal R, the flip-flop 213 is reset. That is, a signal of the "L" level is output from the output terminal Q of the flip-flop 213, and a signal of the "H" level is output from the inverting output terminal Qn. The reset signal RST is supplied, for example, from the sequencer 107.

[0147] The flip-flops 213_0 to 213_15 are connected in multiple stages. More specifically, the signal OSC_CLK is input to the clock signal input terminal of the flip-flop 213_0. The inverted data of the data output from the output terminal Q of the flip-flop 213 of the previous stage is input to the clock signal input terminals of the flip-flops 213_1 to 213_15. For example, the flip-flop 213 is referred to as the flip-flop 213_k using a variable k (k is an integer from 1 to 15). In the above case, the inverted data of the data output from the output terminal Q of the flip-flop 213_(k-1) of the previous stage is input to the clock signal input terminal of the flip-flop 213_k.

[0148] For example, the signal output from the output terminal Q of the flip-flop 213 is referred to as the signal preCNT. The output terminals Q of the flip-flops 213_0 to 213_15 each output the signal preCNT. <0> ~preCNT <15> . Signal preCNT <0> ~preCNT <15> Indicates the number of cycles of the signal OSC.

[0149] The adder 214 is connected to the output terminal Q of each flip-flop 213. The adder 214 converts the signal preCNT <0> ~preCNT <15> The result of adding +1 to the 16-bit data shown is used as the 16-bit count value CNT. <0> ~CNT <15> That is, the adder 214 adds +1 to the number of cycles of the signal OSC counted with falling edges.

[0150] 1.1.6 Specific example of allocation of count value CNT of status register

[0151] Next, refer to Fig. 9 , a specific example of the allocation of the count value CNT of the status register 106 is described. Fig. 9 This is a table showing a specific example of address information of the count value CNT<15:0> of the status register 106 .

[0152] like Fig. 9 As shown, for example, the 16-bit count value CNT<15:0> is stored in the register corresponding to the address "Bx" and "By" of the status register 106. More specifically, in the register corresponding to the address "Bx", the corresponding signal DQ <0> ~DQ <7> Store count value CNT <0> ~CNT <7> And, in the register corresponding to the address "By", corresponding to the signal DQ <0> ~DQ <7> Store count value CNT <8> ~CNT <15> In addition, the register storing the count value CNT<15:0> can be set appropriately.

[0153] For example, the memory controller 20 executes an operation (hereinafter referred to as a "GetFeature operation") to read the status information STS from the status register 106 for the target memory chip 11. The memory controller 20 sends a command group for executing the GetFeature operation to read the status information STS including the count value CNT<15:0>.

[0154] 1.2 Counting Action

[0155] Next, the counting operation of the signal OSC in the replica circuit 102 will be described.

[0156] 1.2.1 Counting action instruction sequence

[0157] First, refer to Fig.10 , an example of the instruction sequence of the counting action is explained. Fig.10 : is a diagram showing an example of the instruction sequence of the counting action. Fig.10 In the example, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0158] like Fig.10 As shown, the counting operation of the signal OSC in the replica circuit 102 is performed based on the instruction set corresponding to the counting operation sent from the memory controller 20. The instruction set is a combination of instructions, addresses, data, etc. corresponding to the operation executed by the memory chip 11.

[0159] During the period from time t100 to t110, the memory controller 20 first sends a command "CMD" to the memory chip 11, and sets the command latch enable signal CLE to the "H" level. The command "CMD" sent here is a command to instruct the execution of a counting operation. The memory chip 11 extracts the command "CMD" in conjunction with the toggle of the write enable signal bWE.

[0160] Next, the memory controller 20 sends the address "LUN" to the memory chip 11 and sets the address latch enable signal ALE to "H" level. The address "LUN" is the address information of the memory chip 11 to be executed for the counting operation. The memory chip 11 extracts the address "LUN" in conjunction with the toggle of the write enable signal bWE.

[0161] Next, the memory controller 20 sends the address "xxh" to the memory chip 11, and establishes the address latch enable signal ALE at the "H" level. The address "xxh" is information (recipe) indicating whether the counting action is to be executed on one memory chip 11 or on all memory chips 11 connected to one channel CH of the memory interface circuit 27. For example, when the address "xxh" is "00h", one memory chip 11 becomes the target. In addition, when the address "xxh" is "01h", all memory chips 11 connected to one channel CH become the target. The memory chip 11 cooperates with the bi-state trigger of the write enable signal bWE to extract the address "xxh". In addition, Fig.10 In the example, "xxh" is shown as an address, but it is not limited to this. "xxh" may also be a command. In this case, the command latch enable signal is set to the "H" level, and the address latch enable signal ALE is set to the "L" level.

[0162] When the sequencer 107 receives the address "xxh", it sends the signal OSC_ST of "H" level to the replica circuit 102 during the period of time t110 to t120. The signal OSC_ST is an internal signal that notifies the replica circuit 102 (counter 202) to perform the counting operation. After the sequencer 107 sends the signal OSC_ST of one pulse, it sets the signal OSC_ST to "L" level.

[0163] Next, the sequencer 107 sends a reset signal RST of "H" level to the replica circuit 102. When receiving the reset signal RST of "H" level, each flip-flop 213 of the counter 202 is reset. That is, the flip-flop 213 outputs a signal of "L" level from the output terminal Q, and outputs a signal of "H" level from the inverting output terminal Qn. After the sequencer 107 sends the reset signal RST of one pulse, the reset signal RST is set to "L" level.

[0164] Next, at time t120, the memory controller 20 sends address "00h" to the memory chip 11, and sets the address latch enable signal ALE to "H" level to establish. The address "00h" sent next to the address "xxh" is information indicating the start of the counting operation. The memory chip 11 extracts the address "00h" in conjunction with the toggle of the write enable signal bWE. In addition, Fig.10 In the example of , "00h" is shown as an address, but the present invention is not limited to this. "00h" may also be a command.

[0165] When the sequencer 107 receives the address "00h", it sends the "H" level start signal EN to the replica circuit 102 at time t130. When the oscillator 201 receives the "H" level start signal EN, it starts oscillating the signal OSC. In the counter 202, during the period from time t130 to t150, that is, during the period when the start signal EN is at the "H" level, the AND circuit 212 outputs the signal OSC_CLK which is the inverted signal OSC. The counter 202 accumulates in accordance with the rising edge of the signal OSC_CLK. In other words, the counter 202 accumulates in accordance with the falling edge of the signal OSC. The counter 202 outputs the value of +1 added to the accumulated result as the count value CNT<15:0>.

[0166] Next, after a preset execution time (hereinafter referred to as "counting execution time tRuntime") has passed since the memory controller 20 sends the address "00h" indicating the start of the counting action, at time t140, the memory controller 20 sends the address "00h" to the memory chip 11 again, and sets the address latch start signal ALE to the "H" level to establish it. The address "00h" here is information indicating the end of the counting action. The memory chip 11 extracts the address "00h" in conjunction with the bi-state touch-off of the write start signal bWE. In other words, the counting execution time tRuntime is the interval between the bi-state touch-off of the write start signal bWE corresponding to the address "00h" indicating the start of the counting action and the bi-state touch-off of the write start signal bWE corresponding to the address "00h" indicating the end of the counting action. In addition, Fig.10 In the example of , "00h" is shown as the address, but the present invention is not limited to this. "00h" may also be a command. In addition, the address indicating the start of the counting operation and the address indicating the end of the counting operation may be different.

[0167] When the sequencer 107 receives the address "00h", it sets the start signal EN to the "L" level at time t150. When the oscillator 201 receives the start signal EN at the "L" level, it starts oscillating the signal OSC. In the counter 202, when the start signal EN is set to the "L" level, the AND circuit 212 outputs the signal OSC_CLK at the "L" level. As a result, the counter 202 ends the counting operation.

[0168] 1.2.2 Specific example of count value

[0169] Next, refer to Fig.11 and Fig.12 , a specific example of the count value CNT is described. Fig.11 A comparative example of counting operation is shown. Fig.12 A specific example of the count value CNT of the counting operation of the counter 202 according to the present embodiment is shown.

[0170] In the following description, the count value CNT specified in advance by the specification is referred to as the "CNT specification value". The CNT specification value is set based on the number of cycles of the signal OSC that counts the execution time tRuntime. Therefore, the CNT specification value is a value accumulated based on the rising edge of the signal OSC (the starting position of one cycle). In addition, in the following description, the CNT specification value and the count value CNT are described using decimal values.

[0171] First, a comparative example is described. As a comparative example, similar to the CNT specification value, a case where the count value CNT is accumulated at the rising edge of the signal OSC is described. In this case, the counter 202 accumulates the number of cycles (count times) at the rising edge of the signal OSC and directly outputs the accumulated value as the count value CNT.

[0172] like Fig.11 As shown in the comparative example, if the oscillator 201 starts oscillating (outputting) the signal OSC, the counter 202 starts accumulating the count value CNT at the rising edge of the signal OSC. Therefore, the count value CNT represents the number of cycles of the signal OSC, similarly to the CNT specification value. In the above case, the counter 202 starts accumulating the count value CNT at the oscillation start position ( Fig.11 The counter 202 accumulates the count value CNT for each cycle of the signal OSC. The oscillator 201 ends the oscillation of the signal OSC after the count execution time tRuntime has elapsed. The oscillation end position of the signal OSC ( Fig.11 The “Stop” of the signal deviates from the waveform of the signal OSC.

[0173] For example, if the CNT specification value is set to "N" (N is an integer greater than 1), then the period in which the count value CNT is also "N" becomes the period from when the count value CNT is accumulated to "N" to the moment before it is accumulated to "N+1". For example, when the oscillation end position of the signal OSC is the moment before the count value CNT is accumulated to "N+1", the error of the end position of the signal OSC relative to the CNT specification value "N" (hereinafter also referred to as the granularity error) is at most equivalent to approximately 1 cycle of the signal OSC. In other words, the maximum 1 cycle of the signal OSC becomes the granularity error of the replica circuit 102. 1 cycle of the signal OSC is 2×(tDQS2DQ). Therefore, the maximum value of the granularity error generated during the counting execution time tRuntime can be expressed as 2×(tDQS2DQ) / tRuntime.

[0174] Next, the counting operation of this embodiment will be described.

[0175] like Fig.12 As shown, the counter 202 accumulates the number of cycles at the falling edge of the signal OSC, and outputs the result of adding +1 to the accumulated value as the count value CNT. Therefore, the timing of the accumulation of the CNT specification value is different from the timing of the accumulation of the count value CNT. The counter 202 accumulates the count value CNT to N at the falling edge of the N-1th cycle of the signal OSC. That is, the counter 202 accumulates the count value CNT to N after 0.5 cycles of the N-1th cycle. In other words, the count value CNT is accumulated 0.5 cycles in advance relative to the CNT specification value (the number of cycles of the signal OSC). Therefore, the period when the count value CNT is "N" is from the falling edge of the N-1th cycle of the signal OSC to the falling edge of the Nth cycle. Therefore, the granularity error of the end position of the signal OSC relative to the CNT specification value "N" is reduced by approximately 0.5 cycles of the signal OSC at most. The maximum value of the granularity error generated during the counting execution time tRuntime can be expressed as tDQS2DQ / tRuntime.

[0176] 1.2.3 Counting Action Process

[0177] Next, refer to Fig.13 , an example of the counting action process is described. Fig.13 This is a flowchart showing an example of the flow of the counting operation.

[0178] like Fig.13 As shown, first, the CPU 22 of the memory controller 20 issues an instruction group for instructing the execution of a counting operation (S1). The CPU 22 sends the instruction group to the memory chip 11. For example, the memory controller 20 causes the memory chip 11 to periodically execute a counting operation. In addition, for example, the memory system 1 may also have a mechanism for monitoring changes in the voltage or temperature of the memory chip 11. For example, the CPU 22 may also determine whether to execute a counting operation based on the monitoring results of the voltage or temperature of the memory chip 11.

[0179] When the sequencer 107 of the memory chip 11 receives the instruction group for the counting operation, the counting operation is started in the replica circuit 102 (S2). Fig.10 As described, during the period from time t100 to time t110, the sequencer 107 receives the command "CMD", the address "LUN", and the address "xxh" from the memory controller 20. During the period from time t110 to time t120, the sequencer 107 transmits a single-pulse signal OSC_ST and a reset signal RST.

[0180] Oscillator 201 starts to output signal OSC (S3). More specifically, when using Fig.10At time t120 described above, the sequencer 107 receives the address "00h" indicating the start from the memory controller 20. Fig.10 At time t130 described above, the sequencer 107 sets the enable signal EN to the "H" level. Based on the enable signal EN at the "H" level, the oscillator 201 starts to output the signal OSC.

[0181] Counter 202 is in use Fig.10 During the period from time t130 to time t150 described above, the number of cycles of the signal OSC is counted at the falling edge of the signal OSC (S4).

[0182] The counter 202 outputs the value obtained by adding +1 to the number of cycles ( S5 ) as the count value CNT. The count value CNT is stored in the status register 106 .

[0183] When the counting operation is completed, the CPU 22 reads the count value CNT from the memory chip 11 ( S6 ). For example, the CPU 22 issues a command group for the feature acquisition operation and reads the count value CNT from the status register 106 of the memory chip 11 .

[0184] The CPU 22 calculates the difference between the count value CNT read out and the count value CNT of the counting operation performed last time ( S7 ). For example, the count value of the counting operation performed last time is stored in the RAM 24 .

[0185] The CPU 22 checks whether the absolute value of the difference is greater than a preset threshold value ( S8 ).

[0186] When the absolute value of the difference is greater than the preset threshold value (S8_Yes), the CPU 22 performs write training (S9). That is, the sequencer 107 of the memory chip 11 performs write training based on the command of the CPU 22.

[0187] On the other hand, when the absolute value of the difference is less than or equal to the preset threshold value (S8_No), the CPU 22 ends the counting operation.

[0188] 1.3 Effects of this Implementation

[0189] According to the configuration of this embodiment, the processing capability of the semiconductor device can be improved. This effect will be described in detail.

[0190] For example, when the signal DQ is extracted asynchronously from the signal DQS and the signal bDQS to the memory chip 11, the time tDQS2DQ becomes longer than when the signal DQ is extracted synchronously from the signal DQS and the signal bDQS to the memory chip 11. The optimal value of the time tDQS2DQ changes according to changes in the voltage or temperature in the memory chip 11. Therefore, the memory controller 20, for example, regularly performs write training to adjust the timing of sending the signal DQ and the signals DQS and bDQS. However, the execution time of the write training is relatively long. In addition, during the execution of the write training, write actions and read actions, etc. cannot be performed. Therefore, when the frequency of the write training becomes higher, the processing capacity of the memory chip 11 decreases.

[0191] In contrast, in the configuration of this embodiment, the memory chip 11 (semiconductor device) includes a replica circuit 102 including an oscillator 201 that outputs a signal OSC and a counter 202 that counts the number of cycles of the signal OSC. The memory chip 11 can perform the counting operation of the replica circuit 102 based on the control of the memory controller 20. The memory controller 20 can determine whether to perform write training based on the result of the counting operation. Therefore, the implementation timing of the write training can be optimized, and the processing capability of the memory chip 11 can be improved.

[0192] Furthermore, according to the configuration of this embodiment, the timer 202 can count 0.5 cycles earlier than the number of cycles of the signal OSC. Therefore, compared with the case of accumulating in accordance with the number of cycles of the signal OSC, the granularity error of the count value CNT with respect to the count execution time tRuntime can be set to 1 / 2. Therefore, according to the configuration of this embodiment, the same degree of counting accuracy as when accumulating in accordance with the number of cycles of the signal OSC can be achieved with 1 / 2 of the count execution time tRuntime. Therefore, the processing capability of the memory chip 11 can be improved.

[0193] Furthermore, according to the configuration of this embodiment, since the particle size error can be set to 1 / 2, the accuracy of the counting operation can be improved.

[0194] 1.4 Variations of the First Embodiment

[0195] Next, a modification of the first embodiment will be described. In the modification, a case where the method of sending commands and addresses is different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0196] 1.4.1 Composition of memory chips

[0197] First, refer to Fig.14 , an example of the structure of the memory chip 11 is described. Fig.141 is a block diagram showing an example of the structure of the memory chip 11 (semiconductor device). Fig.14 In the example of FIG. 1 , a part of the connection between the components is indicated by an arrow line, but the connection between the components is not limited to this.

[0198] The memory chip 11 of this example has two modes when inputting and outputting data and information with the memory controller 20 .

[0199] The first mode is a mode in which the signal DQ is used for input and output of data DAT, but not for input of command CMD and address ADD and output of status information STS. The protocol of the first mode is also referred to as "SCA (Separate CommandAddress input) protocol". In the first mode, the input of command CMD and address ADD and output of status information STS are executed in the logic control circuit 103. In addition, in the first mode, a ready / busy signal bRB can also be output from the logic control circuit 103. In the above case, the ready / busy circuit 108 is connected to the logic control circuit 103.

[0200] The second mode is a mode in which the signal DQ described in the first embodiment is used for inputting and outputting data DAT, inputting commands CMD and addresses ADD, and outputting status information STS. The second mode is the same as the first embodiment, so the description thereof is omitted.

[0201] like Fig.14 As shown, the memory chip (NAND flash memory) 11 of this example is similar to that of the first embodiment. Figure 2 Similarly, the first embodiment includes an input / output circuit 101, a replica circuit 102, a logic control circuit 103, an address register 104, a command register 105, a status register 106, a sequencer 107, a ready / busy circuit 108, a voltage generating circuit 109, a memory cell array 120, a row decoder 121, a sense amplifier 122, a data register 123, and a column decoder 124. The configuration of the replica circuit 102, the address register 104, the command register 105, the status register 106, the sequencer 107, the ready / busy circuit 108, the voltage generating circuit 109, the memory cell array 120, the row decoder 121, the sense amplifier 122, the data register 123, and the column decoder 124 is the same as that of the first embodiment.

[0202] When the first mode is selected, the input / output circuit 101 receives the command CMD and the address ADD from the logic control circuit 103. In addition, the input / output circuit 101 transmits state information STS to the logic control circuit 103.

[0203] The logic control circuit 103 receives the signal CA_bCE, the signal CA_CLK, the read enable signals RE and bRE, and the signal SCA from the memory controller 20. In addition, the logic control circuit 103 transmits and receives the signal CA1 and the signal CA0 to and from the memory controller 20.

[0204] The signal CA_bCE corresponds to the chip enable signal bCE described in Embodiment 1. The signal CA_bCE is asserted at, for example, a low ("L") level.

[0205] Signals CA0 and CA1 are signals indicating commands, addresses, or status information STS in the first mode. In the second mode, command latch enable signal CLE is input to the input terminal of signal CA1. Also, address latch enable signal ALE is input to the input terminal of signal CA0.

[0206] The signal CA_CLK is a selection signal for the signal CA0 and the signal CA1 in the first mode. For example, when the command CMD or the address ADD is input, the logic control circuit 103 extracts the signal CA0 and the signal CA1 at the rising edge and the falling edge of the signal CA_CLK. In addition, when the logic control circuit 103 outputs the state information STS, the signal CA0 and the signal CA1 are output based on the signal CA_CLK. In the second mode, the write enable signal bWE is input to the terminal corresponding to the signal CA_CLK.

[0207] The read enable signals RE and bRE are used to output the signal DQ in the first mode, but may also be used to output the status information STS.

[0208] The signal SCA is a control signal for mode switching. For example, when the signal SCA is at an "H" level, the first mode is selected, and when the signal SCA is at an "L" level, the second mode is selected.

[0209] 1.4.2 Command sequence for command and address input in mode 1

[0210] Next, refer to Fig.15 , an example of the instruction sequence of command and address input in the first mode is described. Fig.15 1 is a diagram showing an example of the instruction sequence of the instruction and address input in the first mode. Fig.15 In the example, the signal DQ, the signals DQS and bDQS, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0211] like Fig.15As shown, in the first mode, the combination of the 6-bit signal CA0 and the 6-bit signal CA1 indicates the type of information and the 8-bit information. Hereinafter, the combination of the signal CA0 and the signal CA1 is referred to as a "frame". The type of information indicates, for example, any one of the command CMD, the address ADD, or the status information STS.

[0212] A frame is composed of a combination of a header group indicating the type of information and a body group indicating the content of the information.

[0213] The header group is a group of 4 bits (each bit is referred to as a "header") consisting of the first 2 bits of signal CA0 and the first 2 bits of signal CA1. In each of signal CA0 and signal CA1, the first bit in the header group is referred to as the first header. The second bit in the header group is referred to as the second header.

[0214] The body group is a group of 8 bits (each bit is referred to as a "body") consisting of the last 4 bits of signal CA0 and the last 4 bits of signal CA1. In each of signal CA0 and signal CA1, the first bit in the body group is referred to as the first body. The second bit in the body group is referred to as the second body. The third bit in the body group is referred to as the third body. The fourth bit in the body group is referred to as the fourth body. For example, the first body of signal CA0 corresponds to signal DQ in the second mode. <0> The first body of signal CA1 corresponds to signal DQ in the second mode <1> The second body of signal CA0 corresponds to signal DQ in the second mode. <2> The second body of signal CA1 corresponds to signal DQ in the second mode <3> The third body of signal CA0 corresponds to signal DQ in the second mode. <4> The third body of signal CA1 corresponds to signal DQ in the second mode <5> The fourth body of signal CA0 corresponds to signal DQ in the second mode. <6> The fourth body of signal CA1 corresponds to signal DQ in the second mode <7> .

[0215] When selecting the first mode, the memory controller 20 sets the signal CA_bCE to “L” level and sets the signal SCA to “H” level. Thus, the first mode is selected in the target memory chip 11 .

[0216] First, the memory controller 20 transmits the first header of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 extracts the first header in accordance with the rising edge of the signal CA_CLK at time t0.

[0217] Next, the memory controller 20 transmits the second header of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 extracts the second header in accordance with the falling edge of the signal CA_CLK at time t1.

[0218] Next, the memory controller 20 transmits the first body of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 extracts the first body in response to the rising edge of the signal CA_CLK at time t2.

[0219] Next, the memory controller 20 transmits the second body of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 extracts the second body in accordance with the falling edge of the signal CA_CLK at time t3.

[0220] Next, the memory controller 20 transmits the third body of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 extracts the third body in accordance with the rising edge of the signal CA_CLK at time t4.

[0221] Next, the memory controller 20 transmits the fourth body of the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 extracts the fourth body in accordance with the falling edge of the signal CA_CLK at time t5.

[0222] For example, when frame transmission is completed, the memory controller 20 sets the signal CA_bCE to the “H” level and sets the signal SCA to the “L” level.

[0223] As described above, when the first mode is selected, the signal DQ, the signal DQS and the signal bDQS, and the signal RE and the signal bRE are not used for the input of the command CMD and the address ADD. Therefore, the input of the command CMD and the address ADD can be performed in parallel with the input and output of the data DAT using the signal DQ and the signal DQS and the signal bDQS. The memory controller 20 can instruct the memory chip 11 to perform the counting operation without using the signal DQ and the signal DQS and the signal bDQS.

[0224] 1.4.3 Command sequence of feature acquisition action in mode 1

[0225] Next, refer to Fig.16 , the instruction sequence of the feature acquisition action in the first mode is explained. Fig.16 1 is a diagram showing an example of the instruction sequence of the feature acquisition operation in the first mode. Fig.16 In the example, the signal DQ, the signals DQS and bDQS, the signal CA_bCE, the signal SAC, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0226] like Fig.16 As shown, first, at time t10 to t15, an input operation of a frame corresponding to the command CMD instructing execution of a feature acquisition operation is performed. The interval between each time at time t10 to t21 is denoted as "tCLK1".

[0227] More specifically, first, at time t10, for example, a signal CA0 indicating "0" and a signal CA1 indicating "0" are input as a first header.

[0228] Next, at time t11, for example, a signal CA0 indicating "1" and a signal CA1 indicating "1" are input as a second header. For example, a header group of "0", "0", "1", "1" indicates that the body group to be input next is a command CMD.

[0229] Next, during the period from time t12 to t15, the main body group of the command CMD is input. More specifically, at time t12, the signal CA0 and the signal CA1 representing the first main body are input. Next, at time t13, the signal CA0 and the signal CA1 representing the second main body are input. Next, at time t14, the signal CA0 and the signal CA1 representing the third main body are input. Next, at time t15, the signal CA0 and the signal CA1 representing the fourth main body are input.

[0230] Next, at time t16 to t21, an input operation of a frame corresponding to the address ADD of the status register 106 is performed.

[0231] More specifically, first, at time t16, for example, a signal CA0 indicating "0" and a signal CA1 indicating "0" are input as the first header.

[0232] Next, at time t17, for example, a signal CA0 indicating "1" and a signal CA1 indicating "1" are input as a second header. For example, a header group of "0", "0", "0", "1" indicates that the next body group to be input is the address ADD.

[0233] Next, during the period from time t18 to t21, the body group of the address ADD is input. More specifically, at time t18, the signal CA0 and the signal CA1 representing the first body are input. Next, at time t19, the signal CA0 and the signal CA1 representing the second body are input. Next, at time t20, the signal CA0 and the signal CA1 representing the third body are input. Next, at time t21, the signal CA0 and the signal CA1 representing the fourth body are input.

[0234] When the input of the address ADD is completed at time t21, the sequencer 107 sets the ready / busy signal bRB to the "L" level and starts the read operation of the state information STS (for example, the count value CNT) from the target address of the state register 106 to the logic control circuit 103. During the period tFEAT when the ready / busy signal bRB is at the "L" level, the read operation is performed and the read state information STS is stored in the register (not shown) of the logic control circuit 103. When the read operation is completed, the sequencer 107 sets the ready / busy signal bRB to the "H" level.

[0235] When receiving the ready / busy signal bRB at the “H” level, the memory controller 20 transmits a header group indicating output (DOUT) state information STS to the memory chip 11 .

[0236] More specifically, first, at time t22, for example, a signal CA0 indicating "0" and a signal CA1 indicating "0" are input as the first header.

[0237] Next, at time t23, for example, a signal CA0 indicating "0" and a signal CA1 indicating "0" are input as a second header. For example, a header group of "0", "0", "0", "0" is a header group that instructs the logic control circuit 103 to output the state information STS.

[0238] After a predetermined waiting time (period tW2R) has passed since the header group was input, the memory controller 20 sends a signal CA_CLK to the memory chip 11 to specify the timing of outputting the status information STS. More specifically, at time t24, the memory controller 20 sends a signal CA_CLK of an "H" level to the memory chip 11. In addition, at time t25, the memory controller 20 sends a signal CA_CLK of an "L" level to the memory chip 11. After time t25, the memory controller 20 repeats the toggle switch (switching between the "L" level and the "H" level) of the signal CA_CLK. For example, the toggle switch interval (the interval between the rise and fall of the signal CA_CLK) of the signal CA_CLK in the output operation of the status information STS is set to the period tCLK2. The period tCLK2 may also be shorter than the period tCLK1.

[0239] Based on the signal CA_CLK, the output action of the state information STS is performed. The logic control circuit 103 outputs the signal CA1 as the state information STS. In addition, the logic control circuit 103 outputs the signal CA0 as the selection signal of the signal CA1. The logic control circuit 103 generates the signal CA0 based on the signal CA_CLK. Therefore, the interval of the toggle of the signal CA0 is the same as that of the signal CA_CLK, which is the period tCLK2.

[0240] The state information STS is output as the signal CA1 in accordance with the timing of the rising and falling edges of the signal CA0. Therefore, the 8-bit main body of the signal CA1 corresponds to the 8-bit data output of the state information STS. In addition, the signal CA1 is output in accordance with the rising or falling edge of the signal CA0. Therefore, whether the signal CA1 continuously outputs "0" or continuously outputs "1", the division of data can be determined.

[0241] When the output of the status information STS is activated, for example Fig.16 As shown, after inputting a header group indicating output data once, a plurality of body groups constituting the status information STS may be output continuously. In other words, input of the header group may be omitted until the output of the status information STS is completed.

[0242] 1.4.4 Counting action instruction sequence

[0243] Next, refer to Fig.17 , an example of the instruction sequence of the counting action is explained. Fig.17 1 is a diagram showing an example of the instruction sequence of the counting operation in the first mode. Fig.17 In the example, the signal DQ, the signals DQS and bDQS, the signal CA_bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0244] like Fig.17 As shown, in this example, corresponding to the first mode, the memory controller 20 sends the signal CA0, the signal CA1, and the signal CA_CLK to the memory chip 11. In addition, the internal signals (signal OSC_ST, reset signal RST, enable signal EN, signal OSC, signal OSC_CLK, and count value CNT<15:0>) generated in the memory chip 11 are the same as those in the first embodiment. Fig.10 same.

[0245] More specifically, during time t100 to t110, the memory controller 20 first sends a frame corresponding to the command "CMD" as signals CA0 and CA1 to the memory chip 11. The memory chip 11 extracts signals CA0 and CA1 in accordance with the rising and falling edges of the signal CA_CLK.

[0246] Next, the memory controller 20 sends a frame corresponding to the address "LUN" as the signal CA0 and the signal CA1 to the memory chip 11. The memory chip 11 extracts the signal CA0 and the signal CA1 in accordance with the rising edge and the falling edge of the signal CA_CLK.

[0247] Next, the memory controller 20 sends a frame corresponding to the address "xxh" to the memory chip 11 as the signal CA0 and the signal CA1. The memory chip 11 extracts the signal CA0 and the signal CA1 in accordance with the rising and falling edges of the signal CA_CLK. In addition, "xxh" may also be a command.

[0248] When receiving the address "xxh", the sequencer 107 transmits the signal OSC_ST of "H" level to the replica circuit 102 during the period of time t110 to t120. After transmitting the signal OSC_ST of one pulse, the sequencer 107 sets the signal OSC_ST to "L" level.

[0249] Next, the sequencer 107 sends an "H" level reset signal RST to the replica circuit 102. Upon receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending a single pulse of the reset signal RST, the sequencer 107 sets the reset signal RST to an "L" level.

[0250] Next, at time t120, the memory controller 20 sends a frame corresponding to address "00h" as signals CA0 and CA1 to the memory chip 11. The memory chip 11 extracts signals CA0 and CA1 in accordance with the rising and falling edges of the signal CA_CLK. In addition, "00h" may also be a command.

[0251] When the sequencer 107 receives the address "00h", it sends the enable signal EN of "H" level to the replica circuit 102 at time t130. When the oscillator 201 receives the enable signal EN of "H" level, it starts oscillating (outputting) the signal OSC. In the counter 202, during the period from time t130 to t150, that is, during the period when the enable signal EN is at "H" level, the AND circuit 212 outputs the signal OSC_CLK which inverts the signal OSC. The counter 202 accumulates in accordance with the rising edge of the signal OSC_CLK. In other words, the counter 202 accumulates in accordance with the falling edge of the signal OSC. The counter 202 outputs the value of +1 added to the accumulated result as the count value CNT<15:0>.

[0252] Next, after the count execution time tRuntime has elapsed since the address "00h" indicating the start of the count operation was sent, the memory controller 20 sends a frame corresponding to the address "00h" to the memory chip 11 at time t140 as the signal CA0 and the signal CA1. The memory chip 11 extracts the signal CA0 and the signal CA1 in accordance with the rising and falling edges of the signal CA_CLK. In addition, "00h" may also be an instruction. In addition, the address indicating the start of the count operation may be different from the address indicating the end of the count operation.

[0253] When the sequencer 107 receives the address "00h", it sets the start signal EN to the "L" level at time t150. When the oscillator 201 receives the start signal EN at the "L" level, it starts the oscillation of the signal OSC. In the counter 202, when the start signal EN is set to the "L" level, the AND circuit 212 outputs the signal OSC_CLK at the "L" level. That is, the counter 202 ends the counting operation.

[0254] 1.4.5 Effects of Variations of the First Implementation Example

[0255] According to the configuration of this variation, the same effects as those of the first embodiment can be obtained.

[0256] Furthermore, if the configuration of this variation is adopted, the SCA protocol can be applied when inputting instructions and addresses to the memory chip 11. In the SCA protocol, the signal DQ, the signal DQS and the bDQS, and the read enable signals RE and bRE are not used for inputting instructions and addresses. Therefore, the input and output of data can be performed in parallel with the input of instructions and addresses. In other words, the counting operation and the input and output operation of data can be performed in parallel. Therefore, in the memory chip 11, the reduction in the processing capacity of the counting operation can be suppressed.

[0257] 2. Second Implementation Method

[0258] Next, the second embodiment will be described. In the second embodiment, the counter 202 which is different from the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0259] 2.1 Counter Structure

[0260] First, refer to Fig.18 , an example of the structure of the counter 202 is described. Fig.18 2 is a circuit diagram showing an example of the configuration of the counter 202 .

[0261] like Fig.18 As shown, the counter 202 of this embodiment accumulates the number of cycles based on the rising edge of the signal OSC_ST and the falling edge of the signal OSC, and outputs the accumulated result as the count value CNT<15:0>.

[0262] The counter 202 includes an inverter 211, an AND circuit 212, a plurality of flip-flops 213, a delay circuit 221, and an OR circuit 222. For example, the counter 202 includes, as in the first embodiment, a plurality of counters corresponding to the count values ​​CNT <0> ~CNT <15> Flip-flops 213_0 to 213_15.

[0263] The configuration of the inverter 211 and the AND circuit 212 and the use of the first embodiment Figure 8 The configuration of the counter 202 described above is the same. The output terminal of the AND circuit 212 is connected to the first input terminal of the OR circuit 222 .

[0264] The delay circuit 221 is a circuit for delaying the signal OSC_ST. The signal OSC_ST is input to the input terminal of the delay circuit 221. The output terminal of the delay circuit 221 is connected to the second input terminal of the OR circuit 222. The delay circuit 221 outputs a signal OSC_ST_DL which is a delayed signal OSC_ST.

[0265] The output terminal of the OR circuit 222 is connected to the clock signal input terminal of the flip-flop 213_0. The OR circuit 222 performs a logical sum (OR) operation on the signal OSC_CLK and the signal OSC_ST_DL, and outputs the result of the operation as the signal CNT_CLK. The signal CNT_CLK is set to the "H" level when at least one of the signal OSC_CLK and the signal OSC_ST_DL is at the "H" level.

[0266] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0267] The structure of the flip-flop 213 is similar to that of the first embodiment. Figure 8 The clock signal input terminal of the flip-flop 213_0 inputs the signal CNT_CLK.

[0268] In this embodiment, the signal output from the output terminal Q of the flip-flops 213_0 to 213_15 is output as the 16-bit count value CNT <0> ~CNT <15> .

[0269] As described above, the counter 202 of the present embodiment also outputs the accumulated count value CNT at the same timing as that of the first embodiment.

[0270] 2.2 Counting action instruction sequence

[0271] Next, refer to Fig.19 , an example of the instruction sequence of the counting action is explained. Fig.19 : is a diagram showing an example of the instruction sequence of the counting action. Fig.19 In the example, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0272] like Fig.19As shown, during the period from time t100 to time t110, the memory controller 20 and the memory controller 20 using the first embodiment Fig.10 Similarly to the description above, the command “CMD”, the address “LUN” and the address “xxh” are sent to the memory chip 11 in sequence.

[0273] When receiving the address "xxh", the sequencer 107 transmits the signal OSC_ST of "H" level to the replica circuit 102 during the period of time t110 to t120. After transmitting the signal OSC_ST of one pulse, the sequencer 107 sets the signal OSC_ST to "L" level.

[0274] Next, the sequencer 107 sends an "H" level reset signal RST to the replica circuit 102. When receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending a single pulse of the reset signal RST, the sequencer 107 sets the reset signal RST to an "L" level.

[0275] At time t111, the counter 202 receives the reset signal RST of the "H" level, resets the flip-flop 213, and causes the signal OSC_ST_DL, which is a delayed signal of the signal OSC_ST, to rise to the "H" level. As a result, the signal CNT_CLK rises to the "H" level. The counter 202 accumulates at the rising edge of the signal CNT_CLK. Therefore, before the oscillator 201 starts to oscillate the signal OSC, the counter 202 accumulates the count value CNT by +1 in response to the 1 pulse of the signal OSC_ST. That is, the count value CNT is set to "1".

[0276] Next, at time t120, the memory controller 20 and the memory controller 21 use the first embodiment. Fig.10 Similarly to the description above, the address "00h" is sent to the memory chip 11 to instruct the start of the counting operation.

[0277] When the sequencer 107 receives the address "00h", it sends the start signal EN of "H" level to the replica circuit 102 at time t130. When the oscillator 201 receives the start signal EN of "H", it starts the oscillation of the signal OSC. In the counter 202, during the period from time t130 to t150, that is, during the period when the start signal EN is at "H", the AND circuit 212 outputs the signal OSC_CLK which inverts the signal OSC. In addition, the OR circuit 222 outputs the signal CNT_CLK which is synchronized with the signal OSC_CLK. The counter 202 accumulates in accordance with the rising edge of the signal CNT_CLK. In other words, the counter 202 accumulates in accordance with the falling edge of the signal OSC. At this time, the counter 202 accumulates from the state where the count value CNT is "1".

[0278] Next, the memory controller 20 and the memory controller 21 using the first embodiment Fig.10 Similarly, after the count execution time tRuntime has elapsed since the address “00h” for instructing the start of the count operation was sent, the address “00h” is sent again to the memory chip 11 at time t140.

[0279] When receiving address "00h", sequencer 107 sets enable signal EN to "L" level at time t150. Oscillator 201 starts oscillating signal OSC when receiving enable signal EN at "L" level. Counter 202 ends counting operation.

[0280] 2.3 Counting action flow

[0281] Next, refer to Fig. 20 , an example of the counting action process is described. Fig. 20 This is a flowchart showing an example of the flow of the counting operation.

[0282] like Fig. 20 As shown, first, steps S1 and S2 are executed. The operations of steps S1 and S2 are the same as those of the first embodiment. Fig.13 Same description as .

[0283] The counter 202 counts the count value CNT to 1 in response to the 1-pulse signal of the signal OSC_ST (S21). Fig.19 At time t111 described above, the signal OSC_ST_DL, which is a delayed signal of the signal OSC_ST, rises to the "H" level. As a result, the signal CNT_CLK rises to the "H" level. The counter 202 accumulates the count value to 1 at the rising edge of the signal CNT_CLK.

[0284] Next, steps S3 and S4 are executed. The operations of steps S3 and S4 are the same as those of the first embodiment. Fig.13 Same description as .

[0285] Next, steps S6 to S9 are executed. The operations of steps S6 to S9 are the same as those of the first embodiment. Fig.13 Same description as .

[0286] 2.4 Effects of this Implementation

[0287] According to the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0288] In addition, a modification example of the first embodiment is applied to this embodiment.

[0289] 3. Third Implementation Method

[0290] Next, the third embodiment will be described. In the third embodiment, the counter 202 which is different from the first and second embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0291] 3.1 Counter Structure

[0292] First, refer to Fig.21 , an example of the structure of the counter 202 is described. Fig.21 2 is a circuit diagram showing an example of the configuration of the counter 202 .

[0293] like Fig.21 As shown, the counter 202 of this embodiment accumulates the number of cycles based on the rising edge of the signal OSC. Furthermore, the counter 202 adds 0 or 1 to the number of cycles based on the result of performing an exclusive logical AND (exOR) operation on the 1-bit data corresponding to the rising edge of the signal OSC and the 1-bit data corresponding to the falling edge of the signal OSC, and outputs the result as the count value CNT<15:0>.

[0294] The counter 202 includes a plurality of flip-flops 213, an AND circuit 231, an inverter 232, an AND circuit 233, a flip-flop 234, an exOR circuit 235, and a logic circuit 236. For example, the counter 202 includes, as in the first embodiment, a plurality of flip-flops 213, an AND circuit 231, an inverter 232, an AND circuit 233, a flip-flop 234, an exOR circuit 235, and a logic circuit 236. <0> ~CNT <15> Flip-flops 213_0 to 213_15.

[0295] The signal OSC is input to the first input terminal of the AND circuit 231. The first input terminal of the AND circuit 231 is connected to the oscillator 201. The enable signal EN is input to the second input terminal of the AND circuit 231. The output terminal of the AND circuit 231 is connected to the clock signal input terminal of the flip-flop 213_0. The AND circuit 231 performs a logical product (AND) operation on the signal OSC and the enable signal EN, and outputs the result as the signal OSC_CLK_rise. The signal OSC_CLK_rise is a clock signal synchronized with the signal OSC when the enable signal EN is at the "H" level.

[0296] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0297] The structure of the flip-flop 213 is similar to that of the first embodiment. Figure 8The same. The signal OSC_CLK_rise is input to the clock signal input terminal of the flip-flop 213_0. The flip-flop 213_0 extracts data at the rising edge of the signal OSC_CLK_rise, that is, the signal OSC. Therefore, the flip-flops 213_0 to 213_15 accumulate at the rising edge of the signal OSC.

[0298] For example, the signal output from the output terminal Q of the flip-flop 213 is referred to as the signal CNT_rise. The signal CNT_rise is output from the output terminals Q of the flip-flops 213_0 to 213_15, respectively. <0> ~CNT_rise <15> .

[0299] The inverter 232 inverts the signal OSC and outputs it. The input terminal of the inverter 232 is connected to the oscillator 201 . The signal OSC is input to the input terminal of the inverter 232 . The output terminal of the inverter 232 is connected to the first input terminal of the AND circuit 233 .

[0300] The start signal EN is input to the second input terminal of the AND circuit 233. The output terminal of the AND circuit 233 is connected to the clock signal input terminal of the flip-flop 234. The AND circuit 233 performs a logical product (AND) operation on the inversion signal of the signal OSC and the start signal EN, and outputs the result as the signal OSC_CLK_fall. The signal OSC_CLK_fall is a clock signal that inverts the signal OSC when the start signal EN is at the "H" level. For example, when the start signal EN is at the "H" level and the inversion signal of the signal OSC is at the "H" level (that is, the signal OSC is at the "L" level), the signal OSC_CLK_fall is set to the "H" level.

[0301] The flip-flop 234 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0302] The structure of the flip-flop 234 is the same as that of the flip-flop 213. The signal OSC_CLK_fall is input to the clock signal input terminal of the flip-flop 234. The flip-flop 234 extracts data at the rising edge of the signal OSC_CLK_fall, that is, the falling edge of the signal OSC. The data input terminal D of the flip-flop 234 is connected to the inverting output terminal Qn of the flip-flop 234. Therefore, the flip-flop 234 inverts the signal output from the output terminal Q and the inverting output terminal Qn at the rising edge of the signal OSC_CLK_fall input to the clock signal input terminal. The reset signal RST is input to the reset signal input terminal R of the flip-flop 234.

[0303] For example, the signal output from the output terminal Q of the flip-flop 234 is recorded as a signal CNT_fall <0> .

[0304] The first input terminal of the exOR circuit 235 is connected to the output terminal Q of the flip-flop 213_0. The signal CNT_rise is input to the first input terminal of the exOR circuit 235. <0> The second input terminal of the exOR circuit 235 is connected to the output terminal Q of the flip-flop 234. The signal CNT_fall is input to the second input terminal of the exOR circuit 235. <0> The exOR circuit 235 converts the signal CNT_rise <0> With signal CNT_fall <0> Performs an exclusive logical AND (exOR) operation and outputs the result. For example, the signal CNT_rise <0> and signal CNT_fall <0> When both are at the "H" level ("1") or the "L" level ("0"), the output signal of the exOR circuit 235 is set to the "L" level (exOR=0). <0> and signal CNT_fall <0> When any one of them is at the “H” level (“1”), the output signal of the exOR circuit 235 is set to the “H” level (exOR=1).

[0305] The logic circuit 236 is connected to the output terminal Q of each flip-flop 213 and the output terminal of the exOR circuit 235. The logic circuit 236 is input with a signal CNT_rise. <0> ~CNT_rise <15> The logic circuit 236 outputs a signal CNT_rise based on the output signal of the exOR circuit 235. <0> ~CNT_rise <15> The result of adding 0 or +1 to the 16-bit data shown is used as the 16-bit count value CNT <0> ~CNT <15> More specifically, when exOR=0, the logic circuit 236 outputs the signal CNT_rise <0> ~CNT_rise <15> The result of adding +1 to the 16-bit data shown is used as the count value CNT <0> ~CNT <15> On the other hand, when exOR=1, the logic circuit 236 outputs the signal CNT_rise <0> ~CNT_rise <15> The 16-bit data shown is used as the count value CNT <0> ~CNT <15> .

[0306] 3.2 Specific example of count value

[0307] Next, refer to Fig. 22 , a specific example of the count value CNT is described. Fig. 22 2 is a diagram showing a specific example of each signal in the counter 202. Fig. 22 In the example, in order to simplify the description, the CNT specification value, the signal CNT_rise<15:0> and the count value CNT are expressed in decimal.

[0308] like Fig. 22 As shown, at time t200, when the oscillator 201 starts oscillating the signal OSC, the CNT specification value accumulates to "1" at the rising edge of the signal OSC. <0> At the rising edge of the signal OSC, it is inverted to the "H" level and outputs "1". <0> Since the exOR circuit 235 outputs "1" ("H" level), the logic circuit 236 does not add the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "1", the counter 202 outputs "1" as the count value CNT.

[0309] Next, at time t201, the signal CNT_fall <0> At the falling edge of the signal OSC, it is inverted to the "H" level and outputs "1". <0> and signal CNT_fall <0> Both are "1", so the exOR circuit 235 outputs "0". Therefore, the logic circuit 236 adds +1 to the signal CNT_rise<15:0>. As a result, the counter 202 outputs "2" as the count value CNT.

[0310] Next, at time t202, the CNT level value is accumulated to "2". Signal CNT_rise <0> At the rising edge of the signal OSC, it is inverted to the "L" level and outputs "0". <0> is "1", so the exOR circuit 235 outputs "1". Therefore, the logic circuit 236 does not add the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "2", the counter 202 then outputs "2" as the count value CNT.

[0311] Next, at time t203, the signal CNT_fall <0> Inverted to "L" level and output "0". <0> and signal CNT_fall <0> Both are "0", so the exOR circuit 235 outputs "0". Therefore, the logic circuit 236 adds +1 to the signal CNT_rise<15:0>. As a result, the counter 202 outputs "3" as the count value CNT.

[0312] Next, at time t204, the CNT level value is accumulated to "3". Signal CNT_rise <0> At the rising edge of the signal OSC, it is inverted to the "L" level and outputs "0". <0> = is "1", so the exOR circuit 235 outputs "1". Therefore, the logic circuit 236 does not add the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "3", the counter 202 then outputs "3" as the count value CNT.

[0313] Next, at time t205, the signal CNT_fall <0> Inverted to "H" level and output "1". <0> and signal CNT_fall <0> Both are "1", so the exOR circuit 235 outputs "0". Therefore, the logic circuit 236 adds +1 to the signal CNT_rise<15:0>. As a result, the counter 202 outputs "4" as the count value CNT.

[0314] Next, at time t206, the CNT level value is accumulated to "4". Signal CNT_rise <0> At the rising edge of the signal OSC, it is inverted to the "H" level and outputs "1". <0> = is "0", so the exOR circuit 235 outputs "1". Therefore, the logic circuit 236 does not add the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "4", the counter 202 then outputs "4" as the count value CNT.

[0315] As described above, the counter 202 of the present embodiment also outputs the accumulated count value CNT at the same timing as that of the first embodiment.

[0316] 3.3 Counting Action Process

[0317] Next, refer to Fig.23 , an example of the counting action process is described. Fig.23 This is a flowchart showing an example of the flow of the counting operation.

[0318] like Fig.23 As shown, first, steps S1 to S3 are executed. The operations of steps S1 to S3 are the same as those of the first embodiment. Fig.13 Same description as .

[0319] Counter 202 is used Fig. 22 As described above, at the rising edge of the signal OSC (OSC_CLK_rise), the number of cycles of the signal OSC (OSC_CLK_rise) is counted (S31).

[0320] The exOR circuit 235 performs the signal CNT_rise <0> With signal CNT_fall <0> When the result of the operation is 0 (exOR=0) (S32_Yes), the logic circuit 236 outputs a value obtained by adding +1 to the number of cycles (S33) as the count value CNT.

[0321] On the other hand, when the calculation result is 1 (exOR=1) ( S32_No), the logic circuit 236 outputs the number of cycles as the count value CNT.

[0322] Next, steps S6 to S9 are executed. The operations of steps S6 to S9 are the same as those of the first embodiment. Fig.13 Same description as .

[0323] 3.4 Effects of this Implementation

[0324] According to the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0325] In addition, a modification example of the first embodiment is applied to this embodiment.

[0326] 4. Fourth Implementation Method

[0327] Next, a fourth embodiment will be described. In the fourth embodiment, a counter 202 different from the first to third embodiments will be described. Hereinafter, the differences from the first to third embodiments will be mainly described.

[0328] 4.1 Counter Structure

[0329] Next, refer to Fig.24 , an example of the structure of the counter 202 is described. Fig.24 2 is a circuit diagram showing an example of the configuration of the counter 202 .

[0330] like Fig.24 As shown, the counter 202 of this embodiment accumulates the number of cycles based on the rising edge of the signal OSC (signal OSC_CLK2). Furthermore, when the counter 202 ends the counting execution time tRuntime while the signal OSC is at the "L" level, the signal OSC_CLK2 is set to the "H" level, and the number of cycles is increased by +1. The counter 202 outputs the number of cycles as the count value CNT<15:0>.

[0331] The counter 202 includes a plurality of flip-flops 213 and an OR circuit 241. For example, the counter 202 includes a plurality of flip-flops 213 and an OR circuit 241, respectively corresponding to the count value CNT <0> ~CNT <15> Flip-flops 213_0 to 213_15.

[0332] The signal OSC is input to the first input terminal of the OR circuit 241. The first input terminal of the AND circuit 231 is connected to the oscillator 201. The start signal bEN is input to the second input terminal of the OR circuit 241. The start signal bEN is set to the "H" level when the counting action is not performed. The counting action is performed during the period when the start signal bEN is at the "L" level. That is, the oscillator 201 oscillates the signal OSC during the period when the start signal bEN is at the "L" level. The output terminal of the OR circuit 241 is connected to the clock signal input terminal of the flip-flop 213_0. The OR circuit 241 performs a logical sum (OR) operation on the signal OSC and the start signal bEN, and outputs the result as the signal OSC_CLK2. Therefore, the signal OSC_CLK2 is set to the "H" level when the start signal bEN is at the "H" level. In addition, the signal OSC_CLK2 is a clock signal synchronized with the signal OSC when the start signal bEN is at the "L" level.

[0333] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0334] The structure of the flip-flop 213 is similar to that of the first embodiment. Figure 8 The signal OSC_CLK2 is input to the clock signal input terminal of the flip-flop 213_0. The flip-flop 213_0 extracts data at the rising edge of the signal OSC_CLK2, that is, the signal OSC.

[0335] In this embodiment, the signal output from the output terminal Q of the flip-flops 213_0 to 213_15 is output as the 16-bit count value CNT <0> ~CNT <15> .

[0336] 4.2 Specific example of count value

[0337] Next, refer to Fig.25 , a specific example of the count value CNT is described. Fig.25 2 is a diagram showing a specific example of the signal OSC and the signal OSC_CLK2 and the count value CNT in the counter 202. Fig.25 In the example, in order to simplify the description, the CNT standard value and the count value CNT are expressed in decimal.

[0338] like Fig.25 As shown, the counter 202 counts the number of cycles at the rising edge of the signal OSC_CLK2 (that is, the signal OSC). If the start signal bEN of the "H" level is input to the OR circuit 241 of the counter 202, the oscillator 201 ends the oscillation of the signal OSC. At the end position of the counting action ( Fig.25When the signal OSC is at the "L" level, the start signal bEN is at the "H" level, so the OR circuit 241 outputs the signal OSC_CLK2 at the "H" level. That is, the signal OSC_CLK2 rises to the "H" level. As a result, the counter 202 outputs the count value CNT obtained by adding +1 to the number of cycles of the signal OSC. Therefore, in the N-1th cycle of the signal OSC, during the "L" level, the count value CNT is set to "N".

[0339] Furthermore, at the end position of the counting operation, when the signal OSC is at the "H" level, the OR circuit 241 maintains the output of the signal OSC_CLK2 at the "H" level. As a result, the counter 202 outputs the count value CNT without adding +1. Therefore, in the Nth cycle of the signal OSC, during the "H" level period, the count value CNT is set to "N".

[0340] Therefore, the period during which the count value CNT is "N" is the same as in the first embodiment, from the falling edge of the N-1th cycle of the signal OSC to the falling edge of the Nth cycle. As a result, the granularity error of the end position of the signal OSC relative to the CNT specification value "N" is reduced to a maximum of approximately 0.5 cycles of the signal OSC.

[0341] As described above, the counter 202 of the present embodiment also outputs the accumulated count value CNT at the same timing as that of the first embodiment.

[0342] 4.3 Counting action instruction sequence

[0343] Next, refer to Fig.26 , an example of the instruction sequence of the counting action is explained. Fig.26 : is a diagram showing an example of the instruction sequence of the counting action. Fig.26 In the example, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0344] like Fig.26 As shown, during the period from time t100 to time t110, the memory controller 20 and the memory controller 20 using the first embodiment Fig.10 Similarly to the description above, the command “CMD”, the address “LUN” and the address “xxh” are sent to the memory chip 11 in sequence.

[0345] When receiving the address "xxh", the sequencer 107 transmits the signal OSC_ST of "H" level to the replica circuit 102 during the period of time t110 to t120. After transmitting the signal OSC_ST of one pulse, the sequencer 107 sets the signal OSC_ST to "L" level.

[0346] Next, the sequencer 107 sends an "H" level reset signal RST to the replica circuit 102. When receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending a single pulse of the reset signal RST, the sequencer 107 sets the reset signal RST to an "L" level.

[0347] Next, at time t120, the memory controller 20 and the memory controller 21 use the first embodiment. Fig.10 Similarly to the description above, the address "00h" is sent to the memory chip 11 to instruct the start of the counting operation.

[0348] When the sequencer 107 receives the address "00h", it changes the "H" level start signal bEN from the "H" level to the "L" level at time t130. When the oscillator 201 receives the "L" level start signal bEN, it starts the oscillation of the signal OSC. In the counter 202, during the period from time t130 to t150, that is, during the period when the start signal bEN is at the "L" level, the OR circuit 241 outputs the signal OSC_CLK2 synchronized with the signal OSC. The counter 202 accumulates in coordination with the rising edge of the signal OSC_CLK2. In other words, the counter 202 accumulates in coordination with the rising edge of the signal OSC.

[0349] Next, the memory controller 20 and the memory controller 21 using the first embodiment Fig.10 Similarly, after the count execution time tRuntime has elapsed since the address “00h” for instructing the start of the count operation was sent, the address “00h” is sent again to the memory chip 11 at time t140.

[0350] When the sequencer 107 receives the address "00h", it sets the start signal bEN to the "H" level at time t150. When the oscillator 201 receives the start signal bEN at the "H" level, it starts the oscillation of the signal OSC. At this time, when the signal OSC is at the "L" level, the OR circuit 241 outputs the signal OSC_CLK2 at the "H" level based on the start signal bEN at the "H" level. The counter 202 accumulates the number of cycles based on the signal OSC_CLK2 at the "H" level and ends the counting operation.

[0351] 4.4 Counting Action Process

[0352] Next, refer to Fig. 27 , an example of the counting action process is described. Fig. 27 This is a flowchart showing an example of the flow of the counting operation.

[0353] like Fig. 27 As shown, first, steps S1 to S3 are executed. The operations of steps S1 to S3 are the same as those of the first embodiment. Fig.13 Same description as .

[0354] Counter 202 is in use Fig.26 During the period from time t130 to time t150 described above, at the rising edge of the signal OSC_CLK2 (that is, the signal OSC), the number of cycles of the signal OSC is counted (S41).

[0355] Oscillator 201 in use Fig.26 At time t150 described above, when the enable signal bEN at the "H" level is received, the output of the signal OSC is terminated (S42).

[0356] When the signal OSC_CLK2 (that is, the signal OSC) is at the "L" level, the output of the signal OSC is terminated (S43_Yes). Fig.25 As described above, the OR circuit 241 shifts the signal OSC_CLK2 to the "H" level based on the enable signal bEN at the "H" level (S44). As a result, the count value CNT is incremented by +1.

[0357] On the other hand, when the signal OSC_CLK2 (ie, the signal OSC) is at "H" level, when the output of the signal OSC ends (S43_No), the OR circuit 241 maintains the signal OSC_CLK2 at "H" level. As a result, +1 is not added to the count value CNT.

[0358] Next, steps S6 to S9 are executed. The operations of steps S6 to S9 are the same as those of the first embodiment. Fig.13 Same description as .

[0359] 4.5 Effects of this Implementation

[0360] According to the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0361] In addition, a modification example of the first embodiment is applied to this embodiment.

[0362] 4.6 Variations of the Fourth Implementation Example

[0363] Next, a modification of the fourth embodiment will be described. In the modification, a case where the configuration of the replica circuit 102 is different from that of the first embodiment will be described. The following description will focus on the differences from the first to fourth embodiments.

[0364] 4.6.1 Overall structure of the replica circuit

[0365] First, refer to Fig.28 , an example of the overall structure of the replica circuit 102 is described. Fig.28 1 is a diagram showing an example of the overall configuration of the replica circuit 102 .

[0366] like Fig.28 As shown, the replica circuit 102 includes an oscillator 201 and a counter 202 .

[0367] The oscillator 201 outputs an oscillation signal OSC and includes a comparator 203 , drivers 204 and 205 , a pull-up circuit 251 and a disable circuit 252 .

[0368] The comparator 203 and the drivers 204 and 205 are similar to those of the first embodiment. Figure 7 Same description as .

[0369] Pull-up circuit 251 raises the output signal of comparator 203 , that is, signal OSC, to “H” level. Pull-up circuit 251 includes a P-channel MOS transistor 301 .

[0370] A power supply voltage is applied to the source of the transistor 301, for example. The drain of the transistor 301 is connected to the output terminal of the comparator 203. That is, the drain of the transistor 301 is connected to the wiring path of the transmission signal OSC. The enable signal EN is input to the gate of the transistor 301. When the enable signal EN of the "L" level is input, the transistor 301 is turned on. That is, during the period when the counting operation is not performed, the signal OSC is raised to the "H" level.

[0371] The disabling circuit 252 is a circuit for stopping the operation of the comparator 203 (outputting an “L” level). The disabling circuit 252 includes an N-channel MOS transistor 302 .

[0372] The drain of the transistor 302 is connected to the comparator 203. The source of the transistor 302 is grounded (connected to the ground wiring). The enable signal bEN is input to the gate of the transistor 302. When the enable signal bEN of the "H" level is input, the transistor 302 is turned on. That is, during the period when the counting operation is not performed, the output of the comparator 203 is set to the "L" level.

[0373] 4.6.2 Counter Configuration

[0374] Next, refer to Fig.29 , an example of the structure of the counter 202 is described. Fig.29 2 is a circuit diagram showing an example of the configuration of the counter 202 .

[0375] like Fig.29 As shown, the counter 202 of this embodiment accumulates the number of cycles based on the rising edge of the signal OSC, and outputs the number of cycles as the count value CNT<15:0>.

[0376] The counter 202 includes a plurality of flip-flops 213. For example, the counter 202 includes flip-flops 213 corresponding to the count values ​​CNT, respectively, as in the first embodiment. <0> ~CNT <15> Flip-flops 213_0 to 213_15.

[0377] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0378] The structure of the flip-flop 213 is similar to that of the first embodiment. Figure 8 The signal OSC is input to the clock signal input terminal of the flip-flop 213_0. The flip-flop 213_0 extracts data at the rising edge of the signal OSC.

[0379] In this embodiment, the signal output from the output terminal Q of the flip-flops 213_0 to 213_15 is output as the 16-bit count value CNT <0> ~CNT <15> .

[0380] 4.6.3 Counting Action Instruction Sequence

[0381] Next, refer to Fig.30 , an example of the instruction sequence of the counting action is explained. Fig.30 : is a diagram showing an example of the instruction sequence of the counting action. Fig.30 In the example, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0382] like Fig.30 As shown, during the period from time t100 to time t110, the memory controller 20 and the memory controller 20 using the first embodiment Fig.10 Similarly to the description above, the command “CMD”, the address “LUN” and the address “xxh” are sent to the memory chip 11 in sequence.

[0383] When receiving the address "xxh", the sequencer 107 transmits the signal OSC_ST of "H" level to the replica circuit 102 during the period of time t110 to t120. After transmitting the signal OSC_ST of one pulse, the sequencer 107 sets the signal OSC_ST to "L" level.

[0384] Next, the sequencer 107 sends an "H" level reset signal RST to the replica circuit 102. When receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending a single pulse of the reset signal RST, the sequencer 107 sets the reset signal RST to an "L" level.

[0385] Next, at time t120, the memory controller 20 and the memory controller 21 use the first embodiment. Fig.10 Similarly to the description above, the address "00h" is sent to the memory chip 11 to instruct the start of the counting operation.

[0386] When the sequencer 107 receives the address "00h", at time t130, the start signal EN of the "L" level is changed from the "L" level to the "H" level. In addition, the start signal bEN of the "H" level is changed from the "H" level to the "L" level. When the oscillator 201 receives the start signal EN of the "H" level and the start signal bEN of the "L" level, it starts the oscillation of the signal OSC. In the counter 202, during the period from time t130 to t150, that is, during the period when the start signal bEN is at the "L" level, the signal OSC_CLK2 synchronized with the signal OSC is output from the OR circuit 241. The counter 202 accumulates in coordination with the rising edge of the signal OSC_CLK2. In other words, the counter 202 accumulates in coordination with the rising edge of the signal OSC.

[0387] Next, the memory controller 20 and the memory controller 21 using the first embodiment Fig.10 Similarly, after the count execution time tRuntime has elapsed since the address “00h” for instructing the start of the count operation was sent, the address “00h” is sent again to the memory chip 11 at time t140.

[0388] When the sequencer 107 receives the address "00h", it sets the start signal EN to the "L" level and the start signal bEN to the "H" level at time t150. When the oscillator 201 receives the start signal bEN at the "H" level, it starts the oscillation of the signal OSC. At this time, when the signal OSC is at the "L" level, since the pull-up circuit 251 of the oscillator 201 is in the on state, the oscillator 201 outputs the signal OSC at the "H" level. After the counter 202 accumulates the number of cycles based on the signal OSC at the "H" level, it ends the counting operation.

[0389] 4.6.4 Counting Action Process

[0390] Next, refer to Fig.31 , an example of the counting action process is described. Fig.31 This is a flowchart showing an example of the flow of the counting operation.

[0391] like Fig.31 As shown, first, steps S1 to S3 are executed. The operations of steps S1 to S3 are the same as those of the first embodiment. Fig.13 Same description as .

[0392] Counter 202 is in use Fig.30 During the period from time t130 to time t150 described above, the number of cycles of the signal OSC is counted at the rising edge of the signal OSC (S51).

[0393] Oscillator 201 in use Fig.30 At the time t150 described above, when the start signal bEN of the "H" level is received, the output of the signal OSC is terminated (S52). More specifically, the pull-up circuit 251 is turned on based on the start signal EN of the "L" level. In other words, the signal OSC is raised to the "H" level. In addition, the invalidation circuit 252 is turned on based on the start signal bEN of the "H" level.

[0394] When the signal OSC is at the "L" level, if the output of the signal OSC is completed (S53_Yes), the signal OSC is raised to the "H" level. As a result, the count value CNT is increased by +1.

[0395] On the other hand, when the signal OSC is at the "H" level, if the output of the signal OSC is completed (S53_No), the signal OSC maintains the "H" level. Therefore, +1 is not added to the count value CNT.

[0396] Next, steps S6 to S9 are executed. The operations of steps S6 to S9 are the same as those of the first embodiment. Fig.13 Same description as .

[0397] 4.6.5 Effect of this variation

[0398] According to the configuration of this variation, the same effects as those of the first embodiment can be obtained.

[0399] In addition, the modification of the first embodiment is applied to this modification.

[0400] 5. Fifth Implementation Method

[0401] Next, the fifth embodiment will be described. In the fifth embodiment, two examples of applying the replica circuit to different semiconductor devices are shown. The following description will focus on the differences from the first to fourth embodiments.

[0402] 5.1 Example 1

[0403] In the first example, a case where the semiconductor device is a DRAM will be described.

[0404] refer to Fig.32 , an example of the overall structure of the semiconductor device 400 is described. Fig.32 4 is a block diagram showing an example of the overall structure of the semiconductor device 400. Fig.32 In the figure, a part of the connection between the components is indicated by an arrow line, but the connection between the components is not limited to this.

[0405] like Fig.32As shown, the semiconductor device 400, for example, includes a memory cell array 401, a row decoder 402, a column decoder 403, a logic control circuit 404, an instruction / address input circuit 405, a sense amplifier circuit 406, a replica circuit 407, a transmission gate 408, a read / write amplifier circuit (RWAMP: Read / Write Amplifier) ​​409, an input / output circuit 410, a clock input / output circuit 411 and a voltage generating circuit 412.

[0406] The memory cell array 401 includes a plurality of memory cells MC. Each of the memory cells MC of the semiconductor device 400 includes a cell capacitor CC and a cell transistor CT. The gate of the cell transistor CT is connected to a corresponding one of a plurality of word lines WL. One end of the current path of the cell transistor CT is connected to the bit line BL. The other end of the current path of the cell transistor CT is connected to one end of the cell capacitor CC. The other end of the cell capacitor CC is connected to a ground node. The cell capacitor CC can store an amount of charge corresponding to the data to be stored. The cell transistor CT switches the conduction / non-conduction between the memory cell MC and the bit line BL (selection / non-selection of the memory cell). The plurality of memory cells MC are arranged in a two-dimensional array or a three-dimensional array in the memory cell array 401. For example, the memory cell array 401 includes a plurality of memory bodies. Each memory body is a control unit including a plurality of memory cells MC. The plurality of memory bodies can operate independently of each other.

[0407] The row decoder 402 controls selection / non-selection of row-direction wiring (eg, word lines WL) of the memory cell array 401 based on a decoding result of address information and a decoding result of a command.

[0408] The column decoder 403 controls selection / non-selection of wirings (eg, bit lines BL) in the column direction of the memory cell array 401 based on the decoding result of the address information and the decoding result of the command.

[0409] The logic control circuit 404 is a circuit that performs logic control of the entire semiconductor device 400 .

[0410] The logic control circuit 404 executes, for example, write training as appropriate. As in the first to fourth embodiments, write training is executed for the purpose of adjusting the timing between the signal DQ and the signals DQS and bDQS.

[0411] In addition, the logic control circuit 404 periodically performs a counting operation of a clock signal in the replica circuit 407. The clock signal is a pseudo signal of the signal DQS. The logic control circuit 404 determines whether or not to perform write training based on the amount of change in the count value.

[0412] The logic control circuit 404 includes an address decoder 421 , a mode register 422 , and a command decoder 423 .

[0413] The address decoder 421 decodes the address information received from the command / address input circuit 405 , and transmits the decoded result of the address information to each of the row decoder 402 and the column decoder 403 .

[0414] The count value received from the replica circuit 407 is stored in the mode register 422 .

[0415] The instruction decoder 423 decodes the instruction received from the instruction / address input circuit 405 . The instruction decoder 423 transmits the decoding result of the instruction to each of the row decoder 402 and the column decoder 403 .

[0416] The command / address input circuit 405 receives a command / address signal CA supplied from the outside (external device not shown). The command / address signal CA includes a command and address information. The command / address input circuit 405 sends the command and address information to the command decoder 423 and the address decoder 421, respectively.

[0417] The sense amplifier circuit 406 senses and amplifies the signal from the memory cell MC during the read operation. The sense amplifier circuit 406 transmits the signal from the memory cell MC as read data to the input-output circuit 410 via the transmission gate 408 and the RWAMP 409. The sense amplifier circuit 406 receives the write data from the input-output circuit 401 via the transmission gate 408 and the RWAMP 409. The sense amplifier circuit 406 outputs a signal corresponding to the write data to the bit line BL.

[0418] The replica circuit 407 is a circuit that generates a clock signal corresponding to the signal DQS and counts the number of cycles (clock count) of the clock signal. The replica circuit 407 includes a feedback oscillator for generating a clock signal and a counter described in any one of the first to fourth embodiments. The feedback path of the oscillator has the same structure as the transmission path of the signal DQS. The replica circuit 407 sends the count result of the counting operation to the mode register 422.

[0419] The transmission gate 408 controls the data transmission between the sense amplifier circuit 406 and the RWAMP 409 .

[0420] RWAMP 409 amplifies the level (signal value) of a signal corresponding to read data and the level of a signal corresponding to write data.

[0421] The input / output circuit 410 functions as an interface circuit for the signal DQ transmitted between the memory cell array 401 and the outside of the semiconductor device 400. The input / output circuit 410 transmits write data to the memory cell array 401 at a timing synchronized with the internal clock signal CLK received from the clock input / output circuit 411. In addition, the input / output circuit 410 transmits read data to a device outside the semiconductor device 400. For example, the input / output circuit 410 receives a data mask signal DM. The input / output circuit 410 performs mask processing on the signal DQ (data) based on the data mask signal DM.

[0422] The clock input-output circuit 411 is a transceiver circuit for signals DQS and bDQS. The clock input-output circuit 411 performs transceiver of signals DQS and bDQS between the semiconductor device 400 and the outside. When inputting data to the semiconductor device 400, the clock input-output circuit 411 sends the internal clock signal CLK based on the signals DQS and bDQS received from the outside to the input-output circuit 410. The internal clock signal CLK in this example is a signal that delays the signal DQS. In the input-output circuit 410, the input timing of the internal clock signal CLK is synchronized with the input timing of the signal DQ. Thus, the input-output circuit 410 can extract the signal DQ based on the internal clock signal CLK. In the write training, the timing of the signal DQ is optimized in such a way that the delay time of the signal CLK corresponding to the signals DQS and bDQS becomes the time tDQS2DQ. Therefore, the delay time of the internal clock signal CLK relative to the signal DQS is equivalent to the time tDQS2DQ. Furthermore, when the semiconductor device 400 outputs data, the clock input / output circuit 411 outputs the generated signals DQS and bDQS to the outside.

[0423] The voltage generating circuit 412 uses the power supply voltage from the outside (the voltage applied to the power supply node VDD and the voltage applied to the ground node VSS) to generate a plurality of voltages for each of various operation sequences of the semiconductor device 400. The voltage generating circuit 412 sends the generated voltage to other circuits (for example, the RWAMP 409).

[0424] In the first example of the fifth embodiment, the semiconductor device 400 is DRAM, but the present invention is not limited thereto. The semiconductor device 400 may be a random access memory other than DRAM. For example, the semiconductor device 400 may be SRAM (Static RAM).

[0425] In the semiconductor device 400 according to the first example of the fifth embodiment, for example, the replica circuit 102 described in the first to fourth embodiments can be applied to the replica circuit 407 .

[0426] 5.2 Case 2

[0427] In the second example, a case where the semiconductor device 500 is a microcontroller will be described.

[0428] 5.2.1 Structure of semiconductor devices

[0429] First, refer to Fig.33 , an example of the overall structure of the semiconductor device 500 is described. Fig.33 is a block diagram showing the overall structure of the semiconductor device 500. Fig.33 In the figure, a part of the connection between the components is indicated by an arrow line, but the connection between the components is not limited to this.

[0430] like Fig.33 As shown, the semiconductor device 500 includes, for example, a processor 501, a bus control circuit 502, a flash memory 503, a RAM 504, a DA (Digital / Analog) conversion circuit 505, an AD (Analog / Digital) conversion circuit 506, a timer 507, an input / output (I / O) port 508, an oscillator 509, an insertion controller 510, a time difference measurement circuit 511, and a replica circuit 512. The bus of the semiconductor device 500 connects the processor 501, the bus control circuit 502, the flash memory 503, the RAM 504, the DA conversion circuit 505, the AD conversion circuit 506, the timer 507, the input / output port 508, the oscillator 509, the insertion controller 510, the time difference measurement circuit 511, and the replica circuit 512. The bus of the semiconductor device 500 is a transmission path of signals and data in the semiconductor device 500.

[0431] The processor 501 executes various processes in the semiconductor device 500. The processor 501 performs various processes on supplied data. The processor 501 is, for example, a CPU.

[0432] The processor 501 executes training as appropriate, for example. In this example, the training is executed for the purpose of adjusting the timing between the signal received by the input / output port 508 and the internal clocks CLK and bCLK.

[0433] In addition, the processor 501 periodically performs a counting operation of a clock signal in the replica circuit 512, for example. The clock signal is a pseudo signal of the internal clock CLK. The processor 501 determines whether training is performed based on the amount of change in the count value.

[0434] The bus control circuit 502 controls the bus of the semiconductor device 500. The bus control circuit 502 may be provided in the processor 501.

[0435] The flash memory 503 is a storage device capable of storing data in a nonvolatile manner. The flash memory 503 is, for example, a NOR (Not or) type flash memory. Alternatively, the flash memory 503 may be a NAND type flash memory.

[0436] The RAM 504 is a storage device for temporarily storing data and is, for example, a random access memory such as an SRAM or a DRAM.

[0437] The DA conversion circuit 505 converts a digital signal (digital value) into an analog signal (analog value).

[0438] The AD conversion circuit 506 converts the analog signal into a digital signal.

[0439] The timer 507 manages the time (operation timing) within the semiconductor device 500 .

[0440] The input / output port 508 functions as an interface circuit in the semiconductor device 500. The input / output port 508 includes, for example, four ports P1, P2, P3, and P4. The number of ports provided by the input / output port 508 may be 3 or less, or may be 5 or more. The input / output port 508 inputs and outputs signals in a timing synchronized with the internal clocks CLK and bCLK received from the oscillator 509. That is, the input / output port 508 receives a signal including data or an address from the outside of the semiconductor device 500 (for example, a host not shown) via each of the ports P1, P2, P3, and P4. The input / output port 508 sends signals such as data to the outside of the semiconductor device 500 via each of the ports P1, P2, P3, and P4. The input / output port 508 complies with, for example, the GPIO (General Purpose Input / Output) standard, the USART (Universal Synchronous / Asynchronous Receiver Transmitter) standard, or the I2C (Inter-integrated Circuit) standard.

[0441] The oscillator 509 outputs a clock signal as a synchronization signal to the processor 501. The clock signal has a certain period (number of clocks). Thus, the processor 501 performs various processes in a timing synchronized with the clock signal. The period of the clock signal is, for example, 4 MHz, 8 MHz, 12 MHz, or 24 MHz. In addition, the oscillator 509 outputs internal clocks CLK and bCLK to the input / output port 508. The internal clock bCLK is an inverted signal of the internal clock CLK.

[0442] The insertion controller 510 receives an external insertion command. For example, the insertion controller 510 has a register for managing the state of the insertion request. Based on the received external insertion command, the insertion controller 510 sends various insertion requests to the processor 501. According to the insertion request, the processor 501 temporarily interrupts the processing being executed and performs the insertion request processing. After the processing of the insertion request is completed, the processor 501 resumes the interrupted processing.

[0443] The time difference measurement circuit 511 is a circuit that measures the timing deviation (time difference) between the internal clocks CLK and bCLK in the input / output port 508 and the input signal.

[0444] Furthermore, the time difference measurement circuit 511 causes the replica circuit 512 to execute a counting operation of the clock signal based on the control of the processor 501. The clock signal used by the replica circuit 512 is a pseudo signal of the internal clock CLK.

[0445] The replica circuit 512 is a circuit that generates a clock signal corresponding to the internal clock CLK and counts the number of cycles (clock count) of the clock signal. The replica circuit 512 includes a feedback oscillator for generating a clock signal and the counter described in the first to fourth embodiments. The feedback path of the oscillator has the same structure as the transmission path of the internal clock CLK. The replica circuit 512 sends the count result of the counting operation to the processor 501.

[0446] In addition, the semiconductor device 500 may be a system on chip (SoC), a system in package (SIP), or a system on package (SoP). The semiconductor device 500 is used in, for example, an embedded system. The semiconductor device 500 may also be used in, for example, vehicle-mounted devices, home appliances, computers, industrial machinery, railway vehicles, aircraft, and ships.

[0447] In addition, the semiconductor device 500 can also be classified based on bus width, memory structure, command group, etc. The bus width indicates the size of the data bus. For example, the semiconductor device 500 is classified into an 8-bit microcontroller, a 16-bit microcontroller, or a 32-bit microcontroller based on the bus width. The semiconductor device 500 can obtain better performance through a high bus width.

[0448] In the semiconductor device 500 according to the second example of the fifth embodiment, for example, the replica circuit 102 described in the first to fourth embodiments can be applied to the replica circuit 512 .

[0449] 5.2.2 Connection between oscillator and input and output ports

[0450] Next, refer to Fig.34 , an example of connection between the oscillator 509 and the input / output port 508 is described. Fig.341 is a block diagram showing an example of connection between the oscillator 509 and the input / output port 508 .

[0451] like Fig.34 As shown, the semiconductor device 500 further includes an input receiver 520 and a delay circuit 521. In addition, the input / output port 508 includes a latch circuit 522.

[0452] The input receiver 520 is a receiving circuit for the internal clocks CLK and bCLK. The output terminal of the input receiver 520 is connected to the delay circuit 521. For example, the input receiver 520 outputs a signal synchronized with the internal clocks CLK and bCLK.

[0453] The delay circuit 521 is a circuit that delays the signal received from the input receiver 520. The delay circuit 521 is connected to the latch circuit 522. The output signal of the input receiver 520 is delayed by the delay circuit 521 and the wiring delay of the wiring path connecting the input receiver 520 and the latch circuit 522, and is input to the latch circuit 522. The delay time at this time is recorded as time tSkew. That is, the internal clocks CLK and bCLK after the delay time tSkew are input to the latch circuit 522.

[0454] The latch circuit 522 is a circuit that extracts a signal inputted via each of the ports P1, P2, P3, and P4 based on delayed internal clocks CLK and bCLK. The latch circuit 522 is connected to the ports P1, P2, P3, and P4.

[0455] 5.2.3 Counting Action Process

[0456] Next, refer to Fig.35 , an example of the counting action process is described. Fig.35 This is a flowchart showing an example of the flow of the counting operation.

[0457] like Fig.35 As shown, first, the processor 501 instructs the time difference measurement circuit 511 to execute a counting operation in the replica circuit 512 (S101).

[0458] When receiving a count operation instruction from the processor 501, the time difference measurement circuit 511 causes the replica circuit 512 to execute the count operation (S102).

[0459] When the counting operation is completed, the replica circuit 512 transmits the count value CNT to the processor 501 ( S103 ).

[0460] The processor 501 calculates the difference between the received count value CNT and the count value CNT of the last counting operation performed ( S104 ).

[0461] The processor 501 determines whether the difference is greater than a preset threshold ( S105 ).

[0462] When the difference is greater than a preset threshold value ( S105_Yes), the processor 501 performs training ( S106 ) to adjust the time difference (time tSkew).

[0463] On the other hand, when the difference does not reach the preset threshold (S105_No), the processor 501 ends the counting operation.

[0464] 5.3 Effects of this Implementation

[0465] With the configurations of the first and second examples of this embodiment, the same effects as those of the first embodiment can be obtained.

[0466] 6. Variations, etc.

[0467] The semiconductor device 11 of the embodiment includes an oscillator 201 that outputs a first signal OSC and a counter 202 that counts the number of cycles of the first signal. The counter sets the count value of the number of cycles of the first signal to N before the oscillator outputs the Nth (N is an integer greater than or equal to 2) cycle of the first signal.

[0468] By applying the above-described embodiment, a semiconductor device capable of improving processing performance can be provided.

[0469] In addition, the embodiment is not limited to the above-described form, and various modifications can be made.

[0470] The "connection" in the above-described embodiments also includes an indirect connection state with something else such as a transistor or a resistor interposed therebetween.

[0471] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and their equivalents.

[0472] [Explanation of symbols]

[0473] 1 Memory System

[0474] 10 Non-volatile memory

[0475] 11 Memory Chip

[0476] 20 Memory Controller

[0477] 21 Host interface circuit

[0478] 22 CPU

[0479] 23 ROM

[0480] 24,504 RAM

[0481] 25 Buffer memory

[0482] 26 ECC Circuit

[0483] 27 Memory interface circuit

[0484] 101,410 Input and output circuits

[0485] 102,407,512 Replica Circuit

[0486] 103 Logic Control Circuit

[0487] 104 Address register

[0488] 105 Instruction Register

[0489] 106 Status Register

[0490] 107 Sequencer

[0491] 108 Ready / Busy Circuit

[0492] 109 Voltage generating circuit

[0493] 120,401 memory cell array

[0494] 121,402 Line Decoder

[0495] 122 Sense Amplifier

[0496] 123 Data register

[0497] 124,403 column decoder

[0498] 131 Input Circuit

[0499] 132 Output Circuit

[0500] 141,520 Input Receivers

[0501] 142,221,521 Delay Circuit

[0502] 143,522 Latch Circuit

[0503] 151,154,203 Comparator

[0504] 152,153,204,205 Driver

[0505] 201,509 Oscillators

[0506] 202 Counter

[0507] 211,232 Inverter

[0508] 212,231,233 AND circuit

[0509] 213,234 Flip-flop

[0510] 214 Adder

[0511] 222,241 OR circuit

[0512] 235 exOR circuit

[0513] 236 Logic Circuits

[0514] 251 Pull-up circuit

[0515] 252 Invalid circuit

[0516] 301 P-channel MOS transistor

[0517] 302 N-channel MOS transistor

[0518] 400,500 Semiconductor devices

[0519] 404 Logic Control Circuit

[0520] 405 Command / address input circuit

[0521] 406 Sense Amplifier Circuit

[0522] 408 Transmission Gate

[0523] 411 Clock Input and Output Circuit

[0524] 412 Voltage generating circuit

[0525] 421 Address Decoder

[0526] 422 Mode Register

[0527] 423 Instruction Decoder

[0528] 501 Processor

[0529] 502 bus control circuit

[0530] 503 Flash

[0531] 505 DA conversion circuit

[0532] 506 AD conversion circuit

[0533] 507 Timer

[0534] 508 Input and Output Ports

[0535] 510 Insert Controller

[0536] 511 Time difference measurement circuit

[0537] BL bit line

[0538] BLK Block

[0539] MC memory cell transistor

[0540] SGD Select gate line

[0541] ST1, ST2 select transistor

[0542] SU String Unit

[0543] WL Word line.

Claims

1. A semiconductor device comprising: an oscillator, outputting a first signal; and A counter for counting the number of cycles of the first signal; and The counter sets a count value of the number of cycles of the first signal to N before the oscillator outputs an N-th (N is an integer greater than or equal to 2) cycle of the first signal.

2. The semiconductor device according to claim 1, wherein The counter sets the count value of the number of cycles of the first signal to N after 0.5 cycles have passed since the oscillator started to output the (N-1)th cycle of the first signal.

3. The semiconductor device according to claim 1, wherein The first signal alternately repeats a first edge of transitioning from a first logic level to a second logic level different from the first logic level, and a second edge of transitioning from the second logic level to the first logic level. The oscillator starts to output the first signal, and when the first edge is generated for the first time, the counter counts the number of cycles of the first signal using the second edge.

4. The semiconductor device according to claim 3, wherein The counter includes an adder, and outputs a value obtained by adding 1 to the number of cycles of the first signal as the count value.

5. The semiconductor device according to claim 3, wherein The counter adds 1 to the number of cycles of the first signal based on a second signal notifying the start of a counting operation received before the oscillator starts outputting the first signal.

6. The semiconductor device according to claim 1, wherein The first signal alternately repeats a first edge of transitioning from a first logic level to a second logic level different from the first logic level, and a second edge of transitioning from the second logic level to the first logic level. When the oscillator starts to output the first signal and the first edge is generated for the first time, the counter counts the number of cycles of the first signal using the first edge.

7. The semiconductor device according to claim 6, wherein The counter comprises: a first flip-flop, operating based on the first edge of the first signal; a second flip-flop, operating based on the second edge of the first signal; a first circuit for performing an exclusive logical sum operation on a first output signal of the first flip-flop and a second output signal of the second flip-flop; and The logic circuit determines whether to add 1 to the number of cycles of the first signal based on a calculation result of the first circuit.

8. The semiconductor device according to claim 7, wherein The logic circuit adds 1 to the number of cycles of the first signal when the logic level of the first output signal is the same as the logic level of the second output signal, and does not add 1 to the number of cycles of the first signal when the logic level of the first output signal is different from the logic level of the second output signal.

9. The semiconductor device according to claim 6, wherein When the first signal is at the first logic level, when the oscillator stops outputting the first signal, the counter adds 1 to the number of cycles of the first signal. When the first signal is at the second logic level, when the oscillator stops outputting the first signal, the counter does not add 1 to the number of cycles of the first signal.

10. The semiconductor device according to claim 9, wherein The oscillator outputs the first signal during a period when the third signal is at the first logic level, and the counter includes: a second circuit that outputs a fourth signal based on a logical sum operation result of the first signal and the third signal; and The third flip-flop operates based on the first edge of the fourth signal.

11. The semiconductor device according to claim 9, wherein The oscillator comprises: a third circuit including an output terminal for outputting the first signal and an input terminal for inputting the first signal output from the output terminal; and The pull-up circuit is connected to the output terminal of the third circuit.

12. The semiconductor device according to claim 1, further comprising: a latch circuit that extracts a seventh signal input from the outside based on a sixth signal that delays a fifth signal input from the outside; and One cycle of the first signal is equal to a delay time of the sixth signal with respect to the fifth signal.

13. The semiconductor device according to claim 12, wherein The fifth signal and the seventh signal are input asynchronously.

14. The semiconductor device according to claim 12, wherein A maximum value of a granularity error of the count value generated during a first period in which the counter performs a counting operation is equal to a value obtained by dividing the delay time by a length of the first period.

15. The semiconductor device according to claim 14, wherein The first period is based on a command group received from an external controller. The delay time is based on a time difference between the fifth signal and the seventh signal received from the external controller.

16. The semiconductor device according to claim 12, further comprising: a first pad to which the fifth signal is input from the outside; and The second pad receives the seventh signal from the outside; and The number of circuits provided on a first path connecting the first pad and the latch circuit is greater than the number of circuits provided on a second path connecting the second pad and the latch circuit.

17. The semiconductor device according to claim 12, further comprising: The control circuit is configured to perform an operation of adjusting the timing of the fifth signal and the seventh signal when an absolute value of a difference between the count value output by the counter and a count value measured last time is greater than a preset threshold value.

18. A counting method, comprising: using an oscillator that outputs a first signal and a counter that counts the number of cycles of the first signal; and comprising: Start outputting the first signal; and Before the Nth (N is an integer greater than or equal to 2)th cycle of the first signal is output, the count value of the number of cycles of the first signal is set to N.

19. The counting method according to claim 18, wherein Setting the count value to N includes: The count value of the number of cycles of the first signal is set to N after 0.5 cycles have passed since the (N-1)th cycle of the first signal was output.

20. The counting method according to claim 18, wherein Starting to output the first signal includes: initially generating a first edge that transitions from a first logic level to a second logic level different from the first logic level; and Setting the count value to N includes accumulating the number of cycles of the first signal based on a second edge transitioning from the second logic level to the first logic level.

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