Chip selection signal control circuit, processing circuit and memory

Abstract

The chip selection signal control circuit comprises a first control signal generation circuit, a second control signal generation circuit, a chip selection signal sampling circuit and a logic control circuit. Wherein the first control signal generation circuit outputs a first control signal according to a first chip selection sampling signal and a first command address sampling signal obtained by sampling in the first two system sampling periods; the second control signal generation circuit is used for outputting a second control signal according to a second chip selection sampling signal and a second command address sampling signal obtained by sampling in a previous system sampling period; and the logic control circuit is used for controlling the output of the current chip selection sampling signal according to the first control signal and the second control signal.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to a chip select signal control circuit 、 Processing circuit and memory. Background Art

[0002] In the memory, the command address signal is transmitted through the command address bus, and the chip select signal can be used to indicate whether the command address signal is valid. Since various command address signals are collected on the command address bus, various decoding errors may occur in some special cases. Summary of the invention

[0003] In view of this, the present disclosure provides a chip select signal control circuit 、 The processing circuit and the memory can avoid decoding errors of command address signals.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a chip select signal control circuit, the chip select signal control circuit comprising:

[0006] A first control signal generating circuit is configured to receive a first chip select sampling signal and a first command address sampling signal, and output a first control signal of a first level when the levels of the first chip select sampling signal and the first command address sampling signal meet a first preset rule, otherwise, output a first control signal of a second level; wherein the first chip select sampling signal is obtained by sampling the initial chip select signal during the first two system sampling cycles, and the first command address sampling signal is obtained by sampling the initial command address signal during the first two system sampling cycles;

[0007] The second control signal generating circuit is configured to receive a second chip select sampling signal and a second command address sampling signal, and output a second control signal of a first level when the levels of the second chip select sampling signal and the second command address sampling signal meet a second preset rule, otherwise, output a second control signal of a second level; wherein the second chip select sampling signal is obtained by sampling the initial chip select signal in a previous system sampling cycle, and the second command address sampling signal is obtained by sampling the initial command address signal in a previous system sampling cycle;

[0008] a chip select signal sampling circuit, configured to receive the initial chip select signal and a first frequency-divided clock signal, sample the initial chip select signal according to the first frequency-divided clock signal, and output a current chip select sampling signal;

[0009] A logic control circuit is connected to the first control signal generating circuit, the second control signal generating circuit and the chip select signal sampling circuit, and is configured to receive the first control signal, the second control signal and the current chip select sampling signal, and output the current chip select sampling signal when the first control signal and the second control signal meet a third preset rule.

[0010] In some embodiments, the second control signal generating circuit is further configured to receive the first control signal after the first delay and a second divided clock signal, sample the first control signal after the first delay according to the second divided clock signal, and output it as the second control signal.

[0011] In some embodiments, the first control signal generating circuit is further configured to, in the first operating mode, output the first control signal after applying a second delay; or, in the second operating mode, output the first control signal.

[0012] In some embodiments, the chip select signal control circuit also includes: a command address signal sampling circuit, configured to receive an initial command address signal, the first divided clock signal and the second divided clock signal, and to sample the initial command address signal into the first command address sampling signal according to the first divided clock signal; and to sample the initial command address signal into the second command address sampling signal according to the second divided clock signal.

[0013] In some embodiments, the first control signal generating circuit includes: a first NAND gate, a first inverter and a second inverter; the input end of the first NAND gate receives the first chip select sampling signal and the first command address sampling signal respectively; the output end of the first NAND gate is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter; the first NAND gate outputs the first control signal; the first inverter outputs the first control signal after the first delay; the second inverter outputs the first control signal after the second delay.

[0014] In some embodiments, the first control signal generating circuit further includes: a first data selector; a first input end of the first data selector receives the first control signal after the second delay; a second input end of the first data selector receives the first control signal; and a control end of the first data selector receives an operating mode enable signal.

[0015] In some embodiments, the first control signal generating circuit also includes: a first level trigger; the data input end of the first level trigger is connected to the output end of the first data selector; the clock input end of the first level trigger receives the first divided clock signal; the output end of the first level trigger serves as the output end of the first control signal generating circuit.

[0016] In some embodiments, the second control signal generating circuit includes: a second NAND gate, a first D flip-flop and a second data selector; the input ends of the second NAND gate receive the second chip select sampling signal and the second command address sampling signal respectively; the output end of the second NAND gate is connected to the first input end of the second data selector; the data input end of the first D flip-flop receives the first control signal after the first delay, and the clock input end of the first D flip-flop receives the second divided clock signal; the in-phase output end of the first D flip-flop is connected to the second input end of the second data selector; the control end of the second data selector receives the working mode enable signal.

[0017] In some embodiments, the second control signal generating circuit also includes: a second level trigger; the data input end of the second level trigger is connected to the output end of the second data selector; the clock input end of the second level trigger receives the first divided clock signal; the output end of the second level trigger serves as the output end of the second control signal generating circuit.

[0018] In some embodiments, the chip select signal sampling circuit includes: a second D flip-flop, a third inverter and a fourth inverter; the data input end of the second D flip-flop receives the initial chip select signal, and the clock input end of the second D flip-flop receives the first divided clock signal; the in-phase output end of the second D flip-flop is connected to the input end of the third inverter; the output end of the third inverter is connected to the input end of the fourth inverter; and the fourth inverter outputs the current chip select sampling signal.

[0019] In some embodiments, the logic control circuit includes: an OR gate and a third NAND gate; the first input end of the OR gate is connected to the output end of the first control signal generating circuit; the second input end of the OR gate is connected to the output end of the second control signal generating circuit; the output end of the OR gate is connected to the first input end of the third NAND gate; the second input end of the third NAND gate receives the current chip select sampling signal; the output end of the third NAND gate serves as the output end of the logic control circuit.

[0020] In some embodiments, the command address signal sampling circuit includes: a third D flip-flop and a fourth D flip-flop; the data input terminal of the third D flip-flop receives the initial command address signal, the clock input terminal of the third D flip-flop receives the first divided clock signal, and the third D flip-flop outputs the first command address sampling signal; the data input terminal of the fourth D flip-flop receives the initial command address signal, the clock input terminal of the fourth D flip-flop receives the second divided clock signal, and the fourth D flip-flop outputs the second command address sampling signal.

[0021] The embodiment of the present disclosure also provides a chip select signal processing circuit, characterized in that it includes: a chip select signal control circuit as described in the above scheme, and a decoding circuit; the decoding circuit is connected to the chip select signal control circuit, and is configured to receive a current chip select sampling signal, decode the current chip select sampling signal and output it.

[0022] An embodiment of the present disclosure further provides a memory, which includes a chip select signal processing circuit as described in the above solution.

[0023] In some embodiments, the memory is DDR5 DRAM.

[0024] It can be seen that the embodiment of the present disclosure provides a chip select signal control circuit, including: a first control signal generating circuit, a second control signal generating circuit, a chip select signal sampling circuit and a logic control circuit. Among them, the first control signal generating circuit outputs a first control signal according to the first chip select sampling signal and the first command address sampling signal obtained by sampling in the first two system sampling cycles; the second control signal generating circuit outputs a second control signal according to the second chip select sampling signal and the second command address sampling signal obtained by sampling in the previous system sampling cycle; the logic control circuit controls the output of the current chip select sampling signal according to the first control signal and the second control signal. In this way, by using the signals in the previous and the first two system sampling cycles to perform logic checks, it is possible to ensure that the command address signal in the current system sampling cycle is decoded normally, thereby avoiding decoding errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Signal schematic diagram provided for the embodiment of the present disclosure Figure 1 ;

[0026] Figure 2 Signal schematic diagram provided for the embodiment of the present disclosure Figure 2 ;

[0027] Figure 3 A schematic diagram of the structure of the chip select signal control circuit provided in the embodiment of the present disclosure Figure 1 ;

[0028] Figure 4 Signal schematic diagram provided for the embodiment of the present disclosure Figure 3 ;

[0029] Figure 5 Signal schematic diagram provided for the embodiment of the present disclosure Figure 4 ;

[0030] Figure 6 A schematic diagram of the structure of the chip select signal control circuit provided in the embodiment of the present disclosure Figure 2 ;

[0031] Figure 7 A schematic diagram of the structure of the chip select signal control circuit provided in the embodiment of the present disclosure Figure 3 ;

[0032] Figure 8 A schematic diagram of the structure of the chip select signal control circuit provided in the embodiment of the present disclosure Figure 4 ;

[0033] Fig. 9 A schematic diagram of the structure of the command address sampling circuit provided in the embodiment of the present disclosure Figure 1 ;

[0034] Fig.10 A schematic diagram of the structure of the chip select signal control circuit provided in the embodiment of the present disclosure Figure 5 ;

[0035] Fig.11 Signal schematic diagram provided for the embodiment of the present disclosure Figure 5 ;

[0036] Fig.12 Signal schematic diagram provided for the embodiment of the present disclosure Figure 6 ;

[0037] Fig.13 A schematic diagram of the structure of the command address sampling circuit provided in the embodiment of the present disclosure Figure 2 ;

[0038] Fig.14 A schematic diagram of the structure of a chip select signal processing circuit provided in an embodiment of the present disclosure;

[0039] Fig.15 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0041] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] If similar descriptions of "first / second" appear in the invention document, the following description is added. In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0044] It should be noted that the chip select signal is used to select the corresponding chip. When multiple chips are connected to the same bus, the chip select signal is used to distinguish which chip processes the data and address on the bus, that is, the chip select signal triggers the corresponding chip to enter the working state. For example, in the memory, multiple memory chips are included; in order for the CPU (processor) to access the storage unit, it must first select the storage chip through the chip select signal, that is, perform chip selection; then, it can select the corresponding storage unit from the selected storage chip according to the address code, that is, perform word selection, to read / write data. The chip select signal is usually valid at a low level; in the embodiment of the present disclosure, the chip select signal is described as being valid at a low level.

[0045] On the other hand, the command address signal includes the command signal and the address signal, which are transmitted through the bus. For example, in DRAM (dynamic random access memory), the command address signal may include: row address strobe (RAS), column address strobe (CAS), write command (WE), activate command (ACT), and other command signals, as well as address signals (such as A13~A0, etc.).

[0046] Furthermore, the command address signal needs to be indicated by the chip select signal to be valid. Figure 1Taking the design of DDR5DRAM (fifth generation double rate synchronous dynamic random access memory) as an example, the command address signal CA<12:0> input can be sampled as an address and can be sampled and decoded as an instruction, that is, the command address signal CA<12:0> includes the command signal CMD and the address signal ADD. After the chip select signal CS_n indicates valid (that is, the chip select signal CS_n is at a low level), the command address signal CA<12:0> is sampled by the even clock signal CLK_ET for decoding. Among them, the odd clock signal CLK_OT and the even clock signal CLK_ET are obtained by dividing the clock signal CK_t, and are used to sample the command address signal CA<12:0>.

[0047] Here, it should be noted that there are two command modes in DDR5 DRAM, namely 1T CMD and 2TCMD. 1T CMD only needs one system sampling cycle to output the command address signal as the instruction and address; while the command address signal of 2T CMD requires two system sampling cycles to transmit the instruction and address.

[0048] It should also be noted that the clock signal CK_t is the basic reference clock in the chip system; the system sampling period described in the embodiments of the present disclosure refers to the period of the clock signal CK_t, which will not be repeated below.

[0049] Figure 1 In the signal waveform diagram shown, the command address signal CA<12:0> is in 2T CMD mode. Figure 1 , the command address signal CA<12:0> requires two system sampling cycles to transmit the instruction and address. Specifically, the command address signal CA<12:0> transmits the instruction and a part of the address (i.e., CMD+ADD) in the 0th cycle of the clock signal CK_t; the command address signal CA<12:0> transmits the other part of the address (i.e., ADD) in the 2nd cycle of the clock signal CK_t.

[0050] Figure 1 The chip select signal CS_n shown in the example has an effective level (i.e., a low level) that lasts only one system sampling cycle. However, there is a case where the effective level of the chip select signal CS_n lasts for multiple system sampling cycles. For example, in a two-rank chip structure, the chip select signal corresponding to the on-chip termination command NT_ODT_CMD of the non-target chip has an effective level that lasts for two system sampling cycles.

[0051] Figure 2 The following example shows some waveforms of the command address signal and chip select signal of the non-target chip. Figure 2As shown, the command address signal CA includes the read command NT_RD of the non-target chip (i.e., one of the on-chip termination commands), and accordingly, the effective level duration of the chip select signal CS_n is two cycles of the clock signal CK_t. Thus, in the second system sampling cycle during which the effective level of the chip select signal CS_n lasts, the address transmitted by the command address signal CA (the portion outlined by the dotted line) may be mistaken for an instruction, which may lead to incorrect sampling and decoding.

[0052] Figure 3 This is an optional structural diagram of a chip select signal control circuit provided in an embodiment of the present disclosure. Figure 3 As shown, the chip selection signal control circuit 80 includes: a first control signal generating circuit 10 , a second control signal generating circuit 20 , a chip selection signal sampling circuit 30 and a logic control circuit 40 .

[0053] The first control signal generating circuit 10 is configured to receive the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB, and output the first control signal CS_EVEN_PP_T of the first level when the levels of the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB meet the first preset rule, otherwise, output the first control signal CS_EVEN_PP_T of the second level; wherein the first chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n during the first two system sampling cycles, and the first command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal during the first two system sampling cycles.

[0054] The second control signal generating circuit 20 is configured to receive the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB, and output the second control signal CS_EVEN_P_T of the first level when the levels of the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB meet the second preset rule, otherwise, output the second control signal CS_EVEN_P_T of the second level; wherein the second chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n in the previous system sampling cycle, and the second command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal in the previous system sampling cycle.

[0055] The chip select signal sampling circuit 30 is configured to receive an initial chip select signal CS_n and a first frequency-divided clock signal CLK_ET (ie, an even clock signal), sample the initial chip select signal CS_n according to the first frequency-divided clock signal CLK_ET, and output a current chip select sampling signal CS.

[0056] The logic control circuit 40 is connected to the first control signal generating circuit 10, the second control signal generating circuit 20 and the chip select signal sampling circuit 30, and is configured to receive the first control signal CS_EVEN_PP_T, the second control signal CS_EVEN_P_T and the current chip select sampling signal CS, and output the current chip select sampling signal CS when the first control signal CS_EVEN_PP_T and the second control signal CS_EVEN_P_T meet the third preset rule.

[0057] It should be noted that in Figure 3 In the example, the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB are obtained by sampling the even clock signal CLK_ET; the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB are obtained by sampling the odd clock signal CLK_OT ( Figure 3 (not shown) sampled.

[0058] Combination Figure 1 It can be seen that the odd clock signal CLK_OT and the even clock signal CLK_ET are obtained by dividing the clock signal CK_t; that is, the frequency of the odd clock signal CLK_OT and the even clock signal CLK_ET is half the frequency of the clock signal CK_t; the period of the odd clock signal CLK_OT and the even clock signal CLK_ET is twice the period of the clock signal CK_t.

[0059] Continue to refer Figure 1 , since the odd clock signal CLK_OT and the even clock signal CLK_ET are in opposite phases. Therefore, if any sampling edge (rising edge) of the even clock signal CLK_ET is taken as the current sampling edge, then the sampling edge (rising edge) of the odd clock signal CLK_OT is advanced by one system sampling cycle (i.e., advanced by half the cycle of the even clock signal CLK_ET); further, the previous sampling edge (rising edge) of the even clock signal CLK_ET is advanced by two system sampling cycles (i.e., advanced by one cycle of the even clock signal CLK_ET).

[0060] Combination Figure 1 and Figure 3, since the chip select signal sampling circuit 30 receives and samples the initial chip select signal CS_n according to the even clock signal CLK_ET, the current chip select sampling signal CS is obtained. Therefore, the moment when the current chip select sampling signal CS is sampled is two system sampling cycles in advance, which is the sampling edge of the even clock signal CLK_ET; that is, the first chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n by the even clock signal CLK_ET when the first two system sampling cycles are in progress; correspondingly, the first command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal by the even clock signal CLK_ET when the first two system sampling cycles are in progress. Similarly, the moment when the current chip select sampling signal CS is sampled is one system sampling cycle in advance, which is the sampling edge of the odd clock signal CLK_OT; that is, the second chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n by the odd clock signal CLK_OT during the previous system sampling cycle; correspondingly, the second command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal by the odd clock signal CLK_OT during the previous system sampling cycle.

[0061] Figure 4 and Figure 5 The waveforms of different command address signals CA are respectively shown when the effective level of the chip selection signal CS_n continues for multiple system sampling cycles.

[0062] refer to Figure 4 , the command address signal CA includes two consecutive 1T CMD mode commands (ie, PRE and PDE), and the effective level of the chip select signal CS_n lasts for two system sampling cycles. In this way, sampling according to the chip select signal CS_n may cause the second command PDE to be cancelled.

[0063] refer to Figure 3 In the embodiment of the present disclosure, the second control signal generating circuit 20 outputs the second control signal CS_EVEN_P_T according to the second chip selection sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB obtained in the previous system sampling cycle. Figure 4 The second control signal generating circuit 20 can make a comprehensive judgment based on the levels of the chip select signal CS_n and the command address signal CA in the previous system sampling cycle. For example, in the previous system sampling cycle, the chip select signal CS_n is at a low level, and the identification signal in the command address signal CA is at a high level, then it can be determined that the current command PDE is a complete command, and the current command PDE can be sampled and decoded normally when the chip select signal CS_n is at a low level.

[0064] refer to Figure 5 , the read command NT_RD (i.e., one of the on-chip termination commands) of the non-target chip lasts for two system sampling cycles, followed by a command PRE. In this way, sampling based on the chip select signal CS_n may mistakenly take the command PRE as the second system sampling cycle of the 2T CMD mode.

[0065] refer to Figure 3 In the embodiment of the present disclosure, the first control signal generating circuit 10 outputs the first control signal CS_EVEN_PP_T according to the first chip selection sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB obtained in the first two system sampling cycles. Figure 5 The first control signal generating circuit 10 can make a comprehensive judgment based on the levels of the chip select signal CS_n and the command address signal CA in the first two system sampling cycles. For example, in the first two system sampling cycles, the chip select signal CS_n is at a low level, and the command address signal CA represents the read command NT_RD of the non-target chip. Then, it can be determined that the current command PDE is a complete command. The current command PDE can be sampled and decoded normally when the chip select signal CS_n is at a low level, and the read command NT_RD is prevented from being incorrectly decoded in the second system sampling cycle.

[0066] It is understandable that, since various command address signals are collected on the command address bus, various decoding errors may occur. In the disclosed embodiment, the first control signal generating circuit obtains the first control signal according to the levels of the chip select signal and the command address signal in the first two system sampling cycles; the second control signal generating circuit obtains the second control signal according to the levels of the chip select signal and the command address signal in the previous system sampling cycle; further, the logic control circuit controls the output of the current chip select sampling signal according to the first control signal and the second control signal, that is, controls whether the chip select signal acts on the current command address signal. In this way, by using the signals in the previous and first two system sampling cycles to perform logic checks, it is possible to ensure that the command address signal in the current system sampling cycle is decoded normally, thus avoiding decoding errors.

[0067] Figure 6 Another optional structural schematic diagram of the chip select signal control circuit provided in the embodiment of the present disclosure. Figure 6 The example shows that the chip select signal sampling circuit 30 receives and samples the initial chip select signal CS_n according to the odd clock signal CLK_OT to obtain the current chip select sampling signal CS. That is, Figure 6 The example shows Figure 3 The corresponding circuit structure is Figure 6 The various signals shown in the examples can be referred to Figure 3 Pushed.

[0068] Specifically, refer to Figure 6 The first control signal generating circuit 10 is configured to receive the first chip select sampling signal ODD_CS_OT and the first command address sampling signal ODD_CA1_OB, and output the first control signal CS_ODD_PP_T of the first level when the levels of the first chip select sampling signal ODD_CS_OT and the first command address sampling signal ODD_CA1_OB meet the first preset rule, otherwise, output the first control signal CS_ODD_PP_T of the second level; wherein the first chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n during the first two system sampling cycles, and the first command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal during the first two system sampling cycles.

[0069] The second control signal generating circuit 20 is configured to receive the second chip select sampling signal EVEN_CS_OT and the second command address sampling signal EVEN_CA1_OB, and output the second control signal CS_ODD_P_T of the first level when the levels of the second chip select sampling signal EVEN_CS_OT and the second command address sampling signal EVEN_CA1_OB meet the second preset rule, otherwise, output the second control signal CS_ODD_P_T of the second level; wherein the second chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n in the previous system sampling cycle, and the second command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal in the previous system sampling cycle.

[0070] The chip select signal sampling circuit 30 is configured to receive an initial chip select signal CS_n and an odd clock signal CLK_OT, sample the initial chip select signal CS_n according to the odd clock signal CLK_OT, and output a current chip select sampling signal CS.

[0071] The logic control circuit 40 is connected to the first control signal generating circuit 10, the second control signal generating circuit 20 and the chip select signal sampling circuit 30, and is configured to receive the first control signal CS_ODD_PP_T, the second control signal CS_ODD_P_T and the current chip select sampling signal CS, and output the current chip select sampling signal CS when the first control signal CS_ODD_PP_T and the second control signal CS_ODD_P_T meet the third preset rule.

[0072] Understandably, Figure 3 and Figure 6 The circuit structures are shown as examples, corresponding to different sampling clocks. If the initial chip select signal CS_n is sampled with an even clock signal CLK_ET, the operation Figure 3 The circuit shown in FIG. 1 is as follows; if the initial chip select signal CS_n is sampled with the odd clock signal CLK_OT, the operation Figure 6 The circuit shown can be specifically configured according to the actual situation in the chip system.

[0073] Accordingly, Figure 6 In the circuit shown, the first chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n by the odd clock signal CLK_OT during the first two system sampling cycles; the first command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal by the odd clock signal CLK_OT during the first two system sampling cycles; the second chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n by the even clock signal CLK_ET during the previous system sampling cycle; the second command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal by the even clock signal CLK_ET during the previous system sampling cycle.

[0074] In some embodiments of the present disclosure, reference Figure 7 The second control signal generating circuit 20 is further configured to receive the first control signal EVEN_CHK1 after the first delay and the second divided clock signal CLK_OT (i.e., the odd clock signal), sample the first control signal EVEN_CHK1 after the first delay according to the second divided clock signal CLK_OT, and output it as the second control signal CS_EVEN_P_T.

[0075] Continue to refer Figure 7 The first control signal generating circuit 10 is further configured to output the first control signal after applying a second delay in the first working mode; or, in the second working mode, output the first control signal.

[0076] It should be noted that in a memory (such as DRAM), there are two working modes, namely 1N mode and 2N mode. In 1N mode, both the odd clock signal CLK_OT and the even clock signal CLK_ET are sampled; while in 2N mode, only one of the odd clock signal CLK_OT and the even clock signal CLK_ET is sampled.

[0077] exist Figure 7In the embodiment, the level of the working mode enable signal EN represents the working mode of the memory. For example, when the working mode enable signal EN is at a high level, it represents that the memory is in 1N mode (i.e., the first working mode); when the working mode enable signal EN is at a low level, it represents that the memory is in 2N mode (i.e., the second working mode). In other words, the chip select signal control circuit 80 provided in the embodiment of the present disclosure will also make corresponding adjustments according to the different working modes of the memory.

[0078] refer to Figure 7 For the first control signal generating circuit 10, in the 1N mode, the first control signal CS_EVEN_PP_T output by the first control signal generating circuit 10 is subjected to the second delay; in the 2N mode, the first control signal CS_EVEN_PP_T output by the first control signal generating circuit 10 is not subjected to the second delay. Applying the second delay can make the output first control signal CS_EVEN_PP_T match the timing of other signals in the 1N mode.

[0079] Continue to refer Figure 7 For the second control signal generating circuit 20, in the 1N mode, the second control signal generating circuit 20 outputs the second control signal CS_EVEN_P_T according to the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB; in the 2N mode, the second control signal generating circuit 20 samples the first control signal EVEN_CHK1 after the first delay and outputs it.

[0080] It should be noted that Figure 7 In the circuit shown in the example, in the 2N mode, the even clock signal CLK_ET samples the initial chip select signal CS_n, that is, the odd clock signal CLK_OT is not sampled at this time. In this way, the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB obtained by sampling the odd clock signal CLK_OT cannot be applied to the 2N mode. Therefore, in the 2N mode, the second control signal generating circuit 20 can sample the first control signal EVEN_CHK1 after the first delay according to the odd clock signal CLK_OT, thereby replacing the logic check of the signal in the previous system sampling cycle to output the second control signal CS_EVEN_P_T.

[0081] Accordingly, Figure 8 In the circuit shown, in the 2N mode, the initial chip select signal CS_n is sampled by the odd clock signal CLK_OT. Figure 8The second control signal generating circuit 20 is further configured to receive the first control signal ODD_CHK1 after the first delay and the second frequency-divided clock signal CLK_ET (ie, an even clock signal), sample the first control signal ODD_CHK1 after the first delay according to the second frequency-divided clock signal CLK_ET, and output it as the second control signal CS_EVEN_P_T.

[0082] It is understandable that the chip select signal control circuit provided in the embodiment of the present disclosure can make corresponding adjustments according to different working modes of the memory, so as to better adapt to different working modes of the memory and expand the application scope of the circuit.

[0083] In some embodiments of the present disclosure, the chip select signal control circuit further includes: a command address signal sampling circuit. The command address signal sampling circuit is configured to receive an initial command address signal, a first frequency-divided clock signal, and a second frequency-divided clock signal, sample the initial command address signal into a first command address sampling signal according to the first frequency-divided clock signal; and sample the initial command address signal into a second command address sampling signal according to the second frequency-divided clock signal.

[0084] That is to say, reference Fig. 9 The command address signal sampling circuit 50 can sample the initial command address signal CA according to the odd clock signal CLK_OT and output the command address sampling signal ODD_CA1_OB. The command address signal sampling circuit 50 can also sample the initial command address signal CA according to the even clock signal CLK_ET and output the command address sampling signal EVEN_CA1_OB. The command address sampling signals ODD_CA1_OB and EVEN_CA1_OB are used as Figure 3 , Figure 6 , Figure 7 and Figure 8 The input signal in .

[0085] Fig.10 An optional structural diagram of a chip select signal control circuit provided in an embodiment of the present disclosure. Fig.11 and Fig.12 Then Fig.10 The waveform diagram of some signals in the figure. Fig.11 The waveform of some signals of the memory in 1N mode is shown as an example; that is, Fig.11 Both the odd clock signal CLK_OT and the even clock signal CLK_ET are sampled. Fig.12 The waveforms of some signals of the memory in 2N mode are shown as an example; Fig.12 In the process, only the even clock signal CLK_ET is sampled.

[0086] In some embodiments of the present disclosure, reference Fig.10 , the first control signal generating circuit 10 includes: a first NAND gate Nand1, a first inverter Inv1, and a second inverter Inv2. The input end of the first NAND gate Nand1 receives the first chip selection sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB respectively, and the output end of the first NAND gate Nand1 is connected to the input end of the first inverter Inv1. The output end of the first inverter Inv1 is connected to the input end of the second inverter Inv2. Among them, the first NAND gate Nand1 outputs the first control signal EVEN_CHK, the first inverter Inv1 outputs the first control signal EVEN_CHK1 after the first delay, and the second inverter Inv2 outputs the first control signal EVEN_CHK2 after the second delay.

[0087] Continue to refer Fig.10 , the first control signal generating circuit 10 further includes: a first data selector Mux1. The first input terminal (i.e., the "1" input terminal) of the first data selector Mux1 receives the first control signal EVEN_CHK2 after the second delay, the second input terminal (i.e., the "0" input terminal) of the first data selector Mux1 receives the first control signal EVEN_CHK, and the control terminal of the first data selector Mux1 receives the working mode enable signal EN.

[0088] In the disclosed embodiment, the level of the working mode enable signal EN represents the working mode of the memory. When the memory is in 1N mode (i.e., the first working mode), the working mode enable signal EN is at a high level; then, the first data selector Mux1 will select to output the first control signal EVEN_CHK2 (i.e., the signal received at the "1" input terminal) after the second delay. When the memory is in 2N mode (i.e., the second working mode), the working mode enable signal EN is at a low level; then, the first data selector Mux1 will select to output the first control signal EVEN_CHK (i.e., the signal received at the "0" input terminal).

[0089] In some embodiments of the present disclosure, reference Fig.10 The first control signal generating circuit 10 further includes: a first level trigger T1. The data input terminal D of the first level trigger T1 is connected to the output terminal of the first data selector Mux1, the clock input terminal of the first level trigger T1 receives the first frequency-divided clock signal CLK_ET, and the output terminal of the first level trigger T1 serves as the output terminal of the first control signal generating circuit 10.

[0090] In the embodiment of the present disclosure, combining 10 and Fig.12The initial command address signal CA includes the PRE signal and the PDE signal, wherein the PDE signal is the signal that needs to be sampled and decoded currently, and the PRE signal is two system sampling cycles before the PDE signal. The PRE signal is initially sampled by the even clock signal CLK_ET as a high-level pre-sampling command address CA1 (PRE), and is further sampled as a low-level first command address sampling signal EVEN_CA1_OB.

[0091] In addition, the initial chip select signal CS_n is at a valid level (low level) before two system sampling cycles, that is, the initial chip select signal CS_n corresponds to the PRE signal at a low level. Thus, before two system sampling cycles, the initial chip select signal CS_n is sampled by the even clock signal CLK_ET as the first chip select sampling signal EVEN_CS_OT at a high level.

[0092] Furthermore, the first command address sampling signal EVEN_CA1_OB is at a low level, and the first chip selection sampling signal EVEN_CS_OT is at a high level. After the first NAND gate Nand1 performs a NAND operation, a high-level first control signal EVEN_CHK is obtained. In this way, the PRE signal representing the first two system sampling cycles is a command of the 1T CMD mode, and thus the PDE signal of the current system sampling cycle is a new command and can be decoded normally.

[0093] In the embodiment of the present disclosure, combining 10 and Fig.12 If the initial chip select signal CS_n and the pre-sampling command address CA1 (PRE) of the first two system sampling cycles are both at low levels, then it will be recognized as a command of the first two system sampling cycles in the 2T CMD mode. At this time, if the on-chip termination command NT_ODT_CMD (not shown in the figure) is included, the current system sampling cycle can be decoded normally, thereby eliminating the situation where the command after the on-chip termination command NT_ODT_CMD is cancelled.

[0094] In some embodiments of the present disclosure, reference Fig.10, the second control signal generating circuit 20 includes: a second NAND gate Nand2, a first D flip-flop DFF1, and a second data selector Mux2. The input end of the second NAND gate Nand2 receives the second chip selection sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB respectively, and the output end of the second NAND gate Nand2 is connected to the first input end (i.e., the "1" input end) of the second data selector Mux2. The data input end D of the first D flip-flop DFF1 receives the first control signal EVEN_CHK1 after the first delay, the clock input end of the first D flip-flop DFF1 receives the second frequency-divided clock signal CLK_OT, and the in-phase output end Q of the first D flip-flop DFF1 is connected to the second input end (i.e., the "0" input end) of the second data selector Mux2. The control end of the second data selector Mux2 receives the working mode enable signal EN.

[0095] In the disclosed embodiment, the level of the working mode enable signal EN represents the working mode of the memory. When the memory is in 1N mode (i.e., the first working mode), the working mode enable signal EN is at a high level; thus, the second data selector Mux2 will select to output the signal received at its "1" input terminal. When the memory is in 2N mode (i.e., the second working mode), the working mode enable signal EN is at a low level; thus, the first data selector Mux1 will select to output the signal received at its "0" input terminal.

[0096] In some embodiments of the present disclosure, reference Fig.10 The second control signal generating circuit 20 further includes: a second level trigger T2. The data input terminal D of the second level trigger T2 is connected to the output terminal of the second data selector Mux2, the clock input terminal of the second level trigger T2 receives the first frequency-divided clock signal CLK_ET, and the output terminal Q of the second level trigger T2 serves as the output terminal of the second control signal generating circuit 20.

[0097] In the present disclosure, in combination Fig.10 and Fig.11 The initial command address signal CA includes the PRE signal and the PDE signal, wherein the PDE signal is the signal that needs to be sampled and decoded currently, and the PRE signal is one system sampling cycle before the PDE signal. The PRE signal is initially sampled as a high-level pre-sampling command address CA1 (PRE), and is further sampled by the odd clock signal CLK_OT as a low-level second command address sampling signal ODD_CA1_OB.

[0098] In addition, the initial chip select signal CS_n is at a valid level (low level) before a system sampling cycle, that is, the initial chip select signal CS_n corresponds to the PRE signal at a low level. Thus, before a system sampling cycle, the initial chip select signal CS_n is sampled by the odd clock signal CLK_OT as the second chip select sampling signal ODD_CS_OT at a high level.

[0099] Furthermore, the second command address sampling signal ODD_CA1_OB is at a low level, and the second chip selection sampling signal ODD_CS_OT is at a high level. After the NAND operation of the second NAND gate Nand2, a high-level second control signal is obtained (i.e., point A is at a high level). In this way, the PRE signal representing the previous system sampling cycle is a command of the 1T CMD mode, and thus the PDE signal of the current system sampling cycle is a new command and can be decoded normally.

[0100] In the embodiment of the present disclosure, combining 10 and Fig.11 If the initial chip select signal CS_n of the previous system sampling cycle is high, or the initial chip select signal CS_n is low and the initial command address signal CA is high in the previous system sampling cycle, then it will be recognized that no instruction operation was performed in the previous system sampling cycle, or that the command of the 1T CMD mode was being performed. In this way, the current system sampling cycle can be decoded by normal instructions, thereby avoiding two consecutive 1T CMD mode commands from being mistaken for the second cycle of the on-chip termination command NT_ODT_CMD.

[0101] In some embodiments of the present disclosure, reference Fig.10 The chip select signal sampling circuit 30 includes: a second D flip-flop DFF2, a third inverter Inv3 and a fourth inverter Inv4. The data input terminal D of the second D flip-flop DFF2 receives the initial chip select signal CS_n, and the clock input terminal of the second D flip-flop DFF2 receives the first frequency-divided clock signal CLK_ET. The in-phase output terminal Q of the second D flip-flop DFF2 is connected to the input terminal of the third inverter Inv3. The output terminal of the third inverter Inv3 is connected to the input terminal of the fourth inverter Inv4. The fourth inverter Inv4 outputs the current chip select sampling signal CS.

[0102] In the embodiments of the present disclosure, reference Fig.10 The second D flip-flop DFF2 samples the initial chip select signal CS_n under the triggering of the first frequency-divided clock signal CLK_ET (ie, an even clock signal), and obtains the current chip select sampling signal CS after passing through two stages of inverters Inv3 and Inv4.

[0103] In some embodiments of the present disclosure, reference Fig.10The logic control circuit 40 includes: an OR gate Or1 and a third NAND gate Nand3. The first input end of the OR gate Or1 is connected to the output end of the first control signal generating circuit 10, and the second input end of the OR gate Or1 is connected to the output end of the second control signal generating circuit 20. The output end of the OR gate Or1 is connected to the first input end of the third NAND gate Nand3, the second input end of the third NAND gate Nand3 receives the current chip selection sampling signal CS, and the output end of the third NAND gate Nand3 serves as the output end of the logic control circuit 40.

[0104] In the embodiments of the present disclosure, reference Fig.10 The two input ends of the OR gate Or1 receive the first control signal CS_EVEN_PP_T and the second control signal CS_EVEN_P_T respectively, and perform a comprehensive logic judgment, and the judgment result is represented by the level of point B. Since the first control signal CS_EVEN_PP_T is obtained from the first two system sampling cycles, and the second control signal CS_EVEN_P_T is obtained from the previous system sampling cycle, the judgment result output by the OR gate Or1 is a logic check that combines the signals in the previous and first two system sampling cycles.

[0105] Furthermore, the third NAND gate Nand3 outputs or shields the current chip selection sampling signal CS (ie, the level at point C) according to the judgment result output by the OR gate Or1 (ie, the level at point B). Fig.11 or Fig.12 When the level at point B is high, the output at point D is determined by the level at point C, that is, when the level at point B is high, the low level at point C (i.e., the current chip select sampling signal CS sampled as a valid level) is output as a high level at point D. In this way, the valid level of the current chip select sampling signal CS is output, and the current system sampling cycle can be decoded normally.

[0106] It is understandable that, since various command address signals are collected on the command address bus, various decoding errors may occur. In the disclosed embodiment, the first control signal generating circuit obtains the first control signal according to the levels of the chip select signal and the command address signal in the first two system sampling cycles; the second control signal generating circuit obtains the second control signal according to the levels of the chip select signal and the command address signal in the previous system sampling cycle; further, the logic control circuit controls the output of the current chip select sampling signal according to the first control signal and the second control signal, that is, controls whether the chip select signal acts on the current command address signal. In this way, by using the signals in the previous and first two system sampling cycles to perform logic checks, it is possible to ensure that the command address signal in the current system sampling cycle is decoded normally, thus avoiding decoding errors.

[0107] In some embodiments of the present disclosure, reference Fig.13 The command address signal sampling circuit 50 includes: a third D flip-flop DFF3 and a fourth D flip-flop DFF4. The data input terminal D of the third D flip-flop DFF3 receives the initial command address signal CA, the clock input terminal of the third D flip-flop DFF3 receives the first frequency-divided clock signal CLK_ET, and the third D flip-flop DFF3 outputs the first command address sampling signal EVEN_CA1_OB. The data input terminal D of the fourth D flip-flop DFF4 receives the initial command address signal CA, the clock input terminal of the fourth D flip-flop DFF4 receives the second frequency-divided clock signal CLK_OT, and the fourth D flip-flop DFF4 outputs the second command address sampling signal ODD_CA1_OB.

[0108] In the present disclosure, in combination Fig.12 and Fig.13 , the third D flip-flop DFF3 samples the PRE signal of the first two system sampling cycles in the initial command address signal CA under the triggering of the first frequency-divided clock signal CLK_ET (i.e., the even clock signal), and outputs the first command address sampling signal EVEN_CA1_OB. The first command address sampling signal EVEN_CA1_OB is output at the inverting output terminal (i.e., the non-Q terminal) of the third D flip-flop DFF3, therefore, Fig.12 The first command address sampling signal EVEN_CA1_OB shown in FIG. 1 is sampled as a low level.

[0109] Accordingly, combined Fig.11 and Fig.13 , the fourth D flip-flop DFF4 samples the PRE signal of the previous system sampling cycle in the initial command address signal CA under the triggering of the second frequency-divided clock signal CLK_OT (i.e., the odd clock signal), and outputs the second command address sampling signal ODD_CA1_OB. The second command address sampling signal ODD_CA1_OB is output to the inverting output terminal (i.e., the non-Q terminal) of the fourth D flip-flop DFF4, therefore, Fig.11 The second command address sampling signal ODD_CA1_OB shown in FIG. 1 is sampled as a low level.

[0110] The embodiment of the present disclosure also provides a chip selection signal processing circuit, such as Fig.14 As shown, the signal processing circuit 70 includes: a chip select signal control circuit 80 and a decoding circuit 60, wherein the chip select signal control circuit 80 includes the technical features described in the above embodiments.

[0111] refer to Fig.14 The decoding circuit 60 is connected to the chip selection signal control circuit 80. The decoding circuit 60 is configured to receive the current chip selection sampling signal CS, decode the current chip selection sampling signal CS and output it, that is, output the decoded chip selection sampling signal CS1.

[0112] The present disclosure also provides a memory device, such as Fig.15 As shown, the memory 90 includes: a chip select signal processing circuit 70, wherein the chip select signal processing circuit 70 includes the technical features described in the above embodiments.

[0113] In some embodiments of the present disclosure, reference Fig.15 , memory 90 is DDR5 DRAM.

[0114] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0115] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0116] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A chip select signal control circuit, characterized in that: The chip select signal control circuit comprises: A first control signal generating circuit is configured to receive a first chip select sampling signal and a first command address sampling signal, and output a first control signal of a first level when the levels of the first chip select sampling signal and the first command address sampling signal meet a first preset rule, otherwise, output a first control signal of a second level; wherein the first chip select sampling signal is obtained by sampling the initial chip select signal during the first two system sampling cycles, and the first command address sampling signal is obtained by sampling the initial command address signal during the first two system sampling cycles; The second control signal generating circuit is configured to receive a second chip select sampling signal and a second command address sampling signal, and output a second control signal of a first level when the levels of the second chip select sampling signal and the second command address sampling signal meet a second preset rule, otherwise, output a second control signal of a second level; wherein the second chip select sampling signal is obtained by sampling the initial chip select signal in a previous system sampling cycle, and the second command address sampling signal is obtained by sampling the initial command address signal in a previous system sampling cycle; a chip select signal sampling circuit, configured to receive the initial chip select signal and a first frequency-divided clock signal, sample the initial chip select signal according to the first frequency-divided clock signal, and output a current chip select sampling signal; A logic control circuit is connected to the first control signal generating circuit, the second control signal generating circuit and the chip select signal sampling circuit, and is configured to receive the first control signal, the second control signal and the current chip select sampling signal, and output the current chip select sampling signal when the first control signal and the second control signal meet a third preset rule.

2. The chip select signal control circuit according to claim 1, characterized in that: The second control signal generating circuit is further configured to receive the first control signal after the first delay and a second frequency-divided clock signal, sample the first control signal after the first delay according to the second frequency-divided clock signal, and output the sample as the second control signal.

3. The chip select signal control circuit according to claim 2, characterized in that: The first control signal generating circuit is further configured to, in the first working mode, output the first control signal after applying a second delay; or, in the second working mode, output the first control signal.

4. The chip select signal control circuit according to claim 1, characterized in that: The chip select signal control circuit also includes: The command address signal sampling circuit is configured to receive an initial command address signal, the first divided clock signal and a second divided clock signal, and to sample the initial command address signal into the first command address sampling signal according to the first divided clock signal; and to sample the initial command address signal into the second command address sampling signal according to the second divided clock signal.

5. The chip select signal control circuit according to claim 3, characterized in that: The first control signal generating circuit comprises: a first NAND gate, a first inverter and a second inverter; The input end of the first NAND gate receives the first chip selection sampling signal and the first command address sampling signal respectively; the output end of the first NAND gate is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter; The first NAND gate outputs the first control signal; the first inverter outputs the first control signal after the first delay; and the second inverter outputs the first control signal after the second delay.

6. The chip select signal control circuit according to claim 3 or 5, characterized in that: The first control signal generating circuit further includes: a first data selector; The first input end of the first data selector receives the first control signal after the second delay; the second input end of the first data selector receives the first control signal; and the control end of the first data selector receives an operating mode enable signal.

7. The chip select signal control circuit according to claim 6, characterized in that: The first control signal generating circuit further includes: a first level trigger; The data input end of the first level trigger is connected to the output end of the first data selector; the clock input end of the first level trigger receives the first frequency-divided clock signal; and the output end of the first level trigger serves as the output end of the first control signal generating circuit.

8. The chip select signal control circuit according to claim 2 or 3, characterized in that: The second control signal generating circuit comprises: a second NAND gate, a first D flip-flop and a second data selector; The input end of the second NAND gate receives the second chip selection sampling signal and the second command address sampling signal respectively; the output end of the second NAND gate is connected to the first input end of the second data selector; The data input terminal of the first D flip-flop receives the first control signal after the first delay, and the clock input terminal of the first D flip-flop receives the second frequency-divided clock signal; the in-phase output terminal of the first D flip-flop is connected to the second input terminal of the second data selector; The control terminal of the second data selector receives an operation mode enable signal.

9. The chip select signal control circuit according to claim 8, characterized in that: The second control signal generating circuit further includes: a second level trigger; The data input end of the second level trigger is connected to the output end of the second data selector; the clock input end of the second level trigger receives the first frequency-divided clock signal; and the output end of the second level trigger serves as the output end of the second control signal generating circuit.

10. The chip select signal control circuit according to any one of claims 1 to 4, characterized in that: The chip selection signal sampling circuit comprises: a second D flip-flop, a third inverter and a fourth inverter; The data input terminal of the second D flip-flop receives the initial chip select signal, and the clock input terminal of the second D flip-flop receives the first frequency-divided clock signal; The in-phase output terminal of the second D flip-flop is connected to the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the fourth inverter; The fourth inverter outputs the current chip selection sampling signal.

11. The chip select signal control circuit according to any one of claims 1 to 4, characterized in that: The logic control circuit comprises: an OR gate and a third NAND gate; The first input end of the OR gate is connected to the output end of the first control signal generating circuit; the second input end of the OR gate is connected to the output end of the second control signal generating circuit; The output end of the OR gate is connected to the first input end of the third NAND gate; the second input end of the third NAND gate receives the current chip selection sampling signal; the output end of the third NAND gate serves as the output end of the logic control circuit.

12. The chip select signal control circuit according to claim 4, characterized in that: The command address signal sampling circuit comprises: a third D flip-flop and a fourth D flip-flop; The data input terminal of the third D flip-flop receives the initial command address signal, the clock input terminal of the third D flip-flop receives the first frequency-divided clock signal, and the third D flip-flop outputs the first command address sampling signal; The data input terminal of the fourth D flip-flop receives the initial command address signal, the clock input terminal of the fourth D flip-flop receives the second frequency-divided clock signal, and the fourth D flip-flop outputs the second command address sampling signal.

13. A chip select signal processing circuit, characterized in that: include: The chip select signal control circuit according to any one of claims 1 to 12, and a decoding circuit; The decoding circuit is connected to the chip selection signal control circuit, and is configured to receive a current chip selection sampling signal, decode the current chip selection sampling signal, and then output it.

14. A memory, characterized in that: The memory includes the chip select signal processing circuit as claimed in claim 13.

15. The memory according to claim 14, characterized in that: The memory is DDR5 DRAM.

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