Memory and storage system

Abstract

The invention relates to the field of semiconductor circuit design, in particular to a memory and a memory system, the memory comprising: n memory blocks, n being a positive integer; the activation control circuit is configured to receive the address signal and the activation signal, count the activation signal corresponding to each storage block based on the address signal, and generate and output a row hammer refreshing indication signal corresponding to the storage block when the number of the activation signal corresponding to any storage block meets an activation preset value; wherein the address signal indicates the memory block which is currently subjected to the activation operation; the row hammer refresh control circuit is coupled with the activation control circuit and is configured to receive a refresh signal and a row hammer refresh indication signal, and generate a target storage block row hammer refresh signal corresponding to the storage block based on the refresh signal and the row hammer refresh indication signal, the target storage block row hammer refresh signal is used for indicating the corresponding storage block to execute a row hammer refresh operation so as to reduce the power consumption of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a memory and a storage system. Background Art

[0002] Dynamic Random Access Memory (DRAM) stores data through a structure (1T1C) of one transistor connected to a storage area, where the transistor is controlled by a word line (WL). When the WL is turned on, the charge in the storage area is shared with the charge of the bit line (BL) to read data from the target storage area or write data to the target storage area.

[0003] However, frequent activation of word lines will lead to charge loss in adjacent storage areas, which may cause errors in the data stored in the storage area, namely the Row Hammer phenomenon of the memory. Row Hammer is a vulnerability existing in DRAM devices. Its main manifestation is that when an attacker hammers certain rows of memory, it will cause the memory cells in other rows to flip accordingly.

[0004] As DRAM manufacturing becomes more precise, components become physically smaller. It is very difficult to integrate more memory capacity on a chip without electromagnetic interference between memory cells. This makes it possible for reading and writing to a single area of ​​memory to interfere with adjacent areas, resulting in the Row Hammer phenomenon.

[0005] The idea of ​​Row Hammer protection is to monitor the number and address of ACTs, find out potential attacked addresses, and then refresh the two rows near the attacked addresses to maintain data integrity.

[0006] However, the Row Hammer protection strategy operates on all storage blocks (banks / bank groups) together, that is, when one bank is attacked, all banks perform Row Hammer protection together, which greatly increases the power consumption of the memory. Summary of the invention

[0007] The embodiments of the present disclosure provide a memory and a storage system to optimize the Row Hammer protection strategy of the memory, thereby reducing the power consumption of the memory.

[0008] An embodiment of the present disclosure provides a memory, comprising: n memory blocks, where n is a positive integer; an activation control circuit, configured to receive an address signal and an activation signal, count the activation signals corresponding to each memory block based on the address signal, and generate and output a row hammer refresh indication signal corresponding to the memory block when the number of activation signals corresponding to any memory block meets an activation preset value; wherein the address signal indicates the memory block currently being activated; a row hammer refresh control circuit, coupled to the activation control circuit, configured to receive a refresh signal and a row hammer refresh indication signal, and generate a target memory block row hammer refresh signal corresponding to the memory block based on the refresh signal and the row hammer refresh indication signal, wherein the target memory block row hammer refresh signal is used to instruct the corresponding memory block to perform a row hammer refresh operation.

[0009] The row hammer refresh indication signal is used to indicate a storage block whose corresponding number of activation signals satisfies a preset activation value, i.e., a storage block that may generate a Row Hammer phenomenon; the row hammer refresh control circuit generates a row hammer refresh signal for a target storage block based on the refresh signal and the row hammer refresh indication signal, i.e., the storage block needs to be protected against Row Hammer and the number of activation signals corresponding to the storage block satisfies a preset activation value, and generates a row hammer refresh signal for the target storage block of the storage block, so as to perform a supplementary refresh on only the target storage block during the supplementary refresh process, i.e., the Row Hammer protection strategy in the disclosed embodiment is to perform Row Hammer protection only on storage blocks that may generate a Row Hammer phenomenon, and avoid the supplementary refresh process for storage blocks that will not generate a Row Hammer phenomenon, thereby reducing the power consumption of the memory.

[0010] Optionally, the activation control circuit includes: n activation control modules, the activation control modules corresponding to the storage blocks one by one; an identification module, which receives an address signal and an activation signal and is configured to generate a target storage block activation signal corresponding to the address signal based on the address signal and the activation signal, the target storage block activation signal being used to drive the activation control module corresponding to the storage block corresponding to the address signal; each activation control module is configured to count based on the corresponding target storage block activation signal to generate an activation count value, and when the activation count value meets the activation preset value, generate and output a row hammer refresh indication signal corresponding to the storage block.

[0011] Optionally, each activation control module includes: a counting unit, configured to count based on the corresponding target storage block activation signal to generate an activation count value; a comparison unit, coupled to the counting unit and receiving an activation preset value, configured to generate and output a row hammer refresh indication signal corresponding to the storage block when the activation count value meets the activation preset value.

[0012] Optionally, each activation control module includes: a cascade of k levels of D flip-flops, the input end of each level of the D flip-flop is connected to the inverting output end, k is an integer greater than 1; the clock end of the first level of the D flip-flop is used to receive the target storage block activation signal, the clock end of the j-th level of the D flip-flop is connected to the inverting output end of the j-1-th level of the D flip-flop, 2≤j≤k, and the output end of the last level of the D flip-flop is used to output a row hammer refresh indication signal.

[0013] Optionally, the activation control module is arranged in a corresponding storage block.

[0014] Optionally, the row hammer refresh control circuit includes: a first control module, coupled to the activation control circuit, configured to generate a row hammer refresh enable signal based on any row hammer refresh indication signal; a second control module, coupled to the first control module, configured to generate a row hammer refresh signal based on the refresh signal and the row hammer refresh enable signal; n processing modules, the n processing modules corresponding one-to-one to n storage blocks, each processing module coupled to the second control module and the corresponding activation control circuit, configured to generate and output a target storage block row hammer refresh signal corresponding to the storage block based on the row hammer refresh signal and the row hammer refresh indication signal corresponding to the storage block.

[0015] Optionally, the first control module includes: an OR logic circuit including n input terminals, the n input terminals respectively corresponding to receiving n row hammer refresh indication signals corresponding to n storage blocks, and an output terminal for outputting a row hammer refresh enable signal.

[0016] Optionally, the first control module includes: an XOR logic circuit including n input terminals, the n input terminals respectively corresponding to receiving n row hammer refresh indication signals corresponding to n storage blocks, and an output terminal for outputting a row hammer refresh enable signal.

[0017] Optionally, the processing module includes: an AND logic circuit, a first input end for receiving a row hammer refresh signal, a second input end for receiving a row hammer refresh indication signal corresponding to a corresponding storage block, and an output end for outputting a row hammer refresh signal of a target storage block.

[0018] Optionally, the processing module is arranged in a corresponding storage block.

[0019] Optionally, the memory further includes: a decoding circuit for receiving and decoding a control command issued by the memory controller to generate at least one of a refresh signal, an activation signal and an address signal.

[0020] Another embodiment of the present disclosure further provides a storage system, including: a storage controller and a memory, the memory responds to a control command issued by the storage controller, and the memory is based on the memory structure provided by the above embodiment to optimize the memory's Row Hammer protection strategy, thereby reducing the memory's power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of the structure of an activation control circuit provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the structure of another activation control module provided by an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of the structure of a row hammer refresh control circuit provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of the principle of a first control module and a processing module provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of the structure of a memory including a decoding circuit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] As can be seen from the background technology, the idea of ​​Row Hammer protection is to monitor the number and address of ACTs, find out potential attacked addresses, and then refresh the two rows near the attacked addresses to maintain data integrity.

[0029] Specifically, the number and address of the activation signal (Action, ACT) received by the memory are monitored. When the number of ACTs received by the same address reaches a preset value, it indicates that the current address may cause the Row Hammer phenomenon. The adjacent rows of the current address are refreshed to avoid the occurrence of the Row Hammer phenomenon.

[0030] For the above-mentioned Row Hammer protection strategy, since the number and address of the activation signal (Action, ACT) are monitored without distinguishing the specific storage block (bank / bank group) information, when a storage block may produce the Row Hammer phenomenon, the current addresses of all storage blocks will be supplemented and refreshed. Such an operation is a redundant step for the storage blocks that will not produce the Row Hammer phenomenon, thereby increasing the power consumption of the memory.

[0031] In addition, using the number of ACTs as a standard for starting the Row Hammer protection strategy will cause the Row Hammer protection strategy to be started too frequently, which increases the time for the memory to perform supplementary refresh, that is, increases the refresh time of the memory, resulting in a decrease in the refresh efficiency of the memory.

[0032] An embodiment of the present disclosure provides a memory to optimize the Row Hammer protection strategy of the memory, thereby reducing the power consumption of the memory.

[0033] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0034] Figure 1 A schematic diagram of the structure of the memory provided in this embodiment, Figure 2 A schematic diagram of the structure of the activation control circuit provided in this embodiment, Figure 3 This is a schematic diagram of the structure of another activation control module provided in this embodiment. Figure 4 A schematic diagram of the structure of the row hammer refresh control circuit provided in this embodiment, Figure 5 A schematic diagram of the principle of the first control module and the processing module provided in this embodiment, Figure 6 The schematic diagram of the structure of the memory including the decoding circuit provided in the present embodiment is as follows. The memory provided in the present embodiment is described in detail in conjunction with the accompanying drawings, as follows:

[0035] refer to Figure 1 , the memory 100 comprises:

[0036] n storage blocks 101, n is a positive integer; it should be noted that, in this embodiment, each storage block 101 may refer to a single storage block bank in an actual setting, or a storage block group bank group. For each storage block 101, the storage block 101 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of storage cells, wherein corresponding storage cells are set at the intersections of the word lines WL and the bit lines BL, that is, each storage block corresponds to a word line WL and a bit line BL, and the memory selects the corresponding word line and bit line based on the corresponding address signal, thereby selecting a target storage cell from a large number of storage cells.

[0037] It should be noted that, in the following description, this embodiment uses the memory 100 corresponding to n=4 memory blocks 101 (respectively memory block a, memory block b, memory block c and memory block d) as an example to help those skilled in the art understand the Row Hammer protection strategy provided by the present disclosure, but does not constitute a limitation on this embodiment. In specific applications, the value of the specific memory block 101 is set based on the number of memory blocks in the applicable memory.

[0038] The activation control circuit 102 is configured to receive an address signal ADD and an activation signal ACT, and count the activation signal ACT corresponding to each storage block 101 based on the address signal ADD, and when the number of activation signals corresponding to any storage block 101 meets the activation preset value, generate and output a row hammer refresh indication signal Flag corresponding to the storage block 101, wherein the address signal ADD is used to indicate the storage block 101 on which the activation operation is currently being performed.

[0039] It should be noted that, since the present embodiment is mainly used to improve the Row Hammer protection strategy, the time for the activation control circuit to count the activation signal ACT corresponding to each storage block 101 based on the address signal ADD is within the interval between two adjacent refresh commands REF, thereby realizing the regulation of the supplementary refresh target in the next refresh command REF.

[0040] The row hammer refresh control circuit 103 is coupled to the activation control circuit 102, and is configured to receive a refresh signal REF and a row hammer refresh indication signal Flag, and generate a target storage block row hammer refresh signal Ref corresponding to the storage block 101 based on the refresh signal REF and the row hammer refresh indication signal Flag, and the target storage block row hammer refresh signal Ref is used to instruct the corresponding storage block 101 to perform a row hammer refresh operation.

[0041] It should be noted that the refresh signal REF mentioned in this embodiment is used to instruct the memory 100 to perform a supplementary refresh function, that is, to instruct the memory 100 to perform Row Hammer protection. As for the normal refresh function of the memory 100, it is not closely related to the core content of the present disclosure and is not described in detail in this embodiment.

[0042] For the activation control circuit 102, specifically, the count value of counting the activation signal ACT corresponding to storage block a is count a, the count value of counting the activation signal ACT corresponding to storage block b is count b, the count value of counting the activation signal ACT corresponding to storage block c is count c, and the count value of counting the activation signal ACT corresponding to storage block d is count d.

[0043] The count a is compared with the activation preset value a. When the count a is greater than or equal to the activation preset value a, a row hammer refresh indication signal Flag corresponding to the storage block a is generated and output. <1> ; Count b is compared with the activation preset value b. When count b is greater than or equal to the activation preset value b, a row hammer refresh indication signal Flag corresponding to the storage block b is generated and output <2> ; Count c is compared with the activation preset value c. When count c is greater than or equal to the activation preset value c, a row hammer refresh indication signal Flag corresponding to the storage block c is generated and output <3> ; Count d is compared with the activation preset value d. When the count d is greater than or equal to the activation preset value d, a row hammer refresh indication signal Flag corresponding to the storage block d is generated and output <4> ;Flag <1> 、Flag <2> 、Flag <3> and Flag <4> Together they form Flag<4:1>, i.e. Flag <n:1>.

[0044] In one example, if the row hammer refresh indication signal Flag <n:1>High level is valid, when Flag <n:1>= "0100", it proves that the count c corresponding to the storage block c is greater than or equal to the activation preset value c; when Flag <n:1>= "0011", it proves that the count a corresponding to the storage block a is greater than or equal to the activation preset value a and the count b corresponding to the storage block b is greater than or equal to the activation preset value b. <n:1>The low level is valid. When Flag <n:1>= "0111", it proves that the count d corresponding to the storage block d is greater than or equal to the activation preset value d; when Flag <n:1>= "1001", it proves that the count b corresponding to the storage block b is greater than or equal to the activation preset value b and the count c corresponding to the storage block c is greater than or equal to the activation preset value c. In addition, in the subsequent description of this disclosure, the row hammer refresh indication signal Flag is used. <n:1>The high level is described as effective to help those skilled in the art understand the Row Hammer protection strategy provided by the present disclosure, and does not constitute a limitation on the present embodiment.

[0045] When the row hammer refresh control circuit 103 receives the refresh signal, it will refresh the row hammer based on the valid row hammer refresh indication signal Flag. <n:1>Generate a valid target memory block row hammer refresh signal accordingly; specifically, if the target memory block row hammer refresh signal Ref <n:1>High level is valid, when Flag <n:1>= "0100", then the generated Ref <n:1>= "0100", target memory block row hammer refresh signal Ref <n:1>Used to instruct storage block c to perform supplementary refresh; when Flag <n:1>= "0011", then the generated Ref <n:1>= "0011", target memory block row hammer refresh signal Ref <n:1>It is used to instruct memory block a and memory block b to perform supplementary refresh. If the target memory block row hammer refresh signal Ref <n:1>The low level is valid. When Flag <n:1>= "0100", then the generated Ref <n:1>= "1011", target memory block row hammer refresh signal Ref <n:1>Used to instruct storage block c to perform supplementary refresh; when Flag <n:1>= "0011", then the generated Ref <n:1>= "1100", target memory block row hammer refresh signal Ref <n:1>Used to instruct storage block a and storage block b to perform supplementary refresh.

[0046] In summary, the row hammer refresh indication signal Flag is used to indicate the storage block 101 whose number of activation signals corresponding to the storage block 101 satisfies the activation preset value, i.e., the storage block 101 that may produce the Row Hammer phenomenon; the row hammer refresh control circuit 103 generates the target storage block row hammer refresh signal Ref based on the refresh signal REF and the row hammer refresh indication signal Flag, i.e., the memory needs to perform Row Hammer protection, and the number of activation signals corresponding to the storage block 101 satisfies the activation preset value of the storage block 101, and generates the target storage block row hammer refresh signal Ref for the storage block 101, so as to implement supplementary refresh only for the target storage block during the supplementary refresh process, i.e., the Row Hammer protection strategy in the embodiment of the present disclosure is to perform Row Hammer protection only for the storage block 101 that may produce the Row Hammer phenomenon, and avoid the supplementary refresh process for the storage block that will not produce the Row Hammer phenomenon, thereby reducing the power consumption of the memory.

[0047] It should be noted that for Figure 1 In the circuit shown, the activation control circuit 102 is also used to provide a storage body control signal for the storage block 101. The storage body control signal is used for the storage block 101 to implement a normal storage function. The storage function of the storage block 101 is irrelevant to the core content of the present disclosure and is not described in detail in this embodiment.

[0048] In some embodiments, reference Figure 2 , activation control circuit 102, including:

[0049] There are n activation control modules 201, and the activation control modules 201 correspond to the storage blocks 101 one by one; that is, storage block a corresponds to activation control module a, storage block b corresponds to activation control module b, storage block c corresponds to activation control module c, and storage block d corresponds to activation control module d.

[0050] The identification module 202 receives the address signal ADD and the activation signal ACT, and is configured to generate a target storage block activation signal corresponding to the address signal ADD based on the address signal ADD and the activation signal ACT, and the target storage block activation signal is used to drive the activation control module 201 corresponding to the storage block 101 corresponding to the address signal ADD.

[0051] Specifically, when the address signal ADD indicates an address in storage block a, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module a; when the address signal ADD indicates an address in storage block b, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module b; when the address signal ADD indicates an address in storage block c, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module c; when the address signal ADD indicates an address in storage block d, the target storage block activation signal generated by the identification module 202 is used to drive the activation control module d.

[0052] In some embodiments, the target memory block activation signal is also used to drive other control logic circuits of the corresponding memory block to generate other control signals for controlling the corresponding memory block to perform an activation operation.

[0053] Each activation control module 201 is configured to count based on the corresponding target memory block activation signal to generate an activation count value, and to generate and output a row hammer refresh indication signal Flag corresponding to the memory block 101 when the activation count value satisfies an activation preset value.

[0054] For activating the row hammer refresh indication signal Flag <c>, where c is any value greater than or equal to 1 and less than or equal to n, and the size of the specific value corresponds to the output of the activation control module 201. Specifically, the activation control module 201 is used to count the target storage block activation signal corresponding to the storage block a to generate the activation count value a, and when the activation preset value a is greater than or equal to the preset value a, the row hammer refresh indication signal Flag corresponding to the storage block a is generated. <1> The activation control module 201 is used to count the target storage block activation signal corresponding to the storage block b to generate an activation count value b, and when the activation preset value b is greater than or equal to the preset value b, a row hammer refresh indication signal Flag corresponding to the storage block b is generated. <2> The activation control module 201 is used to count the target storage block activation signal corresponding to the storage block c to generate an activation count value c, and when the activation preset value c is greater than or equal to the preset value c, a row hammer refresh indication signal Flag corresponding to the storage block c is generated; <3> The activation control module 201 is used to count the target storage block activation signal corresponding to the storage block d to generate an activation count value d, and when the activation preset value d is greater than or equal to the preset value d, a row hammer refresh indication signal Flag corresponding to the storage block d is generated. <4> .

[0055] For activating the control module 201, in one example, continue to refer to Figure 2 Each activation control module 201 includes: a counting unit 210, configured to count based on the corresponding target storage block activation signal to generate an activation count value; a comparison unit 220, coupled to the counting unit 210 and receiving the activation preset value, configured to generate and output a row hammer refresh indication signal Flag corresponding to the storage block 101 when the activation count value meets the activation preset value. <c>.

[0056] For the comparison unit 220, in some embodiments, the activation preset value can be set in the comparison unit 220 in the form of a fixed value; in other embodiments, the activation preset value can be configured through a mode register, and can also be adjusted in the test mode of the memory, and different activation preset values ​​can be set for each storage block 101 according to the performance of each storage block 101, such as the number of weak addresses.

[0057] In another example, refer to Figure 3 Each activation control module 201 includes: a cascade of k-level D flip-flops 230, the input terminal D of each D flip-flop 230 is connected to the inverting output terminal Q-, k is an integer greater than 1; the clock terminal Ck of the first-level D flip-flop 230 is used to receive the target storage block activation signal, the clock terminal Ck of the j-th level D flip-flop 230 is connected to the inverting output terminal Q- of the j-1-th level D flip-flop 230, 2≤j≤k, and the output terminal Q of the last level D flip-flop 230 is used to output the row hammer refresh indication signal Flag <c>.

[0058] Specifically, when the first-stage D flip-flop 230 receives the target memory block activation signal, the data Q outputted from the output terminal <0> Inverting, the corresponding inverting output terminal output data QN <0> Inverting, while QN <0> As the input of the clock terminal Ck of the second stage D flip-flop 230, when QN <0> The output terminal of the second-stage D flip-flop 230 outputs the data Q <1> Inverting, the corresponding inverting output terminal output data QN <1> Inverting... and QN <k-1>As the input of the clock terminal Ck of the k-th stage D flip-flop 230, when QN <k-1>Valid, the data Flag outputted from the output terminal of the k-th D flip-flop 230 <c>Inverting; In summary, every time 2 k-1 After the target storage block is activated, the row hammer refresh indication signal Flag <c>Inverted, that is, when the activation control module 201 is initially invalid, the row hammer refresh indication signal Flag <c>, and the activation control module 201 receives 2 k-1 After the target storage block activation signal is generated, the row hammer refresh indication signal Flag generated by the activation control module 201 is activated. <c>Flipped to valid, it can be seen that by setting a specific value of k, the size of the activation count value can be adjusted based on the cascaded D flip-flop 230.

[0059] In some embodiments, k can be set in the form of a fixed value, that is, the number of cascaded D flip-flops in the activation control module 201 is fixed, and the activation preset value is fixedly set; in other embodiments, the number k of cascaded D flip-flops in the activation control module 201 can be configured through a mode register, and can also be adjusted in the test mode of the memory, and different k values ​​can be set for each storage block 101 according to the performance of each storage block 101, such as the number of weak addresses.

[0060] It should be noted that, in other embodiments, the input terminal D of the D flip-flop connected to the inverting output terminal Q- can also be set to that the output terminal Q is connected to the input terminal of an inverter, and the output terminal of the inverter is connected to the input terminal D; accordingly, the input terminal D of the next-level D flip-flop connected to the inverting output terminal Q- of the previous-level D flip-flop can be set to that the input terminal D of the next-level D flip-flop is connected to the output terminal of the inverter.

[0061] It should be noted that, in some embodiments, the reset terminal RN of each stage of the D flip-flop is also used to receive a reset signal, so as to reset the row hammer refresh indication signal Flag corresponding to the activation control module 201 in the initial power-on stage of the memory. <c>, thereby preventing erroneous counting of the activation control module 201.

[0062] In some embodiments, the activation control module 201 is set in the corresponding storage block 101, that is, the activation control module a corresponding to storage block a is set in storage block a, the activation control module b corresponding to storage block b is set in storage block b, the activation control module c corresponding to storage block c is set in storage block c, and the activation control module d corresponding to storage block d is set in storage block d, so as to simplify the length of the data transmission line between the n activation control modules 201 and the n storage blocks 101.

[0063] In some embodiments, reference Figure 4 , the row hammer refresh control circuit 103 comprises:

[0064] The first control module 301 is coupled to the activation control circuit 102 and is configured to refresh the indication signal Flag based on any row hammer. <n:1>Generate a row hammer refresh enable signal; specifically, when the row hammer refresh indication signal Flag <1> 、Flag <2> 、Flag <3> and Flag <4> If any one of the signals is a valid signal, the first control module 301 will generate a row hammer refresh enable signal, which is used to indicate that there is a storage block 101 in the memory 100 that has been opened a number of times greater than a preset value.

[0065] The second control module 302 is coupled to the first control module 301, and is configured to generate a row hammer refresh signal based on the refresh signal REF and the row hammer refresh enable signal; specifically, when the refresh signal REF and the row hammer refresh enable signal are both valid signals, the second control module 302 generates a row hammer refresh signal, and the row hammer refresh signal is used to instruct the memory 100 to perform a supplementary refresh, that is, to instruct the memory 100 to perform Row Hammer protection.

[0066] n processing modules 303, the n processing modules 303 correspond to the n storage blocks 101 one by one, each processing module 303 is coupled to the second control module 302 and the corresponding activation control circuit 102, and is configured to refresh the row hammer refresh signal and the row hammer refresh indication signal Flag corresponding to the storage block 101 based on the row hammer refresh signal and the row hammer refresh indication signal Flag corresponding to the storage block 101 <c>, generates and outputs the target memory block row hammer refresh signal Ref corresponding to the memory block <n:1>.

[0067] Specifically, when the row hammer refresh signal and the row hammer refresh indication signal Flag <n:1>is a valid signal, and the processing module a is based on the row hammer refresh signal and the row hammer refresh indication signal Flag corresponding to the storage block a. <1> Generate a target memory block row hammer refresh signal Ref corresponding to memory block a <1> , the target memory block row hammer refresh signal Ref <1> It is used to instruct storage block a to perform supplementary refresh in the next refresh process, that is, to instruct storage block a to perform Row Hammer protection in the next refresh process; processing module b is based on the row hammer refresh signal and the row hammer refresh indication signal Flag corresponding to storage block b. <2> Generate a target memory block row hammer refresh signal Ref corresponding to memory block b <2> , the target memory block row hammer refresh signal Ref <2> It is used to instruct storage block b to perform supplementary refresh in the next refresh process, that is, to instruct storage block b to perform Row Hammer protection in the next refresh process; processing module c is based on the row hammer refresh signal and the row hammer refresh indication signal Flag corresponding to storage block c. <3> Generate a target memory block row hammer refresh signal Ref corresponding to memory block c <3> , the target memory block row hammer refresh signal Ref <3> It is used to instruct the storage block c to perform supplementary refresh in the next refresh process, that is, to instruct the storage block c to perform Row Hammer protection in the next refresh process; the processing module d is based on the row hammer refresh signal and the row hammer refresh indication signal Flag corresponding to the storage block d. <4> Generate a target memory block row hammer refresh signal Ref corresponding to memory block d <4> , the target memory block row hammer refresh signal Ref <4> It is used to instruct the memory block d to perform supplementary refresh in the next refresh process, that is, to instruct the memory block d to perform Row Hammer protection in the next refresh process. <c>Generate target memory block row hammer refresh signal Ref <c>, thereby realizing supplementary refresh of the storage block 101 that needs Row Hammer protection, and shielding the refresh signal received by the storage block 101 that does not need Row Hammer protection, thereby avoiding supplementary refresh of the storage block 101 that does not need Row Hammer protection.

[0068] In some embodiments, the processing module 303 is arranged in the corresponding storage block 101, that is, the processing module a corresponding to storage block a is arranged in storage block a, the processing module b corresponding to storage block b is arranged in storage block b, the processing module c corresponding to storage block c is arranged in storage block c, and the processing module d corresponding to storage block d is arranged in storage block d, so as to simplify the length of the data transmission line between the n processing modules 303 and the n storage blocks 101.

[0069] In some embodiments, reference Figure 5 The first control module 301 includes: an OR logic circuit 401, the OR logic circuit 401 includes n input terminals, the n input terminals respectively receive n row hammer refresh indication signals Flag corresponding to n storage blocks 101, and the output terminal is used to output a row hammer refresh enable signal.

[0070] Specifically, the input terminal a receives the row hammer refresh indication signal Flag corresponding to the storage block a. <1> , the input terminal b receives the row hammer refresh indication signal Flag corresponding to the storage block b <2> , the c input terminal corresponds to receiving the row hammer refresh indication signal Flag corresponding to the storage block c <3> , the d input terminal corresponds to receiving the row hammer refresh indication signal Flag corresponding to the storage block d <4> , thereby realizing based on the OR logic circuit 401 that when there is a valid row hammer refresh indication signal Flag <n:1>When the row hammer refresh enable signal is output.

[0071] In some embodiments, the OR logic circuit 401 can be replaced by an XOR logic circuit. Accordingly, the XOR logic circuit includes n input terminals, which respectively receive n row hammer refresh indication signals Flag corresponding to n storage blocks 101, and the output terminal is used to output a row hammer refresh enable signal.

[0072] Specifically, due to the row hammer refresh indication signal Flag output by n storage blocks <n:1>At the same time, the memory does not need to perform supplementary refresh. At this time, the XOR logic circuit outputs an invalid level, which meets the requirements; the row hammer refresh indication signal Flag output by n storage blocks <n:1>If there is a valid and different valid, the target memory needs to perform a supplementary refresh. At this time, the XOR logic circuit outputs a valid level to meet the requirements.

[0073] It should be noted that, based on the foregoing, the activation control circuit 102 counts the activation count value between two refresh commands, and in this process there may be multiple storage blocks 101 whose activation count values ​​meet the activation preset value, and the resources for the supplementary refresh process in a single refresh command are limited. If the storage block 101 whose activation count value meets the activation preset value cannot be supplemented in the current refresh command, it will be postponed to the next refresh command for supplementary refresh.

[0074] In some embodiments, reference Figure 5 The processing module 303 includes an AND logic circuit 402, a first input terminal for receiving a row hammer refresh signal, and a second input terminal for receiving a row hammer refresh indication signal Flag corresponding to the corresponding storage block 101. <c>The output terminal is used to output the target storage block row hammer refresh signal Ref <c>.

[0075] Specifically, processing module a includes an AND logic circuit a, processing module b includes an AND logic circuit b, processing module c includes an AND logic circuit c, and processing module d includes an AND logic circuit d; and logic circuit a receives a row hammer refresh indication signal Flag corresponding to storage block a. <1> , and when the row hammer refresh signal and the row hammer refresh indication signal Flag <1> When valid, based on the row hammer refresh signal and the row hammer refresh indication signal Flag <1> Generate target memory block row hammer refresh signal Ref <1> ; The logic circuit b receives the row hammer refresh indication signal Flag corresponding to the storage block b <2> , and when the row hammer refresh signal and the row hammer refresh indication signal Flag <2> When valid, based on the row hammer refresh signal and the row hammer refresh indication signal Flag <2> Generate target memory block row hammer refresh signal Ref <2> ; The logic circuit c receives the row hammer refresh indication signal Flag corresponding to the storage block c <3> , and when the row hammer refresh signal and the row hammer refresh indication signal Flag <3> When valid, based on the row hammer refresh signal and the row hammer refresh indication signal Flag <3> Generate target memory block row hammer refresh signal Ref <3> ; The logic circuit d receives the row hammer refresh indication signal Flag corresponding to the storage block d <4> , and when the row hammer refresh signal and the row hammer refresh indication signal Flag <4> When valid, based on the row hammer refresh signal and the row hammer refresh indication signal Flag <4> Generate target memory block row hammer refresh signal Ref <4> ; Through the logic circuit, when the row hammer refresh signal is valid, it corresponds to the row hammer refresh indication signal Flag <c>Generate target memory block row hammer refresh signal Ref <c>.

[0076] In some embodiments, reference Figure 6 The memory 100 further includes: a decoding circuit 105, which is used to receive and decode a control command issued by the memory controller to generate at least one of a refresh signal REF, an activation signal ACT and an address signal ADD.

[0077] For the memory provided in this embodiment, the row hammer refresh indication signal Flag is used to indicate the memory block 101 whose number of activation signals corresponding to the memory block 101 satisfies the activation preset value, i.e., the memory block 101 that may generate the Row Hammer phenomenon; the row hammer refresh control circuit 103 generates the target memory block row hammer refresh signal Ref based on the refresh signal REF and the row hammer refresh indication signal Flag, i.e., the memory needs to perform Row Hammer protection, and the number of activation signals corresponding to the memory block 101 satisfies the activation preset value of the memory block 101, and generates the target memory block row hammer refresh signal Ref for the memory block 101, so as to implement supplementary refresh only for the target memory block during the supplementary refresh process, i.e., the Row Hammer protection strategy in the disclosed embodiment is to perform Row Hammer protection only for the memory block 101 that may generate the Row Hammer phenomenon, and avoid the supplementary refresh process for the memory block that will not generate the Row Hammer phenomenon, thereby reducing the power consumption of the memory.

[0078] It should be noted that the features disclosed in the memory provided in the above embodiments can be arbitrarily combined without conflict to obtain a new memory embodiment.

[0079] Another embodiment of the present disclosure provides a storage system, including: a storage controller and a memory, the memory responds to a control command issued by the storage controller, and the memory is based on the memory structure provided by the above embodiment to optimize the memory's Row Hammer protection strategy, thereby reducing the memory's power consumption.

[0080] Specifically, the storage controller can provide various control signals to operate the memory. The storage controller can be built into various types of host devices, such as: a central processing unit (CPU), a graphics processing unit (GPU), a multimedia processor (MMP), a digital signal processor, and an application processor (AP). In some embodiments, the storage controller can be stacked with the memory on the same substrate and a corresponding single package can be set.

[0081] The memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0082] The connection between the storage controller and the memory is realized through multiple buses, wherein the multiple buses can be signal transmission paths, links or channels for sending signals. The multiple buses can include a command address bus and a data bus. The command address bus is usually a unidirectional bus for transmitting the command signal CMD and the address signal to the memory in one direction. The data bus is usually a bidirectional bus for bidirectionally transmitting the data signal DQ between the storage controller and the memory.

[0083] Specifically, the storage controller sends the command signal CMD and the address signal to the memory through the command address bus. In some embodiments, the command address bus can be separately set as a command bus and an address bus. The storage controller is coupled to the memory through the data bus, and receives the data signal DQ from the memory through the data bus, or sends the data signal DQ to the memory. In some embodiments, the data bus can be separately set as a digital sub-bus and a clock sub-bus, wherein the clock sub-bus is set as a unidirectional bus, and the storage controller sends the system clock signal to the memory through the clock sub-bus, so that the storage controller and the memory can perform data communication synchronously based on the system clock signal.

[0084] Based on the above, the memory controller provides various command signals CMD through the command address bus to control the operation of the memory. Figure 6 As described above, the control command CMD provided by the storage controller is recognized by the decoding circuit 105, thereby obtaining the refresh signal REF, the activation signal ACT, the address signal ADD, and the read command signal RD and the write command signal WT used by the memory 100 for reading and writing (not related to the core scheme of the present disclosure, and will not be described in detail in this embodiment). The activation signal ACT can be used by the memory 100 to implement the activation operation, and can enable a specific word line in a certain storage block in the memory 100 based on the address signal ADD received together with the activation signal ACT. The memory 100 can perform a read operation based on the read command signal RD, and can select a specific bit line based on the address signal ADD received together with the read command signal RD, and the memory 100 performs a read operation on the total data of the storage cells between the enabled word lines and bit lines. Similarly, the memory 100 can perform a write operation based on the write command signal WT, and can select a specific bit line based on the address signal ADD received together with the write command signal WT, and the memory 100 performs a write operation on the total data of the storage cells between the enabled word lines and bit lines. When the read operation or the write operation is completed, the memory 100 ends the activation operation and may disable the enabled word line.

[0085] Further, the storage controller can generate a control command for refreshing, and the control command is decoded by the decoding circuit 105 to obtain a refresh signal, and the refresh signal includes a periodic refresh signal and a non-periodic refresh signal. For data retention of the memory 100, the periodic refresh signal is periodically generated by the storage controller at a constant time interval and provided to the memory 100. The storage controller may include a clock counter, and based on the value of the clock counter, generates a periodic refresh command signal every time a predetermined time passes. In addition, the storage controller can generate a non-periodic refresh command signal by detecting a row hammer situation, and the non-periodic refresh command signal is used to instruct the memory 100 to perform a supplementary refresh on the adjacent address of the address that may generate a row hammer situation when the refresh device is refreshed.

[0086] For the memory 100 provided in the present embodiment, the row hammer refresh indication signal Flag is used to indicate the memory block 101 whose number of activation signals corresponding to the memory block 101 satisfies the activation preset value, i.e., the memory block 101 that may generate the Row Hammer phenomenon; the row hammer refresh control circuit 103 generates the target memory block row hammer refresh signal Ref based on the refresh signal REF and the row hammer refresh indication signal Flag, i.e., the memory needs to perform Row Hammer protection, and the number of activation signals corresponding to the memory block 101 satisfies the activation preset value of the memory block 101, and generates the target memory block row hammer refresh signal Ref for the memory block 101, so as to implement supplementary refresh only for the target memory block during the supplementary refresh process, i.e., the Row Hammer protection strategy in the present disclosed embodiment is to perform Row Hammer protection only for the memory block 101 that may generate the Row Hammer phenomenon, and avoid the supplementary refresh process for the memory block that will not generate the Row Hammer phenomenon, thereby reducing the power consumption of the memory.

[0087] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.< / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c> < / c>

Claims

1. A memory, characterized in that: include: n storage blocks, n is a positive integer; The activation control circuit is configured to receive an address signal and an activation signal, count the activation signals corresponding to each of the storage blocks based on the address signal, and generate and output a row hammer refresh indication signal corresponding to the storage block when the number of the activation signals corresponding to any one of the storage blocks meets an activation preset value; wherein the address signal indicates the storage block currently being activated; A row hammer refresh control circuit is coupled to the activation control circuit and is configured to receive a refresh signal and the row hammer refresh indication signal, and generate a target storage block row hammer refresh signal corresponding to the storage block based on the refresh signal and the row hammer refresh indication signal, wherein the target storage block row hammer refresh signal is used to instruct the corresponding storage block to perform a row hammer refresh operation.

2. The memory according to claim 1, characterized in that: The activation control circuit comprises: n activation control modules, each of which corresponds to each of the storage blocks; an identification module, receiving the address signal and the activation signal, and configured to generate a target storage block activation signal corresponding to the address signal based on the address signal and the activation signal, wherein the target storage block activation signal is used to drive the activation control module corresponding to the storage block corresponding to the address signal; Each of the activation control modules is configured to count based on the corresponding target storage block activation signal to generate an activation count value, and when the activation count value meets an activation preset value, generate and output a row hammer refresh indication signal corresponding to the storage block.

3. The memory according to claim 2, characterized in that: Each of the activation control modules comprises: A counting unit configured to count based on the corresponding target storage block activation signal to generate the activation count value; The comparison unit is coupled to the counting unit and receives an activation preset value, and is configured to generate and output the row hammer refresh indication signal corresponding to the storage block when the activation counting value satisfies the activation preset value.

4. The memory according to claim 2, characterized in that: Each of the activation control modules comprises: A cascade of k levels of D flip-flops, wherein the input end of each level of the D flip-flop is connected to the inverting output end, and k is an integer greater than 1; The clock end of the first-level D flip-flop is used to receive the target storage block activation signal, the clock end of the j-th level D flip-flop is connected to the inverting output end of the j-1-th level D flip-flop, 2≤j≤k, and the output end of the last level D flip-flop is used to output the row hammer refresh indication signal.

5. The memory according to any one of claims 2 to 4, characterized in that: The activation control module is arranged in the corresponding storage block.

6. The memory according to claim 1, characterized in that: The row hammer refresh control circuit comprises: A first control module, coupled to the activation control circuit, configured to generate a row hammer refresh enable signal based on any of the row hammer refresh indication signals; A second control module, coupled to the first control module, configured to generate a row hammer refresh signal based on the refresh signal and the row hammer refresh enable signal; n processing modules, the n processing modules corresponding one-to-one to the n storage blocks; each of the processing modules is coupled to the second control module and the corresponding activation control circuit, and is configured to generate and output the target storage block row hammer refresh signal corresponding to the storage block based on the row hammer refresh signal and the row hammer refresh indication signal corresponding to the storage block.

7. The memory according to claim 6, characterized in that: The first control module comprises: an OR logic circuit comprising n input terminals, the n input terminals respectively corresponding to receiving the n row hammer refresh indication signals corresponding to the n storage blocks, and an output terminal for outputting the row hammer refresh enable signal.

8. The memory according to claim 6, characterized in that: The first control module comprises: an XOR logic circuit comprising n input terminals, wherein the n input terminals respectively receive n row hammer refresh indication signals corresponding to the n storage blocks, and an output terminal is used to output the row hammer refresh enable signal.

9. The memory according to claim 6, characterized in that: The processing module includes: an AND logic circuit, a first input end for receiving the row hammer refresh signal, a second input end for receiving the row hammer refresh indication signal corresponding to the corresponding storage block, and an output end for outputting the target storage block row hammer refresh signal.

10. The memory according to any one of claims 6 to 9, characterized in that: The processing module is arranged in the corresponding storage block.

11. The memory according to claim 1, characterized in that: Also includes: The decoding circuit is used to receive and decode the control command issued by the storage controller to generate at least one of the refresh signal, the activation signal and the address signal.

12. A storage system, characterized in that: include: A storage controller and a memory, wherein the memory responds to a control command issued by the storage controller, and the memory is constructed based on the memory according to any one of claims 1 to 11.

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