Row Hammer Protection for Memory Devices

Abstract

The present application is directed to row hammer protection for a memory device. A memory device may identify a threshold for associated row accesses to a memory array (e.g., access commands or activations to the same row address or row address space). In a first operating mode, the memory device may execute a command received from a host device on the memory array. The memory device may determine that a metric of the received row access command satisfies the threshold for associated row access. The memory device may switch the memory array from the first operating mode to a second operating mode based on satisfying the threshold. The second operating mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.

Description

[0001] Cross-references

[0002] This patent application claims priority to PCT application No. PCT / US2019 / 047616, filed by Schaefer et al. on August 22, 2019, entitled “ROW HAMMER PROTECTION FOR A MEMORY DEVICE,” which claims priority to U.S. patent application No. 16 / 546,252, filed by Schaefer et al. on August 20, 2019, entitled “ROW HAMMER PROTECTION FOR A MEMORY DEVICE,” and U.S. provisional patent application No. 62 / 728,490, filed by Schaefer et al. on September 7, 2018, entitled “ROW HAMMER PROTECTION FOR A MEMORY DEVICE,” each of which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to row hammer protection for memory devices. Background Art

[0004] The following relates generally to systems including at least one memory device, and more particularly to row hammer protection for memory devices.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states in the memory device. For example, binary devices most often store one of two states, often represented by a logical 1 or a logical 0. Other devices can store more than two states. To access stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory devices such as FeRAM can maintain their stored logic state for a long period of time, even without an external power source. Volatile memory devices such as DRAM and SRAM can lose their stored state over time unless connected to an external power source. Dynamic memory devices such as DRAM can also use periodic refresh to maintain the memory cell state.

[0007] In some cases, the memory state of some types of memory, such as dynamic random access memory (DRAM), can be affected by frequent row activations, which can be referred to as row hammering. For example, if rows are repeatedly accessed within a time interval (e.g., row hammering), leakage, parasitic currents, or charge pumping caused by the repeated accesses to one or more rows can cause data corruption in physically adjacent (e.g., neighboring) rows that are not being accessed. As the size of memory decreases, the number of physically adjacent rows that can experience data corruption during row hammering (e.g., the number of victim rows) can increase. Generally speaking, improvements to memory devices can include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Furthermore, improving memory device performance (e.g., increasing reliability, increasing data retention) in the presence of row hammering can be desirable. Summary of the Invention

[0008] A method is described. In some examples, the method may include identifying a threshold for row access of a memory array, the memory array comprising a plurality of rows; receiving a row access command for the memory array from a host in a first operating mode; determining, for a row from the plurality of rows, that a metric of the row access command satisfies the threshold; and switching the memory array from the first operating mode to a second operating mode based at least in part on determining that the metric of the row access command satisfies the threshold, wherein the second operating mode is associated with restricting access to at least one of the plurality of rows of the memory array.

[0009] A method is described. In some examples, the method may include identifying a threshold for row access of a memory array, the memory array comprising a plurality of rows; receiving a plurality of row access commands for the memory array from a host; determining, for a row in the plurality of rows, that a pattern of the plurality of row access commands satisfies the threshold; and transmitting an indication to the host based at least in part on determining that the pattern of the plurality of row access commands satisfies the threshold.

[0010] A device is described. In some examples, the device may include a memory array having a plurality of rows; a memory interface coupled to the memory array and a host, the memory interface operable to receive a row access command from the host; and circuitry coupled to the memory array and the memory interface, the circuitry operable to: identify a threshold for row access of the memory array; execute the row access command on the memory array in a first operating mode; determine, for a row in the plurality of rows, that a metric of the row access command satisfies the threshold; and switch the memory array from the first operating mode to a second operating mode based at least in part on determining that the metric of the row access command satisfies the threshold, wherein the second operating mode is associated with restricting access to at least one of the plurality of rows of the memory array.

[0011] A device is described. In some examples, the device may include a memory array having a plurality of rows; a memory interface coupled to the memory array and a host, the memory interface operable to receive a row access command from the host; and circuitry coupled to the memory array and the memory interface, the circuitry operable to: identify a threshold for row access of the memory array; execute the row access command on the memory array; determine, for a row in the plurality of rows, that executing the row access command satisfies the threshold; and transmit an indication to the host via the memory interface that executing the row access command satisfies the threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An example of a system supporting row hammer protection for a memory device as disclosed herein is described.

[0013] Figure 2 An example of a memory die supporting row hammer protection for a memory device as disclosed herein is described.

[0014] Figure 3 An example of a system supporting row hammer protection for a memory device as disclosed herein is described.

[0015] Figures 4 to 6A process flow supporting row hammer protection for a memory device as disclosed herein is shown.

[0016] Figure 7 A block diagram illustrating circuitry supporting row hammer protection for a memory device as disclosed herein is shown.

[0017] Figure 8 and 9 A flow chart illustrating one or more methods of supporting row hammer protection for a memory device as disclosed herein is shown. DETAILED DESCRIPTION

[0018] Memory devices may operate under various conditions as part of electronic devices, such as personal computers, wireless communication devices, servers, Internet of Things (IoT) devices, electronic components of motor vehicles, and the like. In some cases, memory devices supporting applications for certain embodiments (e.g., motor vehicles, and in some cases, motor vehicles with autonomous or semi-autonomous driving capabilities) may be subject to increased reliability constraints. Consequently, memory devices (e.g., DRAM) used for some applications may be expected to operate with a reliability that is limited by relatively high industry specifications (e.g., higher reliability constraints).

[0019] Some memory types can lose their stored state or change their stored state to a different state under frequent row activations, or row hammering. That is, if a single row, group of rows, or pattern of rows is accessed at a relatively high frequency, the memory state of the victim row (e.g., an adjacent or neighboring row) can be affected. In some cases (e.g., automotive applications), increased reliability of the memory cells may be desirable (e.g., for critical safety functions). That is, it may be necessary to prevent dynamic memory cells from changing their stored state due to row hammering. For example, dynamic memory cells (e.g., DRAM cells) of a memory device can lose their stored data if the data is not periodically refreshed, and row hammering can cause the dynamic memory cells to lose their stored state or change their stored state to a different state in less time (e.g., a refresh cycle is faster). Additionally, some applications may have different memory access patterns during normal or predicted use.

[0020] Techniques for improving row hammer protection for a memory device are described. For example, a memory device may utilize a threshold corresponding to a maximum measure of related accesses to a memory array (e.g., access commands or activations to the same row address or the same row address space). In the event that the memory device detects a measure (e.g., number or pattern) of row access commands that meets (e.g., is equal to or greater than) the threshold (e.g., the memory device detects row hammer), the memory device may take action based on the detection of row hammer. In one example, the memory device may activate a safe mode of the memory array associated with the detected row hammer. The safe mode may prevent row accesses to at least one row of the memory array, thereby reducing the chance of further data corruption resulting from frequent row accesses. Additionally or alternatively, the memory device may transmit a notification to a host device indicating the detected row hammer associated with the memory array. Based on the notification, the host device may take circumventive measures to prevent an application from performing additional row accesses at the memory array associated with the row hammer.

[0021] First, in reference Figure 1 、 2 The features of the present disclosure are described in the context of the memory systems and devices described in and 3. Figure 4 、 5 Features of the present disclosure are described in the context of the process flows described in and 6. Further disclosed are methods related to row hammer protection for memory devices. Figure 7-9 These and other features of the present disclosure are illustrated and described with reference to the device diagrams and flow diagrams in the accompanying drawings.

[0022] Figure 1 An example of a system 100 utilizing one or more memory devices according to aspects disclosed herein is illustrated. The system 100 can include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 can include one or more memory devices, but for ease of description, the one or more memory devices can be described as a single memory device 110.

[0023] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. In some cases, system 100 is an automotive system, such as a vehicle control system, a fleet management system, a location tracking system, a navigation system, an infotainment system, or the like. In other cases, system 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, or the like. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100. In some examples, system 100 is configured for bidirectional wireless communication with other systems or devices using a base station or access point. In some examples, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0024] At least a portion of the system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device (e.g., a graphics processing unit (GPU)), a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, and the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as a host or a host device.

[0025] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses / space that may potentially be used or referenced by system 100. In some instances, memory device 110 may be configured to cooperate with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be used to support modulation schemes for modulated signals, different pin designs for transmitting signals, different packaging for system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0026] The memory device 110 can be configured to store data for components of the system 100. In some cases, the memory device 110 can act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands can include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 can include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies can be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0027] System 100 may additionally include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may electronically communicate with each other using a bus 140.

[0028] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In such cases, the processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system on a chip (SoC), among other examples.

[0029] BIOS component 125 may be a software component comprising a BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may comprise a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0030] Peripheral component 130 can be any input device or output device, or an interface for such a device, that can be integrated into or with system 100. Examples can include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot, such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot. Peripheral component 130 can be other components that are understood by those skilled in the art to be peripheral devices.

[0031] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input 145, or output 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0032] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0033] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, another processor on a printed device or printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0034] The components of system 100 may be composed of general or special purpose circuits designed to perform their functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein.

[0035] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0036] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, a tier, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high stacked memory dies, three high stacked memory dies, four high stacked memory dies, five high stacked memory dies, six high stacked memory dies, seven high stacked memory dies, eight high stacked memory dies). This can increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn can reduce production costs or increase the performance of the memory array, or both. In some 3D memory devices, different stacks can share at least one common access line, such that some stacks can share at least one of a word line, a digit line, and / or a plate line.

[0037] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command instructing the memory device 110 to store certain data on behalf of a component of the system 100 (e.g., the processor 120), or a read command instructing the memory device 110 to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, and the like.

[0038] A local memory controller 165 (e.g., local to the memory die 160) can be configured to control the operation of the memory die 160. Furthermore, the local memory controller 165 can be configured to communicate with (e.g., receive and transmit data and / or commands to) the device memory controller 155. The local memory controller 165 can support the device memory controller 155 in controlling the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 105 can perform the various functions described herein. Thus, the local memory controller 165 can be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0039] The external memory controller 105 can be configured to facilitate communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 can act as a liaison between the components of the system 100 and the memory device 110, such that the components of the system 100 may not need to know the operational details of the memory device 110. The components of the system 100 can present requests (e.g., read commands or write commands) to the external memory controller 105, which the external memory controller 105 can satisfy. The external memory controller 105 can convert or translate the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 can include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 can include a common data clock that generates a common (source) data clock signal.

[0040] In some cases, the external memory controller 105 or other components of the system 100, or the functionality thereof described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or the functionality thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controllers 165. Likewise, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may in some cases be performed by the external memory controller 105 (separate from or included in the processor 120 ).

[0041] Components of system 100 can exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 can enable communication between external memory controller 105 and memory device 110. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 can include a first terminal comprising one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin can be an example of a conductive input or output point of a device of system 100, and a pin can be configured to function as part of a channel. In some cases, a pin or pad of a terminal can be part of a signal path of channel 115. Additional signal paths can be coupled to the terminals of a channel for routing signals within the components of system 100. For example, memory device 110 may include signal paths (e.g., internal to memory device 110 or a component thereof, such as signal paths internal to memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0042] Channel 115 (and associated signal paths and terminals) can be dedicated to transmitting specific types of information. In some cases, channel 115 can be an aggregate channel and thus can include multiple individual channels. For example, data channel 190 can be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc.

[0043] In some cases, channels 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channel 186 may include a read command that specifies the address of the desired data. In some cases, CA channel 186 may register on rising and / or falling clock signal edges. In some cases, CA channel 186 may include eight or nine signal paths.

[0044] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., a CK_t signal and a CK_c signal), and the signal paths of CK channels 188 may be configured accordingly. In some cases, the clock signals may be single-ended. In some cases, the clock signals may be 1.5 GHz signals. CK channels 188 may include any number of signal paths. In some cases, clock signals CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Clock signals CK may therefore be variously referred to as control clock signals CK, command clock signals CK, or system clock signals CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0045] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110. Data channels 190 may transfer signals that may be modulated using a variety of different modulation schemes (e.g., NRZ, PAM4).

[0046] In some cases, channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

[0047] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write," the write clock signal WCK (e.g., the WCK_t signal and the WCK_c signal) may provide a timing reference generally used for access operations of the memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., the WCK_t signal and the WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0048] The channel 115 can use a variety of different architectures to couple the external memory controller 105 with the memory device 110. Examples of various architectures can include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path can at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0049] Various modulation schemes may be used to modulate signals transmitted over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and the like.

[0050] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. A multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and the like. A multi-symbol signal, or PAM4 signal, may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0051] System 100 can be configured to employ techniques for improving row hammer protection for memory device 110. Memory device 110 can utilize a threshold corresponding to a maximum metric of related accesses to memory array 170 (e.g., access commands or activations to the same row address or the same row address space). If memory device 110 detects a metric (e.g., number or pattern) of row access commands that meets the threshold (e.g., memory device 110 detects row hammer), memory device 110 can take action based on the detection of row hammer. In one example, memory device 110 can activate a safe mode of memory array 170 associated with the detected row hammer. The safe mode can prevent row accesses to at least one row of memory array 170, thereby reducing the chance of further data corruption resulting from frequent row accesses. Additionally or alternatively, memory device 110 can transmit a notification to a host (e.g., external memory controller 105) indicating the detected row hammer associated with memory array 170. The host may take workaround measures to prevent the application from performing extra row accesses at the memory array 170 that are associated with row hammering.

[0052] Figure 2 An example of a memory device 200 according to various examples of the present disclosure is illustrated. The memory die 200 may be a reference Figure 11 . An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic at a time (e.g., a logic 0 and a logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic at a time (e.g., a logic 00, a logic 01, a logic 10, or a logic 11).

[0053] Memory cell 205 can store a charge representing a programmable state in capacitor 230. DRAM architectures can include capacitor 230 that includes a dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are also possible. For example, nonlinear dielectric materials can be used.

[0054] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210 and / or digit line 215. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, and digit lines, or the like, are interchangeable and do not affect understanding or operation. Activating or selecting word line 210 or digit line 215 may include applying a voltage to the corresponding line.

[0055] The memory die 200 may arrange access lines (e.g., word lines 210 and digit lines 215) in a grid-like pattern. Memory cells 205 may be located at the intersections of the word lines 210 and digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections.

[0056] Access to memory cells 205 can be controlled by row decoder 220 or column decoder 225. For example, row decoder 220 can receive a row address from local memory controller 260 and activate word lines 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and activate digit lines 215 based on the received column address. For example, memory die 200 can include a plurality of word lines 210 labeled WL_1 through WL_M and a plurality of digit lines 215 labeled DL_1 through DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, such as WL_1 and DL_3, a memory cell 205 can be accessed at their intersection. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of a memory cell 205.

[0057] Memory cell 205 may include a logic storage component, such as capacitor 230 and switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switch component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell plate reference voltage, such as Vpl, or may be grounded, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switch component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0058] Selecting or deselecting memory cell 205 can be accomplished by activating or deactivating switch component 235. Capacitor 230 can be in electronic communication with digit line 215 using switch component 235. For example, when switch component 235 is deactivated, capacitor 230 can be isolated from digit line 215, and when switch component 235 is activated, capacitor 230 can be coupled to digit line 215. In some cases, switch component 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, where the voltage difference between the transistor gate and the transistor source can be greater than or less than the transistor's threshold voltage. In some cases, switch component 235 can be a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switch component 235, and switch component 235 can be activated / deactivated based on the voltage applied to word line 210.

[0059] The word line 210 can be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with the gate of the switching element 235 of the memory cell 205 and can be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include the switching element 235.

[0060] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing element 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0061] Sensing component 245 can be configured to detect a state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be extremely small. Therefore, sensing component 245 may include one or more sense amplifiers to amplify the signal output by memory cell 205. The sense amplifiers can detect small changes in charge on digit line 215 during a read operation and, based on the detected charge, can generate a signal corresponding to a logic state 0 or a logic state 1. During a read operation, capacitor 230 of memory cell 205 can output a signal (e.g., release charge) to its corresponding digit line 215. The signal can cause the voltage of digit line 215 to change. Sensing component 245 can be configured to compare the signal received from memory cell 205 across digit line 215 with reference signal 250 (e.g., a reference voltage). Sensing component 245 can determine the storage state of memory cell 205 based on the comparison. For example, in binary signaling, if digit line 215 has a higher voltage than reference signal 250, sensing component 245 can determine that the storage state of memory cell 205 is a logic 1, and if digit line 215 has a lower voltage than reference signal 250, sensing component 245 can determine that the storage state of memory cell 205 is a logic 0. Sensing component 245 can include various transistors or amplifiers to detect and amplify the difference in signals. The detected logic state of memory cell 205 can be output as output 255 via column decoder 225. In some cases, sensing component 245 can be part of another component (e.g., column decoder 225, row decoder 220). In some cases, sensing component 245 can be in electronic communication with row decoder 220 or column decoder 225.

[0062] The local memory controller 260 may control the operation of the memory unit 205 via various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1 In some cases, one or more of the row decoder 220, column decoder 225, and sense component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to receive data from the external memory controller 105 (or reference Figure 1 The device memory controller 155 (described herein) receives commands and / or data, translates the commands and / or data into information that can be used by the memory die 200, performs one or more operations on the memory die 200, and communicates data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 260 can generate row and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or varied and can be different for the various operations discussed in operating the memory die 200.

[0063] In some cases, the local memory controller 260 can be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 can be programmed during a single write operation. The local memory controller 260 can identify the target memory cell 205 on which the write operation is to be performed. The local memory controller 260 can identify the target word line 210 and the target digit line 215 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. Local memory controller 260 may apply a specific signal (eg, voltage) to digit line 215 during a write operation to store a specific state (eg, charge) in capacitor 230 of memory cell 205 that may indicate a desired logic state.

[0064] In some cases, the local memory controller 260 can be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in the memory cells 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 260 can identify the target memory cell 205 on which the read operation is to be performed. The local memory controller 260 can identify the target word line 210 and target digit line 215 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and target digit line 215 (e.g., apply a voltage to the word line 210 or digit line 215) to access the target memory cell 205. The target memory cell 205 can pass a signal to the sensing component 245 in response to the biased access line. The sensing component 245 can amplify the signal. The local memory controller 260 may trigger the sensing component 245 (e.g., latch the sensing component 245) and, in turn, compare the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. As part of a read operation, the local memory controller 260 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155).

[0065] In some memory architectures, accessing a memory cell 205 can degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture can partially or completely discharge the capacitor 230 of the target memory cell 205. The local memory controller 260 can perform a rewrite operation or a refresh operation to restore the memory cell 205 to its original logic state. The local memory controller 260 can rewrite the logic state to the target memory cell 205 after the read operation. In some cases, the rewrite operation can be considered part of the read operation. In addition, activating a single access line (e.g., word line 210) can disturb the state stored in some memory cells in electronic communication with that access line. As a result, a rewrite operation or a refresh operation can be performed on one or more memory cells that may not have been accessed.

[0066] Figure 3 An example of a system 300 that supports row hammer protection techniques for a memory device is described. The system 300 may include the memory devices described herein. Figure 1 and 2 For example, system 300 may include a host device 305, which may be a reference Figure 1The example of the external memory controller 105 described; the memory device 310, which may be referenced Figure 1 and 2 The examples of memory device 110, memory die 160, or memory die 200 described; controller 320, which may be referenced Figure 1 and 2 The described instances of the device memory controller 155, one or more local memory controllers 165, or local memory controller 260, or any combination thereof; the memory array 325, which may be referenced Figure 1 An example of a memory array 170 is depicted. Memory device 310 may also include a threshold storage device 330 and a redundant row access detection circuit 335.

[0067] Host device 305 may send commands to memory device 310, which may be received via memory interface 315. The commands may include individual row access commands (e.g., individual read or write commands) or burst commands (multiple sequential row or column access commands). Controller 320 may receive commands from memory interface 315, process the commands, and execute the commands on memory array 325. Controller 320 may operate memory array 325 according to an operating mode. As used herein, an access mode may include controller 320 executing a command issued from host device 305 to a specified portion of memory array 325 (e.g., all received commands). Memory array 325 may include one or more memory banks, each of which may include one or more rows and / or one or more columns. Each command may include an access command, which may include an activation (e.g., read, write, etc.) to a row address within memory array 325. The controller 320 may execute a plurality of access commands (eg, a pattern of access commands) on the memory array 325 , thereby accessing a pattern of banks, rows, and / or columns within the memory array 325 .

[0068] Threshold storage 330 may store thresholds associated with access commands or accesses for memory device 310. The thresholds may define a number of correlated accesses that, when exceeded, may cause data corruption from row hammering. In some cases, the correlated accesses may correspond to a maximum number of accesses to the same row address or the same row address space (e.g., a row group, a bank, etc.). Additionally or alternatively, the correlated accesses may correspond to a sum of accesses to one or more access patterns for the row address space. The maximum number of correlated accesses may occur sequentially or within a specific time window (e.g., a refresh cycle, a portion of a refresh cycle), a specific number of access operations, or some other criteria.

[0069] In some cases, memory device 310 may have associated preconfigured thresholds. For example, threshold storage 330 may store preconfigured thresholds that are fixed by a vendor (e.g., a DRAM vendor). Threshold storage 330 may include values for preconfigured thresholds that are, for example, hardwired (e.g., stored in one or more fuses, antifuses, or otherwise stored in one or more memory elements that are non-volatile and preconfigurable (e.g., read-only memory (ROM) or one-time programmable (OTP) memory)).

[0070] Memory device 310 can be used to support a variety of applications. In some cases, each application may access memory array 325 of memory device 310 according to a known access pattern. That is, the intended purpose of the application may result in a specific set of access patterns. For example, a general-purpose application (e.g., with a variety of intended purposes) may access memory array 325 according to an unpredictable access pattern. Alternatively, a specialized application (e.g., with a narrower intended purpose) may access memory array 325 according to a more predictable access pattern and may have discernible boundaries between access commands to related or adjacent addresses (e.g., a single row or a group of rows). For specialized applications (e.g., applications within an autonomous vehicle), certain access patterns may be determined to be less likely than others. For example, a specialized application may be less likely to exhibit an access pattern similar to row hammering during its normal operation. It may be desirable for memory device 310 to utilize lower thresholds associated with some applications (e.g., specialized applications) compared to other applications (e.g., general-purpose applications). Alternatively, a dedicated application may likely exhibit an access pattern similar to row hammering in its normal operation.Here, the memory device 310 may need to utilize a higher threshold.

[0071] In some cases, different portions of the memory array 325 (e.g., rows, banks, etc.) may be associated with different thresholds. For example, some portions of the memory array 325 may be protected areas in which a lower number of accesses is allowed. In one example, some protected areas may have a threshold of a single row access, where any additional row access (e.g., within a refresh cycle) will exceed the threshold and cause the detection of a superfluous row access condition. Thus, the host device 305 may utilize different portions of the memory array 325 for different applications or purposes. For example, portions of the memory array 325 associated with lower thresholds may be used for applications associated with critical functions that rarely, if ever, generate access patterns consistent with row hammering, while other portions of the memory array 325 associated with higher thresholds may be used for general or less critical functions.

[0072] In some cases, the preconfigured thresholds in threshold storage 330 may be adjustable or overwriteable (e.g., as trimming parameters). For example, threshold storage 330 may include OTP memory (e.g., fuses or antifuses) for storing preconfigured thresholds, and host device 305 may program the preconfigured thresholds upon initial memory device 310 power-up or configuration (e.g., the first time host device 305 accesses memory device 310). After programming, the preconfigured thresholds may then be fixed within subsequent power cycles.

[0073] According to various aspects, threshold storage device 330 may include the ability to store programmed (e.g., non-preconfigured) threshold values. In some cases, threshold storage device 330 may include non-volatile memory (e.g., one-time programmable (OTP) memory, electrically erasable programmable read-only memory (EEPROM), ferroelectric random access memory (FRAM), magnetoresistive random access memory (RAM)) for storing the programmed threshold values. Alternatively, threshold storage device 330 may include volatile memory (e.g., DRAM, static random access memory (SRAM), registers) for storing the programmed threshold values. Host device 305 may program threshold storage device 330 to store the programmed threshold values (e.g., after initialization or configuration). The programmed threshold values may be based on the application of memory device 310. That is, while the preconfigured threshold value may represent a number of relevant accesses associated with reduced data retention, certain applications (e.g., specialized applications) may utilize different (e.g., lower) threshold values. For example, the preconfigured threshold value of memory device 310 may be 10,000. However, memory device 310 may be associated with an autonomous vehicle application that may be less likely to exhibit accesses similar to row hammering. Therefore, host device 305 programs threshold storage device 330 (via controller 320 or memory interface 315) to store a programmed threshold value that is less than 10,000. In some cases, host device 305 may program threshold storage device 330 to store the programmable threshold value by programming a mode register within memory device 310. In some cases, host device 305 may program threshold storage device 330 to store a programmable threshold value that is greater than the preconfigured threshold value, but excess row access detection circuitry 335 may be configured to treat the lower of the two threshold values as operational.

[0074] Threshold storage device 330 can store the programmed threshold value and subsequently protect the storage of the programmed threshold value. For example, threshold storage device 330 can include a fuse that can be blown to prevent the programmed threshold value from changing (e.g., threshold storage device 330 can be an OTP memory). In another example, threshold storage device 330 can not adjust the programmed threshold value until a known command sequence is received from host device 305. That is, host device 305 can transmit the command sequence to memory device 310. Memory device 310 (e.g., via controller 320 or redundant row access detection circuit 335) can then determine to store the updated programmed threshold value at threshold storage device 330 based on receiving the command sequence.

[0075] The redundant row access detection circuit 335 may determine which of the preconfigured threshold value or the programmed threshold value to use based on the minimum threshold value (e.g., select the minimum of the preconfigured threshold value or the programmed threshold value). In some other cases, the redundant row access detection circuit 335 may determine which of the preconfigured threshold value or the programmed threshold value to use based on a flag register. The flag register may instruct the redundant row access detection circuit 335 to use the programmed threshold value. For example, if the flag register stores a logic '0', the redundant row access detection circuit 335 may use the preconfigured threshold value. Alternatively, if the flag register stores a logic '1', the redundant row access detection circuit 335 may use the programmed threshold value. In some cases, the host device 305 may set the flag register. In some cases, one or more (e.g., some or all) of the redundant row access detection circuits 335 herein may be integrated into the controller 320.

[0076] The redundant row access detection circuit 335 may include circuit components configured to determine a row access metric. The redundant row access detection circuit 335 may be or include a counter, a timer, or the like. The row access metric may indicate a number of related accesses (e.g., a number or pattern of accesses to the same or similar rows, banks, etc.). The redundant row access detection circuit 335 may receive an access indication (e.g., an access command received from the host device 305) from the memory interface 315 or the controller 320. That is, during an access mode, the controller 320 may execute the access command received from the host device 305 on the memory array 325. The controller 320 may further provide the access indication to the redundant row access detection circuit 335. Based on the accesses, the redundant row access detection circuit 335 may determine the number of related accesses and compare the row access metric to a threshold value (e.g., a preconfigured threshold value or a programmed threshold value) from the threshold storage device 330. If the redundant row access detection circuitry 335 determines that the row access metric meets the threshold, the redundant row access detection circuitry 335 may provide an indication to the controller 320. The indication may include information indicating one or more rows (e.g., a row group, a bank) for which the row access metric meets the threshold. Upon receiving the indication that the row access metric meets the threshold, the controller 320 may transition one or more portions of the memory array 325 from an access mode to a secure mode. The secure mode may prevent additional row accesses to the memory array 325 that would increase the probability that a bit of the memory array 325 will change memory state (e.g., due to a row hammering access pattern). As used herein, a secure mode includes access restriction conditions for at least one row of the memory array 325.

[0077] In addition to or in lieu of entering secure mode, the controller 320 can transmit an indication to the host device 305 that the row access metric satisfies the threshold. In some cases, the indication can include information about the row or row pattern for which the access metric satisfies the threshold (e.g., a triggering condition). Additionally or alternatively, information about the row or row pattern for which the triggering condition occurred can be stored (e.g., in the controller 320 or in the redundant row access detection circuit 335) for access by the host device 305. Thus, upon receiving the indication, the host device 305 can read one or more registers of the memory device that include information about the row or row pattern for which the access metric satisfies the threshold.

[0078] The secure mode may include the controller 320 blocking access commands directed to the memory array 325. In one example, the secure mode may include the controller 320 blocking access commands to each of the banks of the memory array 325. In another example, the secure mode may include the controller 320 blocking access commands to a single bank (e.g., the victim bank of the access command). Here, the controller 320 may block access commands to the single bank while the remaining banks within the memory array 325 may continue to operate in the access mode (e.g., the controller 320 may propagate the access commands to the remaining banks). During the secure mode, the controller 320 may initiate a refresh operation on one or more banks associated with the secure mode.

[0079] Controller 320 may maintain secure mode for a predetermined period of time (e.g., a period of time or a number of clocks) or until a command to return to access mode is received from host device 305. A reset procedure may cause memory array 325 to transition from secure mode to access mode. The command to reset to access mode may include a single command, a command sequence known to both host device 305 and controller 320. This sequence may serve as a protection key. Here, host device 305 may transmit the command sequence (e.g., the protection key) to memory device 310. Controller 320 may recognize the command sequence and transition one or more banks or rows from secure mode to access mode. Due to the time taken to transition into secure mode and receive the sequence to re-enter access mode, any victim cells of memory array 325 may be fully refreshed upon resuming access mode. Thus, any attempted row hammering may cause cycling in and out of secure mode, but the state of the memory cells may not be compromised.

[0080] In addition to entering safe mode, or in situations where safe mode is not entered, controller 320 may perform other mitigation measures for a detected row hammer condition. For example, instead of placing the entire bank or banks in self-refresh mode, controller 320 may perform additional background refresh operations on victim rows (e.g., those rows that may be affected by the detected row hammer).

[0081] Figure 4 An example diagram of a process flow 400 supporting row hammer protection techniques for a memory device is shown. Features of the process flow 400 may be referenced by Figures 1 to 3 The memory device described (eg, referring to Figures 1 to 3 The described memory device 110, memory die 160, memory die 200, or memory device 310) or a component of a memory device (such as device memory controller 155, local memory controller 165, local memory controller 260, controller 320, or redundant row access detection circuit 335) is implemented or performed.

[0082] At block 405, circuitry associated with a memory device may receive a command from a host device. The command may be a row access command for a memory array. The circuitry may operate according to an access mode, which includes the circuitry executing the command from the host device on the memory array. For example, the circuitry may correspond to Figure 3 The memory interface 315, the controller 320, the redundant row access detection circuit 335 or the threshold storage device 330 are also included.

[0083] At block 410, the circuitry may determine whether a threshold associated with an access command to the memory array has been exceeded. The threshold may define a number of related accesses (e.g., a portion of a pattern) that, when exceeded, may create a risk of data corruption caused by row hammering. In some cases, the row access command received at block 405 may be associated with one or more rows that have undergone multiple related accesses. The circuitry may generate a metric for the related accesses and compare the metric to the threshold. When the circuitry determines that the metric for the memory access meets the threshold, the circuitry may proceed to block 415. Alternatively, when the circuitry determines that the metric does not meet the threshold, the circuitry may continue to operate in the access mode, for example, at block 430.

[0084] At block 415 , the circuitry may optionally transmit a notification to the host device indicating that the threshold has been met.

[0085] At block 420, the circuitry may cause the memory array to transition from an access mode to a safe mode of operation. The safe mode may prevent additional row accesses to the memory array that would increase the probability of bits of the memory array changing memory states (e.g., due to a row hammering access pattern). The safe mode may further include the circuitry performing a refresh operation on the portion of the memory array operating in the safe mode. In some cases, the circuitry may determine to transition from one safe mode of operation to multiple different safe mode operations. Each different safe mode of operation may include transitioning at least a portion of the memory array into the safe mode. For example, a first safe mode of operation may include the circuitry blocking access commands to a row or group of rows. In a second safe mode of operation, the circuitry may block commands to an entire row address space or bank. In a third safe mode of operation, the circuitry may block commands to the entire memory array. In some examples, (e.g., in either the first or second safe modes), portions of the memory array not operating in the safe mode may continue to operate normally (e.g., depending on the access mode). That is, the circuitry may transition a portion of the memory array to a secure mode (eg, thereby blocking access commands to that portion) while executing access commands for the host device to the memory device to other portions of the memory array.

[0086] At block 425, the controller may identify whether a reset procedure has been executed on the portion of the memory array that has transitioned to secure mode operation. The reset procedure may cause the memory array to transition from secure mode to access mode. When the circuitry determines that the reset procedure has been executed, the circuitry may proceed to block 430, where the circuitry may cause one or more portions of the memory array that have been operating in secure mode to transition to access mode. Alternatively, when the circuitry determines that the reset procedure has not been executed, the controller may proceed to block 420 (e.g., the circuitry may continue to block access commands to the one or more portions of the memory array that are operating in secure mode).

[0087] Figure 5 An example diagram of a process flow 500 supporting row hammer protection techniques for a memory device is shown. Features of the process flow 500 may be referenced by Figures 1 to 3 The memory device described (eg, referring to Figures 1 to 3 The described memory device 110, memory die 160, memory die 200, or memory device 310) or a component of a memory device (such as device memory controller 155, local memory controller 165, local memory controller 260, controller 320, or redundant row access detection circuit 335) is implemented or performed.

[0088] At block 505, circuitry associated with a memory device may receive a command from a host device. The command may be a row access command for a memory array. The circuitry may operate according to an access mode, which includes the circuitry executing the command from the host device on the memory array. For example, the circuitry may correspond to Figure 3 The memory interface 315, the controller 320, the redundant row access detection circuit 335 or the threshold storage device 330 are also included.

[0089] At block 510, the circuitry may determine whether a threshold associated with an access command to the memory array has been met. The threshold may define a number of related accesses (e.g., a portion of a pattern) that, when exceeded, may create a risk of data corruption due to row hammering. In some cases, the row access command received at block 505 may be associated with a row that has undergone multiple related accesses. The circuitry may generate a metric for the related accesses and compare the metric to the threshold. When the circuitry determines that the threshold for the memory device has been met, the circuitry may proceed to block 515. Alternatively, when the circuitry determines that the threshold for the memory device has not been met, the circuitry may continue to operate in the access mode, for example, at block 525.

[0090] At block 515, the circuitry may transmit a notification to the host device indicating that the threshold has been met. Transmission of the notification may include, for example, changing the state of a pin coupled to the host device (e.g., a multi-function or dedicated pin). In some other examples, the notification may be transmitted via sideband port communication (e.g., via an Inter-Integrated Circuit (I2C) bus or a Joint Test Action Group (JTAG) bus). The notification may be transmitted via one or more bits within a data packet. Additionally or alternatively, the notification may be stored in one or more bits of a register, and the host may poll the circuitry to determine the value stored in the register (e.g., via a pin or sideband port communication). The host device may take any number of responsive actions based on the notification. For example, in some cases, the host device may receive the notification and may block commands that may correspond to one or more portions of the memory array indicated by the threshold being met (e.g., not sending the commands to the memory device), may allow the memory device to continue normal operation (e.g., may determine that the access that generated the notification is legal or valid, or determine that continued operation of the memory device is mission-critical), or may block one or more applications from issuing subsequent access commands to the memory device. Additionally or alternatively, the circuit system may continue with block 520.

[0091] At block 520, the circuitry may optionally block access commands corresponding to a portion of the memory array. The controller may block access commands for a predetermined amount of time before proceeding to block 525. That is, the controller may cause a portion of the memory array to transition into a secure mode. In some cases, the controller may allow access commands issued from the host device to a portion of the memory array that is not operating in secure mode. That is, the circuitry may operate a portion of the memory array according to secure mode while operating some other portion of the memory array according to access mode.

[0092] At block 525, the circuitry may transition the entire memory array to an access mode of operation. That is, the controller may resume executing access commands (eg, all access commands) issued from the host device to the memory array.

[0093] Figure 6 An example of a process flow 600 that supports row hammer protection techniques for a memory device is described. In some examples, process flow 600 can implement aspects of systems 100 and 300, memory die 200, and process flows 400 and 500. Process flow 600 can include operations performed by application 605, which can be an instance of software running on a processor. Host 610 can be a reference Figure 1 、 3, 4 and 5. The application 605 may be executed on a processor separate from the host 610. Alternatively, the application 605 may be executed on a processor that is a component of the host 610. The memory device 615 may be a reference Figures 1 to 5 Examples of memory devices (eg, memory device 110, memory die 160, memory die 200, or memory device 310) are described.

[0094] Application 605 may issue access commands 620, which may be logical or virtual memory access commands. Host 610 may execute access commands 620, which may cause host 610 to perform memory functions on memory device 615. Host 610 may transmit access commands 625 to memory device 615. Memory device 615 may operate according to an access mode, which may include executing all access commands received from host 610.

[0095] At 630, memory device 615 can detect a redundant row access (e.g., row hammer) condition. In some cases, memory device 615 can detect the redundant row access condition by determining that a metric (e.g., number or pattern) associated with access commands, including access command 625, satisfies a threshold associated with access commands for memory device 615.

[0096] The memory device 615 may transmit an indication 635 of the detected excess row access condition to the host 610. The indication 635 may include an indication of the row, row group, or bank associated with the detected excess row access condition. At 645, the memory device 615 may optionally enter a secure mode. The secure mode may restrict access to at least one row (e.g., a row, a row group, a bank, a plurality of banks) of a memory array of the memory device 615.

[0097] At 640, the host 610 may perform workaround measures for the redundant row access condition detected by the memory device 615. In some cases, the workaround measures may include causing the memory device 615 to enter a safe mode (e.g., self-refresh mode). Alternatively, the host 610 may prevent commands executed by the application 605 from generating memory access commands to at least a portion of the memory device 615. That is, the host 610 may not transmit access commands to the memory device that access a row, a group of rows, or one or more banks associated with the detected redundant row access condition. For example, the host 610 may process the access command 650 that requires access to the memory device 615 instead of executing the access command to the memory device 615. In some other cases, the host 610 may account for the redundant row access condition by, for example, temporarily switching to a redundant memory device. That is, any commands executed based on the application 605 may be transmitted to and / or executed by a memory device other than the memory device 615. In some other cases, the host 610 can circumvent the excess row access condition by shutting down the application 605 (e.g., suspending execution of commands from the application 605). The shutting down can be temporary (e.g., the host 610 can shut down the application 605 for a predetermined amount of time to react to the excess row access condition indication). Additionally or alternatively, the shutting down can occur based on the timing of a refresh operation (e.g., the host 610 can shut down the application 605 for the amount of time necessary to refresh one or more banks in the memory device 615 associated with the detected excess row access condition).

[0098] Host 610 may optionally cause a reset command 655 to be transmitted to memory device 615 to cause memory device 615 to transition from secure mode to access mode. That is, host 610 may transmit reset command 655 to memory device 615 if memory device 615 has already entered secure mode. For example, if the command received from host 610 is associated with one or more banks corresponding to a detected excess row access condition, the controller associated with memory device 615 may not execute the command. At 655, host 610 may transmit a reset command, triggering memory device 615 to transition from secure mode to access mode. The command to reset to access mode may include a single command, or a sequence of commands that may be known to host 610 and memory device 615. Memory device 615 may recognize the command sequence and transition from secure mode to access mode (not shown).

[0099] Figure 7A block diagram 700 is shown of a circuit system 705 that supports row hammer protection for a memory device as disclosed herein. The circuit system 705 can be an example of aspects of a controller, a memory interface, a redundant row access detection circuit, or a threshold storage device as described herein. The circuit system 705 can include a threshold identifier 710, an access command receiver 715, a threshold determination component 720, a mode switching component 725, a command sequence component 730, a refresh mode component 735, a command inhibition component 740, and an indication component 745. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0100] Threshold identifier 710 may identify a threshold value for row access of a memory array, the memory array including a row set. In some examples, threshold identifier 710 may identify a threshold value for row access of a memory array, the memory array including a row set. In some examples, threshold identifier 710 may receive signaling from a host indicating a second threshold value for row access, wherein the identified threshold value is based on the second threshold value. In some examples, threshold identifier 710 may determine the threshold value by comparing the second threshold value with a third threshold value (e.g., a preconfigured threshold value) stored in a non-volatile memory. In some examples, threshold identifier 710 may determine the threshold value based on a minimum value of the second threshold value received from the host and the third threshold value stored in the non-volatile memory.

[0101] The access command receiver 715 may receive a row access command for the memory array from the host in a first operating mode. For example, the first operating mode may be an access mode as described herein. In some examples, the access command receiver 715 may receive a row access command set for the memory array from the host. In some examples, the access command receiver 715 may receive a row access command for a second row of the memory array. In some examples, the access command receiver 715 may receive a command sequence from the host indicating the operating mode based on transmitting the indication to the host.

[0102] Threshold determination component 720 can determine, for rows in a row set, that a metric of row access commands satisfies a threshold. In some examples, threshold determination component 720 can determine, for rows in a row set, that a pattern or metric of a set of row access commands satisfies a threshold.

[0103] The mode switching component 725 can switch the memory array from a first operating mode to a second operating mode based on determining that a metric of a row access command satisfies a threshold, wherein the second operating mode is associated with restricting access to at least one row in a set of rows of the memory array. For example, the second operating mode can be a secure mode as described herein.

[0104] In some examples, the mode switching component 725 may switch the memory array from the second mode to the first mode based on receiving the command sequence. In some examples, the mode switching component 725 may start a timer immediately after switching the memory array from the first mode to the second mode. In some examples, the mode switching component 725 may switch the memory array from the second mode to the first mode based on the expiration of the timer. In some examples, the mode switching component 725 may select the second operating mode from the set of operating modes according to a configured setting. In some examples, the mode switching component 725 may cause the second bank of the memory array to operate in the first mode.

[0105] The command sequence component 730 can receive a command sequence from a host operating in the second mode to reset the memory array to the first mode.

[0106] The refresh mode component 735 can cause a first bank of the memory array associated with the row to operate in a self-refresh mode.In some examples, the refresh mode component 735 can cause a set of banks of the memory array to operate in a self-refresh mode.

[0107] The command suppression component 740 can suppress row access commands to the memory array bank associated with the row. In some examples, the command suppression component 740 can suppress access to a second row of the memory array based on receiving a row access command for the second row. In some cases, the second row and the row are the same row.

[0108] The indication component 745 can transmit an indication to the host based on determining that the pattern of the set of row access commands satisfies a threshold.

[0109] Figure 8 A flowchart illustrating a method 800 for supporting row hammer protection for a memory device as disclosed herein is shown. The operations of method 800 may be implemented by a device or components thereof as described herein. For example, the operations of method 800 may be performed by circuitry as described herein. In some examples, the device may execute an instruction set to control functional elements of the device to perform the functions described below. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the functions described below.

[0110] At 805, the device may identify a threshold for row access of a memory array comprising a row set. The operations of 805 may be performed according to the methods described herein. In some examples, the threshold may be determined by reference to Figure 7 Aspects of the operations of the threshold identifier 805 are described.

[0111] At 810, the device may receive a row access command for a memory array from a host in a first operating mode. For example, the first operating mode may be an access mode as described herein. The operations of 810 may be performed according to the methods described herein. In some examples, the device may be referred to as Figure 7 Aspects of the operations of the access command receiver 810 are described.

[0112] At 815, the device may determine, for a row in the row set, that a metric for a row access command set satisfies a threshold. The operations of 815 may be performed according to the methods described herein. In some examples, the reference Figure 7 Aspects of the operation of the threshold determination component execution 815 are described.

[0113] At 820, the device may switch the memory array from a first operating mode to a second operating mode based on determining that a metric of a row access command satisfies a threshold, wherein the second operating mode is associated with restricting access to at least one row in a row set of the memory array. For example, the second operating mode may be a security mode as described herein. The operations of 820 may be performed according to the methods described herein. In some examples, the operation may be performed by reference to Figure 7 The described mode switching component performs aspects of the operations of 820 .

[0114] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for: identifying a threshold for row access of a memory array, the memory array comprising a plurality of rows; receiving a row access command for the memory array from a host in a first operating mode; determining, for a row in the plurality of rows, that a metric of the row access command satisfies the threshold; and switching the memory array from the first operating mode to a second operating mode based at least in part on determining that the metric of the row access command satisfies the threshold, wherein the second operating mode is associated with restricting access to at least one row in the plurality of rows of the memory array.

[0115] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for: receiving a command sequence from the host operating in the second mode to reset the memory array to the first mode; and switching the memory array from the second mode to the first mode based on receiving the command sequence.

[0116] In some examples, the methods and apparatus described herein may additionally include processes, features, means, or instructions for: starting a timer upon causing the memory array to switch from the first mode to the second mode; and causing the memory array to switch from the second mode to the first mode based on expiration of the timer.

[0117] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for receiving signaling from the host indicating a second threshold for row access, wherein identifying the threshold may be based on the second threshold.

[0118] In some examples of the methods and apparatus described herein, the threshold identifying row accesses may include processes, features, means, or instructions for determining the threshold by comparing the second threshold to a third threshold that may be stored in non-volatile memory.

[0119] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for selecting the second operating mode from a set of operating modes according to configured settings.

[0120] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for: while causing the memory array to operate in the second mode, causing a first bank of the memory array associated with the row to operate in a self-refresh mode; and causing a second bank of the memory array to operate in the first mode.

[0121] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for causing a bank of the memory array to operate in a self-refresh mode while causing the memory array to operate in the second mode.

[0122] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for suppressing row access commands to a bank of the memory array associated with the row while operating the memory array in the second mode.

[0123] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for: receiving a row access command for a second row of the memory array while operating the memory array in the second mode; and inhibiting access to the second row of the memory array based on receiving the row access command for the second row.

[0124] In some examples of the methods and apparatus described herein and the non-transitory computer-readable media described herein, the second row and the row may be the same row.

[0125] Figure 9 A flowchart illustrating a method 900 for supporting row hammer protection for a memory device as disclosed herein is shown. The operations of method 900 may be implemented by a device or components thereof as described herein. For example, the operations of method 900 may be performed by circuitry as described herein. In some examples, the device may execute an instruction set to control functional elements of the device to perform the functions described below. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the functions described below.

[0126] At 905, the device may identify a threshold for row access of a memory array comprising a row set. The operations of 905 may be performed according to the methods described herein. In some examples, the threshold may be determined by reference to Figure 7 Aspects of the operations of the threshold identifier 905 are described.

[0127] At 910, the device may receive a row access command set for a memory array from a host. The operations of 910 may be performed according to the methods described herein. In some examples, the device may receive a row access command set for a memory array from a host. Figure 7 Aspects of the operations of the access command receiver 910 are described.

[0128] At 915, the device may determine, for a row in the row set, whether a pattern or metric of a row access command set satisfies a threshold. The operation of 915 may be performed according to the methods described herein. In some examples, the method may be referenced by Figure 7 Aspects of the operation of the threshold determination component execution 915 are described.

[0129] At 920, the device may transmit an indication to the host based on determining that the pattern of the row access command set meets the threshold. The operations of 920 may be performed according to the methods described herein. In some examples, the reference Figure 7 The described aspects of the operation of the instruction component perform 920.

[0130] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for: identifying a threshold for row access of a memory array, the memory array comprising a row set; receiving a row access command set for the memory array from a host; determining, for a row in the row set, that a pattern of the row access command set satisfies the threshold; and transmitting an indication to the host based on determining that the pattern of the row access command set satisfies the threshold.

[0131] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for determining the threshold based on a minimum of a second threshold received from the host and a third threshold stored in non-volatile memory.

[0132] Some examples of the methods and apparatus described herein may additionally include processes, features, means, or instructions for receiving a command sequence from the host indicating an operating mode based on transmitting the indication to the host.

[0133] It should be noted that the methods described herein describe possible embodiments, and that operations and steps may be rearranged or otherwise modified, and that other embodiments are possible. Additionally, aspects from two or more methods may be combined.

[0134] In some examples, an apparatus or device may use general-purpose or special-purpose hardware to perform aspects of the functionality described herein. The apparatus or device may include a memory array having a row set; a memory interface coupled to the memory array and a host, the memory interface operable to receive a row access command from the host; and circuitry coupled to the memory array and the memory interface. The circuitry may be operable to execute the row access command on the memory array in a first operating mode; determine, for a row in the row set, that a metric of the row access command satisfies a threshold; and based on determining that the metric of the row access command satisfies the threshold, switch the memory array from the first operating mode to a second operating mode, wherein the second operating mode is associated with restricting access to at least one row in the row set of the memory array.

[0135] In some examples, the circuit system may be operable to, while causing the memory array to operate in the second mode, receive a command sequence from the host via the memory interface for resetting the memory array to the first mode; and based on receiving the command sequence, cause the memory array to switch to the first mode.

[0136] In some examples, the circuitry may be operable to initiate a timer upon switching the memory array from the first mode to the second mode; and switch the memory array from the second mode to the first mode based on expiration of the timer.

[0137] In some examples, the circuitry may be operable to identify the threshold based on comparing a second threshold received from the host with a third threshold that may be stored in non-volatile memory.

[0138] In some examples, the circuitry may be operable to select the second operating mode from a set of operating modes according to a configured setting.

[0139] In some examples, the circuitry may be operable to cause a first bank of the memory array associated with the row to operate in a self-refresh mode; and cause a second bank of the memory array to operate in a mode different from the self-refresh mode.

[0140] In some examples, the circuitry may be operable to cause a bank of the memory array to operate in a self-refresh mode.

[0141] In some examples, the circuitry may be operable to determine whether to execute the row access command for at least some of the banks of the memory array.

[0142] In some examples, the circuitry can be operable to receive a row access command for a second row of the memory array; and inhibit access to the second row of the memory array after receiving the row access command. In some examples, the second row and the row can be the same row.

[0143] In some examples, the apparatus or device may include a memory array having a row set; a memory interface coupled to the memory array and a host, the memory interface operable to receive a row access command from the host; and circuitry coupled to the memory array and the memory interface. The circuitry may be operable to execute the row access command on the memory array; determine, for a row in the row set, that executing the row access command satisfies the threshold; and transmit, via the memory interface, to the host an indication that executing the row access command satisfies the threshold.

[0144] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have multiple bit widths.

[0145] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed circuits based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0146] The term "isolation" refers to a relationship between components where signals cannot flow between them. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller isolates two components, it prevents signals from flowing between them using the conductive path that previously allowed signal flow.

[0147] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0148] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., most of the carriers are signals), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0149] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "superior" to other examples. The detailed description includes specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0150] In the accompanying drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0151] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0152] The various illustrative blocks and modules described in conjunction with the present disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0153] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including being distributed so that parts of the functions are implemented in different physical locations. Furthermore, as used herein, including in the claims, the term "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0154] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disc storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code devices in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0155] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: identifying a threshold for access of a memory array, the memory array comprising dynamic random access memory cells; In an access operation mode, receiving an access command for the memory array from a host; determining, based at least in part on receiving the access command, that a counter associated with a first bank of the memory array satisfies the threshold; and Based at least in part on determining that the counter satisfies the threshold, switching the memory array from the access operating mode to a first secure operating mode of a plurality of secure operating modes, wherein the first secure operating mode is associated with an inhibit command to each of a plurality of banks of the memory array including the first bank, and a second secure operating mode of the plurality of secure operating modes is associated with an inhibit command to the first bank of the memory array.

2. The method according to claim 1, further comprising: receiving a command sequence from the host operating in the first secure operating mode to reset the memory array to the access operating mode; and Based at least in part on receiving the command sequence, the memory array is switched from the first security operating mode to the access operating mode.

3. The method of claim 1 , further comprising: starting a timer immediately after switching the memory array from the access operating mode to the first security operating mode; and The memory array is switched from the first security operating mode to the access operating mode based at least in part on expiration of the timer.

4. The method of claim 1 , further comprising: Signaling is received from the host indicating a second threshold for access, wherein identifying the threshold is based at least in part on the second threshold.

5. The method of claim 4, wherein identifying the threshold of access comprises: The threshold is determined by comparing the second threshold to a third threshold stored in a non-volatile memory.

6. The method of claim 1 , further comprising: The first secure operating mode is selected from the plurality of secure operating modes according to configured settings.

7. The method of claim 1 , further comprising, while causing the memory array to operate in the second secure operating mode: causing the first bank of the memory array to operate in a self-refresh mode; and A second bank of the memory array is caused to operate in the access mode of operation.

8. The method of claim 1 , further comprising, while causing the memory array to operate in the first secure operating mode: Each bank of the memory array is operated in a self-refresh mode.

9. The method of claim 1 , further comprising, while causing the memory array to operate in the second secure operating mode: Access commands to the first bank of the memory array are suppressed.

10. The method of claim 1, further comprising, while causing the memory array to operate in the first secure operating mode: receiving an access command associated with the memory array; and Access for the memory array is inhibited based at least in part on receiving the access command associated with the memory array.

11. The method according to claim 1 , wherein: The access command is a row access command, and The counter includes an indication of a number of the row access commands associated with the first bank of the memory array.

12. A method comprising: identifying a threshold for access of a memory array, the memory array comprising dynamic random access memory cells; In an access operation mode, receiving a plurality of access commands for the memory array from a host; determining, based at least in part on receiving the plurality of access commands, that a pattern of the plurality of access commands associated with a first bank of the memory array satisfies the threshold; notifying the host that the pattern of the plurality of access commands associated with the first bank of the memory array satisfies the threshold; and A command sequence is received from the host based at least in part on notifying the host, indicating a first secure operating mode of a plurality of secure operating modes, wherein the first secure operating mode is associated with an inhibit command to each of a plurality of banks of the memory array including the first bank, and a second secure operating mode of the plurality of secure operating modes is associated with an inhibit command to the first bank of the memory array.

13. The method of claim 12, further comprising: The threshold is determined based at least in part on a minimum of a second threshold received from the host and a third threshold stored in non-volatile memory.

14. An apparatus comprising: a memory array having dynamic random access memory cells; a memory interface coupled to the memory array and a host, the memory interface being operable to receive an access command from the host; and circuitry coupled to the memory array and the memory interface, the circuitry being operable to: identifying a threshold for access to the memory array; executing the access command on the memory array in an access operation mode; determining, based at least in part on receiving the access command, that a counter associated with a first bank of the memory array satisfies the threshold; and Based at least in part on determining that the counter satisfies the threshold, switching the memory array from the access operating mode to a first secure operating mode of a plurality of secure operating modes, wherein the first secure operating mode is associated with an inhibit command to each of a plurality of banks of the memory array including the first bank, and a second secure operating mode of the plurality of secure operating modes is associated with an inhibit command to the first bank of the memory array.

15. The apparatus of claim 14, the circuit system further operable to: while causing the memory array to operate in the first secure operating mode, receiving from the host via the memory interface a command sequence for resetting the memory array to the access operating mode; and Based at least in part on receiving the command sequence, the memory array is switched to the access mode of operation.

16. The apparatus of claim 14, the circuit system further operable to: starting a timer immediately after switching the memory array from the access operating mode to the first security operating mode; and The memory array is switched from the first security operating mode to the access operating mode based at least in part on expiration of the timer.

17. The apparatus of claim 14, the circuit system further operable to: The threshold is identified based at least in part on comparing a second threshold received from the host to a third threshold stored in non-volatile memory.

18. The apparatus of claim 14, the circuit system further operable to: The first secure operating mode is selected from the plurality of secure operating modes according to configured settings.

19. The apparatus of claim 14, the circuitry further operable, when causing the memory array to operate in the second secure operating mode: causing the first bank of the memory array to operate in a self-refresh mode; and A second bank of the memory array is operated in a mode different from the self-refresh mode.

20. The apparatus of claim 14, the circuitry further operable, when causing the memory array to operate in the first secure operating mode: Each bank of the memory array is operated in a self-refresh mode.

21. The apparatus of claim 14, the circuitry further operable, when causing the memory array to operate in the second secure operating mode: A determination is made as to whether to execute the access command for a second bank of the memory array.

22. The apparatus of claim 14, the circuitry further operable, when causing the memory array to operate in the first secure operating mode: receiving an access command associated with the memory array; and Access for the memory array is inhibited after receiving the access command associated with the memory array.

23. An apparatus comprising: a memory array having dynamic random access memory cells; a memory interface coupled to the memory array and a host, the memory interface being operable to receive an access command from the host; and circuitry coupled to the memory array and the memory interface, the circuitry being operable to: identifying a threshold for access to the memory array; In an access operation mode, executing the access command on the memory array; determining that execution of the access command associated with a first bank of the memory array satisfies the threshold; notifying the host that execution of the access command associated with the first bank of the memory array satisfies the threshold based at least in part on executing the access command; and Receiving a command sequence from the host indicating a first secure operating mode of a plurality of secure operating modes based at least in part on notifying the host, wherein the first secure operating mode is associated with an inhibit command to each of a plurality of banks of the memory array including the first bank, and a second secure operating mode of the plurality of secure operating modes is associated with an inhibit command to the first bank of the memory array.

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