Semiconductor manufacturing apparatus, semiconductor manufacturing system, and semiconductor device manufacturing method

Abstract

The invention provides a semiconductor manufacturing apparatus, a semiconductor manufacturing system and a manufacturing method of a semiconductor device, which can recalculate an appearance inspection result after changing a reference point after appearance inspection. The semiconductor manufacturing apparatus includes a mounting head, a substrate recognition camera, and a control device. The control device is configured to: (a) capture an image of a product-use bare chip mounted on a product-use substrate by a mounting head, together with the product-use substrate, by means of a substrate recognition camera, and acquire an image; (b) checking the relative positions of the bare chip for the product and the substrate for the product on the basis of the image and the pre-recorded positioning model position of the bare chip for the reference, the positioning model position of the substrate for the reference, the checking reference position of the bare chip for the reference, and the checking reference position of the substrate for the reference; and (c) recording the positioning pattern position of the bare chip for the product and the positioning pattern position of the substrate for the product, which are calculated on the basis of the positioning model position of the bare chip for reference and the positioning model position of the substrate for reference.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing apparatus, and can be applied to, for example, a die mounter having a visual inspection function for accuracy confirmation. Background Art

[0002] As a process in the manufacturing process of semiconductor devices, a bare chip separated from a wafer is picked up by a chip mounting device (semiconductor manufacturing device) such as a chip mounter, and the picked-up bare chip is mounted on a substrate. In addition, in the chip mounter, a camera is used to capture an image of the substrate (inspection object) on which the bare chip is mounted, and a relative position inspection (appearance inspection) of the bare chip and the substrate is performed based on the image. In this relative position inspection, the center of the bare chip and the center of the tab (package area of ​​the substrate) are sometimes used as reference positions (reference points) (for example, Japanese Patent Gazette No. 2022-98312).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-98312 Summary of the invention

[0006] For example, when the inspection object carried out of a semiconductor manufacturing apparatus is subjected to the above-mentioned appearance inspection at a reference point different from the reference point in the semiconductor manufacturing apparatus, different offset amounts are calculated even if the relative positions of the bare chip and the substrate are the same.

[0007] The present invention aims to provide a technique for recalculating the appearance inspection result even if the reference point is changed after the appearance inspection. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0008] The outline of the representative aspects of the present invention will be briefly described as follows.

[0009] That is, the semiconductor manufacturing device includes a mounting head, a substrate recognition camera, and a control device. The control device is configured to (a) use the substrate recognition camera to capture an image of the product bare chip mounted on the product substrate by the mounting head together with the product substrate, (b) inspect the relative position of the product bare chip and the product substrate based on the image and the pre-recorded positioning model position of the reference bare chip, the positioning model position of the reference substrate, the inspection reference position of the reference bare chip, and the inspection reference position of the reference substrate, and (c) record the positioning pattern position of the product bare chip and the positioning pattern position of the product substrate calculated based on the positioning model position of the reference bare chip and the positioning model position of the reference substrate.

[0010] Effects of the Invention

[0011] According to the present invention, it is possible to recalculate the appearance inspection result after changing the reference point after the appearance inspection. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic plan view showing a configuration example of a die mounter in the embodiment.

[0013] Figure 2 It is explained in Figure 1 A diagram of the schematic structure when viewed from the direction of arrow A.

[0014] Figure 3 Yes means Figure 1 A block diagram showing a schematic configuration of a control system for a chip mounter.

[0015] Figure 4 It means use Figure 1 A flow chart of a method for manufacturing a semiconductor device using a chip mounter is shown.

[0016] Figure 5 This is a flowchart for explaining the teaching operation.

[0017] Figure 6 It is a diagram showing positioning patterns and reference points in a reference substrate and a reference bare chip.

[0018] Figure 7 The diagram shows the positioning pattern in the product substrate and the product bare chip.

[0019] Figure 8 This is a flowchart for explaining the inspection operation.

[0020] Fig. 9 The diagram shows examples of the registration coordinates of the positioning model, the inspection reference point coordinates at the time of registration, the measurement position coordinates of the positioning pattern, and the calculated inspection reference point coordinates.

[0021] Fig.10 It is a diagram for explaining reference points of a substrate and reference points of a bare chip.

[0022] Fig.11 It is a diagram for explaining reference points of a substrate and reference points of a bare chip.

[0023] Fig.12 This is a diagram for explaining an example in which different offset amounts are calculated due to different reference points for inspection.

[0024] Description of Reference Numerals

[0025] 1. Chip mounter (semiconductor manufacturing equipment)

[0026] 41···Placement head

[0027] 44···Substrate recognition camera

[0028] 80···Control unit (control device) DETAILED DESCRIPTION

[0029] The following are explanations of the embodiments and variations using the accompanying drawings. However, in the following description, the same structural elements are sometimes marked with the same reference numerals and repeated descriptions are omitted. In addition, in order to make the description clearer, there are cases where the width, thickness, shape, etc. of each part are schematically shown in the accompanying drawings compared with the actual state. In addition, the relationship between the dimensions of each element, the ratio of each element, etc. may not be consistent between multiple drawings.

[0030] use Figure 1 and Figure 2 The structure of a die mounter as one embodiment of a semiconductor manufacturing apparatus will be described. Figure 1 It is a schematic plan view showing a configuration example of a die mounter in the embodiment. Figure 2 It is explained in Figure 1 A diagram of the schematic structure when viewed from the direction of arrow A.

[0031] The die mounter 1 generally includes a wafer supply unit 10, a pickup unit 20, an intermediate stage unit 30, a mount unit 40, a conveying unit 50, a substrate supply unit 60, a substrate unloading unit 70, and a control unit (control device) 80. The Y2-Y1 direction is the front-to-back direction of the die mounter 1, the X2-X1 direction is the left-to-right direction, and the Z1-Z2 direction is the up-down direction. The wafer supply unit 10 is arranged at the front side of the die mounter 1, and the mount unit 40 is arranged at the rear side.

[0032] The wafer supply unit 10 includes a wafer cassette elevator 11 , a wafer holding table 12 , a peeling unit 13 , and a wafer recognition camera 14 .

[0033] The wafer box elevator 11 moves a wafer box (not shown) storing a plurality of wafer rings WR up and down to a wafer transfer height. A wafer correction tank (not shown) performs alignment of the wafer ring WR supplied from the wafer box elevator 11. A wafer extractor (not shown) takes out a wafer box from the wafer ring WR and supplies it to the wafer holding table 12, or takes it out from the wafer holding table 12 and stores it in a wafer box.

[0034] A wafer W is bonded (attached) to the dicing tape DT, and the wafer W is divided into a plurality of bare chips D. The dicing tape DT is held by a wafer ring WR. The wafer W is, for example, a semiconductor wafer, and the bare chips D are semiconductor chips. A film-like adhesive material DF called a die attach film (DAF) is attached between the wafer W and the dicing tape DT. The adhesive material DF is cured by heating.

[0035] The wafer holding table 12 moves in the X1-X2 direction and the Y1-Y2 direction by a driving unit not shown in the figure, so that the bare chip D to be picked up is moved to the position of the peeling unit 13. In addition, the wafer holding table 12 rotates the wafer ring WR in the XY plane by a driving unit not shown in the figure. The peeling unit 13 moves in the up-down direction by a driving unit not shown in the figure. The peeling unit 13 peels the bare chip D from the dicing tape DT.

[0036] The wafer recognition camera 14 recognizes the pick-up position of the bare chip D picked up from the wafer W, and performs a surface inspection of the bare chip D.

[0037] The pickup unit 20 has a pickup head 21 and a pickup head table (PHT) 23. The pickup head 21 is provided with a collet 22 for adsorbing and holding the stripped bare chip D at the front end. The pickup head 21 picks up the bare chip D from the wafer supply unit 10 and places it on the intermediate stage 31. The pickup head table 23 moves the pickup head 21 in the Z1-Z2 direction, the Y1-Y2 direction, and the X1-X2 direction. In addition, the pickup head table 23 can also rotate the pickup head 21.

[0038] The intermediate stage section 30 includes an intermediate stage 31 for placing a bare chip D, and a stage recognition camera 34 for recognizing the bare chip D on the intermediate stage 31. The intermediate stage 31 includes a suction hole for adsorbing the placed bare chip D. The placed bare chip D is temporarily held on the intermediate stage 31. The intermediate stage 31 is a placement stage for placing the bare chip D, and is also a pick-up stage for picking up the bare chip D.

[0039] The mounting section 40 includes a mounting head 41, a mounting head table (BHT) 43, a substrate recognition camera 44, and a mounting platform 46. The mounting head 41 is provided with a collet 42 that holds the bare chip D at the front end by suction. The mounting head table moves the mounting head 41 in the Z1-Z2 direction, the Y1-Y2 direction, and the X1-X2 direction. In addition, the mounting head table 43 can also rotate the mounting head 41. The substrate recognition camera 44 photographs the substrate S and recognizes the mounting position. Here, the substrate S includes, for example, a wiring substrate and a lead frame. A plurality of product areas (hereinafter referred to as package areas P) that eventually become one package are formed on the substrate S. In addition, position recognition marks (not shown) of the package areas P are formed on the substrate S. When the bare chip D is placed on the substrate S, the mounting platform 46 rises to support the substrate S from below. The mounting platform 46 has a suction port (not shown) for vacuum adsorption of the substrate S, and can fix the substrate S. The mounting platform 46 has a heating section (not shown) for heating the substrate S.

[0040] With such a structure, the placement head 41 corrects the pickup position and posture based on the shooting data of the stage recognition camera 34, and picks up the bare chip D from the intermediate stage 31. In addition, the placement head 41 performs placement on the packaging area P of the substrate S based on the shooting data of the substrate recognition camera 44, or performs placement in the form of stacking on the bare chip already mounted on the packaging area P of the substrate S.

[0041] The conveying section 50 includes a conveying claw 51 for gripping and conveying the substrate S and a conveying channel 52 for moving the substrate S. The substrate S is moved in the X1 direction by a nut (not shown) provided on the conveying claw 51 of the conveying channel 52 driven by a ball screw (not shown) provided along the conveying channel 52. With such a structure, the substrate S moves from the substrate supply section 60 along the conveying channel 52 to the mounting position, and after mounting, moves to the substrate unloading section 70, and the substrate S is delivered to the substrate unloading section 70.

[0042] The substrate supply unit 60 takes out the substrate S held in the transport jig and carried in from the transport jig and supplies it to the transport unit 50. The substrate unloading unit 70 holds the substrate S transported by the transport unit 50 in the transport jig.

[0043] Next, use Figure 3 The control unit 80 will be described. Figure 3 Yes means Figure 1 A block diagram showing a schematic configuration of a control system for a chip mounter.

[0044] The control system 8 includes a control unit (control device) 80, a drive unit 86, a signal unit 87, and an optical system 88. The control unit 80 is generally configured as a computer having a control and computing device 81 mainly composed of a CPU (Central Processing Unit), a storage device 82, an input / output device 83, a bus 84, and a power supply unit 85. The storage device 82 includes a main storage device 82a and an auxiliary storage device 82b. The main storage device 82a is composed of a RAM (Random Access Memory) storing a processing program, etc. The auxiliary storage device 82b is composed of a HDD (Hard Disk Drive) or SSD (Solid State Drive) storing control data and image data required for control, etc. In addition, an external storage device can be connected to the control unit 80.

[0045] The input / output device 83 includes a monitor 83a for displaying device status and information, a touch panel 83b for inputting operator instructions, a mouse 83c for operating the monitor 83a, and an image capture device 83d for capturing image data from the optical system 88. The input / output device 83 also includes a motor control device 83e and an I / O signal control device 83f. The motor control device 83e controls the XY stage (not shown) of the wafer supply unit 10, the pickup head stage 23, the drive unit of the placement head stage 43, the drive unit of the peeling unit 13, and the like. The I / O signal control device 83f captures signals from a signal unit 87 including various sensors and switches or knobs for controlling the brightness of a lighting device, etc., or performs control. The optical system 88 includes a wafer recognition camera 14, a stage recognition camera 34, and a substrate recognition camera 44. The wafer recognition camera 14, the stage recognition camera 34, and the substrate recognition camera 44 convert light intensity and color into numerical values. The control and calculation device 81 takes in necessary data via the bus 84 and performs calculations, controls the pickup head 21 and the like, and sends information to the monitor 83a and the like.

[0046] The control unit 80 stores the image data captured by the wafer recognition camera 14, the stage recognition camera 34, and the substrate recognition camera 44 in the storage device 82 via the image capture device 83d. The control and computing device 81 uses software programmed based on the stored image data to perform positioning of the bare chip D and the packaging area P of the substrate S, and to perform appearance inspection of the bare chip D and the substrate S. The control and computing device 81 uses software to operate the drive unit 86 with the help of the motor control device 83e based on the calculated positions of the bare chip D and the packaging area P of the substrate S. Through this process, the bare chip on the wafer is positioned, and the pickup head worktable 23 and the placement head worktable 43 are operated to place the bare chip D on the packaging area P of the substrate S.

[0047] The control unit 80 can be configured by installing the above-mentioned program stored in an external storage device into a computer. The external storage device includes, for example, an HDD, a USB memory, an SSD, etc. The auxiliary storage device 82b and the external storage device constitute a computer-readable recording medium. Hereinafter, they are collectively referred to as recording media. When the term recording medium is used in this specification, there is a case where only the auxiliary storage device 82b is included, only the external storage device is included, or both of them are included. In addition, the provision of programs and data to the computer and the provision of programs and data from the computer to the external device can also be carried out without using an external storage device, but using communication means such as the Internet or a dedicated line.

[0048] use Figure 4 A part of the manufacturing process of the semiconductor device (the manufacturing method of the semiconductor device) using the die mounter 1 will be described. Figure 4 It means using Figure 1 In the following description, the operation of each part constituting the die mounter 1 is controlled by the control unit 80 .

[0049] (Wafer loading process: process S1)

[0050] The wafer ring WR is supplied to the wafer cassette of the wafer cassette elevator 11. The supplied wafer ring WR is supplied to the wafer holding table 12.

[0051] (Substrate loading process: process S2)

[0052] The transport jig storing the substrate S is supplied to the substrate supply unit 60 . The substrate S is taken out from the transport jig in the substrate supply unit 60 , and the substrate S is fixed to the transport claw 51 .

[0053] (Picking process: process S3)

[0054] After step S1, the wafer holding table 12 is moved so that the desired bare chip D can be picked up from the dicing tape DT. The bare chip D is photographed by the wafer recognition camera 14, and the bare chip D is positioned and surface inspected based on the image data obtained by the photographing. By performing image processing on the image data, the offset (X, Y, θ directions) of the bare chip D on the wafer holding table 12 from the bare chip position reference point of the chip mounter is calculated and positioned. In addition, with respect to the bare chip position reference point, the predetermined position of the wafer holding table 12 is set as the initial setting of the device in advance and maintained. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0055] The positioned bare chip D is peeled from the dicing tape DT by the peeling unit 13 and the pickup head 21. The bare chip D peeled from the dicing tape DT is sucked and held by the collet 22 provided on the pickup head 21, and is conveyed to the intermediate stage 31 and placed.

[0056] The bare chip D on the intermediate stage 31 is photographed by the stage recognition camera 34, and the bare chip D is positioned and inspected on the surface based on the image data obtained by the photographing. By performing image processing on the image data, the offset (X, Y, θ directions) of the bare chip D on the intermediate stage 31 from the bare chip position reference point of the chip mounter is calculated and positioned. In addition, regarding the bare chip position reference point, the predetermined position of the intermediate stage 31 is set as the initial setting of the device in advance and maintained. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0057] The pickup head 21 that has conveyed the bare chip D to the intermediate stage 31 returns to the wafer supply unit 10. Following the above-described steps, the next bare chip D is peeled from the dicing tape DT, and thereafter, the bare chips D are peeled one by one from the dicing tape DT following the same steps.

[0058] (Mounting process: process S4)

[0059] The substrate S is transported to the mounting platform 46 by the transport unit 50. The substrate S placed on the mounting platform 46 is photographed by the substrate recognition camera 44, and image data is acquired by photographing. By performing image processing on the image data, the offset (X, Y, θ directions) of the substrate S from the substrate position reference point of the chip mounter 1 is calculated. In addition, regarding the substrate position reference point, the predetermined position of the mounting unit 40 is set as the initial setting of the device in advance and maintained.

[0060] The suction position of the mounting head 41 is corrected according to the offset of the bare chip D on the intermediate stage 31 calculated in step S3, and the bare chip D is sucked by the collet 42. The mounting head 41 that has sucked the bare chip D from the intermediate stage 31 mounts the bare chip D on a predetermined position of the substrate S supported on the mounting stage 46. The bare chip D mounted on the substrate S is photographed by the substrate recognition camera 44, and based on the image data obtained by the photographing, an inspection is performed to determine whether the bare chip D is mounted at the desired position (inspection of the relative position of the bare chip D and the substrate S), etc.

[0061] The mounting head 41 that mounted the bare chip D on the substrate S returns to the intermediate stage 31. Following the above steps, the next bare chip D is picked up from the intermediate stage 31 and mounted on the substrate S. This step is repeated to mount the bare chips D on all the packaging areas P of the substrate S.

[0062] (Substrate unloading process: process S5)

[0063] The substrate S on which the bare chip D is mounted is transported to the substrate unloading unit 70. In the substrate unloading unit 70, the substrate S is taken out from the transport claw 51 and stored in a transport jig. The transport jig storing the substrate S is unloaded from the die mounter 1.

[0064] As described above, the bare chip D is mounted on the substrate S and is carried out from the die mounter 1. Then, for example, the transport jig holding the substrate S on which the bare chip D is mounted is transported to the wire bonding step, and the electrodes of the bare chip D are electrically connected to the electrodes of the substrate S via the Au wire or the like. Then, the substrate S is transported to the injection molding step, and the bare chip D and the Au wire are sealed with an injection resin (not shown), thereby completing the semiconductor package.

[0065] In the case of stacking, the wire bonding process is followed, and the conveying jig carrying the substrate S with the bare chip D mounted thereon is carried into the die mounter and the bare chip D is stacked on the bare chip D mounted on the substrate S. After being carried out of the die mounter, the bare chip D is electrically connected to the electrode of the substrate S via the Au wire in the wire bonding process. The bare chip D above the second layer is peeled off from the dicing tape DT by the above method, and then conveyed to the mounting section and stacked on the bare chip D. After repeating the above process for a predetermined number of times, the substrate S is conveyed to the injection molding process, and a plurality of bare chips D and the Au wire are sealed with an injection resin (not shown), thereby completing the stacking package.

[0066] use Figures 5 to 8 The relative position inspection of the bare chip D and the substrate S (also referred to as the appearance inspection of the mounting position accuracy) will be described. Figure 5 This is a flowchart for explaining the teaching operation. Figure 6 It is a diagram showing positioning patterns and reference points in a reference substrate and a reference bare chip. Figure 7 The diagram shows the positioning pattern in the product substrate and the product bare chip. Figure 8 This is a flowchart for explaining the inspection operation.

[0067] The appearance inspection of the mounting position accuracy is performed by bare chip positioning and substrate positioning. The positioning algorithm mainly uses pattern matching (search algorithm using template matching) using a template model (positioning model), and is set to operate under a commonly known normalized correlation. The result is set as the consistency rate. Template matching has a teaching action for reference learning and an inspection action in the production of product assembly.

[0068] Figure 5 The teaching action shown is in Figure 4 This is an action performed before the placement process shown (continuous action during mass production).

[0069] (Step S11)

[0070] The control unit 80 acquires a reference image by photographing the reference component using the substrate recognition camera 44. Here, the reference component is the substrate S on which the reference bare chip D is mounted.

[0071] (Step S12)

[0072] The control unit 80 stores the position (coordinates) of the reference point of the reference component in the storage device. Figure 6 The reference point SR of the substrate S and the reference point DR of the bare chip D are shown. The coordinates of the reference point SR are set to P SR . Set the coordinates of the reference point DR to P DR. The reference point SR is, for example, calculated based on the boundary pattern of the packaging area P drawn on the substrate S (for example, the center point of the packaging area P) or a specific pattern. The reference point DR is, for example, calculated based on the edge of the bare chip D (for example, the center point of the bare chip D) or a specific pattern. In addition, the entry is not temporarily stored in the main storage device 82a, but is saved to the auxiliary storage device 82b and / or the external storage device in a manner that can be used in subsequent processes. The data entered in the teaching action can be used during mass production and when recalculating the appearance inspection results described later. In addition, the data entered in the inspection action described later can be used when recalculating the appearance inspection results.

[0073] (Step S13)

[0074] The control unit 80 sets the unique area containing the characteristic pattern selected from the reference image by the operator of the die mounter using the human-machine interface (touch panel 83b or mouse 83c) as the positioning model. Here, the characteristic pattern of the unique area is, for example, Figure 6 A cross-shaped position identification mark as shown in FIG. A wiring (lead) having a characteristic pattern (e.g., an L-shaped pattern) or a circular lead formed in the wiring of the substrate S may be used as a position identification mark. In addition, a pad formed on the bare chip D may be used as a position identification mark.

[0075] Then, the control unit 80 calculates the position (coordinates) of the positioning model, saves it, and records it in the storage device. Below, as a positioning model, an example of using positioning models SM1 and SM2 of two substrates and positioning models DM1 and DM2 of two bare chips is described. The positions of the positioning models SM1 and SM2 of the substrate are set to Pa1 and Pa2. The positions of the positioning models DM1 and DM2 of the bare chips are set to Pc1 and Pc2. In addition, the positioning model of the substrate and the positioning model of the bare chip can also be one each.

[0076] (Step S14)

[0077] The control unit 80 stores the positional relationship (coordinates) between the positioning model and the reference point of the reference member in the storage device. SM1 , P SM2 The positional relationship between the substrate reference point SR and the substrate positioning models SM1 and SM2 is defined as Pb1 and Pb2. The coordinates of the bare chip positioning models DM1 and DM2 are defined as P DM1 , P DM2 The positional relationship between the reference point DR of the bare chip and the positioning models DM1 and DM2 of the bare chip is represented by Pd1 and Pd2.

[0078] (Step S15)

[0079] The control unit 80 stores and records the image of the positioning model (hereinafter referred to as the model image) in the storage device 82 .

[0080] Next, use Figure 7 and Figure 8 right Figure 4 The inspection operation during the production process (continuous operation process during mass production) in the mounting process shown will be described.

[0081] (Step S21)

[0082] In step S21, the control unit 80 captures a product image by using the substrate recognition camera 44. Here, the product component is the substrate S on which the bare chip D for the product is mounted.

[0083] (Step S22)

[0084] The control unit 80 compares the model image saved in the teaching operation with the product image, and calculates the position (coordinates) of the image of the portion most similar to the model image (hereinafter referred to as the pattern image). Here, the pattern image is the pattern image for determining the position of the substrate S (hereinafter referred to as the substrate positioning pattern) SS1, SS2 and the pattern image for determining the position of the bare chip D (hereinafter referred to as the bare chip positioning pattern) DS1, DS2. The position measurement results (coordinates) of the substrate positioning patterns SS1, SS2 are set to Pe1, Pe2. The position measurement results (coordinates) of the bare chip positioning patterns DS1, DS2 are set to Pg1, Pg2.

[0085] (Step S23)

[0086] The control unit 80 compares the coordinates of the pattern image with the coordinates of the model image to calculate the position of the product component.

[0087] The control unit 80 calculates the position (P1, Pa2) of the reference point SRT of the product substrate based on the position (Pa1, Pa2) of the substrate positioning models SM1, SM2, the positional relationship (Pb1, Pb2) between the reference point SR of the substrate and the substrate positioning models SM1, SM2, and the position (Pe1, Pe2) of the substrate positioning patterns SS1, SS2. SRT ).

[0088] The control unit 80 calculates the position (Pc1, Pc2) of the reference point DRT of the product bare chip based on the position (Pc1, Pc2) of the bare chip positioning models DM1, DM2, the positional relationship (Pd1, Pd2) between the bare chip reference point DR and the bare chip positioning models DM1, DM2, and the position (Pg1, Pg2) of the bare chip positioning patterns DS1, DS2. DRT ).

[0089] (Step S24)

[0090] The control unit 80 determines the position of the reference point SRT of the product substrate based on the position (P SRT ) and the position of the reference point DRT of the bare chip for product (P DRT ) calculates the offset (dv) relative to the ideal positional relationship (dm). The ideal positional relationship (dm) is the coordinate of the reference point SR of the reference substrate (P SR ) and the coordinates of the reference point DR of the reference bare chip (P DR )’s positional relationship.

[0091] (Step S25)

[0092] The control unit 80 stores and records Pe1 and Pe2, which are position measurement results (coordinates of pattern images) of the substrate alignment patterns SS1 and SS2, and Pg1 and Pg2, which are position measurement results (coordinates of pattern images) of the bare chip alignment patterns DS1 and DS2, in a storage device.

[0093] The parameters required for the visual inspection of the above-mentioned mounting position accuracy are as follows.

[0094] Parameter (Pa): Position of the positioning models SM1 and SM2 of the substrate during teaching (Pa1, Pa2)

[0095] Parameter (Pb): Coordinates of the substrate reference point SR during teaching (P SR ), the coordinates of the substrate positioning models SM1 and SM2 (P SM1 , P SM2 ) and their positional relationship (Pb1, Pb2)

[0096] Parameter (Pc): Position of the bare chip positioning patterns DM1 and DM2 during teaching (Pc1, Pc2)

[0097] Parameter (Pd): Coordinates of the bare chip reference point DR during teaching (P DR ), the coordinates of the bare chip positioning models DM1 and DM2 (P DM1 , P DM2 ) and its positional relationship (Pd1, Pd2)

[0098] Parameter (Pe): Position measurement results (Pe1, Pe2) of the substrate positioning patterns SS1 and SS2 during inspection

[0099] Parameter (Pf): The position of the reference point SRT of the substrate obtained from the parameters (Pa, Pb, Pe) SRT )

[0100] Parameter (Pg): Position measurement results (Pg1, Pg2) of the bare chip positioning patterns DS1 and DS2 during inspection

[0101] Parameter (Ph): The position of the reference point DRT of the bare chip obtained from the parameters (Pc, Pd, Pg). DRT )

[0102] Parameter (Pi): The deviation (dv) of the positional relationship (ds) between the substrate and the bare chip obtained from the parameters (Pf, Ph) from the ideal positional relationship (dm) (the positional relationship (dm) between the substrate and the bare chip)

[0103] The positional deviation (dv) can be obtained from these results.

[0104] At this time, if the parameters (Pa to Pd) are treated as constants after teaching, they will be values ​​that do not change during the inspection of the operating time (production operation). The parameters (Pe, Pg) are the measurement results determined in the measurement during each inspection. The parameters (Pf, Ph, Pi) are calculated values ​​obtained from the parameters.

[0105] Thus, the only new data obtained by each measurement during the inspection are the parameters (Pe, Pg). The data of all the parameters (Pe, Pg) of the inspection are entered and maintained, so that even if the values ​​of the parameters (Pb) and (Pd) are changed after the inspection, all the parameters (Pi) as the inspection results can be recalculated. Thus, even if the coordinates of the reference point are changed after all the inspections are completed, the inspection results can be recalculated.

[0106] use Fig. 9 Examples of the parameter (Pa), parameter (Pb), parameter (Pe), and parameter (Pf) are described. Fig. 9 It is a diagram showing examples of the input coordinates of the positioning model in the substrate, the reference point coordinates at the time of input, the measured position coordinates of the positioning pattern, and the calculated inspection reference point coordinates. The input coordinates of the positioning model are the position (coordinates) of the reference model inputted to the reference component. The reference point coordinates at the time of input are the position (coordinates) of the reference point inputted to the reference component. The measured position coordinates of the positioning pattern are the position measurement results (coordinates) of the positioning pattern of the product component. The inspection reference point coordinates are the position (coordinates) of the reference point of the product component.

[0107] The input coordinates (P) of the positioning models SM1 and SM2 as parameters (Pa) SM1 , P SM2 ) are (X1, Y1), (X2, Y2). The reference point coordinates (P) are used as the input parameters (Pb). SR) is (X1T, Y1T). The measured position coordinates (Pe1, Pe2) of the positioning pattern as the parameter (Pe) are (X1_1, Y1_1), (X2_1, Y2_1), etc. The calculated inspection reference point coordinates (Pf) as the parameter (Pf) are (X1_1, Y1_1, Y2_1, etc. SRT ) is (X1T_1, Y1T_1), etc.

[0108] If the input coordinates (PSM1, PSM2) of the substrate and the recognition results (Pe1, Pe2) of the substrate are maintained, the reference point coordinates (P SR ) can be changed after recognition. Even if it is changed after recognition, the reference point coordinates (P SRT In addition, the reference point coordinates (P DR ) can be changed after recognition. Even if it is changed after recognition, the reference point coordinates (P DRT ). This also enables recalculation of deviations when different reference points are set after the appearance inspection. By incorporating this function into the device, deviations when reference points are changed can be checked after all inspections are completed.

[0109] use Figure 10 to Figure 12 The effects of this embodiment will be described. Fig.10 It is a diagram for explaining reference points of a substrate and reference points of a bare chip. Fig.11 Yes Description Fig.10 A diagram showing the details of the reference points of the RP. Fig.12 This is a diagram for explaining an example in which different offset amounts are calculated due to different reference points for inspection.

[0110] Visual inspection of placement position accuracy in chip placement machines, e.g. Fig.10 As shown in RC, there is a case where the center of the bare chip D and the center of the packaging area P of the substrate S are used as references. This reference point is called the first reference point. In this case, the positioning patterns SS1 and SS2 of the two substrates and the positioning patterns DS1 and DS2 of the two bare chips are used.

[0111] On the other hand, in the visual inspection of the placement position accuracy after the chip is unloaded from the chip mounter, Fig.10 RP and Fig.11 As shown, there is a case where the position recognition mark M of the substrate and the pad BP of the bare chip D in the vicinity thereof are used as reference points. In this case, one substrate positioning pattern SS and one bare chip positioning pattern DS are used.

[0112] For example, the position identification mark M is in the shape of a cross, and the edge of the Y2 side of the reference lead extending in the horizontal direction (X1-X2 direction) and the edge of the X1 side of the reference lead extending in the vertical direction (Y1-Y2 direction) become the reference point. In addition, the upper right (X1 side and Y1 side) corner of the pad BP on the upper left (most Y1 side of the X2 side) of the bare chip D becomes the reference point. This reference point is called the second reference point.

[0113] The second reference point is used, for example, when the appearance inspection device is a microscope with a narrow field of view. In addition, it is used when NAND flash is stacked, when the accuracy of the edge of the bare chip on the side where the pad exists is important and the positional relationship of the edge on the opposite side is not important, etc.

[0114] As mentioned above, sometimes the appearance inspection of the chip placement position accuracy of the chip placement machine is performed using the first reference point, and the appearance inspection of the placement position accuracy after the chip is removed from the chip placement machine is performed using the second reference point. That is, there may be a situation where the management methods of placement accuracy are different. The difference between the two appearance inspection results with different reference points is explained.

[0115] Fig.12 RC shows the case where the reference point DR of the inspection is the first reference point, and the reference point DRT of the bare chip Dio coincides with the reference point DR of the bare chip Dip. The dotted line shows the bare chip Dip in the ideal position, and the solid line shows the bare chip Dio of the inspection object. The bare chip Dio is rotated 5° to the right with the center of the bare chip (reference point DRT) as the rotation center. Therefore, the offset of XY is 0, and the offset of only the rotation of θ is -5° (assuming that the left rotation is positive).

[0116] Fig.12 RP1 shows the case where the reference point DR of the inspection is the second reference point, and the positional relationship between the bare chip Dip and the bare chip Dio is exactly the same as RC. In this case, the offset of the θ rotation of the appearance inspection result is -5°, the same as RC, but the offset of XY is not 0, but X=4, Y=3.

[0117] Fig.12 RP2 shows the case where the reference point DR of the inspection is the second reference point, similarly to RP1, and the reference point DRT of the bare chip Dio coincides with the reference point DR of the bare chip Dip. The offset of the θ rotation of the appearance inspection result is -5°, similarly to RC, but the XY offset is 0. Although RC and RP2 have different positional relationships, they have the same result due to the different reference points DR, i.e., the XY offset is 0 and the θ offset is -5°.

[0118] The determination of the reference point of the inspection in this way will cause the appearance inspection results to change. In addition, the statistical results of the accuracy of the statistical calculation of the N number of results (for example, the standard deviation value) will also change. Depending on the determination method of the reference point of the inspection, the XY accuracy results will also change.

[0119] According to the embodiment, at least one of the following effects is achieved.

[0120] (a) After the visual inspection, the reference point is changed and the visual inspection result can be recalculated. Thus, the same inspection result can be used after the inspection to compare how the accuracy result changes due to the difference in the reference point.

[0121] (b) The difference between the accuracy count of the die mounter (device) at the reference point (e.g., the center of the bare die and the center of the bond) defined by the initial value and the accuracy count specified by the user can be compared and counted in the recalculation under the same production data (e.g., displayed on the monitor 83a). This can simply explain that the accuracy of the device is within the user's specification.

[0122] (c) Depending on the user, the user may not realize that the results are different due to the difference in the reference point. However, the device can compare and count the results and make it easy to understand and confirm.

[0123] <Modification>

[0124] Hereinafter, several representative variations of the embodiments are illustrated. In the following description of the variations, for parts having the same structure and function as those described in the above-mentioned embodiments, the same reference numerals as those in the above-mentioned embodiments can be used. Furthermore, for the description of the above-mentioned parts, the description in the above-mentioned embodiments can be appropriately cited within the scope of no technical contradiction. In addition, a part of the above-mentioned embodiments and all or part of the plurality of variations can be appropriately combined and applied within the scope of no technical contradiction.

[0125] The above nine data (parameters (Pa to Pi) are required for recalculation. On this basis, the images during teaching can also be saved in advance (one each for the splice and the bare chip). This allows the reference points to be redesignated using the image, and redesignation can be performed in a way that makes it easy to understand the positional relationship.

[0126] In addition, the required data (parameters (Pa to Pi)) may be output to an offline device (a computer outside the device, etc.), and software capable of recalculating may be prepared in the offline device. Thus, the result when the reference point is changed can be confirmed even if the device (chip mounter) is not used.

[0127] As mentioned above, the invention completed by the present inventors has been specifically described based on the embodiment and the modified examples. However, the present invention is not limited to the above-mentioned embodiment and the modified examples, and various modifications can be made, of course.

[0128] In the embodiment, an example using a die bonding film is described, but a pre-processing section for applying an adhesive to a substrate may be provided without using a die bonding film. The pre-processing section includes a pre-processing head for applying a paste adhesive and a pre-processing table for driving the pre-processing head in the vertical direction and the horizontal direction.

[0129] In the embodiment, a chip mounting machine is described which uses a pickup head to pick up a bare chip from a wafer supply unit and places it on an intermediate stage, and uses a mounting head to mount the bare chip placed on the intermediate stage to a substrate. However, the present invention is not limited to this and can also be applied to a chip mounting device which uses a mounting head to pick up a bare chip from a wafer supply unit and places it on a substrate.

[0130] The present invention can also be applied to a die mounter that does not have an intermediate stage and a pickup head but mounts a bare chip of a wafer supply unit onto a substrate using a mounting head, for example.

[0131] In addition, it can also be applied to a flip chip mounter that does not have an intermediate stage but picks up a bare chip from a wafer supply unit and flips a bare chip pickup head upside down to deliver the bare chip to a mounting head and mounts it on a substrate using the mounting head.

Claims

1. A semiconductor manufacturing device, characterized in that: Equipped with mounting head, substrate recognition camera and control device, The control device is configured as follows: The substrate recognition camera is used to photograph and acquire an image of the bare chip for product mounted on the substrate for product by the mounting head together with the substrate for product, Inspecting the relative position of the product bare chip and the product substrate based on the image and the pre-recorded positioning model position of the reference bare chip, the positioning model position of the reference substrate, the inspection reference position of the reference bare chip, and the inspection reference position of the reference substrate, The positioning pattern position of the product bare chip and the positioning pattern position of the product substrate calculated based on the positioning model position of the reference bare chip and the positioning model position of the reference substrate are entered.

2. The semiconductor manufacturing device according to claim 1, characterized in that The control device is further configured as follows: changing the inspection reference position of the reference bare chip and the inspection reference position of the reference substrate, Based on the entered positioning model position of the reference bare chip, the positioning model position of the reference substrate, the positioning pattern position of the product bare chip and the positioning pattern position of the product substrate, as well as the changed inspection reference position of the reference bare chip and the inspection reference position of the reference substrate, the relative position inspection result is recalculated.

3. The semiconductor manufacturing device according to claim 1, characterized in that: The control device is configured such that, during the inspection of the relative position, The reference position of the product bare chip and the reference position of the product substrate are calculated based on the positioning model position of the reference bare chip, the positioning model position of the reference substrate, the inspection reference position of the reference bare chip, the inspection reference position of the reference substrate, the positioning pattern position of the product bare chip and the positioning pattern position of the product substrate, The relative position is checked based on a reference position of the product bare chip and a reference position of the product substrate.

4. The semiconductor manufacturing device according to claim 1, characterized in that The positioning pattern of the product bare chip is the pattern most similar to the positioning pattern of the reference bare chip, The alignment pattern of the product substrate is a pattern most similar to the alignment pattern of the reference substrate.

5. The semiconductor manufacturing device according to claim 1, wherein: There are two positioning models for the reference bare chip and two positioning models for the reference substrate.

6. The semiconductor manufacturing device according to claim 1, characterized in that: The inspection reference position of the reference bare chip and the inspection reference position of the reference substrate are the center of the reference bare chip and the center of the reference substrate, respectively.

7. The semiconductor manufacturing device according to claim 6, characterized in that: The inspection reference position of the reference substrate that is changed and recorded is an alignment mark of the reference substrate, and the inspection reference position of the reference bare chip that is changed and recorded is a pad of the reference bare chip provided near the alignment mark.

8. A semiconductor manufacturing device system, characterized in that: have: A semiconductor manufacturing device having a mounting head, a substrate recognition camera, and a control device; and computer, The control device is configured as follows: The substrate recognition camera is used to photograph and acquire an image of the bare chip for product mounted on the substrate for product by the mounting head together with the substrate for product, Inspecting the relative position of the product bare chip and the product substrate based on the image, the positioning model position of the reference bare chip recorded during teaching, the positioning model position of the reference substrate, the inspection reference position of the reference bare chip, and the inspection reference position of the reference substrate, inputting the positioning pattern position of the product bare chip and the positioning pattern position of the product substrate calculated based on the positioning model position of the reference bare chip and the positioning model position of the reference substrate, The computer is configured to obtain, from the semiconductor manufacturing device, the positioning model position of the reference bare chip, the positioning model position of the reference substrate, the inspection reference position of the reference bare chip, the inspection reference position of the reference substrate, the positioning pattern position of the product bare chip, and the positioning pattern position of the product substrate.

9. The semiconductor manufacturing device system according to claim 8, characterized in that: The computer is further configured as follows: changing the inspection reference position of the reference bare chip and the inspection reference position of the reference substrate, The inspection result of the relative position can be recalculated based on the acquired positioning model position of the reference bare chip, the positioning model position of the reference substrate, the positioning pattern position of the product bare chip and the positioning pattern position of the product substrate, and the changed inspection reference position of the reference bare chip and the inspection reference position of the reference substrate.

10. A method for manufacturing a semiconductor device, characterized in that: have: The step of carrying the substrate into the semiconductor manufacturing apparatus according to claim 1; and A step of mounting a bare chip onto the substrate using the mounting head.

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