High-frequency TSV silicon adapter plate and design method thereof

Abstract

The invention provides a high-frequency TSV silicon adapter plate and a design method thereof. Two ends of a ground wire through silicon via and two ends of a ground wire redundant through silicon via in the high-frequency TSV silicon adapter plate are electrically coupled with grounding pads respectively; the two ends of the signal line through silicon via and the two ends of the signal line redundant through silicon via are electrically coupled with the signal line bonding pads respectively. The ground wire through-silicon via and the ground wire redundant through-silicon via are first through-silicon vias, the signal line through-silicon via and the signal line redundant through-silicon via are second through-silicon vias, and a preset distance exists between the first through-silicon via and the second through-silicon via. The first through silicon vias and the second through silicon vias in the high-frequency TSV silicon adapter plate are designed to be distributed in a quasi-coaxial mode, the problem that impedance between the through silicon vias in the high-frequency TSV silicon adapter plate and a transmission line is discontinuous is solved by adjusting the distance between the first through silicon vias and the second through silicon vias, and the radio frequency performance of the high-frequency TSV silicon adapter plate is improved; and meanwhile, the redundant through silicon vias which are only used for improving the error-tolerant rate in the field of digital signal transmission at present are designed in the silicon adapter plate for the first time, the signal through silicon via and the redundant through silicon vias share a bonding pad, the radio frequency performance of the silicon adapter plate is optimized, and the process reliability of the silicon adapter plate is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a high-frequency TSV silicon adapter plate and a design method thereof. Background Art

[0002] High-frequency impedance discontinuity in integrated circuits will lead to reflection loss, causing part of the signal to be reflected while the other part of the signal will be distorted and continue to propagate, thus greatly affecting the RF transmission performance of the integrated circuit's signal channel. As the integration of circuits increases, the wiring density of the transmission path also increases accordingly, and the number of layers crossed by the wiring increases. All of these result in insufficient space for hardware optimization, and the reflection loss cannot be effectively improved through traditional methods. Especially at the interface between chip-package and package-board, the capacitive parasitic effects generated by vias, wiring, pads, and solder balls are large, resulting in impedance discontinuity and impedance resonance.

[0003] In the prior art, in the field of PCB (Printed Circuit Board), impedance control can generally be achieved through the design of anti-pads. However, the anti-pad design is suitable for a multi-layer metal layer structure, where a large piece of ground copper is laid outside the metal layer to dig out the anti-pad area to achieve impedance control; however, the silicon adapter board only has two metal layers on the front and back sides, and the silicon through-holes pass through the intermediate medium silicon to achieve signal interconnection of the metal layers on the front and back sides. Therefore, when the anti-pad design is performed by laying copper outside the metal layer of the silicon adapter board, only a reference ground structure can be formed on the metal layers on the front and back sides, and a closed ground cavity structure cannot be formed around the TSV (Through Silicon Via) of the silicon adapter board, resulting in a serious impact on the RF performance of the silicon adapter board when the anti-pad is designed on the silicon adapter board. At the same time, during the manufacturing process, interconnection failure may occur due to misalignment of pads or insufficient filling of conductive materials. Redundant through silicon via design can be used to reduce the risk of interconnection failure. However, when redundant TSVs used in the digital field are directly designed into the silicon adapter, the RF impedance characteristics of the silicon adapter are easily deteriorated. Therefore, people in this field generally do not design redundant TSVs in silicon adapters.

[0004] Therefore, the high-frequency TSV silicon adapter board cannot solve the problem of impedance discontinuity at the connection between its TSV and the transmission line through the anti-pad. At the same time, the use of redundant TSV designed to improve the signal fault tolerance rate is prone to deterioration of the RF impedance, resulting in the RF transmission performance of the high-frequency TSV silicon adapter board being seriously affected in RF application scenarios. This is more obvious in highly integrated high-frequency TSV silicon adapter boards, making it difficult for highly integrated high-frequency TSV silicon adapter boards to use redundant TSV to improve the fault tolerance rate, resulting in poor process reliability of the high-frequency TSV silicon adapter board.

[0005] Therefore, there is an urgent need for a structure or method that can solve the impedance discontinuity problem in high-frequency TSV silicon adapters, achieve impedance optimization, and improve the reliability of the through silicon via manufacturing process.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0007] In view of the above shortcomings of the prior art, an object of the present invention is to provide a high-frequency TSV silicon adapter plate and a design method thereof, so as to solve the problems of impedance discontinuity and low reliability of through silicon via process in the prior art high-frequency TSV silicon adapter plate.

[0008] To achieve the above object, the present invention provides a high-frequency TSV silicon adapter board, the high-frequency TSV silicon adapter board comprising: ground line silicon vias, signal line silicon vias, ground line redundant silicon vias and / or signal line redundant silicon vias, ground transmission lines, signal transmission lines, ground pads and signal line pads;

[0009] Two ends of the ground through silicon via are respectively electrically coupled to one of the ground pads; two ends of the signal through silicon via are respectively electrically coupled to one of the signal pads;

[0010] When the redundant ground through silicon via exists, both ends of the redundant ground through silicon via are electrically coupled to the ground pad where the redundant ground through silicon via is located; each ground pad where the redundant ground through silicon via is located includes n redundant ground through silicon vias, where n is an integer greater than or equal to 0;

[0011] When the signal line redundant through silicon via exists, both ends of the signal line redundant through silicon via are electrically coupled to the signal line pad where the signal line through silicon via is located; each signal line pad where the signal line through silicon via is located includes m signal line redundant through silicon vias, where m is an integer greater than or equal to 0;

[0012] The ground through silicon via and the ground redundant through silicon via are both first through silicon vias, the signal through silicon via and the signal redundant through silicon via are both second through silicon vias, the first through silicon via and the second through silicon via are both perpendicular to the first plane, and there is a preset distance between each of the first through silicon vias and each of the second through silicon vias;

[0013] The ground pad is electrically connected to the ground transmission line, and the signal line pad is electrically connected to the signal transmission line.

[0014] Optionally, m and n are not 0 at the same time.

[0015] Optionally, the ground pad where one of the ground through silicon vias is located includes one ground redundant through silicon via, and the signal pad where one of the signal through silicon vias is located includes one signal redundant through silicon via.

[0016] Optionally, projections of each of the first through silicon vias on the first plane are all on a first circle, projections of each of the second through silicon vias on the first plane are all on a second circle, and the first circle and the second circle are concentric circles.

[0017] Optionally, a line connecting each of the first TSVs and the closest second TSV coincides with a radial direction of the first circle.

[0018] Optionally, a diameter of each of the first through silicon vias is 5 micrometers to 20 micrometers, and a thickness of each of the first through silicon vias is 25 micrometers to 200 micrometers.

[0019] Optionally, a diameter of each of the second through silicon vias is 5 micrometers to 20 micrometers, and a thickness of each of the second through silicon vias is 25 micrometers to 200 micrometers.

[0020] Optionally, projections of the first through silicon vias on the first plane are all located within projections of the ground pads on the first plane.

[0021] Optionally, a projection of the second through silicon via on the first plane is located within a projection of the signal line pad on the first plane.

[0022] The present invention also provides a design method for a high-frequency TSV silicon adapter board, the design method is used to design any one of the high-frequency TSV silicon adapter boards described above, the design method comprising:

[0023] A simulation model of the high-frequency TSV silicon adapter board is designed, wherein the high-frequency TSV silicon adapter board includes ground silicon vias, signal silicon vias, ground redundant silicon vias and / or signal redundant silicon vias, ground transmission lines, signal transmission lines, ground pads and signal pads; the ground silicon vias and the signal silicon vias are both perpendicular to the first plane; the two ends of the ground silicon vias are each electrically coupled to one of the ground pads; the two ends of the signal silicon vias are each electrically coupled to one of the signal pads; when the ground redundant silicon vias exist, the two ends of the ground redundant silicon vias are each electrically coupled to the ground pads where the ground silicon vias are located; each of the The ground pad where the ground through silicon via is located includes n ground redundant through silicon vias, where n is an integer greater than or equal to 0; when the signal line redundant through silicon via exists, both ends of the signal line redundant through silicon via are electrically coupled to the signal line pad where the signal line through silicon via is located; the signal line pad where each signal line through silicon via is located includes m signal line redundant through silicon vias, where m is an integer greater than or equal to 0; the ground through silicon via and the ground redundant through silicon via are both first through silicon vias, the signal line through silicon via and the signal line redundant through silicon via are both second through silicon vias, and there is a preset distance between each of the first through silicon vias and each of the second through silicon vias;

[0024] Adjusting the number of redundant silicon vias for ground lines and / or redundant silicon vias for signal lines; adjusting the distance between the first silicon via and the second silicon via, simulating the adjusted simulation model, and measuring the S11 curve, S21 curve and impedance curve of the simulation model measured by a time domain reflectometer;

[0025] Select the number of redundant ground through silicon vias and / or redundant signal line through silicon vias corresponding to the minimum change in the impedance curve measured by the time domain reflectometer with the matching impedance as the reference line, the minimum S11 reflection coefficient in the S11 curve, and the minimum RF insertion loss in the S21 curve, and the distance between the first through silicon via and the second through silicon via;

[0026] The number and spacing of the first through silicon vias and the second through silicon vias in the high-frequency TSV silicon transfer board are determined by selecting the number of redundant ground through silicon vias and / or redundant signal through silicon vias and the distance between the first through silicon via and the second through silicon via.

[0027] As described above, the high-frequency TSV silicon adapter board and the design method thereof of the present invention have the following beneficial effects:

[0028] The present invention adjusts the spacing between the first through silicon via and the second through silicon via by designing the positions of the redundant through silicon via and the through silicon via in the high-frequency TSV silicon adapter board, reduces the impedance discontinuity problem between the through silicon via and the transmission line in the high-frequency TSV silicon adapter board without an anti-pad for adjustment, and improves the radio frequency performance of the high-frequency TSV silicon adapter board;

[0029] The present invention is the first to design redundant silicon vias, which are currently only used in the field of digital signal transmission to improve fault tolerance, into a silicon adapter. The signal silicon via and multiple redundant silicon vias share a pad, thereby optimizing the RF performance of the silicon adapter and improving the signal fault tolerance and process reliability of the silicon adapter.

[0030] The present invention can further improve the effect of reducing the impedance discontinuity problem by arranging the first through silicon via and the second through silicon via to be quasi-coaxially distributed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Shown is a schematic structural diagram of a high-frequency TSV silicon adapter board in Example 1 of the present invention.

[0032] Figure 2 It shows a comparison of S11 reflection coefficient curves of transmission lines and TSV signals passing through a high-frequency TSV silicon adapter board with different numbers of first TSVs and second TSVs in an example of Embodiment 1 of the present invention.

[0033] Figure 3 It shows a comparison of S21 insertion loss curves of transmission lines and TSV signals passing through a high-frequency TSV silicon adapter board with different numbers of first TSVs and second TSVs in an example of Embodiment 1 of the present invention.

[0034] Figure 4 It shows a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 1 of the present invention.

[0035] Figure 5 It shows a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 1 of the present invention.

[0036] Figure 6 It shows a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 1 of the present invention.

[0037] Figure 7 Shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 2 of the present invention.

[0038] Figure 8 Shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 2 of the present invention.

[0039] Fig. 9 Shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 4 of the present invention.

[0040] Fig.10 It shows a comparison of TDR measured impedance curves of a transmission line and a through silicon via signal passing through a high-frequency TSV silicon adapter board at different first through silicon via and second through silicon via distances in an example of Embodiment 4 of the present invention.

[0041] Fig.11 It shows a comparison of S11 reflection coefficient curves of a transmission line and a through silicon via signal passing through a high-frequency TSV silicon adapter board at different first through silicon via and second through silicon via distances in an example of Embodiment 4 of the present invention.

[0042] Component number description

[0043] 10. First through silicon via; 11. Ground through silicon via; 12. Ground redundant through silicon via; 20. Second through silicon via; 21. Signal line through silicon via; 22. Signal line redundant through silicon via; 31. Ground transmission line; 32. Signal transmission line; 41. Ground pad; 42. Signal line pad. DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0046] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0047] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] Embodiment 1:

[0050] This embodiment provides a high-frequency TSV silicon adapter board, such as Figure 1 As shown, the high-frequency TSV silicon adapter board includes: a ground line silicon through via 11, a signal line silicon through via 21, a ground line redundant silicon through via 12 and / or a signal line redundant silicon through via 22, a ground transmission line 31, a signal transmission line 32, a ground pad 41 and a signal line pad 42;

[0051] Both ends of the ground through silicon via 11 are electrically coupled to one of the ground pads 41 ; both ends of the signal through silicon via 21 are electrically coupled to one of the signal pads 42 ;

[0052] When the redundant ground through silicon via 12 exists, both ends of the redundant ground through silicon via 12 are electrically coupled to the ground pad 41 where the ground through silicon via 11 is located; each ground pad 41 where the ground through silicon via 11 is located includes n redundant ground through silicon vias 12, where n is an integer greater than or equal to 0;

[0053] When the signal line redundant through silicon via 22 exists, both ends of the signal line redundant through silicon via 22 are electrically coupled to the signal line pad 42 where the signal line through silicon via 21 is located; each signal line pad 42 where the signal line through silicon via 21 is located includes m signal line redundant through silicon vias 22, where m is an integer greater than or equal to 0;

[0054] The ground through silicon via 11 and the ground redundant through silicon via 12 are both first through silicon vias 10, the signal through silicon via 21 and the signal redundant through silicon via 22 are both second through silicon vias 20, the first through silicon vias 10 and the second through silicon vias 20 are both perpendicular to the first plane, and there is a preset distance between each of the first through silicon vias 10 and each of the second through silicon vias 20;

[0055] The ground pad 41 is electrically connected to the ground transmission line 31 , and the signal line pad 42 is electrically connected to the signal transmission line 32 .

[0056] In the prior art, high-frequency impedance discontinuity in an integrated circuit can lead to reflection loss, so that part of the signal will be reflected, and the other part of the signal will be distorted and continue to propagate, thus greatly affecting the radio frequency transmission performance of the signal channel of the integrated circuit. In the field of PCB (Printed Circuit Board), impedance control can generally be performed by designing an anti-pad. However, the anti-pad design is suitable for a multi-layer metal layer structure, and a large piece of copper foil is laid outside the metal layer to dig out an anti-pad area to achieve impedance control; however, the silicon adapter board has only two metal layers on the front and back sides, and the silicon through-hole passes through the intermediate medium silicon to realize the signal interconnection of the metal layers on the front and back sides. Therefore, when the anti-pad design is performed by laying copper outside the metal layer of the silicon adapter board, only a reference ground structure can be formed on the metal layers on the front and back sides, and a closed ground cavity structure cannot be formed around the TSV (Through Silicon Via) of the silicon adapter board, resulting in a serious impact on the radio frequency performance of the silicon adapter board when the anti-pad is designed on the silicon adapter board. At the same time, during the manufacturing process, interconnection failure may occur due to misalignment of the pads or insufficient filling of the conductive material. A redundant through silicon via design can be used to reduce the risk of interconnection failure. However, when redundant TSVs used in the digital field are directly designed into the silicon adapter, the RF impedance characteristics of the silicon adapter are easily deteriorated. Therefore, people in this field generally do not design redundant TSVs in silicon adapters. There is currently no research on the impact of redundant TSV structures on the RF performance of silicon adapters.

[0057] The present invention can adjust the capacitance impedance formed by the first through silicon via 10 and the second through silicon via 20 by setting the spacing between the first through silicon via 10 and the second through silicon via 20 in the high-frequency TSV silicon adapter board, so that under the condition that the high-frequency TSV silicon adapter board cannot be designed with an anti-pad due to process limitations, the impedance discontinuity problem between the through silicon via and the transmission line in the high-frequency TSV silicon adapter board can still be significantly reduced, thereby greatly improving the RF performance of the high-frequency TSV silicon adapter board; at the same time, in a circuit with a higher degree of integration, interconnection failure due to misalignment of the TSV pad or insufficient filling of the conductive material may lead to product integrity problems. In order to prevent the failure of the whole body, redundant TSV is set, and the deterioration of the RF performance of the silicon adapter board is avoided by designing the distance between the redundant TSV and other silicon vias, the product yield can be effectively improved. Therefore, in the circuit with higher integration, more redundant TSV will be designed, so that the positions of the redundant ground silicon vias 11 and the redundant signal silicon vias 21 in the high-frequency TSV silicon adapter board have greater room for adjustment, and by designing multiple silicon vias to connect the same pad, there is no need to introduce redundant transmission line structures, which is more conducive to solving the impedance discontinuity problem between the silicon vias and the transmission lines in the high-frequency TSV silicon adapter board.

[0058] Specifically, the high-frequency TSV silicon transfer board in the present invention refers to a high-frequency silicon transfer board including TSV.

[0059] Specifically, the redundant ground line silicon vias 11 and the redundant signal line silicon vias 21 are provided to solve the impedance discontinuity problem of the high-frequency TSV silicon adapter board, but the increase of these redundant silicon vias will also improve the circuit reliability of the high-frequency TSV silicon adapter board, breaking the technical prejudice in the prior art to avoid the use of redundant TSV in the high-frequency TSV silicon adapter board in order to avoid the deterioration of the RF performance of the high-frequency TSV silicon adapter board, thereby achieving a dual improvement in RF performance and signal fault tolerance.

[0060] Specifically, the number of the ground through silicon vias 11 and the signal through silicon vias 21 are both integers greater than or equal to 1, and can be designed according to the needs of circuit design. The positions of the ground redundant through silicon vias 12 and the signal redundant through silicon vias 22 are determined according to the ground through silicon vias 11 and the signal through silicon vias 21.

[0061] In this embodiment, n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.

[0062] Specifically, the number of the redundant ground through silicon vias 12 and the redundant signal line through silicon vias 22 can be set according to the signal fault tolerance requirements of the circuits in the high-frequency adapter board.

[0063] Specifically, the number and distance of the first through silicon vias 10 and the second through silicon vias 20 described in the present invention are only the structural design of the connection between a transmission line and the through silicon via in the high-frequency TSV silicon adapter board. The connection between each transmission line and the through silicon via of the high-frequency TSV silicon adapter board can adopt a similar structural design method, and different connections can also select different numbers and distances of the first through silicon vias 10 and the second through silicon vias 20 according to needs.

[0064] Specifically, “the two ends of the ground wire silicon via 11 are respectively electrically coupled to one of the grounding pads 41” means that one end of the ground wire silicon via 11 is electrically coupled to one grounding pad 41, and the other end is electrically coupled to another grounding pad 41; “the two ends of the signal line silicon via 21 are respectively electrically coupled to one of the signal line pads 42” means that one end of the signal line silicon via 21 is electrically coupled to one signal line pad 42, and the other end is electrically coupled to another signal line pad 42.

[0065] Specifically, the first through silicon via 10, the second through silicon via 20, the ground redundant through silicon via 12 and the signal line redundant through silicon via 21 are all through silicon vias (TSVs), the ground redundant through silicon via 12 and the signal line redundant through silicon via 21 are all redundant TSVs, and the ground transmission line 31 and the signal transmission line 32 are all transmission lines.

[0066] In one embodiment, Figure 1As shown, at the connection between each transmission line and the through silicon via of a high-frequency TSV silicon adapter board, one of the ground pads 41 includes two first through silicon vias 10, and one of the signal line pads 42 includes two second through silicon vias 20.

[0067] Specifically, when the distance between the first through silicon via 10 and the second through silicon via 20, the sizes of the ground pad 41 and the signal line pad 42 are constant, as shown in FIG. Figure 2 The figure shows a comparison of the signal S11 reflection coefficient curves of the transmission line and the through silicon vias through the high-frequency TSV silicon adapter board with different numbers of first through silicon vias 10 and second through silicon vias 20, wherein 1S1G represents a high-frequency adapter board including 1 first through silicon via 10 and 1 second through silicon via 20, 2S2G represents a high-frequency adapter board including 2 first through silicon vias 10 and 2 second through silicon vias 20, and 4S4G represents a high-frequency adapter board including 4 first through silicon vias 10 and 4 second through silicon vias 20; it can be seen that the reflection coefficient of the signal S11 reflection coefficient curve of the transmission line and the through silicon vias through the high-frequency TSV silicon adapter board including 2 first through silicon vias 10 and 2 second through silicon vias 20 is below -10dB within 60GHz, which is in a matching state, indicating that the impedance matching of the high-frequency adapter board including 2 first through silicon vias 10 and 2 second through silicon vias 20 is the best;

[0068] And, if Figure 3 The figure shows a comparison of insertion loss curves of the signal S21 of the transmission line and the through-silicon via through the high-frequency TSV silicon adapter board with different numbers of first through-silicon vias 10 and second through-silicon vias 20, wherein 1S1G represents a high-frequency adapter board including 1 first through-silicon via 10 and 1 second through-silicon via 20, 2S2G represents a high-frequency adapter board including 2 first through-silicon vias 10 and 2 second through-silicon vias 20, and 4S4G represents a high-frequency adapter board including 4 first through-silicon vias 10 and 4 second through-silicon vias 20; it can be seen that the insertion loss curves of the signal S21 of the transmission line and the through-silicon via through the high-frequency TSV silicon adapter board including 2 first through-silicon vias 10 and 2 second through-silicon vias 20 have the smallest RF loss within 60 GHz; it can be judged that the high-frequency TSV silicon adapter board obtained with this number of first through-silicon vias 10 and second through-silicon vias 20 has the best RF performance.

[0069] In one embodiment, Figure 4 As shown, at the connection between a transmission line and a through silicon via of the high-frequency TSV silicon adapter board, the first through silicon via 10 includes a ground line through silicon via 11 and a ground line redundant through silicon via 12, and the second through silicon via 20 includes a signal line through silicon via 21 and a signal line redundant through silicon via 22.

[0070] In one embodiment, Figure 5As shown, at the connection between each transmission line and the through silicon via of a high-frequency TSV silicon adapter board, one of the ground pads 41 includes four first through silicon vias 10, and one of the signal line pads 42 includes four second through silicon vias 20.

[0071] In one embodiment, Figure 6 As shown, at the connection between a transmission line and a through silicon via of the high-frequency TSV silicon adapter board, the first through silicon via 10 includes one ground through silicon via 11 and three ground redundant through silicon vias 12, and the second through silicon via 20 includes one signal line through silicon via 21 and three signal line redundant through silicon vias 22.

[0072] In one embodiment, projections of each of the first TSVs 10 on the first plane are on a first circle, projections of each of the second TSVs 20 on the first plane are on a second circle, and the first circle and the second circle are concentric circles.

[0073] The present invention arranges the first through silicon via 10 and the second through silicon via 20 in the above-mentioned quasi-coaxial distribution, so that the capacitive impedance formed by the first through silicon via 10 and the second through silicon via 20 is more obvious, so that the distance between the first through silicon via 10 and the second through silicon via 20 has a significant effect on the impedance, thereby further solving the problem of impedance discontinuity at the connection between the through silicon via and the transmission line on the high-frequency TSV silicon adapter. At the same time, it is more convenient to carry out orderly experimental design of the spacing between the corresponding first through silicon via 10 and the second through silicon via 20, which is beneficial to improving the efficiency of designing redundant through silicon vias in a high-flat silicon adapter, and can improve the RF performance and space utilization of the high-frequency TSV silicon adapter.

[0074] In one embodiment, a line connecting each of the first TSVs 10 and the closest second TSV 20 coincides with a radial direction of the first circle.

[0075] The present invention arranges the first through silicon via 10 and the closest second through silicon via 20 to be distributed radially, so that the capacitive impedance formed by the first through silicon via 10 and the second through silicon via 20 is more obvious, so that the distance between the first through silicon via 10 and the second through silicon via 20 has a greater effect on the impedance, which can further facilitate the impedance adjustment between the two corresponding first through silicon vias 10 and the second through silicon vias 20, thereby better solving the problem of impedance discontinuity in the high-frequency adapter board.

[0076] In one embodiment, the signal line pad 42 is circular, and the ground pad 41 is a ring concentric with the signal line pad 42 .

[0077] In one embodiment, the diameter of each of the first TSVs 10 is 5 micrometers to 20 micrometers, and the thickness of each of the first TSVs 10 is 25 micrometers to 200 micrometers.

[0078] In one embodiment, the diameter of each of the second TSVs 20 is 5 micrometers to 20 micrometers, and the thickness of each of the second TSVs 20 is 25 micrometers to 200 micrometers.

[0079] In one embodiment, the projections of the first through silicon vias 10 on the first plane are all located within the projections of the ground pads 41 on the first plane.

[0080] In one embodiment, a projection of the second through silicon via 20 on the first plane is located within a projection of the signal pad 42 on the first plane.

[0081] The present invention arranges the first through silicon via 10 and the second through silicon via 20 within the projection of the corresponding ground pad 41 and the signal line pad 42 so that the pads can completely carry the corresponding through silicon vias, thereby ensuring the welding yield of the high-frequency TSV silicon adapter board and further improving the RF performance of the high-frequency TSV silicon adapter board.

[0082] Embodiment 2:

[0083] This embodiment provides a high-frequency TSV silicon adapter board, which has substantially the same features as the high-frequency TSV silicon adapter board in Embodiment 1, except that:

[0084] In this embodiment, the high-frequency TSV silicon adapter board does not include redundant signal line silicon vias 22, and each signal line pad 42 where the signal line silicon via 21 is located includes 0 redundant signal line silicon vias 22; each ground wire silicon via 11 is located on the grounding pad 41 including n redundant ground wire silicon vias 12, where n is an integer greater than or equal to 1.

[0085] In one embodiment, Figure 7 As shown, at the connection between each transmission line and the through silicon via of a high-frequency TSV silicon adapter board, one of the ground pads 41 includes two first through silicon vias 10, and one of the signal line pads 42 includes one second through silicon via 20.

[0086] In one embodiment, Figure 8 As shown, at the connection between a transmission line and a through silicon via of the high-frequency TSV silicon adapter board, the first through silicon via 10 includes a ground through silicon via 11 and a ground redundant through silicon via 12 , and the second through silicon via 20 is a signal line through silicon via 21 .

[0087] Embodiment 3:

[0088] This embodiment provides a high-frequency TSV silicon adapter board, which has substantially the same features as the high-frequency TSV silicon adapter board in Embodiment 1, except that:

[0089] In this embodiment, the high-frequency TSV silicon adapter board does not include redundant ground silicon vias 12, and each of the ground silicon vias 11 located on the ground pad 41 includes 0 redundant ground silicon vias 12; each of the signal line silicon vias 21 located on the signal line pad 42 includes m redundant signal line silicon vias 22, where m is an integer greater than or equal to 1.

[0090] In one embodiment, at the connection between each transmission line and the through silicon via of a high-frequency TSV silicon adapter board, one of the ground pads 41 includes one first through silicon via 10 , and one of the signal line pads 42 includes two second through silicon vias 20 .

[0091] In one embodiment, at the connection between a transmission line and a through silicon via of the high-frequency TSV silicon adapter, the first through silicon via 10 is a ground through silicon via 11, and the second through silicon via 20 includes a signal line through silicon via 21 and a signal line redundant through silicon via 22.

[0092] Embodiment 4:

[0093] This embodiment provides a high-frequency TSV silicon adapter board, which has substantially the same features as the high-frequency TSV silicon adapter board in Embodiment 1, except that:

[0094] In this embodiment, the high-frequency TSV silicon adapter board does not include redundant ground silicon vias 12 and redundant signal silicon vias 22. Each of the ground silicon vias 11 located on the ground pad 41 includes 0 redundant ground silicon vias 12; each of the signal line silicon vias 21 located on the signal line pad 42 includes 0 redundant signal line silicon vias 22.

[0095] In one embodiment, Fig. 9 As shown, at the connection between a transmission line and a through silicon via of the high-frequency TSV silicon adapter board, one of the ground pads 41 includes a first through silicon via 10, and the first through silicon via 10 is a ground line through silicon via 11; one of the signal line pads 42 includes a second through silicon via 20, and the second through silicon via 20 is a signal line through silicon via 21.

[0096] In one embodiment, the preset distance between the ground through silicon via 11 and the signal through silicon via 21 is 60 micrometers.

[0097] Specifically, Fig.10The figure shows a comparison of the signal TDR (Time Domain Reflectometry) curves of the transmission line and the silicon through hole through the high-frequency TSV silicon adapter board when the preset distance space between the ground silicon through hole 11 and the signal silicon through hole 21 is 40 microns, 60 microns, 80 microns, and 90 microns respectively. The characteristic impedance of the transmission line measured by the time domain reflectometer changes with time. It can be seen that the impedance continuity between the preset distance of 60 microns and the matching impedance of 50Ω is the best;

[0098] like Fig.11 The figure shows a comparison of the reflection coefficient curves of the signal S11 of the transmission line through the high-frequency TSV silicon adapter and the silicon through via when the preset distance space between the ground silicon through via 11 and the signal silicon through via 21 is 40 microns, 60 microns, 80 microns, and 90 microns respectively. It can be seen that the reflection coefficient is the smallest when the preset distance is 60 microns, and the impedance matching is the best.

[0099] It can be seen that adjusting the distance between the first through silicon via 10 and the second through silicon via 20 can play a role in adjusting the impedance continuity and the impedance matching effect, which also indirectly reflects that the high-frequency TSV silicon adapter board in Examples 1-3 can also improve the impedance continuity and RF performance by adjusting the distance between the first through silicon via 10 and the second through silicon via 20.

[0100] Embodiment 5:

[0101] This embodiment provides a method for designing a high-frequency TSV silicon adapter, the design method is used to design a high-frequency TSV silicon adapter described in any one of embodiments 1-4.

[0102] The design method of the high-frequency TSV silicon adapter board of the present invention will be described in detail below. It should be noted that the order does not strictly represent the design method order of the high-frequency TSV silicon adapter board protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0103] First, step 1 is performed to design a simulation model of the high-frequency TSV silicon adapter board, wherein the high-frequency TSV silicon adapter board includes a ground through silicon via 11, a signal line through silicon via 21, a ground redundant through silicon via 12 and / or a signal line redundant through silicon via 22, a ground transmission line 31, a signal transmission line 32, a ground pad 41 and a signal line pad 42; the ground through silicon via 11 and the signal line through silicon via 21 are both perpendicular to the first plane; the two ends of the ground through silicon via 11 are each electrically coupled to one of the ground pads 41; the two ends of the signal line through silicon via 21 are each electrically coupled to one of the signal line pads 42; when the ground redundant through silicon via 12 exists, the two ends of the ground redundant through silicon via 12 are each electrically coupled to the ground pad 41 where the ground through silicon via 11 is located; The ground pad 41 where each of the ground through silicon vias 11 is located includes n ground redundant through silicon vias 12, where n is an integer greater than or equal to 0; when the signal line redundant through silicon vias 22 are present, both ends of the signal line redundant through silicon vias 22 are electrically coupled to the signal line pad 42 where the signal line through silicon vias 21 are located; the signal line pad 42 where each of the signal line through silicon vias 21 is located includes m signal line redundant through silicon vias 22, where m is an integer greater than or equal to 0; the ground through silicon vias 11 and the ground redundant through silicon vias 12 are both first through silicon vias 10, the signal line through silicon vias 21 and the signal line redundant through silicon vias 22 are both second through silicon vias 20, and there is a preset distance between each of the first through silicon vias 10 and each of the second through silicon vias 20.

[0104] Preferably, the simulation model is an electronic model to improve measurement efficiency and reduce trial and error costs. Specifically, the simulation model can also be set as a physical structure to ensure consistency between the measurement results and the actual structure, thereby improving the effect of solving the impedance discontinuity problem of the actual high-frequency TSV silicon adapter.

[0105] Then, perform step 2, adjust the number of redundant ground through silicon vias 12 and / or redundant signal line through silicon vias 22; adjust the distance between the first through silicon via 10 and the second through silicon via 20, simulate the adjusted simulation model, and measure the S11 curve, S21 curve and impedance curve measured by the time domain reflectometer of the simulation model.

[0106] Next, proceed to step 3, and select the number of ground redundant silicon vias 12 and / or signal redundant silicon vias 22 corresponding to the smallest change in the impedance curve measured by the time domain reflectometer with the matching impedance as the reference line, the smallest S11 reflection coefficient in the S11 curve, and the smallest RF insertion loss in the S21 curve, and the distance between the first silicon via 10 and the second silicon via 20.

[0107] In one embodiment, the matching impedance is 50Ω, and the high-frequency TSV silicon transfer board includes a 50Ω matching microstrip line.

[0108] Finally, step 4 is performed to select the number of redundant ground through silicon vias 12 and / or redundant signal line through silicon vias 22 and the distance between the first through silicon vias 10 and the second through silicon vias 20 as the number and spacing of the first through silicon vias 10 and the second through silicon vias 20 in the high-frequency TSV silicon transfer board.

[0109] In summary, the high-frequency TSV silicon adapter board and the design method thereof of the present invention can be designed to have a quasi-coaxial distribution of the first through silicon via and the second through silicon via in the high-frequency TSV silicon adapter board, and the spacing between the first through silicon via and the second through silicon via is adjusted by setting the positions of the redundant through silicon via and the through silicon via, thereby reducing the impedance discontinuity problem between the through silicon via and the transmission line in the high-frequency TSV silicon adapter board under the condition of adjusting the size of the quasi-coaxial area, and improving the RF performance of the high-frequency TSV silicon adapter board; at the same time, the present invention is the first to design redundant through silicon vias, which are currently only used in the field of digital signal transmission to improve fault tolerance, in the silicon adapter board, and the signal through silicon via and multiple redundant through silicon vias share a pad, thereby optimizing the RF performance of the silicon adapter board, and improving the signal fault tolerance and process reliability of the silicon adapter board; in addition, by designing multiple through silicon vias to connect the same pad, no redundant transmission line structure is introduced, and the RF impedance discontinuity problem can be further optimized while improving the signal fault tolerance.

[0110] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A high-frequency TSV silicon adapter board, characterized in that: The high-frequency TSV silicon adapter plate includes: ground line silicon vias, signal line silicon vias, ground line redundant silicon vias and / or signal line redundant silicon vias, ground transmission lines, signal transmission lines, ground pads and signal line pads; Two ends of the ground through silicon via are respectively electrically coupled to one of the ground pads; two ends of the signal through silicon via are respectively electrically coupled to one of the signal pads; When the redundant ground through silicon via exists, both ends of the redundant ground through silicon via are electrically coupled to the ground pad where the redundant ground through silicon via is located; each ground pad where the redundant ground through silicon via is located includes n redundant ground through silicon vias, where n is an integer greater than or equal to 0; When the signal line redundant through silicon via exists, both ends of the signal line redundant through silicon via are electrically coupled to the signal line pad where the signal line through silicon via is located; each signal line pad where the signal line through silicon via is located includes m signal line redundant through silicon vias, where m is an integer greater than or equal to 0; The ground through silicon via and the ground redundant through silicon via are both first through silicon vias, the signal through silicon via and the signal redundant through silicon via are both second through silicon vias, the first through silicon via and the second through silicon via are both perpendicular to the first plane, and there is a preset distance between each of the first through silicon vias and each of the second through silicon vias; The ground pad is electrically connected to the ground transmission line, and the signal line pad is electrically connected to the signal transmission line.

2. The high-frequency TSV silicon adapter board according to claim 1, characterized in that: m and n are not 0 at the same time.

3. The high-frequency TSV silicon adapter board according to claim 2, characterized in that: The ground pad where one of the ground through silicon vias is located includes one ground redundant through silicon via, and the signal pad where one of the signal through silicon vias is located includes one signal redundant through silicon via.

4. The high-frequency TSV silicon adapter board according to claim 1, characterized in that: The projections of each of the first through silicon vias on the first plane are all on a first circle, the projections of each of the second through silicon vias on the first plane are all on a second circle, and the first circle and the second circle are concentric circles.

5. The high frequency TSV silicon adapter board according to claim 4, characterized in that: A connecting line between each of the first TSVs and the second TSV that is closest to it coincides with a radial direction of the first circle.

6. The high-frequency TSV silicon adapter board according to claim 1, characterized in that: The diameter of each of the first through silicon vias is 5 micrometers to 20 micrometers, and the thickness of each of the first through silicon vias is 25 micrometers to 200 micrometers.

7. The high frequency TSV silicon adapter board according to claim 1, characterized in that: The diameter of each of the second through silicon vias is 5 micrometers to 20 micrometers, and the thickness of each of the second through silicon vias is 25 micrometers to 200 micrometers.

8. The high frequency TSV silicon adapter board according to claim 1, characterized in that: The projections of the first through silicon vias on the first plane are all located within the projections of the ground pads on the first plane.

9. The high-frequency TSV silicon adapter board according to claim 1, characterized in that: A projection of the second through silicon via on the first plane is located within a projection of the signal line pad on the first plane.

10. A design method for a high-frequency TSV silicon adapter board, characterized in that: The design method is used to design the high-frequency TSV silicon adapter board according to any one of claims 1 to 9, and the design method comprises: A simulation model of the high-frequency TSV silicon adapter board is designed, wherein the high-frequency TSV silicon adapter board includes ground silicon vias, signal silicon vias, ground redundant silicon vias and / or signal redundant silicon vias, ground transmission lines, signal transmission lines, ground pads and signal pads; the ground silicon vias and the signal silicon vias are both perpendicular to the first plane; the two ends of the ground silicon vias are each electrically coupled to one of the ground pads; the two ends of the signal silicon vias are each electrically coupled to one of the signal pads; when the ground redundant silicon vias exist, the two ends of the ground redundant silicon vias are each electrically coupled to the ground pads where the ground silicon vias are located; each of the The ground pad where the ground through silicon via is located includes n ground redundant through silicon vias, where n is an integer greater than or equal to 0; when the signal line redundant through silicon via exists, both ends of the signal line redundant through silicon via are electrically coupled to the signal line pad where the signal line through silicon via is located; the signal line pad where each signal line through silicon via is located includes m signal line redundant through silicon vias, where m is an integer greater than or equal to 0; the ground through silicon via and the ground redundant through silicon via are both first through silicon vias, the signal line through silicon via and the signal line redundant through silicon via are both second through silicon vias, and there is a preset distance between each of the first through silicon vias and each of the second through silicon vias; Adjusting the number of redundant silicon vias for ground lines and / or redundant silicon vias for signal lines; adjusting the distance between the first silicon via and the second silicon via, simulating the adjusted simulation model, and measuring the S11 curve, S21 curve and impedance curve of the simulation model measured by a time domain reflectometer; Select the number of redundant ground through silicon vias and / or redundant signal line through silicon vias corresponding to the minimum change in the impedance curve measured by the time domain reflectometer with the matching impedance as the reference line, the minimum S11 reflection coefficient in the S11 curve, and the minimum RF insertion loss in the S21 curve, and the distance between the first through silicon via and the second through silicon via; The number and spacing of the first through silicon vias and the second through silicon vias in the high-frequency TSV silicon transfer board are determined by selecting the number of redundant ground through silicon vias and / or redundant signal through silicon vias and the distance between the first through silicon via and the second through silicon via.

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