RF transistor amplifier package

Abstract

An RF transistor amplifier includes an RF transistor amplifier die having a semiconductor layer structure; an interconnect structure having opposite first and second sides, wherein the first side of the interconnect structure is adjacent to a surface of the RF transistor amplifier die such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement; and one or more circuit elements at the first side and / or the second side of the interconnect structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 018,721, filed on September 11, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to microelectronic devices, and more particularly to high-power, high-frequency transistor amplifiers. Background Technology

[0004] Circuits requiring high power handling capabilities while operating at high frequencies are becoming increasingly common, including high-frequency bands such as R-band (0.5-1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12-18 GHz), K-band (18-27 GHz), Ka-band (27-40 GHz), and V-band (40-75 GHz). In particular, there is now a high demand for radio frequency (“RF”) transistor amplifiers used to amplify RF signals at frequencies such as 500 MHz and higher (including microwave frequencies). These RF transistor amplifiers may need to exhibit high reliability, good linearity, and the ability to handle high output power levels.

[0005] Most RF transistor amplifiers are implemented using silicon or wide-bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. As used herein, the term “group III nitride” refers to those semiconductor compounds formed between nitrogen and group III elements of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have empirical formulas in which one mole of nitrogen is combined with a total of one mole of group III elements.

[0006] Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal-oxide-semiconductor (“LDMOS”) transistors. Silicon LDMOS RF transistor amplifiers can exhibit high levels of linearity and can be manufactured relatively inexpensively. Group III nitride-based RF transistor amplifiers are typically implemented as high electron mobility transistors (“HEMTs”) and are primarily used in applications requiring high power and / or high-frequency operation where LDMOS RF transistor amplifiers may have inherent performance limitations.

[0007] An RF transistor amplifier may include one or more amplification stages, each typically implemented as a transistor amplifier. To increase output power and current handling capability, RF transistor amplifiers are often implemented in a "unit cell" configuration, where a large number of individual "unit cell" transistors are arranged in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or parallel.

[0008] RF transistor amplifiers often include matching circuitry, such as (1) impedance matching circuitry, designed to improve impedance matching between the RF transistor amplifier die and the transmission lines connected thereto (for RF signals at the amplifier's fundamental operating frequency), and (2) harmonic termination circuitry, designed to at least partially terminate harmonics, such as second and third harmonics, that may be generated during device operation. One or more RF transistor amplifier dies, along with the impedance matching and harmonic termination circuitry, may be encapsulated in a package. Electrical leads may extend from the package for electrically connecting the RF transistor amplifier to external circuitry elements such as input and output RF transmission lines and bias voltage sources.

[0009] As mentioned above, group III nitride-based RF transistor amplifiers are often used in high-power and / or high-frequency applications. Typically, a significant amount of heat is generated within the die of a group III nitride-based RF transistor amplifier during operation. If the RF transistor amplifier die becomes too hot, its performance (e.g., output power, efficiency, linearity, gain, etc.) may deteriorate and / or the RF transistor amplifier die may be damaged. Therefore, group III nitride-based RF transistor amplifiers are typically housed in packages optimized for heat removal. Summary of the Invention

[0010] According to embodiments of the present invention, an RF transistor amplifier is provided that offers an improved semiconductor package, including fewer bonding wires with improved connectivity options. RF transistor amplifiers according to some embodiments described herein can be cheaper and / or easier to manufacture and assemble, while providing improved performance.

[0011] According to some embodiments of the present invention, a radio frequency (“RF”) transistor amplifier includes: an RF transistor amplifier die having a semiconductor layer structure; an interconnect structure having opposing first and second sides, wherein the first side of the interconnect structure is adjacent to the surface of the RF transistor amplifier die, such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement; one or more circuit elements on the first and / or second sides of the interconnect structure; and encapsulation material on the RF transistor amplifier die and the interconnect structure.

[0012] In some embodiments, one or more circuit elements are surface-mounted on a first side and / or a second side of the interconnect structure.

[0013] In some embodiments, the RF transistor amplifier die further includes a gate terminal and a drain terminal on a first surface of the RF transistor amplifier die, and a source terminal on a second surface of the RF transistor amplifier die.

[0014] In some embodiments, the RF transistor amplifier further includes a spacer located on and electrically connected to the source terminal of the RF transistor amplifier die.

[0015] In some embodiments, the encapsulating material is also on the spacer.

[0016] In some embodiments, the RF transistor amplifier further includes gate lead pads and drain lead pads on the interconnect structure.

[0017] In some embodiments, the RF transistor amplifier further includes a first through-hole coupled to the gate lead pad and a second through-hole coupled to the drain lead pad.

[0018] In some embodiments, the interconnect structure includes a printed circuit board (PCB).

[0019] In some embodiments, one or more circuit elements include a circuit system comprising at least a portion of a harmonic termination circuit system and / or an impedance matching circuit system.

[0020] In some embodiments, the semiconductor layer structure includes a group III nitride.

[0021] In some embodiments, the semiconductor layer structure further includes a silicon and / or silicon carbide substrate.

[0022] In some embodiments, the semiconductor layer structure includes a high electron mobility transistor (HEMT) or a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

[0023] In some embodiments, the operating frequency of the RF transistor amplifier is between 500 MHz and 75 GHz.

[0024] In some embodiments, the RF transistor amplifier further includes auxiliary spacers located on one or more circuit elements.

[0025] In some embodiments, the encapsulating material exposes the surface of the auxiliary spacer.

[0026] In some embodiments, the encapsulation material exposes the surface of one or more circuit elements.

[0027] According to some embodiments of the present invention, an RF transistor amplifier package includes: an RF transistor amplifier die having a first main surface and a second main surface on the side opposite to the first main surface, the RF transistor amplifier die including a gate terminal and a drain terminal on the first main surface and a source terminal on the second main surface; an interconnection structure on the first main surface of the RF transistor amplifier die, the interconnection structure including a gate lead pad electrically coupled to the gate terminal and a drain lead pad electrically coupled to the drain terminal; an input lead extending from the outside of the RF transistor amplifier package and electrically coupled to the gate lead pad; and an output lead extending from the outside of the RF transistor amplifier package and electrically coupled to the drain lead pad.

[0028] In some embodiments, the interconnect structure further includes a first side adjacent to a first main surface of the RF transistor amplifier die and a second side opposite to the first side; and one or more circuit elements coupled between the gate terminal and the input lead and / or between the drain terminal and the output lead.

[0029] In some embodiments, one or more circuit elements are mounted on a first side and / or a second side of the interconnect structure.

[0030] In some embodiments, input leads and / or output leads are coupled to a first side and / or a second side of the interconnect structure.

[0031] In some embodiments, the RF transistor amplifier package further includes auxiliary spacers located on one or more circuit elements.

[0032] In some embodiments, the RF transistor amplifier package further includes a spacer located on and electrically connected to the source terminal of the RF transistor amplifier die.

[0033] In some embodiments, the RF transistor amplifier package further includes a carrier substrate located on the second main surface of the RF transistor amplifier die, with spacers located between the carrier substrate and the second main surface of the RF transistor amplifier die.

[0034] In some embodiments, the spacer is electrically connected to the carrier substrate.

[0035] In some embodiments, the RF transistor amplifier package further includes sidewalls and a cover, wherein the carrier substrate, sidewalls, and cover define an internal cavity, and the RF transistor amplifier die is located within the internal cavity.

[0036] In some embodiments, the RF transistor amplifier package further includes overmolding material on the interconnect structure and the RF transistor amplifier die.

[0037] In some embodiments, the interconnect structure includes an input matching circuit and / or an output matching circuit.

[0038] In some embodiments, the RF transistor amplifier die is a group III nitride-based RF transistor amplifier die.

[0039] In some embodiments, the RF transistor amplifier die includes a high electron mobility transistor (HEMT) or a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

[0040] In some embodiments, the operating frequency of the RF transistor amplifier package is in the R band, S band, X band, Ku band, K band, Ka band, and / or V band.

[0041] In some embodiments, the input leads are electrically coupled to the gate lead pads through through-holes in the encapsulation material on the interconnect structure.

[0042] According to some embodiments of the present invention, a transistor amplifier package includes: a group III nitride-based amplifier die including a first main surface and a second main surface on the side of the amplifier die opposite to the first main surface, the amplifier die including a gate terminal and a drain terminal on the first main surface and a source terminal on the second main surface; and an interconnect structure on the first main surface of the amplifier die and electrically coupled to the gate terminal and the drain terminal, wherein the interconnect structure includes one or more circuit elements coupled between the gate terminal and a first lead of the transistor amplifier package and / or between the drain terminal and a second lead of the transistor amplifier package. The interconnect structure has a first side and a second side on the side of the interconnect structure opposite to the first side, wherein the first side of the interconnect structure is adjacent to the first main surface of the amplifier die.

[0043] In some embodiments, one or more circuit elements are mounted on a first side and / or a second side of the interconnect structure.

[0044] In some embodiments, the first lead and the second lead are coupled to a first side of the interconnect structure.

[0045] In some embodiments, the first lead and the second lead are coupled to a second side of the interconnect structure.

[0046] In some embodiments, the interconnect structure includes a first interconnect pad and a second interconnect pad on a first side of the interconnect structure, the first interconnect pad being electrically coupled to the gate terminal of the amplifier die, and the second interconnect pad being electrically coupled to the drain terminal of the amplifier die.

[0047] In some embodiments, one or more circuit elements are mounted on a first side and / or a second side of the interconnect structure.

[0048] In some embodiments, the transistor amplifier package further includes a spacer located on and electrically connected to the source terminal of the amplifier die.

[0049] In some embodiments, the transistor amplifier package further includes encapsulation material on the amplifier die, interconnect structure, and spacers.

[0050] In some embodiments, the transistor amplifier package further includes auxiliary spacers on at least one of one or more circuit elements.

[0051] In some embodiments, the encapsulating material exposes the surface of the auxiliary spacer.

[0052] In some embodiments, the encapsulation material exposes the surface of one or more circuit elements.

[0053] In some embodiments, the interconnect structure includes a gate lead pad and a drain lead pad.

[0054] In some embodiments, the transistor amplifier package further includes: a gate connection pad coupled to a gate lead pad via a first through-hole in the encapsulation material; and a drain connection pad coupled to a drain lead pad via a second through-hole in the encapsulation material. The first lead is coupled to the gate connection pad and the second lead is coupled to the drain connection pad.

[0055] In some embodiments, the bottom surfaces of the gate connection pad, the drain connection pad, and the spacer are coplanar.

[0056] In some embodiments, one or more circuit elements include a circuit system comprising at least a portion of a harmonic termination circuit system and / or an impedance matching circuit system.

[0057] Other apparatuses, devices, and / or methods according to some embodiments will become clear to those skilled in the art upon viewing the following drawings and detailed description. All such additional embodiments, in addition to any and all combinations of the embodiments described above, are intended to be included in this description, within the scope of the invention, and protected by the appended claims. Attached Figure Description

[0058] Figure 1A This is a schematic plan view of a conventional group III nitride-based RF transistor amplifier die.

[0059] Figure 1B It is along Figure 1A A schematic cross-sectional view taken from line 1B-1B.

[0060] Figure 1C It is along Figure 1BA schematic cross-sectional view taken along line 1C-1C illustrates a metallization layer formed directly on the top surface of a semiconductor layer structure.

[0061] Figure 1D It is along Figure 1C A schematic cross-sectional view taken from line 1D-1D.

[0062] Figure 1E It is encapsulated in an open cavity package. Figures 1A-1D A schematic cross-sectional view of a group III nitride-based RF transistor amplifier die.

[0063] Figure 1F It is encapsulated in an overmolded package. Figures 1A-1D A schematic cross-sectional view of a group III nitride-based RF transistor amplifier die.

[0064] Figure 2A This is a schematic cross-sectional view of an embodiment of an RF transistor amplifier according to some embodiments of the present invention. Figure 2B and Figure 2C According to some embodiments of the present invention Figure 2A A schematic cross-sectional view of the various package options for the RF transistor amplifier. Figure 2D This is a schematic cross-sectional view of another embodiment of an RF transistor amplifier according to some embodiments of the present invention.

[0065] Figures 3A to 3F This is a schematic diagram illustrating a method for forming an RF transistor amplifier according to some embodiments of the present invention.

[0066] Figures 4A to 4C This is a schematic cross-sectional view of an RF transistor amplifier according to a further embodiment of the present invention.

[0067] Figures 5A to 5C This is a schematic cross-sectional view of an RF transistor amplifier according to an additional embodiment of the present invention.

[0068] Figures 6A to 6D This is a schematic cross-sectional view of an RF transistor amplifier according to an additional embodiment of the present invention.

[0069] Figures 7A to 7F yes Figures 6A to 6D A schematic cross-sectional view of an example of the package options for an RF transistor amplifier.

[0070] Figures 8A to 8C This is a schematic cross-sectional view of an RF transistor amplifier according to an additional embodiment of the present invention.

[0071] Figures 9A to 9D yes Figures 8A to 8CA schematic cross-sectional view of an example of the package options for an RF transistor amplifier. Detailed Implementation

[0072] In the following detailed description, numerous specific details are set forth to provide a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will understand that the present disclosure can be practiced without these specific details. In some instances, well-known methods, processes, components, and circuits have not been described in detail to avoid obscuring the present disclosure. All embodiments disclosed herein are intended to be implementable separately or in any manner and / or in combination. Aspects described with respect to one embodiment may be incorporated into different embodiments, but are not specifically described therewith. That is, features of all embodiments and / or any embodiments may be combined in any manner and / or in any combination.

[0073] Figures 1A to 1D Various views of a conventional group III nitride-based RF transistor amplifier die 10 are schematically illustrated. Specifically, Figure 1A This is a schematic plan view of an RF transistor amplifier die 10 based on group III nitrides, and Figure 1B It is along Figure 1A A schematic cross-sectional view of the RF transistor amplifier die 10 taken from line 1B-1B.

[0074] Figure 1C It is along Figure 1B A schematic cross-sectional view taken along line 1C-1C shows the metallization on the top surface of the semiconductor layer structure of the RF transistor amplifier die 10, and Figure 1D It is along Figure 1C A cross-sectional view of the RF transistor amplifier die 10 taken by line 1D-1D. Figure 1E and Figure 1F It is a diagram. Figures 1A-1D The RF transistor amplifier die 10 can be packaged to provide schematic cross-sectional views of two example configurations of packaged RF transistor amplifiers 1A and 1B, respectively. It should be recognized that... Figures 1A-1F (And many other figures in this application) are highly simplified figures, and actual RF transistor amplifiers may include more unit cells and various circuit systems and components not shown in the simplified figures herein.

[0075] like Figure 1AAs shown, the RF transistor amplifier die 10 includes a gate terminal 22 and a drain terminal 24 exposed on the top side of the RF transistor amplifier die 10. A first circuit element (not shown) can be connected to the gate terminal 22 via, for example, a bonding wire (not shown), and a second circuit element (not shown) can be connected to the drain terminal 24 via, for example, a bonding wire (not shown). For example, the first circuit element can transmit an input RF signal to be amplified to the RF transistor amplifier die 10, and the second circuit element can receive the amplified RF signal output by the RF transistor amplifier die 10. A protective insulating layer or pattern 28 may cover the remainder of the top surface of the RF transistor amplifier die 10.

[0076] like Figures 1B-1D As shown, the RF transistor amplifier die 10 also includes a semiconductor layer structure 30, a top-side metallization structure 20, and a back-side metallization structure that serves as the source terminal 26 of the RF transistor amplifier die 10.

[0077] The semiconductor layer structure 30 includes multiple semiconductor layers. The RF transistor amplifier die 10 can be a HEMT-based RF transistor amplifier die; therefore, the semiconductor layer structure 30 can include at least a channel layer and a barrier layer. (Reference) Figure 1D In the illustrated example, a total of three layers are shown: a semiconductor channel layer 34 and a semiconductor barrier layer 36 formed sequentially on a growth substrate 32, which can be a semiconductor or insulating substrate (such as a SiC or sapphire substrate). The growth substrate 32, even if formed of a non-semiconductor material, is considered part of the semiconductor layer structure 30.

[0078] For example, there is the co-assigned U.S. Patent Publication No. 2002 / 0066908A1, published on June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having Agate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same"; U.S. Patent Publication No. 2002 / 0167023A1, published on November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; U.S. Patent Publication No. 2004 / 0061129, published on April 1, 2004, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses"; and U.S. Patent Publication No. 2004 / 0061129, published on March 15, 2011, entitled "Nitride-Based Transistors With A Protective Layer And A Suitable structures for HEMT devices based on group III nitrides that can utilize embodiments of the present invention are described in U.S. Patent No. 7,906,799, entitled “Low-Damage Recess” and U.S. Patent No. 6,316,793, entitled “Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates”, issued November 13, 2001. The disclosures of these U.S. patents or patents are incorporated herein by reference in their entirety.

[0079] The growth substrate 32 may be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, 4H polytype silicon carbide. Other silicon carbide candidate polytypes may include 3C, 6H, and 15R polytypes. The growth substrate 32 may be a high-purity semi-insulating (HPSI) substrate, available from Cree Corporation. The term "semi-insulating" is used descriptively rather than in an absolute sense herein.

[0080] In some embodiments of the present invention, the bulk SiC crystals of the growth substrate 32 may have a density equal to or greater than approximately 1 x 10⁻⁶ at room temperature. 5The resistivity is measured in ohms-cm. Exemplary SiC substrates that may be used in some embodiments of the invention are manufactured, for example, by Cree Corporation, Durham, NC, the assignee of this invention, and methods for producing such substrates are described, for example, in U.S. Patent No. Re. 34,861, U.S. Patent No. 4,946,547, U.S. Patent No. 5,200,022, and U.S. Patent No. 6,218,680, the disclosures of which are incorporated herein by reference in their entirety. While SiC can be used as a substrate material, embodiments of this application may utilize any suitable substrate, such as sapphire (Al₂O₃), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The growth substrate 32 may be a SiC wafer, and the RF transistor amplifier die 10 may be formed at least partially via wafer-level processing, after which the wafer may be diced to provide a plurality of individual RF transistor amplifier dies 10.

[0081] Compared to sapphire (Al₂O₃) or silicon, SiC has a closer lattice match with group III nitrides, which are very common substrate materials for group III nitride devices. This closer lattice match in SiC can result in higher quality group III nitride films than those typically achievable on sapphire or silicon. SiC also has very high thermal conductivity, so the total output power of group III nitride devices on SiC is generally not as limited by substrate heat dissipation as it would be if the same device were formed on sapphire. Furthermore, the availability of semi-insulating SiC substrates can provide device isolation and reduced parasitic capacitance.

[0082] Optional buffer layers, nucleation layers, and / or transition layers (not shown) may be provided on the growth substrate 32 beneath the channel layer 34. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the SiC growth substrate 32 and the remainder of the semiconductor layer structure 30. Additionally, one or more strain-balanced transition layers may be provided, for example, as described in commonly assigned U.S. Patent Publication 2003 / 0102482A1, published June 5, 2003, entitled “Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors,” the disclosure of which is incorporated herein by reference as if fully set forth herein.

[0083] In some embodiments, the channel layer 34 and the barrier layer 36 may each be formed by epitaxial growth. Techniques for epitaxial growth of group III nitrides have been described, for example, in U.S. Patent Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are incorporated herein by reference in their entirety. The channel layer 34 may have a band gap smaller than that of the barrier layer 36, and the channel layer 34 may also have a greater electron affinity than that of the barrier layer 36. The channel layer 34 and the barrier layer 36 may comprise group III nitride-based materials.

[0084] In some embodiments, the channel layer 34 is a group III nitride material, such as Al. x Ga 1-x N, where 0 ≤ x < 1, is the condition that the energy at the conduction band edge of the channel layer 34 at the interface between the channel and barrier layers 34, 36 is less than the energy at the conduction band edge of the barrier layer 36. In some embodiments of the invention, x = 0 indicates that the channel layer 34 is gallium nitride (“GaN”). The channel layer 34 may also be other group III nitrides, such as InGaN, AlInGaN, etc. The channel layer 34 may be undoped or unintentionally doped and may be grown to a thickness, for example, greater than about 2 nm. The channel layer 34 may also be a multilayer structure, such as a superlattice or a combination of GaN, AlGaN, etc.

[0085] The channel layer 34 may have a band gap smaller than at least a portion of the band gap of the barrier layer 36, and the channel layer 34 may also have a greater electron affinity than the barrier layer 36. In some embodiments, the barrier layer 36 is AlN, AlInN, AlGaN, or AlInGaN, with a thickness between about 0.1 nm and about 10 nm or greater. In particular embodiments, the barrier layer 36 is thick enough and has a sufficiently high Al composition and doping to induce a significant carrier concentration at the interface between the channel layer 34 and the barrier layer 36.

[0086] The barrier layer 36 may be a group III nitride and may have a larger band gap and a smaller electron affinity than the channel layer 34. Therefore, in some embodiments of the invention, the barrier layer 36 may comprise AlGaN, AlInGaN, and / or AlN, or combinations thereof. For example, the barrier layer 36 may be from about 0.1 nm to about 30 nm thick. In some embodiments, the barrier layer 36 may be undoped or doped with an n-type dopant of less than about 10⁻⁶. 19 cm -3 The concentration. In some embodiments of the present invention, the barrier layer 36 is Al. x Ga 1-xN, where 0 < x < 1. In a particular embodiment, the aluminum concentration is approximately 25%. However, in other embodiments of the present invention, the barrier layer 36 comprises AlGaN with an aluminum concentration between approximately 5% and approximately 100%. In a specific embodiment of the present invention, the aluminum concentration is greater than approximately 10%.

[0087] Due to the bandgap difference between the barrier layer 36 and the channel layer 34 and the piezoelectric effect at the interface between the barrier layer 36 and the channel layer 34, a two-dimensional electron gas (2DEG) is induced in the channel layer 34 at the junction between the channel layer 34 and the barrier layer 36. The 2DEG acts as a highly conductive layer, which allows conduction between the source region and the associated drain region of each unit cell transistor 16 (see Figure 1C ), where the source region is the portion of the semiconductor layer structure 30 directly beneath the source finger 56 and the drain region is the portion of the semiconductor layer structure 30 directly beneath the corresponding drain finger 54.

[0088] Although, for illustrative purposes, the semiconductor layer structure 30 is shown as having a channel layer 34 and a barrier layer 36, the semiconductor layer structure 30 may include additional layers / structures / elements, such as one or more buffer and / or nucleation layers between the channel layer 34 and the substrate 32, and / or a cap layer on the barrier layer 36. HEMT structures including a substrate, a channel layer, a barrier layer, and other layers are discussed by way of example in U.S. Patent No. 5,192,987, U.S. Patent No. 5,296,395, U.S. Patent No. 6,316,793, U.S. Patent No. 6,548,333, U.S. Patent No. 7,544,963, U.S. Patent No. 7,548,112, U.S. Patent No. 7,592,211, U.S. Patent No. 7,615,774, U.S. Patent No. 7,548,112, and U.S. Patent No. 7,709,269, the disclosures of which are incorporated herein by reference in their entirety. For example, an AlN buffer layer may be formed on the upper surface of the substrate 32 to provide a suitable crystal structure transition between the grown substrate 32 and the remainder of the RF transistor amplifier die 10. Additionally, one or more strain-balanced transition layers may also and / or alternatively be provided, for example as described in co-owned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as if fully set forth herein. The optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HVPE.

[0089] Referring again to Figure 1BThe semiconductor layer structure 30 has a top side 12 and a bottom side 14. A top-side metallization structure 20 is formed on the top side 12 of the semiconductor layer structure 30, and a source terminal 26 is formed on the bottom side 14 of the semiconductor layer structure 30. The top-side metallization structure 20 specifically includes a conductive (typically metal) gate manifold 42 and a conductive (typically metal) drain manifold 44, conductive gate and drain vias 43 and 45, conductive gate and drain terminals 22 and 24, and gate fingers, drain fingers, and source fingers 52, 54, and 56 (described below). The gate manifold 42 is electrically connected to the gate terminal 22 through the gate via 43, and the drain manifold 44 is electrically connected to the drain terminal 24 through the conductive drain via 45. The gate vias and drain vias 43 and 45 may include, for example, metal-plated vias or metal pillars formed through a dielectric material such as silicon oxide, silicon nitride, or a dielectric underfill material. In some embodiments, the gate via and drain via 43, 45 may be omitted. In such embodiments, the gate manifold 42 may be integrally formed with the gate terminal 22 and / or the drain manifold 44 may be integrally formed with the drain terminal 24.

[0090] like Figure 1C As shown, the RF transistor amplifier die 10 includes a plurality of unit cell transistors 16, one of which is composed of Figure 1C The dashed box indicates this. Each unit cell transistor 16 includes a gate finger 52, a drain finger 54, and a source finger 56. The gate, drain, and source fingers 52, 54, and 56 are formed on the upper surface of the semiconductor layer structure 30 and include a portion of the top-side metallization structure 20. The top-side metallization structure 20 also includes a gate manifold 42 and a drain manifold 44. The gate finger 52 is electrically connected to the gate manifold 42, and the drain finger 54 is electrically connected to the drain manifold 44. The source finger 56 is electrically connected to the source terminal 26 via a plurality of conductive power vias 66 extending through the semiconductor layer structure 30. Figure 1B The conductive electrode via 66 may include a metal-plated via that extends completely through the semiconductor layer structure 30.

[0091] Figure 1E It includes Figures 1A-1D A schematic side view of a group III nitride-based RF transistor amplifier 1A packaged with an RF transistor amplifier die 10. (See diagram) Figure 1E As shown, the packaged RF transistor amplifier 1A includes an RF transistor amplifier die 10 and an open-cavity package 70. The package 70 includes a metal gate lead 72, a metal drain lead 74, a metal base 76, a ceramic sidewall 78, and a ceramic cap 80.

[0092] An RF transistor amplifier die 10 is mounted on the upper surface of a metal base 76 (which may be a metal block or flange) within a cavity defined by a metal base 76, ceramic sidewalls 78, and a ceramic cap 80. The source terminal 26 of the RF transistor amplifier die 10 can be connected to the metal base 76 (e.g., via die attachment material). The metal base 76 provides electrical connection to the source terminal 26 and also serves as a heat dissipation structure to dissipate heat generated within the RF transistor amplifier die 10. Heat is primarily generated in the upper portion of the RF transistor amplifier die 10, where relatively high current densities are generated, for example, in the channel region of the unit cell transistor 16. This heat can be transferred to the source terminal 26 via the source via 66 and the semiconductor layer structure 30, and then to the metal base 76.

[0093] Input matching circuit 90 and / or output matching circuit 92 may also be housed within package 70. Matching circuits 90 and 92 may be impedance matching circuits that match the impedance of the fundamental component of the RF signal input to or output from RF transistor amplifier 1A to the impedance at the input or output terminal of RF transistor amplifier die 10, respectively, and / or harmonic termination circuits configured to ground harmonics of the fundamental RF signal that may exist at the input or output terminal of RF transistor amplifier die 10. More than one input matching circuit 90 and / or output matching circuit 92 may be provided. Figure 1E As schematically shown, input and output matching circuits 90, 92 can be mounted on a metal base 76. Gate lead 72 can be connected to input matching circuit 90 via one or more first bonding wires 82, and input matching circuit 90 can be connected to the gate terminal 22 of RF transistor amplifier die 10 via one or more second bonding wires 84. Similarly, drain lead 74 can be connected to output matching circuit 92 via one or more fourth bonding wires 88, and output matching circuit 92 can be connected to the drain terminal 24 of RF transistor amplifier die 10 via one or more third bonding wires 86. Bonds 82, 84, 86, and 88 can form part of the input and / or output matching circuitry. Gate lead 72 and drain lead 74 can extend through ceramic sidewalls 78. The interior of package 70 may include an inflated cavity.

[0094] Figure 1FThis is a schematic side view of another conventionally packaged group III nitride-based RF transistor amplifier 1B. The RF transistor amplifier 1B differs from the RF transistor amplifier 1A in that it includes a different package 70'. Package 70' includes a metal base 76 (which acts as a metal heat sink and can be implemented as a metal slug) and gate and drain leads 72', 74'. The RF transistor amplifier 1B also includes a plastic overmolded component 78' that at least partially surrounds the RF transistor amplifier die 10, leads 72', 74', and metal base 76. Other components of the RF transistor amplifier 1B may be the same as those of similarly numbered components in the RF transistor amplifier 1A, and therefore further description of them will be omitted.

[0095] As mentioned above, conventional RF transistor amplifiers based on group III nitride packages, such as Figure 1E and Figure 1F The packaged RF transistor amplifiers 1A and 1B typically implement the gate and drain terminals on the upper side of the semiconductor layer structure and the source terminals on the lower side. Power vias extend through the semiconductor layer structure to electrically connect the source fingers in the upper part of the semiconductor layer structure to the source terminals. These conventional RF transistor amplifiers also typically use bonding wires to connect the RF transistor amplifier die to other components of the device, such as matching circuitry and / or input / output leads. These bonding wires have inherent inductance, which may supply some of the inductance for impedance matching and / or harmonic termination circuitry. The amount of inductance provided by the bonding wires can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the bonding wires, allowing the bonding wires to provide the desired amount of inductance. Unfortunately, as applications move to higher frequencies, the inductance of the bonding wires may exceed the inductance desired by the impedance matching and / or harmonic termination circuitry. When this occurs, very short and / or bonding wires with large cross-sectional areas can be used to reduce the inductance. However, very short junction lines can be difficult to solder in place, which can increase manufacturing costs and / or lead to a higher device failure rate. Junction lines with large cross-sectional areas may require larger gate and drain terminals on the RF transistor amplifier die, potentially resulting in an undesirable increase in the overall size of the RF transistor amplifier die. Moreover, in some higher frequency applications, even very short junction lines with large cross-sectional areas can have too much inductance, preventing the matching network from properly terminating, for example, second or third harmonics. While RF transistor amplifiers can be implemented as monolithic microwave integrated circuit (“MMIC”) devices to avoid the problem of excessive inductance in junction lines, MMIC RF amplifiers are more expensive to manufacture and can only be used in the frequency range of the matching circuit, thus reducing flexibility.

[0096] Furthermore, wire bonding equipment typically used in mass production may have a tolerance of + / - 1 mil, meaning that the length of any given bonded wire could differ from the expected length by up to 2 mil. For high-frequency applications, the inductance variation associated with a 2 mil bonded wire can be significant, so if the bonded wire is 1-2 mil shorter or longer than the expected nominal length, the performance of the matching circuit may be degraded.

[0097] According to embodiments of the present invention, a group III nitride-based RF transistor amplifier is provided, comprising an RF transistor amplifier die and incorporating packaging and / or mounting options that may exclude bonding wires for gate and / or drain connections. This can reduce the amount of inductance present in the circuit and the inductance variations that may occur when bonding wire connections are used. In some embodiments, the RF transistor amplifier may be mounted in a flip-chip arrangement, wherein the RF transistor amplifier die may be mounted in a stacked arrangement on another substrate, such as on an interconnect structure. The interconnect structure may include other circuit elements, such as impedance matching and / or harmonic termination circuitry, for example, for the RF transistor amplifier.

[0098] Embodiments of the invention will now be discussed in more detail with reference to the accompanying drawings.

[0099] Figure 2A This is a schematic cross-sectional view of an RF transistor amplifier 200A according to some embodiments of the present invention. Figure 2B and Figure 2C According to some embodiments of the present invention Figure 2A Schematic cross-sectional views of various package options 2000a and 2000b for the RF transistor amplifier 200A.

[0100] refer to Figure 2A Such as Figures 1A to 1D The RF transistor amplifier die 10 shown can be coupled to an interconnect structure 210. The interconnect structure 210 can be coupled to the gate terminal 22 and the drain terminal 24 of the RF transistor amplifier die 10. Although Figure 2A The diagram illustrates interconnect structure 210 directly coupled to RF transistor amplifier die 10, but it will be understood that other connection types are possible. For example, inserters, fan-in structures, fan-out structures, or other types of coupling elements may be coupled between interconnect structure 210 and RF transistor amplifier die 10.

[0101] Interconnect structure 210 may have exposed first interconnect pads 322 and second interconnect pads 324, which may be configured to be coupled to the gate terminal 22 and drain terminal 24 of the RF transistor amplifier die 10, respectively. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first and second interconnect pads 322, 324 to the gate terminal 22 and drain terminal 24, respectively. Although illustrated as a single pad, in some embodiments, one or more of the first and / or second interconnect pads 322, 324 may include multiple pads.

[0102] Interconnect structure 210 can be coupled to RF transistor amplifier die 10 on its first side 201. Furthermore, gate lead pad 382 and drain lead pad 384 can be exposed on the first side 201 of interconnect structure 210. Gate lead pad 382 and drain lead pad 384 can be configured to be electrically coupled to the gate terminal 22 and drain terminal 24 of RF transistor amplifier die 10, respectively, via corresponding conductive paths in interconnect structure 210.

[0103] First and second interconnect pads 322, 324 may be coupled to one or more conductive patterns 373 within the interconnect structure 210. The conductive patterns 373 may provide various wiring and / or circuitry within the interconnect structure 210. The conductive patterns 373 may be encapsulated in an insulating material 315. In some embodiments, the insulating material 315 may include, for example, silicon oxide, silicon nitride, oxides of the conductive patterns 373, polymers, molding compounds, or combinations thereof. In some embodiments, the interconnect structure 210 may be formed as a printed circuit board (PCB). In PCB embodiments, the insulating material 315 may be one or more substrates of the PCB, and the conductive patterns 373 may be traces, pads, and / or conductive vias formed within / through one or more substrates. Although illustrated as being formed within the insulating material 315, it will be understood that in some embodiments, the conductive patterns 373 may be formed on the surface of the interconnect structure 210 (e.g., as traces and / or pads on the PCB).

[0104] In some embodiments, conductive pattern 373 may connect first interconnect pad 322 to one or more first surface connection pads 372 and gate lead pads 382. In some embodiments, first surface connection pads 372 may be exposed on a first side 201 of interconnect structure 210. In some embodiments, first circuit element 350a may be coupled to one or more of the first surface connection pads 372 to be electrically coupled between gate lead pad 382 and first interconnect pad 322. In some embodiments, first circuit element 350a may be coupled between gate lead pad 382 and gate terminal 22 of RF transistor amplifier die 10. Therefore, first circuit element 350a may be electrically coupled between the gate of RF transistor amplifier die 10 and gate lead pad 382. In some embodiments, first circuit element 350a may be coupled to a first side 201 of interconnect structure 210. Therefore, first circuit element 350a may be coupled to the same side of interconnect structure 210 as RF transistor amplifier die 10 (e.g., first side 201).

[0105] Similarly, conductive pattern 373 can connect second interconnect pad 324 to one or more second surface connection pads 374 and drain lead pads 384. In some embodiments, second circuit element 350b can be coupled to one or more of the second surface connection pads 374 to be electrically coupled between drain lead pad 384 and second interconnect pad 324. In some embodiments, second surface connection pad 374 can be exposed on a first side 201 of interconnect structure 210. In some embodiments, second circuit element 350b can be coupled between drain lead pad 384 and drain terminal 24 of RF transistor amplifier die 10. Therefore, second circuit element 350b can be electrically coupled between the drain of RF transistor amplifier die 10 and drain lead pad 384. In some embodiments, second circuit element 350b can be coupled to the first side 201 of interconnect structure 210. Therefore, second circuit element 350b can be coupled to the same side of interconnect structure 210 as RF transistor amplifier die 10 (e.g., first side 201).

[0106] Although Figure 2A The diagram illustrates two second surface connection pads 374 and two first surface connection pads 372, but it will be understood that additional pads and / or connection points may be present on and / or within the interconnect structure 210 to provide electrical paths between the gate lead pad 382, ​​the first circuit element 350a and the gate terminal 22 of the RF transistor amplifier die 10, and / or between the drain lead pad 384, the second circuit element 350b and the drain terminal 24 of the RF transistor amplifier die 10.

[0107] First circuit element 350a and / or second circuit element 350b can provide various electronic capabilities to the RF transistor amplifier 200A. For example, first circuit element 350a and / or second circuit element 350b can include impedances (including, for example, resistive, inductive, and capacitive elements) that can be used for impedance matching and / or harmonic termination. In some embodiments, first circuit element 350a and / or second circuit element 350b can be or include surface mount devices. In some embodiments, first circuit element 350a and / or second circuit element 350b can be or include integrated passive devices (IPDs). In some embodiments, first circuit element 350a and / or second circuit element 350b can be or include harmonic and / or input / output impedance matching elements. Although in Figure 2A The components are illustrated as externally mounted, but in some embodiments, the first circuit element 350a and / or the second circuit element 350b may be implemented within the interconnect structure 210. For example, the first circuit element 350a and / or the second circuit element 350b may be implemented as traces, pads, and / or paths within the structure of the interconnect structure 210 (e.g., as parallel plate capacitors within the interconnect structure 210).

[0108] In some embodiments, the first circuit element 350a can be configured to provide input matching capability. Because it is located between the gate lead pad 382 and the RF transistor amplifier die 10, the first circuit element 350a can influence and / or modulate the signal supplied to the gate of the RF transistor amplifier die 10. Similarly, the second circuit element 350b can be configured to provide output matching capability. Because it is located between the drain lead pad 384 and the RF transistor amplifier die 10, the second circuit element 350b can influence and / or modulate the signal supplied from the drain of the RF transistor amplifier die 10. In some embodiments, the first circuit element 350a and / or the second circuit element 350b can be configured to provide harmonic termination. For example, the first circuit element 350a and / or the second circuit element 350b can be configured to terminate the second or third harmonics of the operating frequency of the RF transistor amplifier 200A.

[0109] By using interconnect structure 210 with exposed connection pads such as first and second surface connection pads 372, 374, surface mount devices can be used to provide circuit elements that can be coupled to RF transistor amplifier die 10. Surface mount devices can be replaced and / or configured as needed to provide a more flexible solution. For example, the same interconnect structure 210 can be used when different types of input / output matching and / or harmonic termination are required, but the first and / or second circuit elements 350a, 350b can be interchanged to provide different capabilities.

[0110] Although the first circuit element 350a and the second circuit element 350b are each illustrated as a single element, it will be understood that in some embodiments, the first circuit element 350a and / or the second circuit element 350b may include multiple discrete devices. The size and / or functionality of the first circuit element 350a may differ from that of the second circuit element 350b. Similarly, the interconnection between the first and second circuit elements 350a, 350b and the RF transistor amplifier die 10 is merely an example, and different configurations of the conductive pattern 373 may be provided without departing from the invention. Figure 2A The illustration shows a first circuit element 350a on the gate side of the RF transistor amplifier die 10 and a second circuit element 350b on the drain side of the RF transistor amplifier die 10. However, it will be understood that in some embodiments, one of the circuit elements may be omitted. For example, in some embodiments, only the first circuit element 350a or the second circuit element 350b may be present.

[0111] In some embodiments, spacers 245 may be formed on the RF transistor amplifier die 10. For example, spacers 245 may be formed on and / or in contact with the source terminal 26 of the RF transistor amplifier die 10. In some embodiments, spacers 245 may be formed of conductive and / or thermally conductive materials, such as metal. In some embodiments, spacers 245 may be or include gold (Au) copper (Cu), Cu alloys, gold-tin (AuSn), and / or epoxy resin, but the invention is not limited thereto. Spacers 245 may be configured to be electrically coupled to the source terminal 26 of the RF transistor amplifier die 10, and thus electrically coupled to the source of the RF transistor amplifier die 10 through a source via 66. In some embodiments, additional connection pads (not shown) may be provided, for example, electrically connected to the source terminal 26 through conductive patterns 373 and / or through spacers 245. In some embodiments, spacers 245 may be thermally conductive. Therefore, spacers 245 may be configured to dissipate heat transferred from the RF transistor amplifier die 10.

[0112] For example, depending on the interface between the source terminal 26 and the spacer 245, the source terminal 26 may directly contact the spacer 245. To improve the electrical and / or thermal interface between the source terminal 26 and the spacer 245, conductive and / or thermally conductive grease may be used between them. Alternatively, bonding layers may be used, such as eutectic bonding, metallic bonding, solder bonding, adhesive materials, or other suitable die attachment or bonding materials with desired electrical and / or thermal properties. Such bonding layers may be formed from different metal layers in the form of metal stacks or alloys of metals or other materials. Depending on the embodiment, the bonding layer may be made of a certain thickness to act as a spacer to provide a planar interface surface to facilitate electrical, thermal, and / or mechanical connections.

[0113] like Figure 2A As shown, in some embodiments, encapsulation material 325 may be formed on the RF transistor amplifier die 10, interconnect structure 210, spacer 245, gate lead pad 382, ​​and / or drain lead pad 384. Encapsulation material 325 can help prevent short circuits, enhance the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, encapsulation material 325 may also encapsulate the RF transistor amplifier die 10 in a protective material. In some embodiments, encapsulation material may include, for example, silicon oxide, silicon nitride, polymers, molding compounds, or combinations thereof.

[0114] In some embodiments, vias 215A and 215B may be formed in the encapsulation material 325. The vias 215A and 215B may include a conductive material and provide conductive paths to the gate lead pad 382 and / or the drain lead pad 384. For example, a first via 215A may electrically connect the gate lead pad 382 to the gate connection pad 282 and expose the gate connection pad 282, and a second via 215B may electrically connect the drain lead pad 384 to the drain connection pad 284.

[0115] In some embodiments, the gate connection pad 282 and the drain connection pad 284 may be substantially coplanar. In some embodiments, the encapsulation material 325 may be configured to expose the bottom surface 245a of the spacer 245, and the gate connection pad 282 and the drain connection pad 284 may also be substantially coplanar with the bottom surface 245a of the spacer 245, but the invention is not limited thereto.

[0116] The use of gate connection pad 282 and drain connection pad 284 allows for direct connections between the RF transistor amplifier die 10, interconnect structure 210, and first and second circuit elements 350a, 350b, and other combinations of pads and / or dies. For example, the RF transistor amplifier 200A can be configured to allow the gate connection pad 282, drain connection pad 284, and / or spacer 245 to be bonded to separate structures. For example, the gate connection pad 282 can be electrically connected (e.g., via solder balls or bumps) to a pad providing a gate signal, the drain connection pad 284 can be electrically connected (e.g., via solder balls or bumps) to a pad providing a drain signal, and the spacer 245 can be electrically connected (e.g., via solder balls or bumps) to a pad providing a source signal (e.g., a ground signal). The orientation of the gate connection pad 282, drain connection pad 284, and spacer 245 can allow for direct connections without requiring bonding wires. This allows for more cost-effective assembly and attachment.

[0117] The RF transistor amplifier 200A, including the interconnect structure 210, can be placed in various types of semiconductor packages. Figure 2B and Figure 2C This is a schematic cross-sectional view of various package options 2000a, 2000b of the RF transistor amplifier 200A according to some embodiments of the present invention. Figure 2B and Figure 2C This includes the components already discussed earlier, such as the RF transistor amplifier 200A, the RF transistor amplifier die 10, and the interconnect structure 210. Therefore, Figure 2B and Figure 2C The discussion will focus on those parts of the embodiments that differ from those discussed with respect to the previous figures.

[0118] refer to Figure 2B According to some embodiments of the present invention, a semiconductor package 2000a may be incorporated into an RF transistor amplifier 200A. The semiconductor package 2000a may be, for example, an open or open-cavity package. The semiconductor package 2000a may include a carrier substrate 410, sidewalls 520, and a cover 525. The carrier substrate 410, sidewalls 520, and cover 525 may define an internal cavity 530. The RF transistor amplifier 200A, including an RF transistor amplifier die 10 and interconnect structure 210, may be deployed within the internal cavity 530.

[0119] The carrier substrate 410 may include materials configured to assist in the thermal management of the semiconductor package 2000a. For example, the carrier substrate 410 may include copper and / or molybdenum. In some embodiments, the carrier substrate 410 may consist of multiple layers and / or include vias / interconnects. In an example embodiment, the carrier substrate 410 may be a multilayer copper / molybdenum / copper metal flange including a core molybdenum layer having a copper cladding layer on any of its main surfaces. The examples of materials for the carrier substrate 410 provided are not intended to limit the invention.

[0120] In some embodiments, the sidewall 520 and / or the cover 525 may be formed of or comprise an insulating material. For example, the sidewall 520 and / or the cover 525 may be formed of or comprise a ceramic and / or PCB. In some embodiments, the sidewall 520 and / or the cover 525 may be formed of, for example, Al2O3. The cover 525 may be adhered to the sidewall 520 using epoxy resin adhesive. The sidewall 520 may be attached to the carrier substrate 410 via, for example, soldering. Leads 415A, 415B may be configured to extend through the sidewall 520, but the invention is not limited thereto.

[0121] In some embodiments, the RF transistor amplifier 200A can be deployed on a carrier substrate 410 and leads 415A, 415B. Leads 415A, 415B can be coupled to the gate connection pad 282 and drain connection pad 284 of the RF transistor amplifier 200A, respectively, using, for example, a conductive die attachment material. In some embodiments, leads 415A, 415B can extend from the sidewall 520 to contact and / or electrically connect to the gate connection pad 282 and / or drain connection pad 284. Therefore, in some embodiments, the use of wire bonding to connect the RF transistor amplifier 200A to leads 415A, 415B can be avoided and / or reduced. Moreover, because the RF transistor amplifier 200A can be attached to the package substrate primarily via conductive die attachment such as solder, the assembly of the semiconductor package 2000a can be simpler and more cost-effective than conventional devices.

[0122] Circuit elements 350a and / or 350b mounted on interconnect structure 210 may include, for example, input matching components and output matching components for impedance matching at the fundamental frequency and / or harmonic termination circuitry systems for terminating intermodulation products to ground. These circuit elements 350a, 350b may be passive RF components, including, for example, resistors, capacitors, and / or inductors implemented in an integrated passive device or printed circuit board. Leads 415A, 415B allow the RF transistor amplifier 200A to be connected to an external device / circuit / power supply. In the depicted embodiment, interconnect structure 210 is used to connect conductive leads 415A, 415B to circuit elements 350a, 350b. The RF signal input to the RF transistor amplifier 200A via the first lead 415A can be transmitted to the circuit element 350a via the interconnect structure 210, and from there to the gate terminal 22 of the RF transistor amplifier die 10. The amplified output RF signal can be transmitted from the drain terminal 24 of the RF transistor amplifier die 10 to the circuit element 350b, and from there through the interconnect structure 210, wherein the RF signal is output via lead 415B.

[0123] In some embodiments, spacer 245 may be electrically and / or thermally coupled to carrier substrate 410. For example, carrier substrate 410 may be electrically grounded, for example, via an external connection (not shown), and spacer 245 may be further electrically coupled to source terminal 26. Thus, a ground signal may be provided to the source finger of RF transistor amplifier die 10. Spacer 245 may also be configured to thermally transfer heat from RF transistor amplifier die 10 to carrier substrate 410. Thus, spacer 245 may assist in the thermal management of RF transistor amplifier 200A. In some embodiments, spacer 245 may be bonded to source terminal 26 on one side, and bonding layers / structures may be provided on the other side of spacer 245 or on substrate 410 to bond spacer 245 to substrate 410.

[0124] In some embodiments, spacer 245 may be electrically isolated from carrier substrate 410 and may be provided within semiconductor package 2000a with a connection to a reference signal (e.g., ground) for direct coupling to spacer 245. In some embodiments, spacer 245 may be electrically insulated and may be provided within semiconductor package 2000a with a connection to a reference signal (e.g., ground) for direct coupling to source terminal 26 of RF transistor amplifier die 10. For example, RF transistor amplifier 200A may provide an electrical connection to which a reference signal can be attached for electrical connection to source terminal 26 of RF transistor amplifier 200A.

[0125] Figure 2B The use of riser 412 is also illustrated. Riser 412 may be part of (e.g., integral with) carrier substrate 410 or an additional separate structure. In some embodiments, riser 412 may include elements such as, for example, spacers (e.g., similarly formed to spacer 425), bonding / attachment layers (e.g., eutectic layers, epoxy resin layers), metal layers, and / or thermally conductive layers. Riser 412 may be formed of one or more layers. In some embodiments, riser 412 may be used to raise the level of RF transistor amplifier 200A and / or provide a planar surface for mounting RF transistor amplifier 200A.

[0126] refer to Figure 2C The semiconductor package 2000b may be combined with the RF transistor amplifier 200A according to an embodiment of the present invention. The semiconductor package 2000b may be, for example, an overmolded plastic (OMP) package. The semiconductor package 2000b may include a carrier substrate 410 on which the RF transistor amplifier 200A, combined with the interconnect structure 210, is deployed.

[0127] The RF transistor amplifier 200A, the RF transistor amplifier die 10, and the interconnect structure 210 can be encapsulated in an overmolding material 540. The overmolding material 540 can be formed of plastic or a plastic polymer compound, which is injection molded around the RF transistor amplifier 200A to provide protection from the external environment.

[0128] A method for manufacturing an OMP semiconductor package 2000b that can be modified to incorporate an RF transistor amplifier 200A including an interconnect structure 210 is described in U.S. Patent No. 9,515,011 entitled “Over-mold plasticpackaged wide band-gap power transistors and MMICS”, issued to Wood et al. on December 6, 2016. The disclosure of that U.S. Patent is incorporated herein by reference as if fully set forth herein.

[0129] In the semiconductor package 2000b according to the invention, leads 415A, 415B can extend from the outside of the semiconductor package 2000b and into the overmolding material 540 to contact and / or electrically connect (e.g., via conductive die attachment material) to the gate connection pad 282 and / or drain connection pad 284 of the RF transistor amplifier 200A. Therefore, in some embodiments, the use of wire bonding to connect the RF transistor amplifier 200A to leads 415A, 415B can be avoided and / or reduced. Moreover, because the RF transistor amplifier 200A can be attached within the semiconductor package 2000b primarily via conductive die attachment such as solder, the assembly of the semiconductor package 2000b can be simpler and more cost-effective than conventional devices.

[0130] As in semiconductor package 2000a, the carrier substrate 410 of semiconductor package 2000b may include materials configured to assist thermal management. For example, carrier substrate 410 may include copper and / or molybdenum. In some embodiments, carrier substrate 410 may consist of multiple layers and / or include vias / interconnects. In some embodiments, carrier substrate 410 may include a metal heat sink as part of a lead frame or a metal strip at least partially surrounded by a plastic overmolded material 540. The examples of materials provided for carrier substrate 410 are not intended to limit the invention. In some embodiments, leads 415A, 415B may be electrically isolated from carrier substrate 410. For example, in some embodiments, an insulating layer 535 may be present between leads 415A, 415B and carrier substrate 410.

[0131] Similar to semiconductor package 2000a, the carrier substrate 410 of semiconductor package 2000b can be electrically coupled and / or thermally coupled to spacer 245. For example, carrier substrate 410 can be electrically grounded, for instance, via an external connection (not shown), and spacer 245 can also be electrically coupled to the source terminal 26 of RF transistor amplifier die 10. Therefore, a ground signal can be provided to the source of RF transistor amplifier die 10. Signals can also be supplied to source terminal 26 via an external connection to spacer 245 and / or via an electrical connection via a conductive pattern coupled to source terminal 26, as discussed herein with respect to semiconductor package 2000a. In some embodiments, semiconductor package 2000b can incorporate riser 412, as discussed herein with respect to... Figure 2A The subject of discussion.

[0132] Figure 2B and Figure 2C The package embodiment shown is merely an example intended to illustrate how the interconnect structure 210 and the RF transistor amplifier die 10 can be coupled within a semiconductor package. It will be understood that many other possible configurations and / or orientations of the semiconductor package are possible without departing from the invention.

[0133] Although Figures 2A to 2C The illustration shows an embodiment in which circuit elements 350a and 350b are located on the bottom surface (e.g., first side 201) of interconnect structure 210 (e.g., between interconnect structure 210 and RF transistor amplifier die 10), but it will be understood that other combinations are also possible. In some embodiments, circuit elements 350a and 350b may be located on the upper surface of interconnect structure 210 (e.g., on interconnect structure 210 opposite to RF transistor amplifier die 10). In some embodiments, circuit elements 350a and 350b may be located on opposite sides of interconnect structure 210. In some embodiments, circuit elements 350a and 350b may be located on the side surfaces of interconnect structure 210.

[0134] Figure 2D This is a schematic cross-sectional view of another embodiment of the RF transistor amplifier 200B according to some embodiments of the present invention. Reference Figure 2D The RF transistor amplifier 200B can be similar to Figure 2A The main difference of the RF transistor amplifier 200A is that the first and second circuit elements 350a and 350b are deployed on the top surface of the interconnect structure 210'.

[0135] Interconnect structure 210' may have a second side 202 opposite to the first side 201 of interconnect structure 210'. A first surface connection pad 372' and a second surface connection pad 374' may be exposed on the second side 202 of interconnect structure 210'. The first and second surface connection pads 372' and 374' may be coupled to a first interconnect pad 322 and a second interconnect pad 324, respectively, via a conductive pattern 373 within interconnect structure 210'. The first and second interconnect pads 322 and 324 may be configured to be coupled to the gate terminal 22 and the drain terminal 24 of RF transistor amplifier die 10, respectively.

[0136] and Figure 2A Similar to interconnect structure 210, interconnect structure 210' may have exposed gate lead pad 382' and exposed drain lead pad 384' on the first side 201 of interconnect structure 210'. Gate lead pad 382' and drain lead pad 384' may be coupled to gate connection pad 282 and drain connection pad 284 respectively through through-holes 215A and 215B.

[0137] In the RF transistor amplifier 200B, a first circuit element 350a can be coupled to a first surface connection pad 372' on the second side 202 (e.g., the top surface) of the interconnect structure 210'. Similarly, a second circuit element 350b can be coupled to a second surface connection pad 374' on the second side 202 (e.g., the top surface) of the interconnect structure 210'. The first circuit element 350a can therefore be electrically coupled in the path between the gate lead pad 382' and the gate terminal 22 of the RF transistor amplifier die 10. Similarly, the second circuit element 350b can therefore be electrically coupled in the path between the drain lead pad 384' and the drain terminal 24 of the RF transistor amplifier die 10.

[0138] As will be understood by those skilled in the art, Figure 2D The RF transistor amplifier 200B can be used with Figure 2A The RF transistor amplifier 200A is mounted in a similar manner in the package, such as... Figure 2B and Figure 2C In semiconductor packages 2000a and 2000b.

[0139] Figures 3A to 3F This is a schematic diagram illustrating a method of forming an RF transistor amplifier 200A by coupling an interconnect structure 210 and an RF transistor amplifier die 10 according to certain embodiments of the present invention. Figure 3AAs shown, an interconnect structure 210 may be provided. The interconnect structure 210 may have a first side 201 and a second side 202. In some embodiments, the first side 201 may include exposed first and second interconnect pads 322, 324 and first and second surface connection pads 372, 374.

[0140] refer to Figure 3B First circuit element 350a and second circuit element 350b may be mounted on the first side 201 of interconnect structure 210. For example, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first circuit element 350a to one or more first surface connection pads 372. Similarly, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the second circuit element 350b to one or more second surface connection pads 374.

[0141] refer to Figure 3C The RF transistor amplifier die 10 can be mounted on the first side 201 of the interconnect structure 210. For example, bonding elements (e.g., solder balls and / or bumps 320) can be used to couple the gate terminal 22 and drain terminal 24 of the RF transistor amplifier die 10 to the first and second interconnect pads 322, 324, respectively. It will be understood that... Figure 3B and Figure 3C The order can be reversed so that the RF transistor amplifier die 10 is coupled to the interconnect structure 210 before the first and second circuit elements 350a, 350b.

[0142] refer to Figure 3D A spacer 245 may be provided on the source terminal 26 of the RF transistor amplifier die. In some embodiments, the spacer 245 may be coupled to the source terminal 26 via a die attachment layer such as a eutectic layer. In some embodiments, the spacer 245 may be coupled to the source terminal 26 via a metal layer to form a eutectic or other metal bond. In some embodiments, the spacer 245 may be coupled to the source terminal 26 via a thermal adhesive.

[0143] refer to Figure 3E Vias 215A and 215B can be formed on the gate lead pad 382 and drain lead pad 384, respectively. For example, vias 215A and 215B can be formed by forming conductive pillars on the gate lead pad 382 and the drain lead pad 384. In some embodiments, vias 215A and 215B may include copper pillars. For example, conductive pillars can be formed by electroplating copper seed layers on the gate lead pads and drain lead pads 382 and 384 and forming vias 215A and 215B thereon using one or more masks. Gate connection pads 282 and drain connection pads 284 can then be formed on the vias 215A and 215B.

[0144] like Figure 3F As shown, encapsulation material 325 can be injected (e.g., via a capillary underfill process) between the conductive structures of the RF transistor amplifier die 10, the first and second circuit elements 350a, 350b, the interconnect structure 210, the vias 215A, 215B, the gate connection pad 282, and / or the drain connection pad 284. Encapsulation material 325 can help prevent short circuits, enhance the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, encapsulation material 325 can also encapsulate the RF transistor amplifier die 10 in a protective material. Encapsulation material 325 can be processed (e.g., planarized) to expose the gate connection pad 282, the drain connection pad 284, and / or the spacer 245.

[0145] In some embodiments, Figure 3E and Figure 3F The order of operations shown can be reversed. For example, in some embodiments, encapsulation material 325 may be formed on the RF transistor amplifier die 10, the first and second circuit elements 350a, 350b, and / or the interconnect structure 210. Vias 215A, 215B may then be formed in the encapsulation material 325. For example, the encapsulation material 325 may be etched or otherwise selectively removed to expose the gate lead pad 382 and the drain lead pad 384. Vias 215A, 215B may then be formed on the gate lead pad 382 and the drain lead pad 384 within the encapsulation material 325. Gate connection pad 282 and / or drain connection pad 284 may be formed on and connected to the vias 215A, 215B to be exposed from the encapsulation material 325, as shown. Figure 3F As shown in the image.

[0146] In some embodiments, portions of the through holes 215A, 215B and / or the encapsulating material 325 may be omitted. For example, Figures 4A to 4C This is a schematic cross-sectional view of an RF transistor amplifier 200C, including an RF transistor amplifier die 10 coupled to an interconnect structure 210, according to some embodiments of the present invention. Figure 4A As shown, the interconnect structure 210 can be connected with... Figures 2A to 2C The interconnection structures are basically similar, therefore, their repeated descriptions will be omitted. For example, Figure 4A An embodiment of the RF transistor amplifier 200C may omit a portion of the encapsulation material 325, the through holes 215A, 215B and / or the gate / drain connection pads 282, 284 and directly expose the gate lead pad 382 and the drain lead pad 384.

[0147] like Figure 4AAs shown, the encapsulation material 325 may be present on portions of the RF transistor amplifier die 10, portions of the first side 201 of the interconnect structure 210, and the first and second circuit elements 350a, 350b. In some embodiments, the bottom surface 245a of the spacer 245 may be exposed by the encapsulation material 325. It will be understood that different configurations of the encapsulation material 325 may be present in some embodiments. For example, in some embodiments, all of the encapsulation material 325 may be removed. In some embodiments, the encapsulation material 325 may be present on the RF transistor amplifier die 10 but not on the first and second circuit elements 350a, 350b.

[0148] In the RF transistor amplifier 200C, the gate lead pad 382, ​​drain lead pad 384, and / or spacer 245 can be directly connected (e.g., via solder balls and / or bumps). Using direct connections can reduce and / or eliminate the use of wire connections.

[0149] It will be understood that the manufacturing method of the RF transistor amplifier 200C can be similar to that regarding Figures 3A to 3F The manufacturing methods of RF transistor amplifiers 200A and 200B are shown. For example, the formation of through-holes 215A and 215B can be omitted when manufacturing RF transistor amplifier 200C (regarding...). Figure 3E (as shown in the diagram), and when forming encapsulating material 325 (about Figure 3F When illustrating, portions of the encapsulation material formed on the gate lead pad 382 and / or drain lead pad 384 can be omitted.

[0150] Figure 4A The RF transistor amplifier 200C shown can be used in a variety of package configurations. Figure 4B and Figure 4C The illustration is related to the article. Figure 2B and Figure 2C The use of the package discussed is similar to that of other packages. For example, the interconnect structure 210 and the RF transistor amplifier die 10 can be placed in an open-cavity semiconductor package 4000a. Figure 4B ) or OMP package 4000b ( Figure 4C (in) (compared to previous information) Figure 2B and Figure 2C The discussion focuses on similar semiconductor packages 4000a and 4000b. Figure 4B and Figure 4CFor the sake of simplicity, the components will not be discussed further. In some embodiments, the gate lead pad 382 may be coupled to the gate lead 415A via bonding elements (e.g., solder balls and / or bumps), and the drain lead pad 384 may also be coupled to the drain lead 415B. It will be understood that a variety of other possible configurations and / or orientations of the semiconductor package are possible without departing from the present invention.

[0151] Leads 415A and 415B can be configured to extend through sidewall 520. Figure 4B ) and / or overmolding material 540 ( Figure 4C However, the invention is not limited thereto. In some embodiments, the RF transistor amplifier die 10 may be deployed on a carrier substrate 410, and the interconnect structure 210 may be deployed on the RF transistor amplifier die 10 and leads 415A, 415B. Leads 415A, 415B may be coupled to a first side 201 of the interconnect structure 210 and may be electrically connected to the RF transistor amplifier die 10 via the interconnect structure 210. Moreover, the interconnect structure 210 can allow for additional internalized functionalities of first and second circuit elements 350a, 350b, such as harmonic termination and / or input / output impedance matching. Furthermore, the use of the interconnect structure 210 allows for greater flexibility, as different performance characteristics (e.g., to address harmonics of different frequencies, different impedances, etc.) can be achieved simply by swapping the interconnect structure 210 and / or the first and second circuit elements 350a, 350b.

[0152] In some embodiments, spacer 245 may be electrically and / or thermally coupled to carrier substrate 410. For example, carrier substrate 410 may be electrically grounded, for example, via an external connection (not shown), and spacer 245 may also be electrically coupled to source terminal 26. Thus, a ground signal can be provided to the source finger of RF transistor amplifier die 10.

[0153] In some embodiments, spacer 245 may be electrically isolated from carrier substrate 410 and may be provided within semiconductor packages 4000a, 4000b with a connection to a reference signal (e.g., ground) for direct coupling to spacer 245. In some embodiments, spacer 245 may be electrically insulated and may be provided within semiconductor packages 4000a, 4000b with a connection to a reference signal (e.g., ground) for direct coupling to source terminal 26 of RF transistor amplifier die 10. For example, RF transistor amplifier 200C may provide an external connection that can be attached to a reference signal for electrical connection to source terminal 26 of RF transistor amplifier 200C.

[0154] exist Figures 4A to 4CIn the diagram, the first and second circuit elements 350a and 350b are illustrated as being located on the same side (first side 201) of the interconnect structure 210. However, the invention is not limited thereto. Figure 2D The implementation is similar and can be modified. Figure 4A In some embodiments, the first and second circuit elements 350a and 350b are located on the second side 202 of the interconnect structure 210, or one of the first and second circuit elements 350a and 350b is located on the first side 201 of the interconnect structure 210 while the other of the first and second circuit elements 350a and 350b is located on the second side 202 of the interconnect structure 210.

[0155] exist Figures 2A to 2C and Figures 4A to 4C In this configuration, the gate lead pad 382 and the drain lead pad 384 are disposed on the same side of the interconnect structure 210 as the first circuit element 350a and the second circuit element 350b. However, embodiments of the present invention are not limited thereto. For example, Figures 5A to 5C This is a schematic cross-sectional view of an RF transistor amplifier 200D comprising an RF transistor amplifier die 10 coupled to an interconnect structure 210”, according to some embodiments of the present invention. Figure 5A As shown, the interconnect structure 210" may include connections with... Figures 2A to 2C Components similar to those in the original text will have their repeated descriptions omitted. For example, Figure 5A An embodiment of the RF transistor amplifier 200D may provide a gate lead pad 382” and a drain lead pad 384” on the second side 202 of the interconnect structure 210” opposite to the first circuit element 350a and the second circuit element 350b”.

[0156] refer to Figure 5A The interconnect structure 210” may have a second side 202 opposite to the first side 201 of the interconnect structure 210”. Gate lead pad 382” and drain lead pad 384” may be located on the second side 202 of the interconnect structure 210”. The gate lead pad and drain lead pads 382”, 384” may be coupled to the first and second circuit elements 350a, 350b respectively via conductive patterns 373 within the interconnect structure 210”. For example, the gate lead pad 382” may be coupled to the first surface connection pad 372 via conductive patterns 373, and the drain lead pad 384” may be coupled to the second surface connection pad 374 via conductive patterns 373. The first and second interconnect pads 322, 324 may be coupled to the first and second circuit elements 350a, 350b respectively via additional conductive patterns 373. The first and second interconnect pads 322 and 324 can be configured to be coupled to the gate terminal 22 and the drain terminal 24 of the RF transistor amplifier die 10, respectively.

[0157] and Figure 2A Unlike interconnect structure 210, interconnect structure 210” can expose the gate lead pad 382” and drain lead pad 384” of the second side 202 of interconnect structure 210”. In RF transistor amplifier 200D, first circuit element 350a can be coupled to the first surface connection pad 372 of the first side 201 of interconnect structure 210”. Similarly, second circuit element 350b can be coupled to the second surface connection pad 374 of the first side 201 of interconnect structure 210”. First circuit element 350a can therefore be electrically coupled in the path between the gate lead pad 382” and the gate terminal 22 of RF transistor amplifier die 10. Similarly, second circuit element 350b can therefore be electrically coupled in the path between the drain lead pad 384” and the drain terminal 24 of RF transistor amplifier die 10.

[0158] Figure 5B and Figure 5C The illustration is related to the article. Figure 2B and Figure 2C The use of encapsulation discussed is similar Figure 5A The use of packaging in this embodiment. For example, the interconnect structure 210” and the RF transistor amplifier die 10 can be placed in an open-cavity semiconductor package 5000a ( Figure 5B ) or OMP package 5000b ( Figure 5C (in) (compared to previous information) Figure 2B and Figure 2C and / or Figure 4B and Figure 4C The discussion focuses on similar semiconductor packages, such as 5000a and 5000b. Figure 5B and Figure 5C For simplicity, the components will not be discussed further. In some embodiments, the gate lead pad 382” may be coupled to the gate lead 415A via bonding elements (e.g., solder balls and / or bumps), and the drain lead pad 384” may also be coupled to the drain lead 415B. In some embodiments, the gate lead 415a and / or the drain lead 415b may extend over the second side 202 of the interconnect structure 210” to be coupled to the gate lead pad 382” and the drain lead pad 384”, respectively. In some embodiments, a portion of the interconnect structure 210” may be below the gate lead 415a and / or the drain lead 415b. It will be understood that a variety of other possible configurations and / or orientations of the semiconductor package are possible without departing from the invention.

[0159] Leads 415A and 415B can be configured to extend through sidewall 520. Figure 5B ) and / or overmolding material 540 ( Figure 5CHowever, the invention is not limited thereto. In some embodiments, the RF transistor amplifier die 10 may be deployed on the carrier substrate 410, the interconnect structure 210” may be deployed on the RF transistor amplifier die 10, and leads 415A, 415B may be deployed on the interconnect structure 210”. Leads 415A, 415B may be coupled to a second side 202 of the interconnect structure 210” and may be electrically connected to the RF transistor amplifier die 10 through the interconnect structure 210”. Moreover, the interconnect structure 210” may be coupled to and / or include first and second circuit elements 350a, 350b that may allow additional internalized functionalities such as harmonic termination and / or input / output impedance matching.

[0160] In some embodiments, spacer 245 may be electrically and / or thermally coupled to carrier substrate 410. For example, carrier substrate 410 may be electrically grounded, for example, via an external connection (not shown), and spacer 245 may be further electrically coupled to source terminal 26. Thus, a ground signal can be provided to the source of RF transistor amplifier die 10.

[0161] In some embodiments, spacer 245 may be electrically isolated from carrier substrate 410 and may be provided within semiconductor packages 5000a, 5000b for direct coupling to a reference signal (e.g., ground). In some embodiments, spacer 245 may be electrically insulated and may be provided within semiconductor packages 5000a, 5000b for direct coupling to the source terminal 26 of RF transistor amplifier die 10. For example, RF transistor amplifier 200D may provide an external connection to which a reference signal can be attached for electrical connection to the source terminal 26 of RF transistor amplifier die 10.

[0162] exist Figures 2A-5C Various embodiments are illustrated in the diagram, showing the encapsulation material 325 of the RF transistor amplifiers 200A-D on the first and second circuit elements 350a, 350b. However, the invention is not limited to this configuration. Depending on the electrical and thermal requirements of the first and second circuit elements 350a, 350b, alternative and / or additional terminal / joint / spacer structures may be used with at least one of the first and second circuit elements 350a, 350b to provide conductivity, thermal conductivity, and / or a mechanical interface with one or more of the first and second circuit elements 350a, 350b.

[0163] In some embodiments, the surfaces of the first and second circuit elements 350a, 350b may be exposed and / or coupled to an auxiliary spacer that is part of an RF transistor amplifier. For example... Figure 6AThis is a schematic cross-sectional view of an RF transistor amplifier 200E, comprising an RF transistor amplifier die 10 coupled to an interconnect structure 210, according to some embodiments of the present invention. Figure 6A As shown, the interconnect structure 210 and / or the RF transistor amplifier die 10 can be connected with... Figures 2A to 2C The interconnect structure and / or RF transistor amplifier die are essentially similar, therefore, their repeated description will be omitted. Figure 6A An embodiment of the RF transistor amplifier 200E may include, for example, a first auxiliary spacer 246a and a second auxiliary spacer 246b.

[0164] In some embodiments, a first auxiliary spacer 246a may be formed on a first circuit element 350a. In some embodiments, a second auxiliary spacer 246b may be formed on a second circuit element 350b. For example, the first auxiliary spacer 246a may be formed on and / or in contact with the first circuit element 350a, and the second auxiliary spacer 246b may be formed on and / or in contact with the second circuit element 350b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be formed of a conductive and / or thermally conductive material such as metal. In some embodiments, the surfaces of the first and / or second auxiliary spacers 246a, 246b may be exposed from the encapsulation material 325. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be or include gold (Au) copper (Cu), Cu alloys, gold-tin (AuSn) and / or epoxy resin, but the invention is not limited thereto. The first and / or second auxiliary spacers 246a, 246b may be configured to be electrically coupled to the first and / or second circuit elements 350a, 350b, and may, for example, be provided with a mechanism through which a ground signal is provided to the first and / or second circuit elements 350a, 350b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be thermally conductive. Therefore, the first and / or second auxiliary spacers 246a, 246b may be configured to dissipate heat transferred from the first and / or second circuit elements 350a, 350b.

[0165] In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be made of a material similar to that of spacer 245, but the invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be made of a material different from that of spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be electrically disconnected from spacer 245. Forming the first and / or second auxiliary spacers 246a, 246b of a material different from that of spacer 245 and / or electrically disconnected from spacer 245 can help limit current sharing and / or current eddy currents between the RF transistor amplifier die 10 and the first and / or second circuit elements 350a, 350b. Although the first auxiliary spacer 246a, the second auxiliary spacer 246b, and spacer 245 are illustrated as separate discrete elements, the invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and spacer 245 may be connected together as a monolithic layer (see, for example...). Figure 6C ).

[0166] The material / thickness of the first and second auxiliary spacers 246a, 246b may be the same as or different from that of spacer 245. In some embodiments, spacer 245 and the first and second auxiliary spacers 246a, 246b have different thicknesses such that the bottoms of the first and second auxiliary spacers 246a, 246b are flush with the bottom of spacer 245 to facilitate the packaging / manufacturing / bonding of the RF transistor amplifier 200E to a package substrate or circuit board. In some embodiments, spacer 245 has the same thickness as the first and second auxiliary spacers 246a, 246b. In still other embodiments, spacer 245 spans the RF transistor amplifier die 210 and at least one or all of the first and second circuit elements 350, 350b to provide, for example, the benefit of a planar interface surface. Additional and / or intervening spacers, bonding elements, and other layers may be provided to provide the desired electrical, thermal, and mechanical interfaces. Depending on the desired electrical, thermal, and / or mechanical properties, these layers may be made of conductive and / or thermally conductive and / or insulating materials.

[0167] In some embodiments, the exposed surfaces of the first auxiliary spacer 246a, the second auxiliary spacer 246b, the spacer 245, the gate connection pad 282, and / or the drain connection pad 284 may be substantially coplanar. That is, the RF transistor amplifier 200E may be configured to be mounted to separate boards (e.g., via an attachment method such as solder).

[0168] It will be understood that the manufacturing method of the RF transistor amplifier 200E can be related to... Figures 3A to 3FThe manufacturing methods for the RF transistor amplifiers 200A and 200B shown are similar. For example, manufacturing the RF transistor amplifier 200E may include placing a first auxiliary spacer 246a on a first circuit element 350a and placing a second auxiliary spacer 246b on a second circuit element 350b. For example, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be electrically connected and / or thermally connected to the first and second circuit elements 350a, 350b, respectively (e.g., via die attachment material). This step may be similar to, for example, placing a spacer 245 on the RF transistor amplifier die 10 (regarding...). Figure 3D Perform the process in a similar manner (as shown in the diagram). Then, you can perform the deposition of encapsulating material 325 (regarding...). Figure 3F (Illustrated) To form an encapsulating material 325 on portions of the first and / or second auxiliary spacers 246a, 246b and expose a portion (e.g., surface) of the first and / or second auxiliary spacers 246a, 246b.

[0169] Figure 6B The diagram illustrates the relationship between... Figures 4A to 4C The RF transistor amplifier 200F includes first and / or second auxiliary spacers 246a, 246b, similar to the RF transistor amplifier 200C. The RF transistor amplifier 200F may include first and / or second auxiliary spacers 246a, 246b respectively on the first and / or second circuit elements 350a, 350b, and may expose gate lead pad 382 and / or drain lead pad 384. The first and / or second auxiliary spacers 246a, 246b of the RF transistor amplifier 200F can be connected to... Figure 6A Those similar to these will be omitted, and repeated descriptions will be omitted.

[0170] As discussed above, in some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be interconnected and / or integrally formed. Figure 6CAn embodiment of an RF transistor amplifier 200F' with an integrated spacer layer 245' is illustrated. The integrated spacer layer 245' may extend to connect and / or contact a first circuit element 350a, a second circuit element 350b, and an RF transistor amplifier die 10 (e.g., the source terminal 26 of the RF transistor amplifier die 10). In some embodiments, the surface 245a' of the integrated spacer layer 245' may be exposed from the encapsulation material 325. In some embodiments, the integrated spacer layer 245' may be formed of the same or similar material as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or spacer 245 described with respect to previous embodiments. For example, the integrated spacer layer 245' may be formed of a conductive and / or thermally conductive material such as a metal. In some embodiments, the integrated spacer layer 245' may be or include gold (Au) copper (Cu), a Cu alloy, gold-tin (AuSn), and / or epoxy resin, but the invention is not limited thereto.

[0171] Although the spacer 245 is illustrated as a uniform layer having a relatively planar upper surface 245b', the invention is not limited thereto. In some embodiments, the upper surface 245b' of the integrated spacer layer 245' may be non-planar. For example, in some embodiments, the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10 may have different heights, and the integrated spacer layer 245' may be formed having an upper surface 245b' having portions located at each of the different heights of the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10.

[0172] Figure 6D An embodiment of the RF transistor amplifier 200G is illustrated, wherein the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. (Reference) Figure 6D The surfaces 350a_s of the first circuit element 350a and / or 350b_s of the second circuit element 350b can be exposed. The exposure of the surfaces 350a_s and 350b_s of the first and / or second circuit elements 350a and 350b allows additional external connections to be applied to the first and / or second circuit elements 350a and 350b. For example, separate electrical connections, such as to a ground signal, can be connected to the first and / or second circuit elements 350a and 350b through their respective exposed surfaces 350a_s and 350b_s.

[0173] Figure 6D The RF transistor amplifier 200G can be constructed, for example, by building Figure 4AThe RF transistor amplifier 200C is then formed by performing a planarization operation on a portion of the encapsulation material 325 to expose the surfaces 350a_s, 350b_s of the first and / or second circuit elements 350a, 350b.

[0174] Figures 6A to 6D The RF transistor amplifiers 200E, 200F, 200F' and 200G shown can be used in a variety of package configurations. Figures 7A to 7F The illustration is related to the article. Figure 2B , Figure 2C , Figure 4B and Figure 4C The use of the package discussed is similar to that of other packages. For example, the interconnect structure 210 and the RF transistor amplifier die 10 can be placed in open-cavity semiconductor packages 7000a_1, 7000a_2 (…). Figure 7A and Figure 7B ) or OMP package 7000b_1, 7000b_2 ( Figure 7C and Figure 7D (in) (compared to previous information) Figure 2B and Figure 2C The discussion focuses on similar semiconductor packages 7000a_1 and 7000b_1. Figure 7A and Figure 7C For the sake of simplicity, the components mentioned will not be discussed further. (This is in contrast to previous discussions about...) Figure 4B and Figure 4C The discussion focuses on similar semiconductor packages 7000a_2 and 7000b_2. Figure 7B and Figure 7D For the sake of simplicity, the components in this document will not be discussed further.

[0175] exist Figure 7A and Figure 7CIn the illustrations, semiconductor packages 7000a_1 and 7000b_1 depict the use of interconnect structure 210 and first and second auxiliary spacers 246a, 246b for an RF transistor amplifier 200E. The RF transistor amplifier 200E may expose gate connection pad 282 and drain connection pad 284, which can be connected to leads 415A, 415B, respectively. In some embodiments, semiconductor packages 7000a_1 and 7000b_1 may house the RF transistor amplifier 200E, wherein the first auxiliary spacer 246a, the second auxiliary spacer 246b, spacer 245, gate connection pad 282, and drain connection pad 284 are substantially coplanar. Depending on the electrical and thermal requirements of the first and second circuit elements 350a, 350b, additional terminal / joint / spacer structures may be used with at least one of the first and second circuit elements 350a, 350b to provide an electrical, thermal and / or mechanical interface between one or more of at least one of the first and second circuit elements 350a, 350b and the carrier substrate 410 in a manner similar to that described for joints / spacers to the RF transistor amplifier die 10.

[0176] Figure 7A and Figure 7B The use of riser 412 is also illustrated. Riser 412 may be part of or an additional separate structure of carrier substrate 410. In some embodiments, riser 412 may include elements such as spacers (e.g., configured similarly to spacers 425 and / or first and second auxiliary spacers 246a, 246b), bonding / attachment layers (e.g., eutectic layers, epoxy resin layers), metal layers, and / or thermally conductive layers. Riser 412 may be formed of one or more layers. In some embodiments, riser 412 may be used to raise the level of RF transistor amplifier 200E and / or provide a planar surface for mounting RF transistor amplifier 200E.

[0177] exist Figure 7B and Figure 7D In the illustrations, semiconductor packages 7000a_2 and 7000b_2 depict the use of interconnect structure 210 of RF transistor amplifier 200F with first and second auxiliary spacers 246a, 246b. RF transistor amplifier 200F may expose gate lead pad 382 and drain lead pad 384, which can be connected to leads 415A, 415B, respectively. In some embodiments, semiconductor packages 7000a_2 and 7000b_2 may house RF transistor amplifier 200E, wherein the first auxiliary spacer 246a, the second auxiliary spacer 246b, and spacer 245 are located at different levels (e.g., at different heights) from the gate lead pad 382 and drain lead pad 384. Figure 7B and Figure 7DIn the diagram, the RF transistor amplifier 200F is shown in semiconductor packages 7000a_2 and 7000b_2, but it will be understood that... Figure 6C and Figure 6D The RF transistor amplifiers 200F' and 200G can also be packaged similarly with necessary modifications.

[0178] refer to Figures 7A to 7D The first and second auxiliary spacers 246a and 246b can be connected to and / or directly contact the carrier substrate 410. In this way, the first and second auxiliary spacers 246a and 246b can be configured to dissipate heat from the first and second circuit elements 350a and 350b and / or provide electrical signals (e.g., ground signals) to the first and second circuit elements 350a and 350b. For example, in some embodiments, the first and second auxiliary spacers 246a and 246b can be conductive and can be used to electrically connect the first and second circuit elements 350a and 350b to the carrier substrate 410. In some embodiments, the first and second auxiliary spacers 246a and 246b can be electrically insulating or conductive, but the first and second circuit elements 350a and 350b can be thermally connected to the carrier substrate 410 to dissipate heat energy (e.g., heat) from the first and second circuit elements 350a and 350b.

[0179] Figure 7E and Figure 7F The illustrations show example semiconductor packages 7000a_3 and 7000b_3 that incorporate an integrated spacer layer 245'. Figure 7E The diagram illustrates the 7000a_3 open-cell semiconductor package and... Figure 7F The diagram illustrates the OMP semiconductor package 7000b_3. Semiconductor packages 7000a_3 and 7000b_3 can utilize an integrated spacer layer 245'. For example... Figure 7E As shown, in addition to the integrated spacer layer 245', some embodiments of the invention may also incorporate first and second auxiliary spacers 246a, 246b. For example, the first and second auxiliary spacers 246a, 246b may be deployed between the integrated spacer layer 245' and one or more of the first and second circuit elements 350a, 350b. The first and second auxiliary spacers 246a, 246b may be used to extend between the integrated spacer layer 245' and one or more of the first and second circuit elements 350a, 350b to provide a planar connection surface. In some embodiments, the first and second auxiliary spacers 246a, 246b may be omitted. For example, the integrated spacer layer 245' may be configured to have a non-planar surface for coupling to the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 210. This embodiment in... Figure 7F As shown in the image.

[0180] Figures 8A to 8C This is a schematic cross-sectional view of additional RF transistor amplifier embodiments 200H, 200I, 200J, which are coupled to mechanisms linked to first and second circuit elements 350a, 350b according to some embodiments of the present invention. A portion of the RF transistor amplifiers 200H, 200I, 200J may be connected to... Figure 5A , Figure 6B , Figure 6C and Figure 6D The parts are basically similar, therefore, repeated descriptions will be omitted. For example, Figures 8A to 8C Embodiments may incorporate interconnect structure 210”, which exposes gate lead pad 382” and / or drain lead pad 384” on a second side 202 (e.g., the upper surface) of interconnect structure 210”. For example Figure 8A An embodiment of the RF transistor amplifier 200H may include with Figure 5A The embodiment is similar to the RF transistor amplifier 200D, but with the addition of a first auxiliary spacer 246a and a second auxiliary spacer 246b.

[0181] In some embodiments, a first auxiliary spacer 246a may be formed on and / or in contact with a first circuit element 350a, and a second auxiliary spacer 246b may be formed on and / or in contact with a second circuit element 350b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be formed of a conductive and / or thermally conductive material such as metal. In some embodiments, the surfaces of the first and / or second auxiliary spacers 246a, 246b may be exposed from the encapsulation material 325. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be or include gold (Au) copper (Cu), Cu alloys, gold-tin (AuSn) and / or epoxy resin, but the invention is not limited thereto. The first and / or second auxiliary spacers 246a, 246b may provide a mechanism for providing a ground signal to the first and / or second circuit elements 350a, 350b or for dissipating heat from the first and / or second circuit elements 350a, 350b, as discussed herein with respect to other embodiments.

[0182] In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be made of a material similar to that of spacer 245, but the invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be made of a material different from that of spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be electrically disconnected (e.g., isolated) from spacer 245.

[0183] Although the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 are illustrated as separate discrete elements, the invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be formed as an integrated (e.g., interconnected) layer. This embodiment in Figure 8B The diagram illustrates an RF transistor amplifier 200I comprising a spacer layer 245'. The integrated spacer layer 245' may extend to contact a first circuit element 350a, a second circuit element 350b, and an RF transistor amplifier die 10 (e.g., the source terminal 26 of the RF transistor amplifier die 10). In some embodiments, the surface of the integrated spacer layer 245' may be exposed from the encapsulating material 325. In some embodiments, the integrated spacer layer 245' may be formed of the same or similar material as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or spacer 245. Although illustrated as a uniform layer having a relatively planar upper surface 245b', the invention is not limited thereto. In some embodiments, the upper surface 245b' of the integrated spacer layer 245' may be non-planar. For example, in some embodiments, the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10 may have different heights, and the integrated spacer layer 245' may be formed to have an upper surface 245b' having portions located at each of the different heights of the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10.

[0184] Figure 8C An embodiment of the RF transistor amplifier 200J is illustrated, wherein the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. The RF transistor amplifier 200J can be combined with... Figure 5A The interconnect structure 210 is similar to the interconnect structure 210, therefore, its repeated description will be omitted. (See reference...) Figure 5A and Figure 8C The upper surface 350a_s of the first circuit element 350a and / or the upper surface 350b_s of the second circuit element 350b may be exposed from the encapsulation material 325. The exposure of the surfaces 350a_s and 350b_s of the first and / or second circuit elements 350a and 350b allows for the application of additional external connections to the first and / or second circuit elements 350a and 350b. For example, separate electrical connections, such as to a ground signal, can be connected to the first and / or second circuit elements 350a and 350b through their respective exposed surfaces 350a_s and 350b_s.

[0185] Figure 8CThe RF transistor amplifier 200J can be constructed, for example, by building Figure 5A The RF transistor amplifier 200D is formed by then performing a planarization operation on a portion of the encapsulation material 325 to expose the surfaces 350a_s, 350b_s of the first and / or second circuit elements 350a, 350b.

[0186] Figures 8A to 8C The RF transistor amplifiers 200H, 200I and 200J shown can be used in a variety of package configurations. Figures 9A to 9D The illustration is related to the article. Figure 5B and Figure 5C The use of the package discussed is similar to that of other packages. For example, the interconnect structure 210” and the RF transistor amplifier die 10 can be placed in an open-cavity semiconductor package 9000a ( Figure 9A ) or OMP package 9000b ( Figure 9B In some embodiments, the integrated spacer layer 245' can be integrated with the open-cell semiconductor package 9000c. Figure 9C ) or OMP package 9000d ( Figure 9D Used together. (This is related to previous information.) Figure 5B and Figure 5C The components discussed are similar to those in semiconductor packages 9000a, 9000b, 9000c, and 9000d. Figures 9A to 9D For the sake of simplicity, the components will not be discussed further. In some embodiments, semiconductor packages 9000a to 9000d may house an RF transistor amplifier 200H, wherein gate lead pad 382” and drain lead pad 384” are exposed on the upper surface of interconnect structure 210”. Figures 9A to 9D In the diagram, transistor amplifier 200H is shown in semiconductor packages 9000a and 9000b, but it will be understood that RF transistor amplifiers 200I and 200J can also be packaged similarly with the necessary modifications.

[0187] refer to Figure 9A and Figure 9BThe first and second auxiliary spacers 246a, 246b can be connected to and / or directly contact the carrier substrate 410. In this way, the first and second auxiliary spacers 246a, 246b can be configured to dissipate heat from the first and second circuit elements 350a, 350b and / or provide electrical signals (e.g., ground signals) to the first and second circuit elements 350a, 350b. Depending on the electrical and thermal requirements of the first and second circuit elements 350a, 350b, additional terminal / connection / spacer structures can be used with at least one of the first and second circuit elements 350a, 350b to provide an electrical, thermal, and / or mechanical interface between at least one or more of the first and second circuit elements 350a, 350b and the substrate 410 in a manner similar to that described for the connection / spacers to the RF transistor amplifier die 10.

[0188] refer to Figure 9C and Figure 9D The first and second auxiliary spacers 246a, 246b can be replaced by an integrated spacer layer 245' coupled to the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10. Although illustrated as having a planar upper surface, in some embodiments, the integrated spacer layer 245' may have a non-planar upper surface (such as...). Figure 7D (As illustrated in the figure). In some embodiments, the first and second auxiliary spacers 246a, 246b may be deployed between the first and second circuit elements 350a, 350b and the integrated spacer layer 245' (such as...). Figure 7C (As shown in the illustration).

[0189] Compared to conventional RF transistor amplifiers, the RF transistor amplifier according to embodiments of the present invention can have several advantages. The reduction (or complete elimination) of bonding wires can lower costs and simplify manufacturing, and can improve the RF performance of the device because the inductance in the impedance matching network can be precisely controlled, avoiding the problem of excessive inductance in the matching network. Furthermore, using the RF transistor amplifier according to embodiments of the present invention increases the possibility of wafer-level packaging, which can further simplify manufacturing and / or reduce production costs. In addition, the use of interconnect structures allows for more modular products, making it relatively easy to modify parts of the RF transistor amplifier.

[0190] Embodiments of this disclosure can be used in RF power products, for example, for 5G and base station and / or mobile phone applications and radar applications.

[0191] Embodiments of the inventive concept have been described above with reference to the accompanying drawings, in which embodiments of the invention are illustrated. However, the inventive concept can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0192] It will be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the invention. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0193] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the terms “comprising,” “including,” “containing,” and / or “comprising” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0194] It will be understood that when a component, such as a layer, region, or substrate, is referred to as "on another component" or "extending to another component," it can be directly on or directly extended to another component, or intermediate components may exist. Conversely, when a component is referred to as "directly on another component" or "directly extending to another component," no intermediate components exist. It will also be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to another component, or intermediate components may exist. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, no intermediate components exist.

[0195] Relative terms such as “below” or “above” or “up” or “down” or “horizontal” or “lateral” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figures. It will be understood that these terms are intended to cover different orientations of the device other than those depicted in the figures.

[0196] Typical embodiments of the invention have been disclosed in the accompanying drawings and description, and although specific terminology has been used, it is for general and descriptive purposes only and not for limiting purposes. The scope of the invention is set forth in the appended claims.

Claims

1. A radio frequency (RF) transistor amplifier, comprising: RF transistor amplifier die; An interconnect structure having opposing first and second sides, wherein the first side of the interconnect structure is adjacent to the first surface of the RF transistor amplifier die, such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement; One or more circuit elements on the first and / or second side of the interconnection structure; Encapsulation material on the RF transistor amplifier die and the interconnect structure; as well as Thermally conductive auxiliary spacers on one or more circuit elements.

2. The RF transistor amplifier according to claim 1, wherein, The RF transistor amplifier die also includes a gate terminal and a drain terminal on the first surface of the RF transistor amplifier die, and a source terminal on the second surface of the RF transistor amplifier die.

3. The RF transistor amplifier according to claim 2, further comprising a spacer located on the source terminal of the RF transistor amplifier die and electrically connected to the source terminal of the RF transistor amplifier die.

4. The RF transistor amplifier according to claim 3, wherein, The spacer and the auxiliary spacer are structurally interconnected or integrally formed.

5. The RF transistor amplifier according to claim 3, wherein, The encapsulating material is also on the spacer.

6. The RF transistor amplifier according to any one of claims 1-5, further comprising a gate lead pad and a drain lead pad on the interconnect structure.

7. The RF transistor amplifier according to claim 6 further includes a first through-hole coupled to the gate lead pad and a second through-hole coupled to the drain lead pad.

8. The RF transistor amplifier according to any one of claims 1-5, wherein, The interconnect structure includes a printed circuit board (PCB).

9. The RF transistor amplifier according to any one of claims 1-5, wherein, The one or more circuit elements include a circuit system comprising at least a portion of a harmonic termination circuit system and / or an impedance matching circuit system.

10. The RF transistor amplifier according to any one of claims 1-5, wherein, The RF transistor amplifier die includes a semiconductor layer structure, which includes group III nitrides.

11. The RF transistor amplifier according to claim 10, wherein, The semiconductor layer structure also includes a silicon and / or silicon carbide substrate.

12. The RF transistor amplifier according to any one of claims 1-5, wherein, The RF transistor amplifier die includes a semiconductor layer structure, which includes a high electron mobility transistor (HEMT) or a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

13. The RF transistor amplifier according to any one of claims 1-5, wherein, The RF transistor amplifier operates at a frequency between 500MHz and 75GHz.

14. The RF transistor amplifier according to claim 1, wherein, The encapsulating material exposes the surface of the auxiliary spacer.

15. A radio frequency (RF) transistor amplifier, comprising: RF transistor amplifier die with semiconductor layer structure; An interconnect structure having opposing first and second sides, wherein the first side of the interconnect structure is adjacent to the first surface of the RF transistor amplifier die, such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement; One or more circuit elements on the first and / or second side of the interconnection structure; as well as The encapsulation material on the RF transistor amplifier die and the interconnect structure, The encapsulation material has a stepped surface to expose the surface of the one or more circuit elements.

16. A radio frequency (RF) transistor amplifier package, comprising: An RF transistor amplifier die has a first main surface and a second main surface on the side of the RF transistor amplifier die opposite to the first main surface, the RF transistor amplifier die including a gate terminal and a drain terminal on the first main surface and a source terminal on the second main surface; The interconnection structure on the first main surface of the RF transistor amplifier die includes a gate lead pad electrically coupled to the gate terminal and a drain lead pad electrically coupled to the drain terminal. An input lead extends from the outside of the RF transistor amplifier package and is electrically coupled to the gate lead pad; and The output lead extends from the outside of the RF transistor amplifier package and is electrically coupled to the drain lead pad. The input lead is electrically coupled to the gate lead pad through a through-hole in the encapsulation material of the interconnect structure. The interconnection structure further includes: A first side adjacent to the first main surface of the RF transistor amplifier die and a second side opposite to the first side; and A first circuit element is coupled between the gate terminal and the input lead.

17. The RF transistor amplifier package of claim 16, wherein, The interconnect structure also includes a second circuit element coupled between the drain terminal and the output lead.

18. The RF transistor amplifier package of claim 17, wherein, One or more circuit elements are mounted on the first and / or second side of the interconnect structure.

19. The RF transistor amplifier package according to claim 17 or claim 18, wherein, The input lead and / or the output lead are coupled to a first side and / or a second side of the interconnect structure.

20. The RF transistor amplifier package according to any one of claims 17-18, further comprising auxiliary spacers located on the one or more circuit elements.

21. The RF transistor amplifier package according to any one of claims 16-18, further comprising a spacer located on and electrically connected to the source terminal of the RF transistor amplifier die.

22. The RF transistor amplifier package of claim 21, further comprising a carrier substrate located on a second main surface of the RF transistor amplifier die, the spacer being located between the carrier substrate and the second main surface of the RF transistor amplifier die.

23. The RF transistor amplifier package according to claim 22, wherein, The spacer is electrically connected to the carrier substrate.

24. The RF transistor amplifier package of claim 22, further comprising sidewalls and a cover, in, The carrier substrate, the sidewalls, and the cover define the internal cavity, and The RF transistor amplifier die is located within the internal cavity.

25. The RF transistor amplifier package of claim 22, further comprising an overmolding material on the interconnect structure and the RF transistor amplifier die.

26. The RF transistor amplifier package according to any one of claims 16-18, wherein, The interconnection structure includes an input matching circuit and / or an output matching circuit.

27. The RF transistor amplifier package according to any one of claims 16-18, wherein, The RF transistor amplifier die is a group III nitride-based RF transistor amplifier die.

28. The RF transistor amplifier package according to any one of claims 16-18, wherein, The RF transistor amplifier die includes a high electron mobility transistor (HEMT) or a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

29. The RF transistor amplifier package according to any one of claims 16-18, wherein, The RF transistor amplifier package operates in the R band, S band, X band, Ku band, K band, Ka band, and / or V band.

30. A transistor amplifier package, comprising: A group III nitride-based amplifier die includes a first main surface and a second main surface on a side of the amplifier die opposite to the first main surface. The amplifier die includes a gate terminal and a drain terminal on the first main surface and a source terminal on the second main surface. as well as An interconnect structure is provided on a first main surface of the amplifier die and electrically coupled to the gate terminal and the drain terminal, wherein the interconnect structure includes one or more circuit elements coupled between the gate terminal and a first lead of the transistor amplifier package and / or between the drain terminal and a second lead of the transistor amplifier package. Encapsulation material is applied to the amplifier die and the interconnect structure; The interconnect structure has a first side and a second side on the side of the interconnect structure opposite to the first side, wherein the first side of the interconnect structure is adjacent to the first main surface of the amplifier die. Wherein, the first lead and the second lead are coupled to a first side of the interconnect structure and the encapsulation material does not cover the ends of the interconnect structure to expose the first lead; The one or more circuit elements include a first circuit element mounted on a first side of the interconnect structure.

31. The transistor amplifier package of claim 30, wherein, The one or more circuit elements also include a second circuit element mounted on a second side of the interconnect structure.

32. The transistor amplifier package according to any one of claims 30-31, wherein, The interconnect structure includes a first interconnect pad and a second interconnect pad on a first side of the interconnect structure. The first interconnect pad is electrically coupled to the gate terminal of the amplifier die, and The second interconnect pad is electrically coupled to the drain terminal of the amplifier die.

33. The transistor amplifier package according to any one of claims 30-31, wherein, One or more circuit elements are mounted on the first and / or second side of the interconnect structure.

34. The transistor amplifier package according to any one of claims 30-31, further comprising a spacer located on and electrically connected to the source terminal of the amplifier die.

35. The transistor amplifier package of claim 34, wherein, The encapsulating material is also on the spacer.

36. The transistor amplifier package of claim 34, further comprising an auxiliary spacer on at least one of the one or more circuit elements.

37. The transistor amplifier package of claim 36, wherein, The encapsulating material exposes the surface of the auxiliary spacer.

38. The transistor amplifier package of claim 37, wherein, The encapsulation material exposes the surface of the one or more circuit elements.

39. The transistor amplifier package of claim 35, wherein, The interconnect structure includes a gate lead pad and a drain lead pad.

40. The transistor amplifier package of claim 39, further comprising: The gate connection pad is coupled to the gate lead pad through a first through hole in the encapsulation material; as well as The drain connection pad is coupled to the drain lead pad through a second through-hole in the encapsulation material. The first lead is coupled to the gate connection pad and the second lead is coupled to the drain connection pad.

41. The transistor amplifier package of claim 40, wherein, The bottom surfaces of the gate connection pad, the drain connection pad, and the spacer are coplanar.

42. The transistor amplifier package according to any one of claims 30-31, wherein, The one or more circuit elements include a circuit system comprising at least a portion of a harmonic termination circuit system and / or an impedance matching circuit system.

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