Optical chip structure, preparation method thereof and electronic equipment

Abstract

The invention relates to an optical chip structure, a preparation method thereof and electronic equipment. The optical chip structure comprises a substrate; the dielectric layer is located on the substrate; the metal layer is located on the dielectric layer, the metal layer comprises a target sub-metal layer, the target sub-metal layer is located at a target position at the top of the metal layer, and the target position is a position corresponding to a target through hole required by the optical chip structure; the dielectric layer is located on the metal layer, the dielectric layer comprises a target through hole, and the target through hole is located at the target position and exposes the target sub-metal layer; and the barrier layer is located on the dielectric layer and in the target through hole. The invention can at least avoid abnormal connection of the through hole caused by deposition of the metal layer into the through hole when the through hole connected with the upper and lower layers of metal is manufactured.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to an optical chip structure and a preparation method thereof, and electronic equipment. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, for optical chips with special processes, the metal layer structure is not the traditional sandwich structure (Ti / TiN+AlCu+Ti / TiN). The metal layer structure is only composed of the lower layer Ti / TiN+AlCu, without the upper layer Ti / TiN as a metal barrier layer.

[0003] In optical chips with special metal layer structures without an upper Ti / TiN barrier layer, when making through holes connecting the upper and lower metal layers, the exposed AlCu is easily heated and diffused into the through holes when Ti / TiN is deposited in the through holes (high-temperature process of about 400°C), resulting in abnormal through-hole connections (resistance can reach more than 100Ω). Summary of the invention

[0004] Based on this, it is necessary to provide an optical chip structure and a preparation method and electronic device to address the above technical problems, which can at least avoid abnormal through-hole connection caused by the deposition of metal layers into the through-holes when making through-holes connecting the upper and lower metal layers.

[0005] In order to achieve the above-mentioned purpose and other purposes, in a first aspect, the present disclosure provides an optical chip structure, including: a substrate; a dielectric layer located on the substrate; a metal layer located on the dielectric layer, the metal layer including a target sub-metal layer, the target sub-metal layer being located at a target position on the top of the metal layer, the target position being a position corresponding to a target through hole required for the optical chip structure; a dielectric layer located on the metal layer, the dielectric layer including a target through hole, the target through hole being located at the target position and exposing the target sub-metal layer; a barrier layer located on the dielectric layer and inside the target through hole.

[0006] In the optical chip structure in the above-mentioned embodiment, a target sub-metal layer is formed at the target position on the top of the metal layer as a metal barrier layer to form a local sandwich structure at the target position. When making a through hole connecting the upper and lower metal layers, the metal at the target through hole position will not be deposited into the target through hole due to the blocking of the target sub-metal layer. Therefore, the embodiment of the present disclosure can at least avoid the situation where the metal layer is deposited into the through hole when making the through hole connecting the upper and lower metal layers, resulting in abnormal through hole connection.

[0007] In one embodiment, the optical chip structure further includes: a metal wiring layer located in the target through hole on the barrier layer, and the metal wiring layer fills the target through hole to form a complete optical chip structure.

[0008] In one embodiment, the metal layer further includes a first metal layer and a second metal layer, the second metal layer is located on the first metal layer, and the target sub-metal layer is located on the second metal layer. The metal layer forms an upper and lower metal layer in the optical chip through the first metal layer and the second metal layer, and forms a sandwich structure with the target sub-metal layer at the target position, which ensures the special structure of the optical chip and avoids the diffusion of the upper and lower metal layers through the local sandwich structure.

[0009] In a second aspect, the embodiments of the present disclosure further provide an electronic device, including: the optical chip structure in any of the above embodiments, which can at least avoid abnormal through-hole connection caused by the deposition of metal layers into the through-holes when making through-holes connecting the upper and lower metal layers.

[0010] In a third aspect, an embodiment of the present disclosure also provides a method for preparing an optical chip structure, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a metal layer on the dielectric layer, the metal layer including a target sub-metal layer, the target sub-metal layer being located at a target position on the top of the metal layer, the target position being a position corresponding to a target through hole required for the optical chip structure; forming a dielectric layer on the metal layer, the dielectric layer including a target through hole, the target through hole being located at the target position and exposing the target sub-metal layer; forming a blocking layer on the dielectric layer, the blocking layer being located in the target through hole.

[0011] In the preparation method of the optical chip structure in the above embodiment, a target sub-metal layer is formed at the target position on the top of the metal layer as a metal barrier layer, and a local sandwich structure is formed at the target position. When making a through hole connecting the upper and lower metal layers, the metal at the target through hole position will not be deposited into the target through hole due to the blocking of the target sub-metal layer. Therefore, the embodiment of the present disclosure can at least avoid the situation where the metal layer is deposited into the through hole when making the through hole connecting the upper and lower metal layers, resulting in abnormal through hole connection.

[0012] In one embodiment, a metal layer is formed on a dielectric layer, comprising: depositing a multilayer structure on the dielectric layer, the multilayer structure comprising a first metal layer, a second metal layer and a sub-metal layer, the second metal layer is located on the first metal layer, and the sub-metal layer is located on the second metal layer; etching the sub-metal layer to form a target sub-metal layer on the second metal layer.

[0013] In the method for preparing the optical chip structure of the above embodiment, upper and lower metal layers including a first metal layer and a second metal layer are formed in the optical chip through deposition and etching technology, and the sub-metal layer is etched to form a sandwich structure at the target position, thereby ensuring the special structure of the optical chip and avoiding the diffusion of the upper and lower metal layers through the local sandwich structure.

[0014] In one of the embodiments, the sub-metal layer is etched, including: using a negative photoresist process to form a patterned photoresist layer on the sub-metal layer; using the patterned photoresist layer as a mask, etching the sub-metal layer to remove the sub-metal layer at positions other than the target position, and exposing the second metal layer at positions other than the target position, and the remaining sub-metal layer is used to form a target sub-metal layer.

[0015] In the method for preparing the optical chip structure of the above embodiment, the sub-metal layer is partially etched by a negative resist process to remove unnecessary sub-metal layers at other locations.

[0016] In one embodiment, forming a dielectric layer on a metal layer includes: forming a dielectric layer on the metal layer based on a deposition process; etching the dielectric layer to form a target through hole at a target position, wherein the target through hole exposes a target sub-metal layer.

[0017] In the method for preparing the optical chip structure of the above embodiment, a target through hole is formed at a target position by etching the dielectric layer, and the target through hole exposes the target sub-metal layer, so that the exposed portion in the through hole is a sandwich structure. When the metal wiring layer is subsequently deposited, the special structure of the optical chip is guaranteed, and the diffusion of the upper and lower metal layers is avoided through the local sandwich structure.

[0018] In one embodiment, forming a barrier layer on the dielectric layer includes: forming the barrier layer on the dielectric layer based on a chemical vapor deposition process; and removing the barrier layer on the dielectric layer except in the target through hole based on a planarization process.

[0019] In one embodiment, the method further includes: forming a metal wiring layer in the target through hole on the barrier layer, wherein the metal wiring layer fills the target through hole.

[0020] In the method for preparing the optical chip structure of the above embodiment, the through hole is filled with a metal wiring layer to form a complete optical chip structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a partial schematic diagram of an optical chip structure provided in an embodiment;

[0023] Figure 2 A schematic diagram of an optical chip structure provided in an embodiment Figure 1 ;

[0024] Figure 3 A schematic diagram of an optical chip structure provided in an embodiment Figure 2 ;

[0025] Figure 4 A schematic diagram of an optical chip structure provided in an embodiment Figure 3 ;

[0026] Figure 5 A schematic diagram of an optical chip structure provided in an embodiment Figure 4 ;

[0027] Figure 6 A schematic diagram of an optical chip structure provided in an embodiment Figure 5 ;

[0028] Figure 7 A schematic diagram of an optical chip structure provided in an embodiment Figure 6 ;

[0029] Figure 8 A schematic diagram of an optical chip structure provided in an embodiment Figure 7 ;

[0030] Fig. 9 is a partial schematic diagram of another optical chip structure provided in an embodiment;

[0031] Fig.10 The present invention is a flow chart of a method for preparing an optical chip structure provided in one embodiment.

[0032] Description of reference numerals:

[0033] 101, diffusion layer; 201, substrate; 202, dielectric layer; 203, metal layer; 2031, first metal layer; 2032, second metal layer; 2033, sub-metal layer; 301, target sub-metal layer; 401, dielectric layer; 501, target through hole; 601, barrier layer; 801, metal wiring layer. DETAILED DESCRIPTION

[0034] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0036] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0038] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0040] See also Figure 1 , Figure 1 This is a partial schematic diagram of the optical chip structure of the prior art provided by this application. Figure 1 As shown in FIG. 1 , due to the formation of the diffusion layer 101 during the deposition process, the metal wiring layer 801 cannot be directly connected to the metal of the upper and lower layers, which leads to abnormal resistance of the through-hole connection.

[0041] As an example, see Figure 1 , Figure 1 Since there is no barrier of the top metal layer of the sandwich structure, during the deposition of the through hole, the AlCu of the middle metal layer can easily diffuse into the through hole to form an aluminum diffusion layer 101. As a result, the metal wiring layer 801 cannot form a connection with the middle metal layer, and the resistance of the through hole connection becomes abnormal, rising from the normal resistance (4Ω-6Ω) to more than 100Ω.

[0042] See also Figure 2-Figure 10 It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0043] Please continue reading Figure 7As an example, one aspect of the present application provides an optical chip structure, including: a substrate 201; a dielectric layer 202, located on the substrate 201; a metal layer 203, located on the dielectric layer 202, the metal layer 203 including a target sub-metal layer 301, the target sub-metal layer 301 is located at a target position on the top of the metal layer, the target position is a position corresponding to a target through hole 501 required for the optical chip structure; a dielectric layer 401, located on the metal layer, the dielectric layer 401 including a target through hole 501, the target through hole 501 is located at the target position and exposes the target sub-metal layer 301; a blocking layer 601, located on the dielectric layer 401, within the target through hole 501.

[0044] In the optical chip structure in the above embodiment, a target sub-metal layer 301 is formed at the target position on the top of the metal layer as a metal barrier layer 601, and a local sandwich structure is formed at the target position. When making a through hole connecting the upper and lower metal layers, the metal layer 203 at the position of the target through hole 501 will not be deposited into the target through hole 501 due to the blocking of the target sub-metal layer 301. Therefore, the embodiment of the present disclosure can at least avoid the situation where the metal layer 203 is deposited into the through hole when making the through hole connecting the upper and lower metal layers, resulting in abnormal through hole connection.

[0045] In the optical chip structure in the above embodiment, specifically, the optical chip structure further includes: a metal wiring layer 801 located in the target through hole 501 on the barrier layer 601, and the metal wiring layer 801 fills the target through hole 501 to form a complete optical chip structure.

[0046] In one embodiment, the metal layer 203 further includes a first metal layer 2031 and a second metal layer 2032, the second metal layer 2032 is located on the first metal layer 2031, and the target sub-metal layer 301 is located on the second metal layer 2032. The metal layer forms an upper and lower metal layer in the optical chip through the first metal layer 2031 and the second metal layer 2032, and forms a sandwich structure at the target sub-metal layer 301 at the target position, which ensures the special structure of the optical chip and avoids the diffusion of the upper and lower metal layers through the local sandwich structure.

[0047] Please refer to Fig.10 As an example, the present disclosure provides a method for preparing an optical chip structure, comprising the following steps:

[0048] Step S1000: providing a substrate 201 .

[0049] Wherein, the substrate 201 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 201 can be a single-layer structure or a multi-layer structure. For example, the substrate 201 can be a silicon substrate 201, a silicon germanium substrate 201, a silicon germanium carbon substrate 201, a silicon carbide substrate 201, a gallium arsenide substrate 201, an indium arsenide substrate 201, an indium phosphide substrate 201 or other III / V semiconductor substrates 201 or II / VI semiconductor substrates 201. Alternatively, for example, the substrate 201 can be a layered substrate 201 including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate 201 should not limit the scope of protection of the present disclosure.

[0050] Step S2000 : forming a dielectric layer 202 on the substrate 201 .

[0051] The dielectric layer 202, namely ILD (Interlayer Dielectric), can prevent electrical signal interference between different metal interconnection layers, provide flat mechanical support for the upper metal interconnection, and reduce parasitic capacitance between metal interconnection lines.

[0052] As an example, the material of the dielectric layer 202 is usually some dielectric material with a low dielectric constant (low-k), and common materials include: silicon dioxide ( ), silicon oxynitride (SiON), fluorocarbons (such as silicon fluoride), etc.

[0053] Step S3000 : forming a metal layer on the dielectric layer 202 .

[0054] The metal layer includes a target sub-metal layer 301 , and the target sub-metal layer 301 is located at a target position on the top of the metal layer, and the target position is a position corresponding to a target through hole 501 required by the optical chip structure.

[0055] Step S4000: forming a dielectric layer 401 on the metal layer.

[0056] The dielectric layer 401 includes a target through hole 501 . The target through hole 501 is located at a target position and exposes the target sub-metal layer 301 .

[0057] Here, the dielectric layer 401 may be an oxide layer, or may be silicon dioxide ( ), silicon oxynitride (SiON), etc. Among them, the dielectric layer 401 can be formed by chemical vapor deposition, physical vapor deposition or thermal oxidation. As an example, the present application can adopt a chemical vapor deposition (CVD) method to convert a gaseous precursor into a solid oxide material and deposit it on the surface of the semiconductor structure through a chemical reaction.

[0058] Step S5000 : forming a blocking layer 601 on the dielectric layer 401 .

[0059] Wherein, the barrier layer 601 is located in the target through hole 501.

[0060] In the optical chip structure in the above embodiment, a target sub-metal layer 301 is formed at the target position on the top of the metal layer as a metal barrier layer 601, and a local sandwich structure is formed at the target position. When making a through hole connecting the upper and lower metal layers, the metal at the position of the target through hole 501 will not be deposited into the target through hole 501 due to the blocking of the target sub-metal layer 301. Therefore, the embodiment of the present disclosure can at least avoid the situation where the metal layer is deposited into the through hole when making the through hole connecting the upper and lower metal layers, resulting in abnormal through hole connection.

[0061] As an example, please refer to Figure 2 In step S3000, first, it is necessary to form Figure 2 The infrastructure in .

[0062] Specifically, the dielectric layer 202 and the metal layer 203 may be deposited on the substrate 201 through a deposition process.

[0063] The metal layer 203 includes a first metal layer 2031 , a second metal layer 2032 and a sub-metal layer 2033 , wherein the second metal layer 2032 is located on the first metal layer 2031 , and the target sub-metal layer 301 is located on the second metal layer 2032 .

[0064] The deposition process may include but is not limited to at least one of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), a plasma enhanced deposition process (PECVD), and a spin-on dielectric layer 401 (SOD). Specifically, the present application uses a chemical vapor deposition process to deposit the multilayer structure in the optical chip structure to achieve a better deposition effect.

[0065] As an example, the material of the first metal layer 2031 includes Ti and TiN, the material of the second metal layer 2032 may be AlCu, and the sub-metal layer 2033 includes Ti and TiN.

[0066] Specifically, in step S3000, a metal layer is formed on the dielectric layer 202, including: depositing a multilayer structure on the dielectric layer 202, the multilayer structure including a first metal layer 2031, a second metal layer 2032 and a sub-metal layer 2033, the second metal layer 2032 is located on the first metal layer 2031, and the sub-metal layer 2033 is located on the second metal layer 2032; etching the sub-metal layer 2033 to form a target sub-metal layer 301 on the second metal layer 2032.

[0067] In the method for preparing the optical chip structure of the above embodiment, upper and lower metal layers including a first metal layer 2031 and a second metal layer 2032 are formed in the optical chip through deposition and etching technology, and the sub-metal layer 2033 is etched to form a sandwich structure at the target position, thereby ensuring the special structure of the optical chip and avoiding the diffusion of the upper and lower metal layers through the local sandwich structure.

[0068] As an example, see Figure 3 , Figure 3 The structure shown is the optical chip structure obtained after step S3000, wherein the sub-metal layer 2033 can be partially etched by using a through-hole mask as a negative resist process, that is, a target sub-metal layer 301 is formed at a target position.

[0069] Among them, the negative photoresist process is a special type of photoresist used in the photolithography process, namely negative photoresist. Unlike positive photoresist, after exposure, the illuminated area of ​​negative photoresist will become stronger and retained during the development process, while the unexposed area will be dissolved and removed.

[0070] As an example, the steps of the negative photoresist process include: Spin Coating, coating negative photoresist on the surface of the wafer or substrate. Spin coating is used to ensure that the photoresist is evenly distributed on the surface of the wafer to form a thin film; Soft Bake, after coating, the wafer is soft-baked, usually at 90°C to 100°C for a few minutes to remove the solvent in the photoresist and enhance the adhesion and uniformity of the film; Exposure, using a mask to expose the wafer coated with negative photoresist to ultraviolet or deep ultraviolet light. Light passes through the mask and irradiates the graphic areas on the wafer that need to be retained. The photoresist undergoes a photochemical reaction in these areas, and the structure becomes more stable and more difficult to dissolve; Post Exposure Bake (PEB), the wafer is baked after exposure to make the photoresist's light reaction more thorough and further enhance the stability of the graphics; Developing, using a developer (usually an alkaline solution) to remove the unexposed areas. Because these unexposed areas have not undergone photochemical reactions, they will be dissolved by the developer, while the exposed areas will be retained to form patterns; hard baking, high-temperature baking of the wafer after development to improve the thermal stability of the photoresist and enhance its etching resistance; etching, the pattern generated by the negative photoresist process is used for subsequent etching processes, usually dry or wet etching, to etch specific areas of the substrate (such as silicon, oxide or metal); photoresist stripping, after the etching process is completed, the residual photoresist is removed by chemical or plasma methods. The negative photoresist process defines the pattern that needs to be retained through exposure and development, and has advantages such as excellent etching resistance and high resolution.

[0071] In step S4000 , a dielectric layer 401 is formed on the metal layer, including: forming the dielectric layer 401 on the metal layer based on a deposition process; etching the dielectric layer 401 to form a target through hole 501 at a target position, wherein the target through hole 501 exposes the target sub-metal layer 301 .

[0072] In the method for preparing the optical chip structure of the above embodiment, a target through hole 501 is formed at a target position by etching the dielectric layer 401, and the target through hole 501 exposes the target sub-metal layer 301, so that the exposed portion in the through hole is a sandwich structure. When the metal wiring layer 801 is subsequently deposited, the special structure of the optical chip is guaranteed, and the diffusion of the upper and lower metal layers is avoided through the local sandwich structure.

[0073] As an example, see Figure 4-Figure 5 Based on the deposition process, the optical chip structure after forming the dielectric layer 401 on the metal layer is Figure 4 The optical chip structure shown in FIG. 1 is obtained by etching the dielectric layer 401 to form a target through hole 501 at a target position. Figure 5 The optical chip structure in .

[0074] Among them, please refer to Figure 4 , Figure 4 The middle dielectric layer 401 is formed on the metal layer, and completely covers the sub-metal layer 2033 and the second metal layer 2032 .

[0075] Among them, please refer to Figure 5 , the target through hole 501 in the dielectric layer 401 is located at the target position and exposes the target sub-metal layer 301 .

[0076] As an example, the dielectric layer 401 may be an oxide layer, or may be silicon dioxide ( ), silicon oxynitride (SiON), etc. Among them, the dielectric layer 401 can be formed by chemical vapor deposition, physical vapor deposition or thermal oxidation. As an example, the present application can adopt a chemical vapor deposition (CVD) method to convert a gaseous precursor into a solid oxide material and deposit it on the surface of the semiconductor structure through a chemical reaction.

[0077] In step S5000 , a barrier layer 601 is formed on the dielectric layer 401 , including: forming the barrier layer 601 on the dielectric layer 401 based on a chemical vapor deposition process; and removing the barrier layer 601 on the dielectric layer 401 except in the target through hole 501 based on a planarization process.

[0078] Among them, the planarization process is used to eliminate the high non-uniformity of the surface during the deposition and patterning of multi-layer thin films, thereby obtaining a flat surface, providing an ideal foundation for subsequent photolithography, etching, and interlayer interconnection process steps. The planarization process methods include: Chemical Mechanical Polishing (CMP), Spin-on Process, Etch-back Process, Reflow Process, etc.

[0079] Here, the present application may adopt a chemical mechanical polishing process (CMP), which combines the principles of chemical etching and mechanical polishing to remove excess surface material layer by layer until the surface becomes flat, using chemical reagents to etch away the surface layer of the material to be polished, reducing the hardness of the material to make it easier to remove, and using a polishing pad and polishing liquid to physically polish the surface to remove the protruding parts through friction. CMP can provide very high flatness and is widely used in the flattening of metal interconnect layers (such as copper), dielectric layers 202 (such as silicon dioxide), etc.

[0080] As an example, see Figure 6-Figure 7 , Figure 6 FIG. 4 shows the optical chip structure before the planarization process, wherein the barrier layer 601 is formed in the dielectric layer 401 and the target through hole 501. Figure 7 The optical chip structure after the planarization process is shown. The planarization process removes the barrier layer 601 on the dielectric layer 401 and only retains the barrier layer 601 in the target through hole 501 .

[0081] The material of the barrier layer 601 may be Ti and TiN.

[0082] After step S5000 , the method further includes: forming a metal wiring layer 801 in the target through hole 501 on the barrier layer 601 , wherein the metal wiring layer 801 fills the target through hole 501 .

[0083] In the method for preparing the optical chip structure of the above embodiment, the through hole is filled with the metal wiring layer 801 to form a complete optical chip structure.

[0084] As an example, see Figure 8 , the metal wiring layer 801 fills the target through hole 501, forming a normal metal wiring in the optical chip structure.

[0085] For further information, see Fig. 9 ,like Fig. 9 As shown in , the metal wiring layer 801 passes through the target through hole 501 to form a connection with the metal layer, avoiding the formation of the aluminum diffusion layer 101 resulting in the metal wiring layer 801 being unable to form a connection with the intermediate metal layer, thereby ensuring the normal resistance value of the optical chip structure.

[0086] The material of the metal wiring layer 801 may be metal tungsten.

[0087] In some embodiments, the present disclosure provides an electronic device, including an optical chip structure of any one of the embodiments of the present disclosure. The electronic device is, for example but not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

[0088] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. An optical chip structure, characterized in that: The optical chip structure comprises: substrate; a dielectric layer, located on the substrate; A metal layer, located on the dielectric layer, the metal layer comprising a target sub-metal layer, the target sub-metal layer being located at a target position on the top of the metal layer, the target position being a position corresponding to a target through hole required by the optical chip structure; a dielectric layer, located on the metal layer, the dielectric layer comprising a target through hole, the target through hole being located at the target position and exposing the target sub-metal layer; A barrier layer is located on the dielectric layer and in the target through hole.

2. The optical chip structure according to claim 1, characterized in that: The optical chip structure further includes: The metal wiring layer is located in the target through hole on the barrier layer, and the metal wiring layer fills the target through hole.

3. The optical chip structure according to claim 1, characterized in that: The metal layer further includes a first metal layer and a second metal layer, wherein the second metal layer is located on the first metal layer, and the target sub-metal layer is located on the second metal layer.

4. An electronic device, characterized in that: include: The optical chip structure according to any one of claims 1 to 3.

5. A method for preparing an optical chip structure, characterized in that: The method comprises: providing a substrate; forming a dielectric layer on the substrate; forming a metal layer on the dielectric layer, the metal layer comprising a target sub-metal layer, the target sub-metal layer being located at a target position on the top of the metal layer, the target position being a position corresponding to a target through hole required by the optical chip structure; forming a dielectric layer on the metal layer, wherein the dielectric layer comprises a target through hole, the target through hole is located at the target position and exposes the target sub-metal layer; A barrier layer is formed on the dielectric layer, wherein the barrier layer is located in the target through hole.

6. The method for preparing an optical chip structure according to claim 5, characterized in that: Forming a metal layer on the dielectric layer, comprising: Depositing a multilayer structure on the dielectric layer, the multilayer structure comprising a first metal layer, a second metal layer and a sub-metal layer, the second metal layer being located on the first metal layer, and the sub-metal layer being located on the second metal layer; The sub-metal layer is etched to form a target sub-metal layer on the second metal layer.

7. The method for preparing an optical chip structure according to claim 6, characterized in that: Etching the sub-metal layer comprises: Using a negative resist process, forming a patterned photoresist layer on the sub-metal layer; The sub-metal layer is etched using the patterned photoresist layer as a mask to remove the sub-metal layer at positions other than the target position, and the second metal layer is exposed at positions other than the target position, and the remaining sub-metal layer is used to form the target sub-metal layer.

8. The method for preparing an optical chip structure according to claim 5, characterized in that: Forming a dielectric layer on the metal layer, comprising: Based on a deposition process, forming a dielectric layer on the metal layer; The dielectric layer is etched to form a target through hole at the target position, wherein the target through hole exposes the target sub-metal layer.

9. The method for preparing an optical chip structure according to claim 5, characterized in that: Forming a barrier layer on the dielectric layer, comprising: Based on a chemical vapor deposition process, forming a barrier layer on the dielectric layer; Based on the planarization process, the barrier layer on the dielectric layer except in the target through hole is removed.

10. The method for preparing an optical chip structure according to claim 5, characterized in that: The method further includes: forming a metal wiring layer in the target through hole on the barrier layer, wherein the metal wiring layer fills the target through hole.

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