Integrated capacitor

Abstract

An integrated capacitor is described. In an example, an integrated capacitor structure includes alternating first and second metal lines in dielectric layers of metallization layers in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. And the first metal plate is positioned above the first metal wires and the second metal wires which are alternated or positioned below the first metal wires and the second metal wires which are alternated. The metal plate is coupled to the first metal line or the second metal line through the via hole.

Description

Technical Field

[0001] Embodiments of the present disclosure pertain to the field of advanced integrated circuit structure fabrication, and in particular, integrated capacitors. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased on the limited footprint of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, which helps to manufacture products with increased capacity. However, the pursuit of greater and greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] Variability in conventional and currently known manufacturing processes may limit the possibility of further scaling to smaller and smaller nodes. Therefore, manufacturing the functional components required for future technology nodes may require the introduction of new methods in current manufacturing processes or the integration of new technologies or replacement of current manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An angled cross-sectional view of an integrated capacitor structure is shown.

[0005] Figure 2 An angled cross-sectional view of an integrated capacitor structure according to an embodiment of the present disclosure is shown.

[0006] Figure 3 is a diagram showing an exemplary simulation according to an embodiment of the present disclosure Figure 2 A diagram showing the benefits of capacitor construction.

[0007] Figure 4 An angled cross-sectional view of an integrated capacitor structure according to an embodiment of the present disclosure is shown.

[0008] Figure 5 is a graph including simulated (EM simulation) capacitance, resistance, and Q factor versus frequency for different capacitors according to an embodiment of the present disclosure.

[0009] Figure 6 A cross-sectional view of an on-die integrated capacitor in a power delivery system according to an embodiment of the present disclosure and a corresponding circuit schematic are shown.

[0010] Figure 7A cross-sectional view of an integrated circuit structure having four metallization layers with metal line compositions and pitches over two metallization layers with different metal line compositions and smaller pitches is shown according to an embodiment of the present disclosure.

[0011] Figure 8 A computing device according to one embodiment of the present disclosure is shown.

[0012] Fig. 9 An interposer including one or more embodiments of the present disclosure is shown.

[0013] Fig.10 is an isometric view of a mobile computing platform according to an embodiment of the present disclosure employing an IC manufactured according to one or more processes described herein or including one or more features described herein.

[0014] Fig.11 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Integrated capacitors are described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features (e.g., integrated circuit design layouts) are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0016] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "used as an example, instance or illustration". Any embodiment described herein as exemplary is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, there is no intention to be bound by any express or implied theory presented in the prior art field, background technology, summary of the invention or the following detailed description.

[0017] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0018] Terminology. The following paragraphs provide definitions or context for terms used in this disclosure, including the appended claims:

[0019] "Comprising". This term is open ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0020] "Configured to." Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such a context, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform those one or more tasks during operation. Thus, even when the specified unit or component is not currently operating (e.g., not turned on or active), the unit or component can be said to be configured to perform a task. Reciting a unit or circuit or component as "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit or component.

[0021] "First," "second," etc. As used herein, these terms serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0022] "Coupled" - The following description refers to elements, nodes or features that are "coupled" together. As used herein, unless expressly specified otherwise, "coupled" means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature (and not necessarily mechanically).

[0023] In addition, certain terms may also be used in the following description for reference purposes only, and therefore are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of portions of a component within a consistent but arbitrary reference system, which may be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0024] "Inhibit" - As used herein, "inhibit" is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, motion, or condition, it may completely prevent a result, consequence, or future state. Additionally, "inhibit" may also refer to reducing or mitigating a result, property, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or state, it need not completely prevent or eliminate that result or state.

[0025] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0026] Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0027] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to FEOL processing.

[0028] According to one or more embodiments of the present disclosure, integrated capacitors are described. One or more embodiments are directed to high performance and low tolerance integrated capacitors. One or more embodiments are directed to hybrid interdigitated and sandwiched mmW high-Q capacitors.

[0029] In a first aspect, a high performance and low tolerance integrated capacitor is described.

[0030] To provide background, passive inductive and capacitive devices are very important for RF and mmW circuits. Capacitors are implemented with closely spaced metal plates or interdigitated fingers and therefore have relatively large process variations. Larger sized inductive devices have much lower variations and therefore the tolerances of capacitor devices often limit the circuit. Another issue is the series inductance of the capacitor, which can dominate the impedance of the device and convert the capacitor into an inductor at very high frequencies.

[0031] Previous approaches to integrating capacitors include implementing circuit techniques that address the above issues, such as adding conditioning circuits, increasing the bandwidth of the circuits. However, these circuit techniques increase power consumption and area in the implementation.

[0032] According to one or more embodiments of the present disclosure, the tolerance of the capacitor is improved by adding additional dielectric and metal layers on top of the capacitor interdigital structures or below the capacitor interdigital structures. Through these layers, additional capacitor contributions are added that have low variation (good control of layer thickness relative to lithographically defined distances) and are independent of the initial variation. In an embodiment, such an arrangement brings an overall reduction in tolerance.

[0033] Advantages of implementing one or more of the embodiments described herein may include the fabrication of device enhanced circuits with lower power consumption and higher frequencies that may be designed for improved data rates.

[0034] As a comparative example, Figure 1 An angled cross-sectional view of an integrated capacitor structure is shown.

[0035] refer to Figure 1 , the integrated capacitor structure 100 includes alternating first metal lines 102 and second metal lines 104, which may be referred to as fingers. The first metal lines 102 are coupled together to a first polarity, for example, at a location entering or leaving a page. The second metal lines 104 are coupled together to a second polarity opposite to the first polarity, for example, at a location entering or leaving a page. The first metal lines 102 and the second metal lines 104 are included in a dielectric layer (e.g., a BEOL dielectric layer, which may generally be referred to as ε-ref). Individual metal lines in the first metal lines 102 and the second metal lines 104 may have a spacing (s), a width (W), a height (h), and a pitch, all of which contribute to the total capacitance of the integrated capacitor structure 100.

[0036] and Figure 1 contrast, Figure 2 An angled cross-sectional view of an integrated capacitor structure according to an embodiment of the present disclosure is shown.

[0037] refer to Figure 2 , the integrated capacitor structure 200 includes alternating first metal lines 202 and second metal lines 204, which may be referred to as fingers. The first metal lines 202 are coupled together to a first polarity, for example, at a location entering or leaving a page. The second metal lines 204 are coupled together to a second polarity opposite to the first polarity, for example, at a location entering or leaving a page. The first metal lines 202 and the second metal lines 204 are included in a dielectric layer (e.g., a BEOL dielectric layer). A single metal line of the first metal lines 202 and the second metal lines 204 may be a combination of Figure 1In an embodiment, the integrated capacitor structure 200 includes at least one metal plate 208 and an intervening dielectric liner 206 (the latter shown having a thickness t, and a liner permittivity ε-liner).

[0038] Reference again Figure 2 , in one embodiment, as depicted, a single metal plate 208 and intervening dielectric liner 206 pair is included above the "interdigitated" capacitors 202 / 204. In another embodiment, one or more additional metal plate and intervening dielectric liner pairs are included above the metal plate 208 and intervening dielectric liner 206. In another embodiment, one or more metal plate and intervening dielectric liner pairs are included below the "interdigitated" capacitors. In another embodiment, one or more metal plate and intervening dielectric liner pairs are included above the "interdigitated" capacitors and below the "interdigitated" capacitors.

[0039] Reference again Figure 1 and Figure 2 , Figure 1 A prior art interdigital capacitor for integrated CMOS capacitors is shown in FIG. A dielectric with a constant dielectric constant is assumed, which is also used in the simulations described below. It should be understood that the capacitor can be a processed layer with different dielectrics. Figure 2 As shown, according to an embodiment of the present disclosure, a thin dielectric 206 (preferably having a relatively higher dielectric constant than the surrounding dielectric layers) and a metal plate are added to the interdigitated structure. The dielectric and metal can be located above the interdigitated structure, below the interdigitated structure, or above and below the interdigitated structure. In an embodiment, because the two polarity interdigits are coupled to the plate with high capacitance, the metal plate is typically floating and causes an increase in capacitance density.

[0040] In an embodiment, in combination Figure 2 This construction of the described capacitor structure can have several advantages. Capacitor density can be increased by additional capacitor components. The added processing operation only includes the added thin layer and does not require high-resolution lithography. Therefore, the processing operation is cheap and existing layers in the process (such as barrier layers) can also be used. The process control of the thickness of such layers can be very good and the tolerance is low. The metal plate can reduce the series inductance of the interdigitated fingers (for example, the inductance of the trace located above the ground plane, which decreases with the distance to the plane). Since the metal can be patterned using process design rules, the thickness can be increased, thereby reducing the sheet resistance. In addition, if a low added height is a preferred choice for the integration scheme, a very thin layer with a good effect on capacitance density and tolerance can be selected. By using fewer metal interdigitated layers (using higher capacitor density), free metal layers can be used for wiring. In addition, parasitic capacitance can also be reduced.

[0041] Figure 3 is a diagram showing an exemplary simulation according to an embodiment of the present disclosure Figure 2 Graph 300 of the benefits of capacitor construction in FIG.

[0042] refer to Figure 3 300, including reference interdigital capacitors (eg, Figure 1 ) and boost capacitors (e.g. Figure 2 ). The parameters are shown in the inset. A fixed pitch of 50nm is used, which is divided into a width of 25nm and a spacing of 25nm. The height of the metal line is 50nm. The geometric parameters are varied by 10% (the pitch is kept constant) and each simulated capacitance value is shown. In this example, Figure 2 The added layer in causes an 80% increase in capacitance. Furthermore, it is clearly visible that the changes in w / s and h have a reduced effect on the capacitance value (for a constant "t-change", the distribution is smaller than in the reference capacitor). The thickness variation of the additional dielectric also contributes to the capacitance variation, but with a tighter control of this thickness, an overall reduction in the variation can be achieved. For the enhanced capacitor, a liner thickness of 5nm was used and a dielectric capacitance twice that of the reference object. The geometric parameters were varied by 10% and the resulting capacitance values ​​are shown in the graph. The logarithmic scale allows an easy assessment of the variation (a constant percentage change causes the same y-axis distribution, regardless of the base value). Figure 2 Possible applications of the capacitor structure in may include RF, mmW, and / or analog circuits that may benefit from the availability of such enhanced capacitors.

[0043] In an embodiment, the first metal line 202 and the second metal line 204 are formed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof, and may include a conductive liner or a barrier located around such a conductive material.

[0044] In an embodiment, the surrounding dielectric (ε-ref) is a low-k dielectric layer, such as found in BEOL structures. In one such embodiment, the low-k dielectric layer is composed of a doped oxide of silicon, a fluorinated oxide of silicon, or a carbon-doped oxide of silicon. In another embodiment, the surrounding dielectric (ε-ref) is composed of an oxide of silicon, such as silicon dioxide (SiO2).

[0045] In an embodiment, the dielectric liner 206 is a high-k material or includes a high-k material. For example, in one embodiment, the dielectric liner 206 is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0046] In an embodiment, the metal plate 208 is composed of a metal layer, such as, but not limited to: metal nitride (TiN or TaN), metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, copper or a conductive metal oxide.

[0047] In a second aspect, a hybrid interdigitated and interlayer mmW high-Q capacitor is described.

[0048] To provide background, passive inductive and capacitive devices are very important for RF and mmW circuits. Capacitors are usually realized by closely spaced metal fingers. This construction provides high capacitance density, about 50% metal density, which is ideal for metal processes using CMP polishing. The Q factor of a capacitor is proportional to ~1 / frequency at high frequencies. For mmW circuits and especially for next generation >100GHz applications, the Q factor of a capacitor is a high priority to achieve low power consumption and low noise circuits.

[0049] In previous approaches, capacitor fingers have been implemented using thicker metal layers, using larger design rules, to reduce resistance. It is also possible to reduce the cell size of the capacitor to produce a capacitor with shorter fingers. In embodiments, these smaller cells can be combined to achieve larger capacitors. Using thicker metal with larger pitches results in a significant reduction in capacitor density and therefore increased area.

[0050] According to one or more embodiments of the present disclosure, an alternating interdigital structure is combined with a capacitor plate. The plate and the interdigital fingers are connected by vias to reduce the series resistance. Therefore, the capacitor is a combination of an interdigital capacitor that utilizes the lateral capacitance between the interdigital fingers and an interlayer metal capacitor that utilizes the vertical capacitance.

[0051] Advantages of implementing capacitor plates connected to the fingers through vias may include significantly reducing the series resistance of the fingers. Thus, the high density of the interdigital capacitors is combined with the low resistance of the sandwich capacitor plates.

[0052] As described above Figure 1 contrast, Figure 4 An angled cross-sectional view of an integrated capacitor structure according to an embodiment of the present disclosure is shown.

[0053] refer to Figure 4, the integrated capacitor structure 400 includes alternating first metal lines 402 and second metal lines 404, which may be referred to as interdigitated fingers. The first metal lines 402 are coupled together to a first polarity, for example, at a location entering or leaving a page. The second metal lines 404 are coupled together to a second polarity opposite to the first polarity, for example, at a location entering or leaving a page. The first metal lines 402 and the second metal lines 404 are included in a dielectric layer (e.g., a BEOL dielectric layer). A single metal line of the first metal lines 402 and the second metal lines 404 may be a combination of Figure 1 4. The integrated capacitor structure 400 is described in detail with reference to FIG. 4. In an embodiment, the integrated capacitor structure 400 includes a first metal plate 408 and a second metal plate 412. The first metal plate 408 is located above the first metal line 402 and the second metal line 404 and is coupled to the first metal line 402 through a first via 410. As indicated by the same shading, the first metal plate 408 and the first metal line 402 have the same polarity. The second metal plate 412 is located below the first metal line 402 and the second metal line 404 and is coupled to the second metal line 404 through a second via 414. As indicated by the same shading, the second metal plate 412 and the second metal line 404 have the same polarity. The polarity of the second metal plate 412 / second metal line 404 is opposite to the polarity of the first metal plate 408 / first metal line 402.

[0054] Reference again Figure 4 In an embodiment, fingers and plates of the same polarity are connected by a dense arrangement of vias. Different configurations of capacitors can be implemented to adapt the device to circuit requirements, available metal stacks, and design rules. The configurations can be easily described using the following nomenclature: P: plate; F: finger; Fv: finger with vertical orientation; Fh: finger with horizontal orientation. Configurations can include: PFP (such as Figure 4 As shown), PFPFP (for capacitors using 5 metal layers), PFFP, P-Fv-P-Fv-P (parallel fingers), P-Fv-P-Fh-P (fingers rotated 90°), P-Fv-Fv-P, P-Fh-Fv-P, etc. For example, the best choice depends on the amount of metal used, the preferred metal orientation, and the connections for the capacitor leads.

[0055] In an embodiment, in order to evaluate the benefits of implementing the embodiments described herein, S parameters of different capacitor layouts using EM simulations and capacitance, series resistance, and Q factor calculated with respect to frequency were simulated. As an example, Figure 5is a graph including simulated (EM simulation) capacitance, resistance, and Q factor versus frequency for different capacitors according to an embodiment of the present disclosure. The embodiments described herein show greatly reduced resistance and improved Q factor. The variant with reduced vias shows the importance of via connections.

[0056] The simulated capacitors have the following constructions: (1) a standard finger capacitor with 5 layers: Fv-Fv-Fv-Fv-Fv (reference); (2) a plate / finger capacitor with full via connections (disclosed): P-Fv-P-Fv-P; (3) a plate / finger capacitor with no vias; (4) a plate / finger capacitor with via connections at the edges of the fingers. The geometry of the capacitors was adjusted to give the same capacitance. For the embodiments described herein, the series resistance of the capacitors was reduced by a factor of 2, which directly translates into a 2x improved Q factor. The versions of the capacitors without vias and with the vias at the edges of the fingers have higher resistance values ​​and indicate that good via connections to the board may be important.

[0057] In an embodiment, if a larger capacitance value is required, board segmentation and partitioning methods can be used to reduce metal density. Figure 2 Possible applications of the capacitor structure in may include RF, mmW, and / or analog circuits that may benefit from the availability of such enhanced capacitors.

[0058] In an embodiment, the first metal line 402 and the second metal line 404 are composed of a conductive material, such as, but not limited to: Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or their alloys, and may include a conductive liner or a barrier located around such a conductive material.

[0059] In an embodiment, the surrounding dielectric (ε-ref) is a low-k dielectric layer, such as found in BEOL structures. In one such embodiment, the low-k dielectric layer is composed of a doped oxide of silicon, a fluorinated oxide of silicon, or a carbon-doped oxide of silicon. In another embodiment, the surrounding dielectric (ε-ref) is composed of an oxide of silicon, such as silicon dioxide (SiO2).

[0060] In an embodiment, metal plates 408 and 412 are formed of a metal layer, such as, but not limited to, metal nitride (TiN or TaN), metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, copper, or a conductive metal oxide.

[0061] In another aspect, the embodiments described herein may be implemented as an on-die integrated capacitor for use in a power delivery system. As an example, Figure 6A cross-sectional view of an integrated capacitor on a die in a power delivery system 600 and a corresponding circuit schematic 602 are shown according to an embodiment of the present disclosure.

[0062] refer to Figure 6 , the power delivery system 600 includes a board 604, a package 606 coupled to the board 604, and a die 608 coupled to the package 606. The die 608 includes an on-die integrated capacitor 610 (e.g., as described above in conjunction with Figure 2-Figure 5 integrated capacitor as described).

[0063] In another aspect, back-end-of-line (BEOL) layers of an integrated circuit typically include conductive microelectronic structures (referred to in the art as vias) to electrically connect metal lines or other interconnects located above the vias to metal lines or other interconnects located below the vias. In accordance with one or more embodiments of the present disclosure, an integrated capacitor (e.g., a capacitor described above in conjunction with a Figure 2-Figure 5 ) as described may be included in a BEOL structure of an integrated circuit.

[0064] As an exemplary but non-limiting BEOL structure, Figure 7 A cross-sectional view of an integrated circuit structure having four metallization layers with metal line compositions and pitches according to an embodiment of the present disclosure is shown, wherein the four metallization layers with metal line compositions and pitches are located above two metallization layers with different metal line compositions and smaller pitches. It should be understood that according to the embodiments described above (e.g., Figure 2-Figure 5 ) can be integrated into the following combination of capacitors Figure 7 One or more layers of the described integrated circuit structure.

[0065] refer to Figure 7 , the integrated circuit structure 700 includes a first plurality of conductive interconnects 704 in and separated by a first inter-layer dielectric (ILD) layer 702, the first inter-layer dielectric (ILD) layer 702 being over a substrate 701. An individual conductive interconnect of the first plurality of conductive interconnects 704 includes a first conductive barrier material 706 along sidewalls and a bottom of a first conductive fill material 708. An individual conductive interconnect of the first plurality of conductive interconnects 704 is along a first direction 798 (e.g., into and out of the page).

[0066] The second plurality of conductive interconnects 714 are located in and separated by the second ILD layer 712, which is located above the first ILD layer 702. An individual conductive interconnect of the second plurality of conductive interconnects 714 includes the first conductive barrier material 706 along the sidewalls and bottom of the first conductive fill material 708. An individual conductive interconnect of the second plurality of conductive interconnects 714 is along a second direction 799 that is orthogonal to the first direction 798.

[0067] The third plurality of conductive interconnects 724 are located in and separated by the third ILD layer 722, which is located above the second ILD layer 712. An individual conductive interconnect of the third plurality of conductive interconnects 724 includes a second conductive barrier material 726 along the sidewalls and bottom of a second conductive fill material 728. The second conductive fill material 728 is different in composition from the first conductive fill material 708. An individual conductive interconnect of the third plurality of conductive interconnects 724 is along a first direction 798.

[0068] The fourth plurality of conductive interconnects 734 are located in and spaced apart by the fourth ILD layer 732, which is located above the third ILD layer 722. A single conductive interconnect of the fourth plurality of conductive interconnects 734 includes the second conductive barrier material 726 along the sidewalls and bottom of the second conductive fill material 728. A single conductive interconnect of the fourth plurality of conductive interconnects 734 is along the second direction 799.

[0069] The fifth plurality of conductive interconnects 744 are located in and spaced apart by the fifth ILD layer 742, which is located above the fourth ILD layer 732. A single conductive interconnect of the fifth plurality of conductive interconnects 744 includes the second conductive barrier material 726 along the sidewalls and bottom of the second conductive fill material 728. The single conductive interconnect of the fifth plurality of conductive interconnects 744 is along the first direction 798.

[0070] The sixth plurality of conductive interconnects 754 are located in and spaced apart by the sixth ILD layer 752, which is located above the fifth ILD layer 742. A single conductive interconnect of the sixth plurality of conductive interconnects 754 includes the second conductive barrier material 726 along the sidewalls and bottom of the second conductive fill material 728. The single conductive interconnect of the sixth plurality of conductive interconnects 754 is along the second direction 799.

[0071] In an embodiment, the second conductive fill material 728 consists essentially of copper, and the first conductive fill material 708 consists essentially of cobalt. In an embodiment, the first conductive fill material 708 includes copper having a first concentration of dopant impurity atoms, and the second conductive fill material 728 includes copper having a second concentration of dopant impurity atoms, the second concentration of dopant impurity atoms being less than the first concentration of dopant impurity atoms.

[0072] In an embodiment, the first conductive barrier material 706 is different in composition from the second conductive barrier material 726. In another embodiment, the first conductive barrier material 706 and the second conductive barrier material 726 have the same composition.

[0073] In an embodiment, the first conductive via 719 is located on and electrically coupled to a single conductive interconnect line 704A in the first plurality of conductive interconnect lines 704. The single conductive interconnect line 714A in the second plurality of conductive interconnect lines 714 is located on and electrically coupled to the first conductive via 719.

[0074] The second conductive via 729 is located on and electrically coupled to the single conductive interconnect line 714B of the second plurality of conductive interconnect lines 714. The single conductive interconnect line 724A of the third plurality of conductive interconnect lines 724 is located on and electrically coupled to the second conductive via 729.

[0075] The third conductive via 739 is located on and electrically coupled to the single conductive interconnect line 724B of the third plurality of conductive interconnect lines 724. The single conductive interconnect line 734A of the fourth plurality of conductive interconnect lines 734 is located on and electrically coupled to the third conductive via 739.

[0076] The fourth conductive via 749 is located on and electrically coupled to the single conductive interconnect line 734B of the fourth plurality of conductive interconnect lines 734. The single conductive interconnect line 744A of the fifth plurality of conductive interconnect lines 744 is located on and electrically coupled to the fourth conductive via 749.

[0077] The fifth conductive via 759 is located on and electrically coupled to the single conductive interconnect line 744B of the fifth plurality of conductive interconnect lines 744. The single conductive interconnect line 754A of the sixth plurality of conductive interconnect lines 754 is located on and electrically coupled to the fifth conductive via 759.

[0078] In one embodiment, the first conductive via 719 includes the first conductive barrier material 706 along the sidewalls and bottom of the first conductive filling material 708. The second conductive via 729, the third conductive via 739, the fourth conductive via 749, and the fifth conductive via 759 include the second conductive barrier material 726 along the sidewalls and bottom of the second conductive filling material 728.

[0079] In an embodiment, the first ILD layer 702, the second ILD layer 712, the third ILD layer 722, the fourth ILD layer 732, the fifth ILD layer 742, and the sixth ILD layer 752 are separated from each other by corresponding etch stop layers 790 located between adjacent ILD layers. In an embodiment, the first ILD layer 702, the second ILD layer 712, the third ILD layer 722, the fourth ILD layer 732, the fifth ILD layer 742, and the sixth ILD layer 752 include silicon, carbon, and oxygen.

[0080] In an embodiment, a single conductive interconnect line in the first plurality of conductive interconnect lines 704 and the second plurality of conductive interconnect lines 714 has a first width (W1). A single conductive interconnect line in the third plurality of conductive interconnect lines 724, the fourth plurality of conductive interconnect lines 734, the fifth plurality of conductive interconnect lines 744, and the sixth plurality of conductive interconnect lines 754 has a second width (W2) greater than the first width (W1).

[0081] It should be understood that the layers and materials described above in conjunction with back-end-of-line (BEOL) structures and processing can be formed on or above an underlying semiconductor substrate or structure (e.g., an underlying device layer of (multiple) integrated circuits). In an embodiment, the underlying semiconductor substrate represents a general workpiece object for manufacturing integrated circuits. Semiconductor substrates typically include wafers or other chips of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to: single crystal silicon, polycrystalline silicon, silicon on insulator (SOI), and similar substrates formed from other semiconductor materials, such as substrates including germanium, carbon, or III-V materials. Depending on the stage of manufacture, semiconductor substrates typically include transistors, integrated circuit systems, etc. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In addition, the depicted structures can be manufactured on lower level interconnect layers of the underlying layer.

[0082] Although the above methods of manufacturing a metallization layer or a portion of a metallization layer, a portion of a BEOL metallization layer are described in detail with respect to selected operations, it should be understood that additional operations or intermediate operations for manufacturing may include standard microelectronics manufacturing processes, such as lithography, etching, thin film deposition, planarization (e.g., chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other operation associated with microelectronic component manufacturing. In addition, it should be understood that the process operations described for the above process flow may be practiced in an alternative order, not every operation needs to be performed, or additional process operations may be performed, or both.

[0083] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or a layer of an insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0084] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are lines and structures using copper, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Therefore, the interconnect may be a single material layer, or may be formed by several layers (including a conductive liner and a filling layer). Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof. Interconnects are also sometimes referred to in the art as traces, conductors, wires, metal, or simply interconnects.

[0085] In an embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials can be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer includes a layer of silicon nitride (e.g., silicon nitride), or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes a metallic substance. For example, a hard mask or other overlying material may include a layer of titanium or another metal nitride (e.g., titanium nitride). Possibly smaller amounts of other materials (e.g., oxygen) may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used, depending on the particular embodiment. The hard mask layer may be formed by CVD, PVD, or other deposition methods.

[0086] In an embodiment, as also used throughout this specification, 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography, etc., are used to perform the lithography operation. Positive or negative photoresists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0087] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, and the like. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0088] Figure 8A computing device 800 is shown according to one embodiment of the present disclosure. The computing device 800 houses a board 802. The board 802 may include a plurality of components, including, but not limited to, a processor 7904 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some embodiments, the at least one communication chip 806 is also physically and electrically coupled to the board 802. In other embodiments, the communication chip 806 is part of the processor 804.

[0089] Depending on the application of the computing device 800, the computing device may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (e.g., hard drive, compact disc (CD), digital versatile disc (DVD), etc.).

[0090] The communication chip 806 can implement wireless communications for transmitting data to and from the computing device 800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments, they may not contain wires. The communication chip 806 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 800 may include multiple communication chips 806. For example, the first communication chip 806 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 806 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0091] The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the embodiments of the present disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated capacitors constructed according to implementations of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from a register or memory or both to transform the electronic data into other electronic data that can be stored in a register or memory or both.

[0092] The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. According to another embodiment of the present disclosure, the integrated circuit die of the communication chip has an integrated capacitor constructed according to an embodiment of the present disclosure.

[0093] In further implementations, another component housed within computing device 800 may contain an integrated circuit die having an integrated capacitor constructed in accordance with implementations of embodiments of the present disclosure.

[0094] In various embodiments, computing device 800 may be a laptop computer, a netbook, a notebook, an ultrabook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, computing device 800 may be any other electronic device that processes data.

[0095] Fig. 9 An interposer 900 including one or more embodiments of the present disclosure is shown. Interposer 900 is an intermediate substrate for bridging a first substrate 902 to a second substrate 904. The first substrate 902 may be, for example, an integrated circuit die. The second substrate 904 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of interposer 900 is to extend the connection to a wider pitch or to rewire the connection to a different connection. For example, interposer 900 may couple an integrated circuit die to a ball grid array (BGA) 906, which may then be coupled to a second substrate 904. In some embodiments, the first substrate 902 and the second substrate 904 are attached to opposite sides of interposer 900. In other embodiments, the first substrate 902 and the second substrate 904 are attached to the same side of interposer 900. And in further embodiments, three or more substrates are interconnected through interposer 900.

[0096] Interposer 900 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, interposer 900 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0097] The interposer 900 may include metal interconnects 908 and vias 910, including but not limited to through silicon vias (TSVs) 912. The interposer 900 may also include embedded devices 914, including both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 900. According to an embodiment of the present disclosure, the devices or processes disclosed herein may be used to manufacture the interposer 900 or to manufacture components included in the interposer 900.

[0098] Fig.10 is an isometric view of a mobile computing platform 1000 employing an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0099] The mobile computing platform 1000 can be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1000 can be any of a tablet computer, a smart phone, a laptop computer, etc., and includes a display screen 1005 that is a touch screen (capacitive, inductive, resistive, etc.) in an exemplary embodiment, a chip-level (SoC) or package-level integrated system 1010, and a battery 1013. As shown in the figure, the higher the integration in the system 1010 achieved by a higher transistor packaging density, the larger the portion of the mobile computing platform 1000 that can be occupied by a battery 1013 or a non-volatile storage device (such as a solid-state drive), or the larger the transistor gate count for improving the functionality of the platform. Similarly, the greater the carrier mobility of each transistor in the system 1010, the greater the functionality. Similarly, the technology described herein can achieve improvements in performance and form factors in the mobile computing platform 1000.

[0100] The integrated system 1010 is further shown in the expanded view 1020. In an exemplary embodiment, the packaged device 1077 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) manufactured according to one or more processes described herein or including one or more features described herein. The packaged device 1077 can also be coupled to the board 1060 together with one or more of its power management integrated circuit (PMIC) 1015, an RF (wireless) integrated circuit (RFIC) 1025 including a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband and an analog front end module further including a power amplifier on the transmit path and a low noise amplifier on the receive path), and the controller 1011. Functionally, the PMIC 1015 performs battery power regulation, DC to DC conversion, etc., and therefore has an input coupled to the battery 1013 and has an output that provides a current source to all other functional modules. As further shown, in an exemplary embodiment, the RFIC 1025 has an output coupled to an antenna to provide for implementing any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth or derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G and higher. In alternative embodiments, each of these board-level modules may be integrated into a separate IC coupled to a packaging substrate of the packaged device 1077, or integrated into a single IC (SoC) coupled to a packaging substrate of the packaged device 1077.

[0101] In another aspect, semiconductor packages are used to protect an integrated circuit (IC) chip or die and also provide an electrical interface for the die to external circuitry. As the demand for smaller electronic devices continues to increase, semiconductor packages are designed to be even more compact and must support greater circuit densities. In addition, the demand for higher performance devices creates a need for an improved semiconductor package that can achieve a thin package profile and low overall warpage that is compatible with subsequent assembly processing.

[0102] In an embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount the die to a ceramic or organic package substrate. Specifically, a C4 solder ball connection can be implemented to provide a flip chip interconnection between a semiconductor device and a substrate. Flip chip or controlled collapse chip connection (C4) is a type of installation for semiconductor devices (e.g., integrated circuit (IC) chips, MEMS, or components) that utilize solder bumps instead of wire bonding. Solder bumps are deposited on C4 pads located on the top side of the substrate package. In order to mount the semiconductor device on the substrate, it is flipped over and placed on the mounting area with the active side facing down. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0103] Fig.11 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure.

[0104] refer to Fig.11 According to an embodiment of the present disclosure, device 1100 includes a die 1102, such as an integrated circuit (IC) manufactured according to one or more processes described herein or including one or more features described herein. Die 1102 includes metallized pads 1104 located thereon. A package substrate 1106 (e.g., a ceramic or organic substrate) includes connections 1108 located thereon. Die 1102 and package substrate 1106 are electrically connected via solder balls 1110 coupled to metallized pads 1104 and connections 1108. An underfill material 1112 surrounds solder balls 1110.

[0105] Processing a flip chip can be similar to regular IC manufacturing, but with some additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of a variety of treatments. A small dot of solder is then deposited on each metallized pad. The chip is then cut from the wafer as normal. To attach the flip chip to a circuit, the chip is turned upside down to bring the solder dots down to the connectors located on the underlying electronics or circuit board. The solder is then re-melted to create an electrical connection, typically using an ultrasonic or alternative reflow process. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases, it is then "bottom-filled" with an electrically insulating adhesive to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed by differential heating of the chip and the rest of the system.

[0106] In other embodiments, newer packaging and die-to-die interconnect methods, such as through silicon vias (TSVs) and silicon interposers, are implemented in accordance with embodiments of the present disclosure to manufacture high-performance multi-chip modules (MCMs) and system-in-package (SiPs) that incorporate integrated circuits (ICs) manufactured according to one or more processes described herein or that include one or more features described herein.

[0107] Thus, embodiments of the present disclosure include integrated capacitors.

[0108] Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Unless otherwise specified, the examples of features provided in the present disclosure are intended to be illustrative rather than restrictive. The above description is intended to cover such substitutions, modifications, and equivalents that are obvious to those skilled in the art having the benefit of the present disclosure.

[0109] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, during the examination of this application (or an application claiming priority thereto), new claims may be made for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of independent claims, and features from corresponding independent claims may be combined in any appropriate manner, not merely in the specific combinations listed in the appended claims.

[0110] The following examples relate to further embodiments. The various features of the different embodiments can be combined in different ways with some features included and other features not included to suit a variety of different applications.

[0111] Example embodiment 1: An integrated capacitor structure, comprising: alternating first metal lines and second metal lines, the alternating first metal lines and second metal lines are located in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines are coupled together, and the second metal lines are coupled together. A first metal plate is located above the alternating first metal lines and second metal lines. The first metal plate is coupled to the first metal lines through a first via.

[0112] Exemplary Embodiment 2: The integrated capacitor structure according to Exemplary Embodiment 1, further comprising: a second metal plate located under the alternating first metal lines and second metal lines, the second metal plate being coupled to the second metal lines through second vias.

[0113] Exemplary Embodiment 3: The integrated capacitor structure according to Exemplary Embodiment 2, wherein the first metal line and the first metal plate are coupled to a first polarity, and the second metal line and the second metal plate are coupled to a second polarity opposite to the first polarity.

[0114] Example Embodiment 4: The integrated capacitor structure of Example Embodiment 1, 2 or 3, wherein the dielectric layer is a low-k dielectric layer.

[0115] Example Embodiment 5: The integrated capacitor structure according to Example Embodiment 1, 2, 3 or 4, wherein the alternating first and second metal lines and the dielectric layer form an interdigitated capacitor structure.

[0116] Example 6: An integrated capacitor structure, comprising: alternating first metal lines and second metal lines, the alternating first metal lines and second metal lines are located in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines are coupled together, and the second metal lines are coupled together. A first metal plate is located under the alternating first metal lines and second metal lines. The first metal plate is coupled to the first metal lines through a first via.

[0117] Exemplary embodiment 7: The integrated capacitor structure according to exemplary embodiment 6 further includes: alternating third metal lines and fourth metal lines, which are located above the alternating first metal lines and second metal lines, the third metal lines are coupled to the first metal lines, and the fourth metal lines are coupled to the second metal lines.

[0118] Exemplary Embodiment 8: The integrated capacitor structure according to Exemplary Embodiment 6 or 7, wherein the first metal line and the first metal plate are coupled to a first polarity, and the second metal line is coupled to a second polarity opposite to the first polarity.

[0119] Example Embodiment 9: The integrated capacitor structure of Example Embodiment 6, 7 or 8, wherein the dielectric layer is a low-k dielectric layer.

[0120] Example Embodiment 10: The integrated capacitor structure according to Example Embodiment 6, 7, 8 or 9, wherein the alternating first and second metal lines and the dielectric layer form an interdigitated capacitor structure.

[0121] Example embodiment 11: A computing device, comprising: a board and a component coupled to the board. The component comprises an integrated capacitor structure, the integrated capacitor structure comprising: alternating first metal lines and second metal lines, the alternating first metal lines and second metal lines are located in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines are coupled together, and the second metal lines are coupled together. A first metal plate is located above the alternating first metal lines and second metal lines, or is located below the alternating first metal lines and second metal lines. The metal plate is coupled to the first metal lines or the second metal lines through a via.

[0122] Exemplary Embodiment 12: The computing device according to Exemplary Embodiment 11, wherein the metal plate is located above the alternating first metal lines and second metal lines.

[0123] Exemplary Embodiment 13: The computing device according to Exemplary Embodiment 11, wherein the metal plate is located under the alternating first metal lines and second metal lines.

[0124] Exemplary Embodiment 14: The computing device of Exemplary Embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0125] Exemplary Embodiment 15: The computing device of Exemplary Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0126] Exemplary Embodiment 16: The computing device of Exemplary Embodiment 11, 12, 13, 14, or 15, further comprising a camera coupled to the board.

[0127] Exemplary Embodiment 17: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15 or 16, further comprising a battery coupled to the board.

[0128] Exemplary Embodiment 18: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a GPS coupled to the board.

[0129] Exemplary Embodiment 19: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, further comprising a display coupled to the board.

[0130] Exemplary Embodiment 20: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated capacitor structure comprising: alternating first and second metal lines, the alternating first and second metal lines being located in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines being coupled together, and the second metal lines being coupled together; as well as A first metal plate is disposed on the alternating first and second metal lines, and the first metal plate is coupled to the first metal line through a first via.

2. The integrated capacitor structure of claim 1 , further comprising: A second metal plate is disposed under the alternating first metal lines and second metal lines, and the second metal plate is coupled to the second metal lines through a second via.

3. The integrated capacitor structure according to claim 2, wherein: The first metal line and the first metal plate are coupled to a first polarity, and the second metal line and the second metal plate are coupled to a second polarity opposite to the first polarity.

4. The integrated capacitor structure according to claim 1, 2 or 3, wherein: The dielectric layer is a low-k dielectric layer.

5. The integrated capacitor structure according to claim 1, 2 or 3, wherein: The alternating first and second metal lines and the dielectric layer form an interdigitated capacitor structure.

6. An integrated capacitor structure comprising: alternating first and second metal lines, the alternating first and second metal lines being located in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines being coupled together, and the second metal lines being coupled together; as well as A first metal plate is disposed under the alternating first and second metal lines, and the first metal plate is coupled to the first metal line through a first via.

7. The integrated capacitor structure of claim 6, further comprising: Alternating third and fourth metal lines, the alternating third and fourth metal lines are located above the alternating first and second metal lines, the third metal lines are coupled to the first metal lines, and the fourth metal lines are coupled to the second metal lines.

8. The integrated capacitor structure according to claim 6 or 7, wherein: The first metal line and the first metal plate are coupled to a first polarity, and the second metal line is coupled to a second polarity opposite to the first polarity.

9. The integrated capacitor structure according to claim 6 or 7, wherein: The dielectric layer is a low-k dielectric layer.

10. The integrated capacitor structure according to claim 6 or 7, wherein: The alternating first and second metal lines and the dielectric layer form an interdigitated capacitor structure.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated capacitor structure, the integrated capacitor structure comprising: alternating first and second metal lines, the alternating first and second metal lines being located in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines being coupled together, and the second metal lines being coupled together; as well as A metal plate is located above the alternating first metal lines and the second metal lines, or below the alternating first metal lines and the second metal lines, and the metal plate is coupled to the first metal lines or the second metal lines through vias.

12. The computing device according to claim 11, wherein: The metal plate is located above the alternating first and second metal lines.

13. The computing device of claim 11, wherein: The metal plate is located under the alternating first and second metal lines.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12 or 13, further comprising: A camera is coupled to the board.

17. The computing device of claim 11, 12 or 13, further comprising: A battery coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: Coupled to the board's GPS.

19. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the panel.

20. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

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