Capacitive coupling in interface for direct bonding of microelectronic devices

Abstract

Capacitive coupling in an interface for direct bonding of microelectronic devices is provided. A microelectronic device includes a first die and a second die directly bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by metal-metal direct bonding, and a capacitive interconnect between the first die and the second die formed at the bonding interface. The direct bonding process creates a direct bond between the dielectric surfaces of the two dies, creates a direct bond between the respective conductive interconnects of the two dies, and creates a capacitive coupling between the two dies at the bonding interface. In one embodiment, the capacitive coupling of each signal line at the bonding interface includes a dielectric material that each signal line forms a capacitor at the bonding interface. The capacitive coupling results from the same direct bonding process that results in conductive interconnects that are directly bonded together at the same bonding interface.

Description

[0001] This application is a divisional application of the Chinese patent application with international application number PCT / US2019 / 048530, international application date August 28, 2019, national application number 201980080676.7, and invention name “Capacitive coupling in interfaces for direct bonding of microelectronic devices”. Background Art

[0002] Direct bonding and direct hybrid bonding sometimes require critical tolerances. When various ways of coupling power, ground, and signal lines at the bonding interface can be designed, these processes can become more forgiving, for example, allowing some misalignment and allowing lower critical tolerances to provide more reliable packages with higher bonding yields.

[0003] Furthermore, the reduction in size of wafer-level packages and microelectronic components is sometimes inhibited by the necessary inclusion of components that are difficult to miniaturize. For example, sometimes a package relies on the relatively large size of discrete capacitors. If the package does not have to rely on large components, the package can be made smaller. In other cases, a certain value of capacitor is required in the integrated circuit design, and if the capacitor can be built into the wafer-level package design, the construction process can be simplified. Summary of the invention

[0004] Capacitive coupling in a directly bonded interface of a microelectronic device is provided. In one embodiment, the microelectronic device includes a first die and a second die directly bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by metal-metal direct bonding, and a capacitive interconnect between the first die and the second die formed at the bonding interface. The direct bonding process produces a direct bond between the dielectric surfaces of the two dies, a direct bond between the corresponding conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In one embodiment, the capacitive coupling of each signal line at the bonding interface includes a dielectric material of each signal line forming a capacitor at the bonding interface. The capacitive coupling results from the same direct bonding process that produces the conductive interconnects directly bonded together at the same bonding interface.

[0005] This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Hereinafter, certain embodiments of the present disclosure will be described with reference to the accompanying drawings, wherein the same reference numerals represent the same elements. However, it should be understood that the accompanying drawings illustrate various embodiments described herein and are not intended to limit the scope of the various technologies described herein.

[0007] Figure 1 is a diagram of an example wafer level packaging structure 100 including an example capacitive coupling with an ultra-thin dielectric layer.

[0008] Figure 2 is a diagram of an example wafer-level package structure in which the ultra-thin dielectric layer includes two component dielectric layers.

[0009] Figure 3 is a diagram of another example wafer-level packaging structure in which the ultra-thin dielectric layer includes multiple component dielectric layers.

[0010] Figure 4 is a diagram of an example wafer level package including a capacitive interface with interleaved conductive plates.

[0011] Figure 5 is a diagram of an example process for fabricating a coupled capacitive wafer level package including a capacitive interface.

[0012] Figure 6 is an illustration of an example directly bonded interface between a first die and a second die including one or more directly bonded conductive interconnects in the same bonding plane as one or more capacitive interconnects formed by the same direct bonding process.

[0013] Figure 7 is an illustration of another example direct-bonded interface between a first die and a second die including one or more directly-bonded conductive interconnects in the same bonding plane as one or more capacitive interconnects formed by the same direct-bonding process.

[0014] Figure 8 is another illustration of an example direct-bonded interface between a first die and a second die including one or more directly-bonded conductive interconnects in the same bonding plane as one or more capacitive interconnects formed by the same direct-bonding process.

[0015] Fig. 9 is a diagram of an example directly bonded interface including conductive interconnects directly bonded together at a bonding interface and example capacitive interconnects also coupled at the bonding interface.

[0016] Fig.10 is a diagram of an example directly bonded interface including conductive interconnects directly bonded together at a bonding interface and example capacitive interconnects also coupled at the same bonding interface with one or more conductive vias at the same bonding interface.

[0017] Fig.11 is a flow chart of an example method for creating capacitive coupling in a directly bonded interface of a microelectronic device. DETAILED DESCRIPTION

[0018] Overview

[0019] The present disclosure describes capacitive coupling in a direct-bonded interface for microelectronic devices. A direct hybrid bonding process for microelectronic dies and wafers also creates capacitive coupling for each individual signal line at the bonding interface. In one embodiment, the direct hybrid bonding process creates a direct bond between the dielectric surfaces of the two dies, a direct bond between the respective power interconnects of the two dies, a direct bond between the respective ground interconnects of the two dies, and a capacitive coupling for each signal line at the bonding interface of the direct hybrid bonding process.

[0020] The direct bonding between dielectric surfaces may be an oxide-to-oxide direct bonding. The direct bonding between corresponding power interconnects is a metal-to-metal direct bonding. The direct bonding between corresponding ground interconnects is also a metal-to-metal direct bonding. The capacitive coupling of each signal line at the bonding interface includes a dielectric material that forms a capacitor at the bonding interface for each signal line, which is produced by a direct hybrid bonding process.

[0021] The example technology enables capacitive coupling with very fine pitch in a package structure. By connecting two opposing surfaces, a very thin dielectric layer on the order of nanometers can be achieved between two conductive areas (plates or pads, i.e., one from each die). The two plates or pads are combined together to form a capacitor with a spacing of, for example, under 50 nanometers.

[0022] In an example embodiment, each component to be coupled has a surface including at least one conductive area, such as a metal pad or plate (i.e., a capacitor plate). An ultra-thin dielectric layer is formed on at least one surface to be coupled. When the two components are permanently in contact with each other, the ultra-thin dielectric layer remains between the two surfaces, forming a capacitive interface between the conductive areas of each respective component. In one embodiment, the ultra-thin dielectric layer can be composed of a plurality of different dielectric layers, but the combined thickness of such multiple layers is less than or equal to about 50 nanometers. The capacitance per unit area of ​​the capacitive interface formed depends on the specific dielectric constant k of the dielectric material used in the ultra-thin layer, the corresponding thickness of the individual dielectric layers in the ultra-thin layer (if more than one dielectric layer is used), and the total thickness of the combined ultra-thin dielectric layers.

[0023] In one embodiment, electrical and ground connections may be made at the edges of the coupling stack, i.e., around the edges of the capacitive interface. Thus, within the surface area of ​​the capacitive interface between the surfaces, in one embodiment, there may be no or very few conductive connections through the ultra-thin dielectric layer. If conductive connections are used in the area of ​​the surface with the capacitive interface, such conductive connections are placed where there are no nearby metal plates participating in the capacitive interface.

[0024] The example capacitive coupling techniques described herein provide many advantages, such as smaller size wafer-level packages, savings in materials used, and potentially lower voltage requirements due to thinner dielectrics and relatively high dielectric constants per unit area, k. For certain applications, such as mobile devices using small size batteries, significantly lower operating voltages can be achieved.

[0025] Example System

[0026] Figure 1 An example wafer-level package structure 100 is shown, which includes a first integrated circuit die 102 and a second integrated circuit die 104. Each integrated circuit die 102 and 104 has a semiconductor 106 and 108 (e.g., silicon), and an underfill layer 110 and 112, which is composed of an insulating or dielectric (e.g., silicon dioxide) to fix conductive regions 114 and 116 and 118 and 120. Each integrated circuit die 102 and 104 has a corresponding surface 122 and 124, which includes at least one of the conductive regions 114 and 116 and 118 and 120.

[0027] An ultra-thin dielectric layer 126 having a thickness of less than or equal to about 50 nanometers is formed on at least one of the surfaces 122 and 124 of at least one of the integrated circuit dies 102 and 104. The ultra-thin dielectric layer can be a coating, a film, a residue, a membrane, a deposition, etc. The coupling stack 100 forms a capacitive interface 128 that includes the ultra-thin dielectric layer 126 and at least one pair of corresponding conductive regions, such as 114 and 118 or 116 and 120, of the first integrated circuit die 102 and the second integrated circuit die 104 on opposite sides of the ultra-thin dielectric layer 126.

[0028] The thickness of the ultra-thin dielectric layer 126 may be in the range of about 2-50 nanometers. For example, the ultra-thin dielectric layer 126 may be 5-6 nanometers thick. In one embodiment, the thickness of the ultra-thin dielectric layer 126 is less than 2 nanometers.

[0029] In one embodiment, the ultra-thin dielectric layer 126 may be composed of silicon oxide (silicon dioxide SiO2). Alternatively, the ultra-thin dielectric layer 126 may be composed of dielectrics such as silicon monoxide, silicon trioxide, aluminum oxide, hafnium oxide, high-k ion metal oxides, hybrid oxygen plasma grown metal oxides and alkylphosphonic acid self-assembled monolayers (SAMs), polymer films, or ionic metal oxide films.

[0030] For example, the ultra-thin dielectric layer 126 may be an atomic layer deposition of hafnium oxide, which precisely controls the thickness of the ultra-thin dielectric layer 126 to 1-2 nanometers.

[0031] In another embodiment, the ultra-thin dielectric layer 126 may be a layer of a metal oxide and an alkylphosphonic acid self-assembled monolayer (SAM) having a thickness of about 5-6 nanometers and a dielectric constant of about 500-800 nF / cm 2 Capacitance per unit area.

[0032] In one example, the two integrated circuit dies 102 and 104 may be coupled together in the stack by mechanically securing the two integrated circuit dies 102 and 104 together at the edge of the stack 100. In another example, the ultra-thin dielectric layer 126 on at least one of the surfaces 122 and 124 of at least one of the integrated circuit dies 102 and 104 may have an adhesive quality for adhering the integrated circuit dies 102 and 104 to each other.

[0033] The power connections 130 and the electrical ground connections 132 between the two integrated circuit dies 102 and 104 may be located at the edges of the stack 100 .

[0034] Figure 2 An example wafer-level package structure 200 is shown, in which an ultra-thin dielectric layer 206 includes multiple component dielectric layers 202 and 204. In this example, a first component dielectric layer 202 is formed on one of the integrated circuit dies 102, and a second component dielectric layer 204 is formed on another integrated circuit die 104. The multiple component dielectric layers 202 and 204 can be composed of the same dielectric material (e.g., silicon oxide) or different dielectric materials. In this example, each component dielectric layer 202 and 204 has a thickness less than or equal to 25 nanometers. When the two integrated circuit dies 102 and 104 are coupled, the resulting entire ultra-thin dielectric layer 206 has a thickness less than or equal to about 50 nanometers. The capacitive interface 208 formed includes the ultra-thin dielectric layer 206 and the corresponding conductive regions 114 and 116 and 118 and 120 of the first integrated circuit die 102 and the second integrated circuit die 104 on opposite sides of the ultra-thin dielectric layer 206.

[0035] Figure 3An example wafer-level package structure 300 is shown in which an ultra-thin dielectric layer 310 includes a plurality of component dielectric layers 302 and 304 and 306 and 308. In this example, a first set of component dielectric layers 302 and 304 are formed on one of the integrated circuit dies 102, while a second set of component dielectric layers 306 and 308 are formed on the other integrated circuit die 104. For example, each set of ultra-thin dielectric layers 302 and 304 or 306 and 308 has a thickness of less than or equal to about 25 nanometers. Alternatively, when two integrated circuit dies 102 and 104 are coupled, the resulting entire ultra-thin dielectric layer 310 has a thickness of, for example, less than or equal to about 50 nanometers. Symmetry of the thickness of the multiple layers is not required. The formed capacitive interface 312 includes the ultra-thin dielectric layers 302 and 304 , and 306 and 308 , and the respective conductive regions 114 and 116 , and 118 and 120 of the first integrated circuit die 102 and the second integrated circuit die 104 on opposite sides of the ultra-thin dielectric layer 310 .

[0036] When multiple layers of ultra-thin dielectric materials are used for different layers (e.g., 302 and 304 or 306 and 308) of the entire ultra-thin dielectric layer 310, the multiple layers may be composed of different dielectric materials, such as one or more layers of silicon oxide, and one or more layers of high-k dielectrics other than silicon oxide, such as silicon monoxide, silicon trioxide, aluminum oxide, hafnium oxide, high-k ion metal oxides, hybrid oxygen plasma grown metal oxides, and alkylphosphonic acid self-assembled monolayers (SAMs) or polymers.

[0037] When multiple layers of ultra-thin dielectric material are used in different layers (e.g., 302 and 304 or 306 and 308) throughout the ultra-thin dielectric layer 310, the multiple layers may be asymmetric with respect to the parallel center planes of the multiple layers. The asymmetry may include differences in the number, arrangement, thickness, or composition of one or more layers in the multiple layers on either side of the parallel center planes of the multiple layers.

[0038] Figure 4 An example implementation of a wafer level package 400 including a capacitive interface 404 having an ultra-thin dielectric layer 402 is shown. Figure 4 As shown, the respective conductive regions 114 and 116 and 118 and 120 of the first integrated circuit die 102 and the second integrated circuit die 104 do not have to be perfectly aligned on opposite sides of the ultra-thin dielectric layer 402 of the capacitive interface 404. The respective conductive regions 114 and 116 and 118 and 120 of the first integrated circuit die 102 and the second integrated circuit die 104 can be staggered relative to each other, and the staggered alignment can be used to obtain a specific capacitance, for example, between the first conductive region 114 and the second conductive region 118 on opposite sides of the capacitive interface 404.

[0039] Figure 5An example process for manufacturing a coupling capacitor wafer-level package 500 including a capacitive interface 510 is shown. In one embodiment, integrated circuit dies 102 and 102' have a semiconductor 106 (e.g., silicon), and an underfill layer 110 composed of an insulating or dielectric (e.g., silicon dioxide) to secure one or more conductive regions 114 and 116. Each integrated circuit die 102 and 102' has a corresponding surface 122 that includes conductive regions 114 and 116. In the process, surface 122 does not have to be flat at this point.

[0040] A dielectric layer 502, such as silicon oxide or a high-k dielectric layer, is formed on the surface 122, including one or more conductive regions 114 and 116 and the exposed portion of the bottom fill layer 110. In one embodiment, the dielectric layer 502 is ground, etched, lapped, or polished, (or deposited), etc. to a thickness of less than or equal to about 50 nanometers. The thickness to be achieved for a given layer of the dielectric 502 may depend on the number of layers that make up the entire ultra-thin dielectric layer 508 and the value of the desired capacitance per unit area. The dielectric layer 502 is etched or otherwise removed, for example, down to the exposed portion of the bottom fill layer 110 to form a flat surface 122.

[0041] Two instances of the same integrated circuit die 102 and 102' can now be coupled to form a stack 506, each integrated circuit die now having a smooth planar surface 504. The capacitive interface 510 created by the coupling includes an ultra-thin dielectric layer 508 and at least one pair of conductive regions 114 and 118 or 116 and 120 on opposing sides of the ultra-thin dielectric layer 508.

[0042] In one variation, an etch stop layer 512 or a grind-polish stop layer may be applied to the initial surface 122 to protect the underlying structures and to assist in the formation of the ultra-thin dielectric layer 508 at an ultra-fine pitch. Thus, the etch stop 512 or grind-polish stop is deposited on the underlying structures, such as the exposed underfill 110 and the conductive regions 114 and 116, to protect the structures (110 and 114 and 116) below the etch stop layer 512 from damage caused by the etching process. Once the desired thickness of the ultra-thin dielectric layer 508 has been achieved by the etching process, the etch stop layer 512 terminates the etching process.

[0043] The etch stop may be a silicon dioxide etch stop, a boron etch stop, an aluminum oxide etch stop, a polysilicon etch stop, a titanium oxide etch stop, or a silicon nitride etch stop.

[0044] The etching or grinding process may be a dry chemical etching process, a wet etching process, for example using a CF 4 , CHF 3 , CH 2F 2 NF 3 or 2 In one embodiment, the ultra-thin dielectric layer 508 or its component layers are formed by deposition, for example, a dielectric such as hafnium oxide (HfO 2 ) by atomic layer deposition.

[0045] The combination of oxygen plasma grown metal oxide (e.g., aluminum oxide) and high quality alkylphosphonic acid self-assembled monolayer (SAM) can be obtained at a process temperature not exceeding about 100°C and can be formed not only on glass (silicon oxide) substrates but also on commercially available flexible plastic substrates such as polyethylene naphthalate or polyethylene terephthalate. Such an ultra-thin dielectric layer 508 can have a total thickness of about 5-6 nanometers and a resistance of about 500-800 nF / cm 2 Capacitance per unit area.

[0046] In one variation, after obtaining the smooth planar surface 504 by etching the dielectric layer 502, an additional ultra-thin dielectric layer 514, such as composed of silicon oxide or other high-k dielectric layer, may be formed over the smooth planar surface 504. Once the integrated circuit dies 102 and 102' have been coupled into the stack 506 to form the capacitive interface 510, the additional ultra-thin dielectric layer 514 may be used to tune the thickness of the resulting capacitive interface 510, thereby tuning the capacitance of the resulting capacitive interface 510. The additional ultra-thin dielectric layer 514 may also be used to increase the resistance of the capacitive interface 510 to charge and voltage leakage or dielectric breakdown.

[0047] Figure 6 An example directly bonded interface 600 between a first die 602 and a second die 604 is shown, which includes one or more directly bonded conductive interconnects 606 in the same bonding plane 600 with one or more capacitive interconnects 608 formed by the same direct bonding process. The two surfaces directly bonded together to achieve the directly bonded interface 600 with the conductive interconnects 606 and the capacitive interconnects 608 may belong to the two dies 602 and 604 in a die-to-die (D2D) process, may be the die 602 and the die 604 on a wafer in a die-to-wafer (D2W) process, or may be the two dies 602 and 604 on a wafer in a wafer-to-wafer (W2W) process.

[0048] In a microfabrication process for manufacturing a device or package, an example first die 602 and an example second die 604 are directly bonded together at a bonding interface 600. A metal-to-metal direct bond is also formed by a direct bonding process to form a conductive interconnect 606 between the first die 602 and the second die 604, the conductive interconnect 606 being formed at the bonding interface 600. A capacitive interconnect 608 between the first die 602 and the second die 604 is formed at the bonding interface 600 by the same one or more direct bonding processes.

[0049] In an embodiment, the first die 602 and the second die 604 are directly bonded together at the bonding interface 600 via a dielectric-to-dielectric direct bond 610 between respective non-metal surfaces of the first die 602 and the second die 604 .

[0050] The dielectric-to-dielectric direct bond 610 (e.g., oxide-to-oxide direct bond) between the respective non-metal surfaces of the first die 602 and the second die 604 also produces a capacitive coupling 612 of the capacitive interconnect 608. The capacitive coupling 612 of the capacitive interconnect 608 includes a first metal 614 in the first die 602 and a second metal 616 in the second die 604. The first metal 614 and the second metal 616 are separated by a dielectric medium 618.

[0051] Figure 7 An example directly bonded interface 700 between the first die 602 and the second die 604 is shown, including one or more directly bonded conductive interconnects 606 in the same bonding plane 700 as one or more capacitive interconnects 702 formed by the same direct bonding process.

[0052] In one embodiment, the first metal 614 of the capacitive interconnect 702 in the first die 602 is recessed from the bonding interface 700 into the space with the dielectric medium 618 , while the second metal 616 of the capacitive interconnect 702 in the second die 604 is flush with the bonding interface 700 .

[0053] Figure 8 An example directly bonded interface 800 between the first die 602 and the second die 604 is shown, including one or more directly bonded conductive interconnects 606 in the same bonding plane 800 as one or more capacitive interconnects 802 formed by the same direct bonding process.

[0054] In one embodiment, the first metal 614 of the capacitive interconnect 802 in the first die 602 is recessed from the bonding interface 800, while the second metal 616 of the capacitive interconnect 802 in the second die 604 is also recessed in the opposite direction from the same bonding interface 800. One or more dielectric materials 804 and 806 may form a dielectric medium 618 between the metals 614 and 616, which creates a capacitive coupling (or capacitor) of the capacitive interconnect 802. Figure 8 The dielectric materials 804 and 806 shown in FIG. 8 are shown as at least one solid dielectric material, and Figure 6 The dielectric material shown in is shown as a gap (eg, an air-filled gap).

[0055] The dielectric medium 618 of the capacitive interconnect 802 may be made of silicon dioxide, silicon nitride, air, or a high dielectric material (eg, Dielectric®), or a mixture or combination of these and other dielectric materials, gases, and substances useful in semiconductor microfabrication.

[0056] The dielectric medium 618 of the capacitive interconnect 802 may be an asymmetric combination of dielectric materials with respect to the level of the bonding interface 800 between the first die 602 and the second die 604 .

[0057] The separation distance between the first metal 614 in the first die 602 and the second metal 616 in the second die 604 may be selected to provide a particular capacitance value or capacitance range for a given capacitive interconnect 802 or a group of capacitive interconnects 802 .

[0058] In one embodiment, the dielectric medium 618 of the capacitive interconnects 608, 702, and 802 can be at least one ultra-thin layer of a dielectric material. The ultra-thin layer of a dielectric material can be a coating, a film, a residue, a membrane, a deposit, or a gap (e.g., an air space). The thickness and dielectric constant of the ultra-thin layer of dielectric material can determine the capacitance or capacitance effect of the capacitive interconnects 608, 702, and 802. The ultra-thin layer of dielectric material can have a thickness of, for example, less than or equal to about 50 nanometers. The ultra-thin layer of dielectric material can also be made of multiple layers. In one embodiment, the thickness of the combined multiple layers is, for example, less than 25 nanometers. In one embodiment, at least one of the multiple layers of dielectric material can be a polymer. The capacitance of the capacitive interconnects 608, 702, and 802 can be determined by the thickness of one or more polymer layers.

[0059] Fig. 9An example direct bonded interface 900 is shown, which includes conductive interconnects 902 that are directly bonded together at the bonding interface 900, and example capacitive interconnects 904 that are also coupled at the bonding interface 900. For example, the conductive interconnect 902 can be a directly bonded power interconnect or a directly bonded ground interconnect. The capacitive interconnect 904 can be, for example, a signal line between the first tube core 602 and the second tube core 604. The bonding interface itself 900 is also directly bonded together, for example, by a non-metal-to-non-metal direct bond. Connecting the corresponding bonding surfaces of each tube core 602 and 604 into the direct bonded interface 900 creates a capacitive coupling ( Figure 6 612).

[0060] One type of direct bonding is direct hybrid bonding, which includes direct bonding of a (non-metallic) dielectric and direct bonding of a metal conductive interconnect 902 at the same bonding interface 900. The dielectric surfaces of the first die 602 and the second die 604 on either side of the bonding interface 900 are directly bonded together by oxide-oxide direct bonding without using any adhesive.

[0061] For conductive interconnect 902, metal pads on either side of bonding interface 900, such as pads 906 and 908, are directly bonded together via metal-to-metal contact bonding without the use of solder or adhesive. In one embodiment, a "direct bond interconnect" ( Brand) direct hybrid bonding is used for a direct hybrid bonding process, which directly bonds the dielectric surfaces of the two tube cores 602 and 604 together at room temperature and then directly bonds the metal pads 906 and 908 together at a higher annealing temperature (Invensas Incorporated, a subsidiary of Xperi Corporation, San Jose, CA). Direct hybrid bonding can provide 100,000-1,000,000 connections per square mm, with the average pitch of each connection being <1μm-40μm. Even greater connection densities are possible for connections with a pitch less than 1μm.

[0062] In one embodiment, the power and ground interconnects 902 may be redundant instances such that if one or more pads 906 are not bonded or vertically aligned, power or ground connections are still made via other instances of the redundant conductive interconnects 902. The direct bond interconnects 902 may have relatively large metal pads to provide better bonding yields and allow for some horizontal misalignment during an example direct hybrid bonding process while ensuring that sufficient surface area of ​​the metal pads 906 and 908 contact each other across the bonding interface 900 to conduct the required current.

[0063] The capacitive interconnects 904 for the signal lines and data lines are not bonded in a direct hybrid bonding process, but rather form capacitive couplings 612 that constitute the signal transfer interface for each capacitive interconnect 904 between the dies 602 and 604 .

[0064] In one embodiment, signal lines using capacitive interconnects 904 may include redundant circuitry for passing signals through the bonding interface 900. Redundant circuitry may provide better yields during manufacturing and / or high availability during use. Redundant signal lines may also be used to achieve a specific total capacitance of the capacitive coupling of a given signal circuit that spans the connected electrical interface 602.

[0065] Fig.10 An example directly bonded interface 1000 is shown, including a conductive interconnect 1002 directly bonded together at the bonding interface 1000, and an example capacitive interconnect 1004 also coupled at the same bonding interface 1000. One or more conductive vias 1006 and 1008, such as through silicon vias (TSVs) or through dielectric vias (TDVs), are also implemented in the example directly bonded first die 602 and second die 604.

[0066] For example, the conductive vias 1006 or 1008 can be fabricated in a via last process. The example conductive via 1008 can be implemented to fully or at least partially penetrate one die 604. Alternatively, the example via 1006 can be implemented to fully or at least partially penetrate the directly bonded dies 602 and 604. The via last conductive vias 1006 and 1008 can provide advantages for process integration to reduce process impact and thermal budget for back end of line (BEOL) processing. For example, the same back-to-front wafer alignment that enables direct hybrid bonding can provide lithographic alignment for via last patterning to integrate the conductive vias 1006 and 1008.

[0067] Example Method

[0068] Fig.11 An example method 1100 for creating capacitive coupling in a directly bonded interface of a microelectronic device is shown. Fig.11 In the flowchart of FIG. 11 , the operations of the example method 1100 are shown as separate blocks.

[0069] At block 1102 , a first direct bond is created between respective dielectric surfaces of two dies at a bonding interface.

[0070] At block 1104 , a second direct bond is created between corresponding conductive interconnects of the two dies at a bonding interface.

[0071] At block 1106 , capacitive coupling is created at the bonding interface for the capacitive interconnect between the two dies.

[0072] Generally, the example method 1100 includes creating a first (non-metallic) direct bond and a second (metallic) direct bond during the same direct bonding operation, which also forms capacitive coupling in the same operation, all of which occur at the same bonding interface during the same direct bonding operation (e.g., a direct hybrid bonding operation).

[0073] For example, direct bonding between dielectric surfaces at a bonding interface includes oxide-oxide direct bonding. Direct bonding between corresponding conductive interconnects includes metal-metal direct bonding. Capacitive coupling includes at least one dielectric material located at a bonding interface between two corresponding metals of two dies that are coupled by performing the same direct bonding operation of oxide-oxide direct bonding and metal-metal direct bonding.

[0074] In one embodiment, an example method may include creating a bonding surface on a die, the bonding surface including a planar dielectric material for direct hybrid bonding, fabricating a first metal pad of a power interconnect associated with the bonding surface, the first metal pad being suitable for direct hybrid bonding, fabricating a second metal pad of a ground interconnect associated with the bonding surface, the second metal pad being suitable for direct hybrid bonding, fabricating at least one recessed metal pad of a signal line associated with the bonding surface, the recessed pad being used to form a capacitive coupling of the signal line across the bonding surface during direct hybrid bonding, and disposing a dielectric material suitable for forming capacitive coupling in a recessed space between the recessed metal pad of the signal line and the bonding surface. As described above, the at least one dielectric material suitable for forming capacitive coupling may be air, or may be silicon dioxide, silicon nitride, a high dielectric material, and the like.

[0075] In an example direct hybrid bonding process, respective dielectric materials of the first die and the second die are directly bonded together to bond the first die and the second die together and form capacitive coupling of signal lines between respective metal pads of the first die and the second die.

[0076] The first die and the second die are then annealed in an exemplary direct hybrid bonding operation to directly bond corresponding first metal pads to form power interconnects and to directly bond corresponding second metal pads to form ground interconnects.

[0077] Although the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate numerous modifications and variations to the description provided herein. The appended claims are intended to cover such modifications and variations as fall within the true spirit and scope of the present disclosure.

Claims

1. A microelectronic device comprising: The first tube die and the second tube die are directly bonded together at a bonding interface; a conductive interconnect, located between the first die and the second die, formed at the bonding interface by metal-metal direct bonding; as well as A capacitive interconnect, located between the first die and the second die, is formed at the bonding interface. 2 . The microelectronic device of claim 1 , wherein the first die and the second die are directly bonded together at the bonding interface using dielectric-to-dielectric direct bonding between respective non-metallic surfaces of the first die and the second die. 3 . The microelectronic device of claim 2 , wherein the dielectric-to-dielectric direct bonding between the first die and the second die produces a capacitive coupling of the capacitive interconnect.

4. The microelectronic device of claim 1, wherein the capacitive interconnect comprises a first metal in the first die and a second metal in the second die, the first metal and the second metal separated by a dielectric medium.

5. The microelectronic device of claim 4, wherein the first metal of the capacitive interconnect in the first die is recessed from the bonding interface and the second metal of the capacitive interconnect in the second die is flush with the bonding interface.

6. The microelectronic device of claim 4, wherein the first metal of the capacitive interconnect in the first die is recessed from the bonding interface, and the second metal of the capacitive interconnect in the second die is also recessed from the bonding interface.

7. The microelectronic device of claim 4, wherein the dielectric medium of the capacitive interconnect comprises silicon dioxide, silicon nitride, air, or a high dielectric material.

8. The microelectronic device of claim 4, wherein the dielectric medium of the capacitive interconnect comprises a combination of dielectric materials selected from the group consisting of air, silicon dioxide, silicon nitride, and a high dielectric material.

9. The microelectronic device of claim 4, wherein the dielectric medium of the capacitive interconnect comprises an asymmetric combination of dielectric materials relative to a horizontal plane of the bonding interface between the first die and the second die.

10. The microelectronic device of claim 4, wherein a separation distance between the first metal in the first die and the second metal in the second die is selected to provide a capacitance value for the capacitive interconnect.

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