Schottky diode triggered unidirectional scr electrostatic discharge protection device and fabrication method

Abstract

The application discloses a Schottky diode triggered unidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method thereof, and is improved on the basis of the unidirectional silicon controlled rectifier. The Schottky diode is embedded in the NW of the unidirectional silicon controlled rectifier, and a P+ region is embedded in the PW, and the Schottky diode and the embedded P+ region are connected through a metal wire. The application embeds a reverse Schottky diode trigger structure on the basis of the conventional unidirectional silicon controlled rectifier electrostatic protection device, and can effectively reduce the trigger voltage of the SCR. The introduced Schottky diode also increases the anode-cathode spacing of the unidirectional silicon controlled rectifier, and can effectively improve the maintaining voltage of the SCR and the heat dissipation capacity of the device. The silicon rectifier electrostatic release device has the characteristics of high maintaining voltage, high failure current and low trigger voltage, and can effectively avoid the latch effect while realizing high protection level.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electrostatic protection, in particular to a low trigger voltage, high failure current Schottky diode triggered unidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method thereof. BACKGROUND

[0002] With the progress of semiconductor process technology, ESD causes integrated circuit chips and electronic products to fail more and more seriously. ESD protection for electronic products and integrated circuit chips has become one of the main problems faced by product engineers.

[0003] The failure modes caused by ESD are hard failure, soft failure, and potential failure. The causes of these failures can be divided into electrical failure and thermal failure. Thermal failure refers to the generation of several amperes to several tens of amperes of current in a local part of the chip when an ESD pulse occurs, which lasts for a short time but generates a large amount of heat, causing the local metal wiring to melt or causing the chip to generate a hot spot, thereby causing secondary breakdown. Electrical failure refers to the electric field strength formed by the voltage applied to the gate oxide layer being greater than the dielectric strength, causing surface breakdown or dielectric breakdown. Due to the increasing threat of ESD to chips, the physical mechanism research has been increasingly valued.

[0004] The cross-sectional view of the traditional unidirectional silicon controlled rectifier electrostatic protection device is shown in Figure 1 , and the equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of the unidirectional SCR, the first N well and the first P well form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current is generated inside the device, the current flows through the first P well, and flows to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the first P well is equivalent to the base voltage drop of the NPN transistor, and when this voltage is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After the transistor is turned on, the base current is provided for the horizontal PNP transistor, and the horizontal PNP transistor is also turned on, which further provides base current for the vertical NPN transistor, forming a positive feedback mechanism, so that the SCR path is completely opened. Therefore, even if there is no avalanche current after that, due to the conduction of the transistor, a large current can also be discharged. SUMMARY

[0005] To solve the above technical problems, the present application provides a Schottky diode triggered unidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method thereof, and is applied to the ESD protection network design of 0-5.5V working voltage.

[0006] The technical solution of the present application to solve the above problems is:

[0007] In a first aspect, the embodiments of the present application provide a Schottky diode triggered unidirectional silicon controlled rectifier electrostatic discharge protection device, comprising a P-type substrate; a first N-well and a first P-well are arranged above the substrate; the first N-well and the first P-well are sequentially arranged from left to right on the P-type substrate; a first N+ implantation, a first P+ implantation, a second P+ implantation, a first metal and a third P+ implantation are sequentially arranged from left to right on the first N-well; a fourth P+ implantation, a second N+ implantation and a fifth P+ implantation are sequentially arranged from left to right in the first P-well;

[0008] The first N+ implantation and the first P+ implantation in the first N-well are connected together and serve as an anode of the device; the second P+ implantation and the third P+ implantation in the first N-well are in a floating state without electrodes; the second N+ implantation and the fifth P+ implantation in the first P-well are connected together and serve as a cathode of the device; the first metal in the first N-well and the fourth P+ implantation in the first P-well are connected together by a metal wire without being connected to a potential.

[0009] Preferably, there are five field oxide isolation regions; a first field oxide isolation region is between the first N+ implantation and the first P+ implantation, a second field oxide isolation region is between the first P+ implantation and the second P+ implantation, a third field oxide is between the third P+ implantation and the fourth P+ implantation, a fourth field oxide is between the fourth P+ implantation and the second N+ implantation, and a fifth field oxide is between the second N+ implantation and the fifth P+ implantation.

[0010] Preferably, the first field oxide isolation region and the second field oxide isolation region are located on the surface of the first N-well; the third field oxide isolation region is located between the first N-well and the first P-well; the fourth field oxide isolation region and the fifth field oxide isolation region are located on the surface of the first P-well.

[0011] Preferably, when an ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the breakdown surface is between the first N-well and the first metal; at this time, the first N-well and the first metal form a Schottky diode D1, and the first N+ implantation, the first N-well, the first metal, the fourth P+ implantation, the first P-well and the fifth P+ implantation form a trigger current path one of the device, and the trigger current path one provides a trigger current after the D1 occurs avalanche breakdown conduction.

[0012] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well and the first P-well constitute a parasitic transistor PNP, and the first N-well, the first P-well and the second N+ injection constitute a parasitic transistor NPN. After D1 undergoes avalanche breakdown, a trigger current is formed to flow through R2 in the first P-well. When the voltage drop through the resistor R2 is greater than 0.7V, the PN junction formed by the first P-well and the second N+ injection is turned on, and then the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect, and the device is successfully triggered.

[0013] Preferably, the base width S1 of the parasitic transistor PNP is adjustable, and when S1 increases, the holding voltage increases.

[0014] In a second aspect, an embodiment of the present invention provides a method for manufacturing a Schottky diode-triggered unidirectional thyristor electrostatic protection device, comprising the following steps:

[0015] Step 1: Generating a first N-well and a first P-well in a P-type substrate;

[0016] Step 2: Generate a first N+ implant, a first P+ implant, a second P+ implant, a first metal, and a third P+ implant on the first N-well from left to right; generate a fourth P+ implant, a second N+ implant, and a fifth P+ implant on the first P-well from left to right;

[0017] Step 3: forming a first field oxygen isolation region between the first N+ implant and the first P+ implant on the first N-well, generating a second field oxygen between the first P+ implant and the second P+ implant on the first N-well, connecting a third field oxygen across the first N-well and the first P-well, generating a fourth field oxygen between the fourth P+ implant and the second N+ implant on the first P-well, and generating a fifth field oxygen between the second N+ implant and the fifth P+ implant on the first P-well;

[0018] Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;

[0019] Step 7: Connect the first N+ injection and the first P+ injection together and use them as the anode of the device, connect the N well between the second P+ injection and the third P+ injection and the fourth P+ injection together without connecting any potential, and connect the second N+ injection and the fifth P+ injection together and use them as the cathode of the device.

[0020] Preferably, before forming the N-well and the P-well on the P-type substrate, the method further includes:

[0021] A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and the photoresist layer is exposed and developed with a mask to form an isolation shallow trench; the silicon dioxide, silicon nitride and isolation shallow trench are etched, the photoresist layer is removed, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is removed.

[0022] The application has the advantages that:

[0023] 1. The application adjusts the breakdown surface, and based on the traditional unidirectional silicon-controlled static protection device, the breakdown surface is changed from the well breakdown between the first N well and the first P well to the Schottky junction breakdown between the first N well and the first metal by introducing the Schottky diode, so that the trigger voltage of the device is effectively reduced, and the device is easier to open.

[0024] 2. In order to better play the performance of the unidirectional silicon-controlled, the first N well is embedded with the Schottky junction, and the first P well is embedded with the second N+ injection, so that the base width of the parasitic transistors PNP and NPN is increased, the positive feedback effect of the SCR path is weakened, the latch-up effect is inhibited, and thus the holding voltage of the device is improved.

[0025] 3. The width S1 of the second P+ injection in the application is adjustable, when S1 is increased, the base width of the parasitic transistors NPN and PNP is widened, so that the emitter injection effect of the parasitic transistor is weakened, the positive feedback effect of the SCR path is inhibited, and the holding voltage is increased. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a sectional view of a traditional unidirectional SCR static protection device.

[0027] Figure 2 It is an equivalent circuit diagram of a traditional unidirectional SCR static protection device.

[0028] Figure 3 It is a sectional view of an embodiment of the application.

[0029] Figure 4 It is an equivalent circuit diagram of an embodiment of the application.

[0030] Figure 5 It is a total current density distribution simulation diagram of a Schottky diode triggered unidirectional silicon-controlled static protection device provided by an embodiment of the application. DETAILED DESCRIPTION

[0031] The application applied to the ESD protection design of an analog switch chip is further described below in combination with the drawings and embodiments.

[0032] As Figure 3As shown, a Schottky diode triggered unidirectional SCR ESD protection device includes a P-type substrate 101; the substrate is provided with an N well 201 and a P well 202; the N well 201 is provided with a first N+ implantation 301, a first P+ implantation 302, a second P+ implantation 303, and a third P+ implantation 304 from left to right in sequence above the N well; a fourth P+ implantation 305, a second N+ implantation 306, and a fifth P+ implantation 307 are sequentially arranged from left to right above the first P well; the two electrodes of the first N+ implantation 301 and the first P+ implantation 302 in the first N well 201 are connected together and serve as the anode of the device; the two electrodes of the second N+ implantation 306 and the fifth P+ implantation 307 in the first P well 202 are connected together and serve as the cathode of the device; the N well between the second N+ implantation 303 and the third P+ implantation 304 in the first N well 202 and the fourth P+ implantation 305 in the first P well 202 are connected together by a metal wire and are not connected to a potential. In this way, the first N well 201 and the first metal 501 are Schottky contact and form a Schottky diode D1, so that when a positive ESD pulse is applied to the anode of the device, the breakdown surface changes from the original first N well 201 / first P well 202 to the first N well 201 / first metal 501, which will lower the trigger voltage of the device and increase the holding voltage of the device

[0033] In an embodiment, the Schottky diode triggered unidirectional SCR ESD protection device has five field oxide isolation regions; there are five field oxide isolation regions; a first field oxide isolation region 401 is between the first N+ implantation 301 and the first P+ implantation 302, a second field oxide isolation region 402 is between the first P+ implantation 302 and the second P+ implantation 303, a third field oxide 403 is between the third P+ implantation 304 and the fourth P+ implantation 305, a fourth field oxide 404 is between the fourth P+ implantation 305 and the second N+ implantation 306, and a fifth field oxide 405 is between the second N+ implantation 306 and the fifth P+ implantation 307.

[0034] In an embodiment, the first field oxide isolation region 401 and the second field oxide isolation region 402 are located on the surface of the first N well 201; the third field oxide isolation region 403 is between the first N well 201 and the first P well 202; the fourth field oxide isolation region 404 and the fifth field oxide isolation region 405 are located on the surface of the first P well 202.

[0035] In an embodiment, as Figures 4 to 5As shown, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the breakdown surface is between the first N well 201 and the first metal 501; at this time, the first N well 201 and the first metal 501 form a Schottky diode D1, and the first N+ implantation 301, the first N well 201, the first metal 501, the fourth P+ implantation 305, the first P well 202 and the fifth P+ implantation 307 form a trigger current path one of the device, and after D1 is turned on by avalanche breakdown, the trigger current path one provides a trigger current.

[0036] When an ESD pulse reaches the anode of the device and the cathode of the device is connected to a ground potential, the first P+ implantation 302, the first N well 201 and the first P well 202 form a parasitic transistor PNP, and the first N well 201, the first P well 202 and the second N+ implantation 306 form a parasitic transistor NPN, and after D1 is turned on by avalanche breakdown, a trigger current flows through R2 in the first P well 202, and when the voltage drop across R2 is greater than 0.7V, the PN junction formed by the first P well 202 and the second N+ implantation 306 is turned on, and then the right parasitic transistor NPN is turned on and provides a base current to the left parasitic transistor PNP, thereby promoting the conduction of the left parasitic transistor PNP, and when the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect, and at this time the device is successfully triggered.

[0037] The base width S1 of the parasitic transistor PNP can be adjusted according to the requirements of the ESD design window in different application scenarios, and when S1 increases, the base width of the parasitic transistor PNP increases, thereby reducing the current gain coefficient β and thereby increasing the holding voltage.

[0038] The embodiment of the present application also provides a manufacturing method of a Schottky diode triggered unidirectional silicon controlled static protection device, comprising the following steps:

[0039] Step one: generating a first N well 201 and a first P well 202 in a P-type substrate 101;

[0040] Step two: generating a first N+ implantation 301, a first P+ implantation 302, a second P+ implantation 303, a first metal 501 and a third P+ implantation 304 on the first N well 201 from left to right; and generating a fourth P+ implantation 305, a second N+ implantation 306 and a fifth P+ implantation 307 on the first P well 202 from left to right;

[0041] Step three: form a first field oxide isolation region 401 between the first N+ implant 301 and the first P+ implant 302 on the first N-well 201, form a second field oxide 402 between the first P+ implant 302 and the second P+ implant 303 on the first N-well 201, form a third field oxide 403 across the first N-well 201 and the first P-well 202, form a fourth field oxide 404 between the fourth P+ implant 305 and the second N+ implant 306 on the first P-well 202, and form a fifth field oxide 405 between the second N+ implant 306 and the fifth P+ implant 307 on the first P-well 202;

[0042] Step six: anneal all the implant regions to eliminate the migration of impurities in the implant regions;

[0043] Step seven: connect the first N+ implant 301 and the first P+ implant 302 together and use them as the anode of the device, connect the N-well between the second P+ implant 303 and the third P+ implant 304 and the fourth P+ implant 305 together without applying a potential, and connect the second N+ implant 306 and the fifth P+ implant 307 together and use them as the cathode of the device.

[0044] The manufacturing method of the Schottky diode triggered unidirectional silicon controlled static protection device has a simple process and is easy to operate. In order to better play the performance of the unidirectional silicon controlled, the device is based on the traditional unidirectional silicon controlled static protection device, and the Schottky diode is introduced to change the breakdown surface from the well breakdown between the first N-well and the first P-well to the Schottky junction breakdown formed by the first N-well and the first metal, so as to effectively reduce the trigger voltage of the device and make the device easier to open. The first N-well is embedded with a Schottky junction, and the first P-well is embedded with a second N+ implant, so as to increase the base width of the parasitic transistors PNP and NPN, weaken the positive feedback effect of the SCR path, and thus inhibit the latch-up effect, thereby improving the holding voltage of the device and effectively improving the protection performance of the device. The device can be used in the ESD protection design of 0-5.5V I / O ports. The example device of the application adopts a 0.18μm CMOS process.

[0045] The preferred embodiments of the application have been described above with the preferred embodiments; however, they are not intended to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A Schottky diode-triggered unidirectional thyristor electrostatic protection device, characterized in that: include: A P-type substrate, with a first N-well and a first P-well provided above the P-type substrate; The P-type substrate is provided with a first N-well and a first P-well from left to right in sequence; the first N-well is provided with a first N+ injection, a first P+ injection, a second P+ injection, a first metal and a third P+ injection in sequence from left to right; The first P well is provided with a fourth P+ injection, a second N+ injection and a fifth P+ injection from left to right; The first N+ injection electrode and the first P+ injection electrode in the first N well are connected together and serve as the anode of the device; The second P+ injection and the third P+ injection in the first N well have no electrodes and are in a floating state; The second N+ injection and the fifth P+ injection electrodes in the first P well are connected together and serve as the cathode of the device; The first metal in the first N-well and the fourth P+ injection of the first P-well are connected together through a metal wire and are not connected to a potential.

2. The Schottky diode-triggered unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: Also includes: five field oxygen isolation zones; The first field oxygen isolation region is between the first N+ injection and the first P+ injection region, the second field oxygen isolation region is between the first P+ injection and the second P+ injection, the third field oxygen is between the third P+ injection and the fourth P+ injection, the fourth field oxygen is between the fourth P+ injection and the second N+ injection, and the fifth field oxygen is between the second N+ injection and the fifth P+ injection.

3. The Schottky diode-triggered unidirectional thyristor electrostatic protection device according to claim 2, characterized in that: The first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region is between the first N-well and the first P-well; the fourth field oxygen isolation region and the fifth field oxygen isolation region are located on the surface of the first P-well.

4. The Schottky diode-triggered unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N-well and the first metal; at this time, the first N-well and the first metal form a Schottky diode D1, and the first N+ injection, the first N-well, the first metal, the fourth P+ injection, the first P-well, and the fifth P+ injection constitute the trigger current path 1 of the device. When D1 undergoes avalanche breakdown and turns on, trigger current path 1 will provide trigger current.

5. The Schottky diode-triggered unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well and the first P-well form a parasitic transistor PNP, and the first N-well, the first P-well and the second N+ injection form a parasitic transistor NPN. After D1 undergoes avalanche breakdown, a trigger current is generated and flows through R2 in the first P-well. When the voltage drop across the resistor R2 is greater than 0.7V, the PN junction formed by the first P-well and the second N+ injection is turned on, and then the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect, and the device is successfully triggered.

6. The Schottky diode-triggered unidirectional thyristor electrostatic protection device according to claim 5, characterized in that: The base width S1 of the parasitic transistor PNP is adjustable. When S1 increases, the holding voltage increases.

7. A method for manufacturing a Schottky diode-triggered unidirectional thyristor electrostatic protection device, comprising the following steps: Step 1: Generating a first N-well and a first P-well in a P-type substrate; Step 2: Generate a first N+ implant, a first P+ implant, a second P+ implant, a first metal and a third P+ implant on the first N well from left to right; Generating a fourth P+ implant, a second N+ implant, and a fifth P+ implant sequentially from left to right on the first P well; Step 3: forming a first field oxygen isolation region between the first N+ implant and the first P+ implant on the first N-well, generating a second field oxygen between the first P+ implant and the second P+ implant on the first N-well, connecting a third field oxygen across the first N-well and the first P-well, generating a fourth field oxygen between the fourth P+ implant and the second N+ implant on the first P-well, and generating a fifth field oxygen between the second N+ implant and the fifth P+ implant on the first P-well; Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas; Step 7: Connect the first N+ injection and the first P+ injection together and use them as the anode of the device, connect the N well between the second P+ injection and the third P+ injection and the fourth P+ injection together without connecting any potential, and connect the second N+ injection and the fifth P+ injection together and use them as the cathode of the device.

8. The method for manufacturing the Schottky diode-triggered unidirectional thyristor electrostatic protection device according to claim 7, characterized in that: The process includes the following steps before step 1: growing a silicon dioxide film on a P-type substrate, and then depositing a silicon nitride layer; spin-coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and isolation shallow groove to remove the photoresist layer, depositing a silicon dioxide layer, and then chemically polishing until the silicon nitride layer is formed to remove the silicon nitride layer.

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