Interlaced via architecture across unit cells

Abstract

Techniques for designing and forming cells with transistor devices are described. In one example, an integrated circuit structure includes a plurality of cells, with adjacent cells having a decreasing distance between them along their height and an interleaved via arrangement. Accordingly, the first cell may be adjacent to the second cell along the shared cell boundary. A first via is provided between the first gate structure of the first cell adjacent to the cell boundary and the first metal layer over the first gate structure, and a second via is provided between the second gate structure of the second cell adjacent to the cell boundary and the second metal layer over the second gate structure. No portion of the first via is aligned with any portion of the second via along the first direction.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits, and more particularly, to designing and forming cells including transistor devices for integrated circuits. Background Art

[0002] In designing and forming integrated circuit structures, standard unit cell libraries are developed with a given number of transistors per unit cell. Multiple signal tracks may also be used in the interconnect layers around the transistors to make connections to the various transistor elements. As devices and unit cells become smaller, it becomes increasingly challenging to design signal tracks to properly route the various signals. Therefore, there remain many important challenges in designing the layout of the various cells of an integrated circuit structure to improve PPA (power, performance, and area) performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a plan view of an integrated circuit structure including a plurality of unit cells having aligned via arrangements resulting in wasted or dead space.

[0004] Figure 2 is a plan view of an integrated circuit structure including a plurality of unit cells having a staggered via arrangement according to an embodiment of the present disclosure.

[0005] Figures 3A-3G is a plan view illustrating various stages in an example process for forming a unit cell having a staggered via arrangement according to some embodiments of the present disclosure.

[0006] Figure 4 A cross-sectional view of a chip package including one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0007] Figure 5 A diagram depicting the design and formation of an embodiment according to the present disclosure is shown. Figure 2 A flow chart of a method for constructing an integrated circuit.

[0008] Figure 6 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0009] It should be understood that the drawings are not necessarily drawn to scale and are not intended to limit the present disclosure to the specific configurations shown. For example, while some of the drawings generally indicate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topology or be otherwise not smooth, given the real-world limitations of the processing equipment and techniques used. Similarly, while the thickness of a given first layer may appear similar to the thickness of a second layer, in reality the first layer may be much thinner or thicker than the second layer; the same is true for other layers or feature sizes. DETAILED DESCRIPTION

[0010] Techniques for designing and forming cells including transistor devices for integrated circuits are described. In one example, the integrated circuit structure includes a plurality of cells, wherein adjacent cells have a distance between them that decreases along their height and a staggered via arrangement. In one example, a first cell may be adjacent to a second cell along a shared cell boundary. In addition, a first via is provided between a first gate structure of a first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of a second cell adjacent to the cell boundary and a second metal layer above the second gate structure. The first gate structure and the second gate structure both extend along a first direction, and the first metal layer and the second metal layer both extend along a second direction different from the first direction. No portion of the first via is aligned with any portion of the second via along the first direction. Many configurations and variations will be apparent from the present disclosure.

[0011] Overview As described above in this article, there are still many important challenges for designing the layout of various cells of the integrated circuit structure. For example, there are only a limited number of signal tracks available for making connections to the various transistor elements of a given cell. This number is based on the unit cell size and lithography limit constraints. As a result, it becomes challenging to achieve smaller unit cells because signal tracks and vias end up being too close together, resulting in parasitic effects that may degrade device performance. Dead space and / or dummy structures can be added to cell boundaries to reduce these effects. However, these techniques can result in wasted area and lower PPA (power, performance, and area) of the integrated circuit structure.

[0012] Therefore, the present invention describes a technique for forming an integrated circuit structure with adjacent cells using a staggered via arrangement that allows for reduced dead space and / or virtual structures between cells. Typically, vias for contacting similar features of adjacent cells are aligned along a given basic direction (e.g., along the height of the cell). However, according to some embodiments, vias for corresponding structures of adjacent cells are purposefully staggered so that no portion of a via overlaps any portion of another via along the height direction of the cell. Since the vias are further separated from each other, more dead space between two cells at the cell boundary can be removed, and the effective size of the cell can be reduced. The term "via" as used herein may also be used to refer to a structure sometimes referred to as a "contact" that extends between a transistor element and a first metal layer of an interconnect structure.

[0013] In some examples, the first cell may be adjacent to the second cell along a first direction with a cell boundary between the two cells. Note that the cell boundary does not refer to a specific structure, but rather identifies a boundary between repeated transistor arrangements. The first cell and the second cell may include the same arrangement of transistor structures, including the same arrangement of contacts between the gate structure and the diffusion region (e.g., source or drain region). The gate structures of the two cells may extend longitudinally along the first direction (e.g., along the height of the cell). In addition, both the first cell and the second cell may include the same arrangement of signal tracks above the respective cells (e.g., four signal tracks above each cell). Each signal track may extend longitudinally along a second direction different from the first direction (e.g., perpendicular to the first direction).

[0014] According to some embodiments, a first signal track above a first cell is adjacent to a second signal track above a second cell and is located on either side of a cell boundary between the two cells. A first through hole extends between the first signal track and a first gate structure of the first cell, and a second through hole extends between the second signal track and a second gate structure of the second cell. Due to the staggered arrangement, no portion of the first through hole overlaps any portion of the second through hole along the first direction. Other through holes coupled to the first and second signal tracks may be similarly misaligned. For example, a third through hole between a first signal track and a third signal track extending in a first direction is not aligned with any portion of a fourth through hole between a second signal track and a fourth signal track extending in a first direction. By separating the through holes in this manner, the distance between the center of the first through hole and the center of the second through hole along the first direction can be reduced to less than 40nm. In some embodiments, the distance between the centers of the first through hole and the second through hole is between about 16nm and about 36nm. In some examples, the distance between the center of the first through hole and the center of the second through hole along the second direction is between about 34nm and about 50nm. Other embodiments may have different geometries.

[0015] According to some embodiments, an integrated circuit structure includes a first unit having two or more first transistor devices, wherein the two or more first transistor devices include a first gate structure extending in a first direction within the first unit and a second unit adjacent to the first unit in the first direction. The second unit has two or more second transistor devices, wherein the two or more second transistor devices include a second gate structure extending in the first direction within the second unit. The integrated circuit structure also includes a first metal layer extending in a second direction different from the first direction and above the first gate structure, a second metal layer extending in the second direction and above the second gate structure, a first through hole extending in a third direction between the first metal layer and the first gate structure below, and a second through hole extending in the third direction between the second metal layer and the second gate structure below. No portion of the second through hole overlaps any portion of the first through hole along the first direction.

[0016] According to some embodiments, an integrated circuit design system includes at least one processor, a non-transitory storage medium storing instructions, and when executed by the at least one processor, the instructions cause the system to perform a method. The method includes accessing a cell library having unit cells, wherein each unit cell has corresponding two or more transistor devices, receiving data about a circuit to be implemented using the unit cells, designing an array of rows and columns containing unit cells to implement the circuit, and designing a plurality of interconnect structures to implement the circuit. The column of unit cells includes a first unit cell and a second unit cell directly adjacent to the first unit cell. The first unit cell includes a first gate structure extending along a first direction within the first unit cell, and the second unit cell includes a second gate structure extending along the first direction within the second unit cell. The plurality of interconnect structures include a first metal layer extending along a second direction different from the first direction and above the first gate structure, a second metal layer extending along the second direction and above the second gate structure, a first through hole extending in a third direction between the first metal layer and the first gate structure below, and a second through hole extending in the third direction between the second metal layer and the second gate structure below. No portion of the second through hole overlaps any portion of the first through hole along the first direction.

[0017] According to some embodiments, an integrated circuit structure includes a first transistor device, a second transistor device, a first through hole, and a second through hole. The first transistor device includes a first source region, a first drain region, a first body including a semiconductor material extending from the first source region to the first drain region in a first direction, and a first gate structure extending above the first body in a second direction different from the first direction. The second transistor device is spaced apart from the first transistor device along the first direction and along the second direction. The second transistor device includes a second source region, a second drain region, a second body including a semiconductor material extending from the second source region to the second drain region in the first direction, and a second gate structure extending above the second body in the second direction. The first through hole is coupled to the first gate structure and extends in a third direction above the first gate structure. The second through hole is coupled to the second gate structure and extends in a third direction above the second gate structure. A distance between a center of the first through hole and a center of the second through hole along the second direction is less than 40 nm.

[0018] According to some embodiments, an integrated circuit structure includes a first unit having two or more first transistor devices, the two or more first transistor devices including a first gate structure extending in a first direction within the first unit and a first contact on a first source region or a drain region adjacent to the first gate structure, and a second unit adjacent to the first unit in the first direction. The second unit has two or more second transistor devices, wherein the two or more second transistor devices include a second gate structure extending in the first direction within the second unit and a second contact on a second source region or a drain region adjacent to the second gate structure. The integrated circuit structure also includes a first metal layer extending in a second direction different from the first direction and above the first contact, a second metal layer extending in the second direction and above the second contact, a first through hole extending in a third direction between the first metal layer and the first contact below, and a second through hole extending in the third direction between the second metal layer and the second contact below. No portion of the second through hole overlaps any portion of the first through hole along the first direction.

[0019] As used herein, "Group IV semiconductor materials" (or "Group IV materials" or generally "IV") include at least one Group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), etc. "Group III-V semiconductor materials" (or "Group III-V materials" or generally "III-V") as used herein include at least one Group III element (e.g., aluminum, gallium, indium) and at least one Group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), gallium nitride (GaN), etc. Note that, for example, Group III may also be referred to as the boron group or IUPAC Group 13, Group IV may also be referred to as the carbon group or IUPAC Group 14, and Group V may also be referred to as the nitrogen group or IUPAC Group 15.

[0020] As used herein, "compositionally different" or "compositionally distinct" materials refer to two materials having different chemical compositions. This compositional difference can be, for example, due to an element in one material that is not in the other (e.g., SiGe is compositionally different from silicon), or by one material having all of the same elements as a second material, but at least one of these elements is intentionally provided in a different concentration in one material relative to the other material (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this diversity in chemical composition, the materials can also have different dopants (e.g., gallium and magnesium) or the same dopants but in different concentrations. In other embodiments, compositionally distinct materials can also refer to two materials having different crystal orientations. For example, (110) silicon is compositionally distinct from or different from (100) silicon. Stacks that produce different orientations can be achieved, for example, by blanket wafer layer transfer. If the two materials are elementally different, then one of the materials has an element that is not present in the other material.

[0021] It should be readily understood that the meaning of "above" and "above" in this disclosure should be interpreted in the broadest manner, such that "above" and "above" not only mean "directly on" something, but also include the meaning of being above something with intervening features or layers therebetween. As used herein, the term "back side" generally refers to the area below one or more semiconductor devices (below the device layers) within a device substrate or in a device substrate region (where the bulk of the device substrate has been removed). Note that if a given structure is flipped, the back side may become the front side, and vice versa. For this reason, and as will be appreciated, the use of terms such as "above," "below," "below," "up," "down," "top," and "bottom" are used for ease of discussion and are not intended to imply a rigid structure or fixed orientation; rather, such terms merely indicate the spatial relationship of a structure when it is in a given orientation.

[0022] As used herein, the term "layer" refers to a material portion including a region having a thickness. A monolayer is a layer composed of a single layer of atoms of a given material. A layer may extend over the entire underlying or superstructure, or may have a range less than the range of the underlying or superstructure. In addition, a layer may be a region of a homogeneous or non-homogeneous continuous structure, wherein the layer has a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereat. A layer may extend horizontally, vertically and / or along a conical surface. A layer may be conformal to a given surface (whether flat or curved) and have a relatively uniform thickness across the entire layer. The phrase "substantially" is used herein, and for the purposes of this disclosure, "A" being substantially equal to "B" means that A and B differ by at most 1 nm or 2 nm (e.g., A is within 1 or 2 nm of B).

[0023] The use of the techniques and structures provided herein can be detected using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name just a few suitable example analysis tools. For example, in some embodiments, such a tool can be used to detect an integrated circuit structure including adjacent cells, wherein the adjacent cells have vias along the cell boundaries between the adjacent cells, and the vias do not overlap along the direction of the cell height. For example, in some examples, at the block level, adjacent cells will not have aligned diffusion (source or drain) contact vias, gate contact vias, and metal M0 contact vias across the top or bottom cell boundaries. In some examples, the first vertical metal wiring track M1 will come out of the cell from which it originates and enter a neighboring cell along the height direction of the cell. Many configurations and variations will be apparent in light of this disclosure.

[0024] Architecture Figure 1 1 is a plan view of an integrated circuit structure 100 including a plurality of cells 102, wherein each cell 102 has a substantially similar height in the Y direction and a width in the X direction. The cells are arranged adjacent to each other in an array of rows and columns, with cell boundaries identified by dashed lines. Each cell contains the same arrangement of transistor structures. For clarity, only some of these structures are shown for the top two rows of cells. Thus, each cell includes at least two transistor devices. For example, a given cell has two or more parallel gate structures 104 extending longitudinally along the cell height (e.g., along the Y direction), and a signal track 106 extending longitudinally along the cell width (e.g., along the X direction).

[0025] A via is formed between the signal track 106 and the gate structure 104 to route signals to and from the transistor gate. A first via 108a from a first cell is formed between the corresponding signal track 106 and the gate structure 104 of the first cell, and a second via 108b from a second cell is formed between the corresponding signal track 106 and the gate structure 104 of the second cell. Because the first via 108a and the second via 108b are aligned with each other along the Y direction, they must be separated by a certain amount of space along the Y direction to minimize the parasitic capacitance between them. However, this then creates dead space between cells along the Y direction and on either side of the cell boundary between adjacent cells along the Y direction. Other vias and / or metal layers may also cause similar problems. For example, a first metal layer 110a from a higher interconnect level above the first cell can be coupled to a given signal line 106 through a third via 112a of the first cell, while a second metal layer 110b from a higher interconnect level above the second cell can be coupled to a given signal line 106 through a fourth via 112b of the second cell. Similarly, the proximity between the third and fourth vias 112a and 112b and between the first and second metal layers 110a and 110b along the Y direction necessitates a minimum spacing between cells along the Y direction. This dead space between cells accumulates across the cell array and reduces the total number of cells and transistor devices that can be implemented on a given die.

[0026] Figure 2 2 is a plan view of an integrated circuit structure 200 according to an embodiment of the present disclosure, the integrated circuit structure 200 includes two adjacent cells with a reduced dead space therebetween. As described above, each cell includes a similar transistor structure. Typically, the transistor structure may be mirrored or otherwise substantially identical between adjacent cells. Therefore, the first cell 202a includes a first gate structure 204a and a second gate structure 204b extending longitudinally along a first direction (e.g., along the Y direction), and the second cell 202b includes a third gate structure 205a and a fourth gate structure 205b extending longitudinally along the first direction (e.g., along the Y direction). Each cell may also include various diffusion contacts contacting the source or drain region of the transistor, such as a first diffusion contact 206a, a second diffusion contact 206b, and a third diffusion contact 206c of the first cell 202a, and a fourth diffusion contact 207a and a fifth diffusion contact 207b of the second cell 202b (the sixth diffusion contact of the second cell 202b may also be present below the metal layer 218). The diffusion contact may also extend longitudinally along the first direction between adjacent gate structures.

[0027] According to some embodiments, the first unit 202a and the second unit 202b each include a plurality of metal layers, which act as signal lines extending above the transistor structure to route signals to or from the transistor structure. For example, the first unit 202a includes four metal layers 208a-208d extending along a second direction different from the first direction (e.g., along the X-axis orthogonal to the first direction), and the second unit 202b includes four metal layers 210a-210d extending along the second direction. In this example arrangement, none of the metal layers 208 / 210 extends on or above the cell boundary extending along the second direction. In some examples, only three metal layers are arranged above the first unit 202a, and three metal layers are arranged above the second unit 202b. The metal layers 208a-208d and 210a-210d can be equally spaced from each other in the first direction.

[0028] According to some embodiments, the first via 212 extends in a third direction (e.g., along the Z direction into and out of the page) between the first gate structure 204a and the first metal layer 208a of the first cell 202a. The first metal layer 208a may extend along the second direction adjacent to the cell boundary between the first cell 202a and the second cell 202b. According to some embodiments, the second via 214 extends in the third direction between the third gate structure 205a and the second metal layer 210a of the second cell 202b. The second metal layer 210a may extend along the second direction adjacent to the cell boundary between the first cell 202a and the second cell 202b. According to some embodiments, the first via 212 and the second via 214 are staggered across the cell boundary such that no portion of the first via 212 overlaps any portion of the second via 214 along the first direction. In some embodiments, the distance d1 between the center of the first via 212 and the center of the second via 214 along the second direction is between about 34nm and about 50nm. The distance may be determined by the process technology used and the width of the gate structure.

[0029] According to some embodiments, staggering the first through hole 212 and the second through hole 214 allows the dead space between the first unit 202 and the second unit 202b to be removed, which results in a reduction in the height of each unit. For example, the distance d2 between the center of the first through hole 212 and the center of the second through hole 214 along the first direction can be less than about 40nm, less than 30nm, or less than 20nm. In some examples, d2 is between about 16nm and about 36nm.

[0030] Other vias may be similarly staggered across the cell boundaries between adjacent first and second cells 202a, 202b. According to some embodiments, the first upper metal layer 216 may extend longitudinally along the first direction and over the metal layers 208a-208d of the first cell 202a, and the second upper metal layer 218 may extend longitudinally along the first direction over the metal layers 210a-210d of the second cell 202b. The third via 220 may extend in a third direction between the first upper metal layer 216 and the first metal layer 208a, and the fourth via 222 may extend in the third direction between the second upper metal layer 218 and the second metal layer 210a. Because the third via 220 and the fourth via 222 are also coupled to the first metal layer 208a and the second metal layer 210a, respectively, the distance d2 between the third via 220 and the fourth via 222 is substantially the same as the distance d2 between the first via 212 and the second via 214. In some embodiments, each of the first upper metal layer 216 and the second upper metal layer 218 may extend in the first direction over the cell boundary between the first cell 202a and the second cell 202b. In some examples, the first upper metal layer 216 may extend over at least a portion of the second metal layer 210a, and the second upper metal layer 218 may extend over at least a portion of the first metal layer 208a.

[0031] In some embodiments, the vias contacting the underlying diffusion contacts may also be staggered across the cell boundaries between adjacent first and second cells 202a, 202b. For example, the fifth via 224 may extend in the third direction between the first metal layer 208a and the diffusion contact 206a of the first cell 202a, and the sixth via 226 may extend in the third direction between the second metal layer 210a and the diffusion contact 207a of the second cell 202b. Because the fifth via 224 and the sixth via 226 are also coupled to the first metal layer 208a and the second metal layer 210a, respectively, the distance d2 between the fifth via 224 and the sixth via 226 is substantially the same as the distance d2 between the first via 212 and the second via 214 or between the third via 220 and the fourth via 222.

[0032] In some embodiments, the cell boundaries of the first cell 202a and the second cell 202b extending along the first direction may include isolation structures, such as a first isolation structure 228 of the first cell 202a and a second isolation structure 230 of the second cell 202b. The isolation structures 228 / 230 may include a dielectric material filled in the gate trench, such as silicon dioxide, to isolate the cells along the second direction. In some other examples, the isolation structures 228 / 230 may include a dummy gate structure that does not participate in the circuit.

[0033] It should be understood that Figure 2 The various cell elements shown in are not intended to be drawn to scale, and certain structures are not shown for clarity. The first cell 202a and the second cell 202b represent two cells of any number of cells arranged in an array having any number of rows and columns of cells.

[0034] Manufacturing method Figures 3A-3G Included are plan views collectively illustrating an example process for forming an integrated circuit having a cell with a staggered via arrangement according to one embodiment of the present disclosure. Each figure shows an example structure resulting from the process flow up to that point in time, so that the structure described evolves as the process flow continues, ultimately forming Figure 3G The structure shown is similar to Figure 2 The structure shown. The integrated circuit structure shown may be part of a larger integrated circuit including other units and / or integrated circuits not shown. Example materials and process parameters are given, but as will be understood, the present disclosure is not intended to be limited to any particular such materials or parameters.

[0035] Figure 3A A plan view of a first unit 301a adjacent to a second unit 301b is shown. According to some embodiments, in an early stage of the manufacturing process, the row of semiconductor fins 302 extends longitudinally along a second direction (e.g., X direction) and also extends along a third direction (e.g., Z direction) over a dielectric layer 304 adjacent to and extending parallel to the semiconductor fins 302. The semiconductor fins 302 may be the same semiconductor material (e.g., silicon) as the semiconductor substrate. In some embodiments, the semiconductor fins 302 include alternating layers of different semiconductor materials, which are used to form a full surround gate (GAA) structure. For example, the semiconductor fins 302 may include sacrificial layers alternating with the semiconductor layers. According to some embodiments, the sacrificial layers have a different material composition than the semiconductor layers. In some embodiments, the sacrificial layers are silicon germanium (SiGe), and the semiconductor layers include semiconductor materials suitable for use as nanoribbons, such as silicon (Si), SiGe, germanium, or III-V materials, such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each sacrificial layer and semiconductor layer, the germanium concentration is different between the sacrificial layer and the semiconductor layer. For example, the sacrificial layer may include a higher germanium content than the semiconductor layer.

[0036] A dielectric layer 304 may be provided to provide shallow trench isolation (STI) between adjacent semiconductor fins 302. The dielectric layer 304 may be any suitable dielectric material, such as silicon dioxide. Note that the dielectric layer 304 may be aligned directly over the cell boundary along the second direction.

[0037] Figure 3B 3 shows that after forming sacrificial gates 306a-306d and spacer structure 308, according to some embodiments, Figure 3A 1. A plan view of the structure shown. The gate mask layer may first be patterned into strips extending parallel to each other in a first direction so as to form corresponding sacrificial gates 306a-306d in corresponding strips below the gate mask layer. Thereafter, the gate mask layer may be removed or may be retained as a capping layer over the sacrificial gates 306a-306d. According to some embodiments, the sacrificial gate material is removed in all areas not protected by the gate mask layer. The sacrificial gates 306a-306d may be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gates 306a-306d include polysilicon.

[0038] According to some embodiments, a spacer structure 308 is formed along the sidewalls of the sacrificial gates 306a-306d. The spacer structure 308 can be deposited and then etched back so that the spacer structure 308 remains mostly only on the sidewalls of any exposed structure. The spacer structure 308 can also be formed along the sidewalls of the exposed fins 302 above the dielectric layer 304. Such sidewall spacers on the fins can be removed in subsequent processing when the source region or the drain region is formed. According to some embodiments, the spacer structure 308 can be any suitable dielectric material, such as silicon nitride, silicon carbonitride, or silicon carbonitride. In one such embodiment, the spacer structure 308 includes a nitride and the dielectric layer 304 includes an oxide to provide a degree of etch selectivity during the final gate processing. Other etch selective dielectric schemes (e.g., oxide / carbide, carbide / nitride) can also be used for the spacer structure 308 and the dielectric layer 304. In other embodiments, the spacer structure 308 and the dielectric layer 304 are identical or otherwise similar in composition, where etch selectivity is not employed. In some embodiments, the spacer structure 308 has a thinner width (along the second direction) than the sacrificial gates 306a-306d.

[0039] Figure 3C 3 shows that after removing the exposed semiconductor fins 302 and subsequently forming source or drain regions 310a / 310b in the areas where the fins were removed, according to some embodiments, Figure 3B 306a-306d) along the second direction.

[0040] According to some embodiments, each cell includes one or more first source or drain regions 310a and one or more second source or drain regions 310b. The first source or drain regions 310a may be aligned together along the second direction, and the second source or drain regions 310b may be aligned together along the second direction. According to some embodiments, the first source or drain region 310a and the second source or drain region 310b are epitaxially grown from the exposed semiconductor material at the end of the semiconductor layer or fin at the edge of the spacer structure 308. In some example embodiments, the first source or drain region 310a is an NMOS source or drain region (e.g., epitaxial silicon), and the second source or drain region 310b is a PMOS source or drain region (e.g., epitaxial SiGe), or vice versa. Dopants such as phosphorus or boron may also be added to the NMOS source or drain region or the PMOS source or drain region, respectively.

[0041] According to some embodiments, a dielectric filler 312 is provided between adjacent source or drain regions 310a and 310b along the source / drain trenches. In some examples, the dielectric filler 312 occupies the remaining volume within the source / drain trenches around and above the source or drain regions 310a and 310b. The dielectric filler 312 can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler 312 extends up to and is coplanar with the top surface of the spacer structure 308 (e.g., after a polishing process).

[0042] The semiconductor fin (or at least the semiconductor layer) extends between each adjacent pair of the first source or drain regions 310a and between each adjacent pair of the second source or drain regions 310b along the second direction under the corresponding sacrificial gates 306a-306d and the spacer structure 308. Thus, a single transistor can be formed between each adjacent pair of source or drain regions 310a / 310b along the second direction. According to some embodiments, each of the first cell 301a and the second cell 301b has four transistors, with two NMOS transistors and two PMOS transistors.

[0043] Figure 3D FIG. 4 shows that after forming a gate structure and a diffusion contact, according to some embodiments, Figure 3C306a-306d and the sacrificial layer. The sacrificial gates 306a-306d are removed using any suitable isotropic etching process and replaced with the gate structure 314. In examples where the fins include alternating semiconductor layers, the sacrificial layers are selectively removed to leave the semiconductor layers as nanoribbons extending between the corresponding source or drain regions. The sacrificial gates 306a-306d and the sacrificial layers can be removed using the same isotropic etching process or different isotropic etching processes. Any number of nanoribbons can be used per transistor, such as three nanoribbons or four nanoribbons, to name a few examples.

[0044] Each gate structure 314 may include a gate dielectric over a semiconductor nanoribbon or semiconductor body within a gate trench, and a gate electrode filling the remainder of the gate trench. The gate dielectric may include any suitable dielectric material (such as silicon dioxide and / or a high-k dielectric material). The gate electrode may include one or more conductive layers that may be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few examples. The gate electrode may include any suitable metal or metal alloy, such as aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides.

[0045] In accordance with some embodiments, various diffusion contacts 316a-316e may be formed within the source / drain trenches to contact the underlying source or drain region. Any portion of the source / drain trenches that does not include a diffusion contact may include another dielectric fill 318, which may be similar to dielectric fill 312. In some embodiments, dielectric fill 318 represents the portion of dielectric fill 312 that remains after forming diffusion contacts 316a-316e. In accordance with some embodiments, diffusion contacts 316a-316e may include any suitable conductive material, such as tungsten, ruthenium, or molybdenum.

[0046] Figure 3E FIG. 3 shows that after forming the gate cut 320 , according to some embodiments, Figure 3D314a-314d of the first cell 301a and the second cell 301b. In some examples, the gate cutouts 320 are aligned with the cell boundaries so that the cell boundaries along the second direction define the center lines of the gate cutouts 320. Therefore, the spacing of the gate cutouts 320 can define the height of the first cell 301a and the height of the second cell 301b. The gate cutouts 320 can extend through at least the entire thickness of the gate structures 314a-314h in the third direction. The gate cutouts 320 can include any number of suitable dielectric materials, such as silicon oxide, silicon nitride, or silicon carbide.

[0047] Figure 3F FIG. 4 shows that after forming signal lines and various vias across first and second cells 301a and 301b, according to some embodiments, Figure 3E 3. Plan view of the structure shown. Note that for clarity, the various dielectric materials are not shown. Thus, dielectric fill 318, spacer structure 308, and gate cut 320 are not shown in this view.

[0048] Any number of first metal layers 322 may be formed over the transistor structure of the first cell 301a, and any number of second metal layers 324 may be formed over the transistor structure of the second cell 301b. In the example shown, four equally spaced first metal layers 322 extend along the second direction, and four equally spaced second metal layers 324 extend along the second direction. In this example arrangement, neither the first metal layer 322 nor the second metal layer 324 extends on or over a cell boundary extending along the second direction. The first and second metal layers 322 / 324 may include any suitable conductive material, such as copper, tungsten, ruthenium, or molybdenum.

[0049] According to some embodiments, first via 326 is formed between first metal layer 322 adjacent to the cell boundary and underlying gate structure 314c, and second via 328 is formed between second metal layer 324 adjacent to the cell boundary and underlying gate structure 314f. Each of first via 326 and second via 328 extends in a third direction and may have substantially the same size and material composition. First via 326 and second via 328 may include any suitable conductive material, such as copper, tungsten, ruthenium, or molybdenum.

[0050] According to some embodiments, first vias 326 and second vias 328 are staggered across the cell boundary such that no portion of first vias 326 overlaps any portion of second vias 328 along the first direction. In some embodiments, a distance d1 between a center of first via 326 to a center of second via 326 along the second direction is between about 34 nm and about 50 nm.

[0051] According to some embodiments, staggering the first through hole 326 and the second through hole 328 allows the dead space between the first unit 301a and the second unit 301b to be removed, which results in a reduction in the height of each unit. For example, the distance d2 between the center of the first through hole 326 to the center of the second through hole 328 along the first direction can be less than about 40nm, less than 30nm, or less than 20nm. In some examples, d2 is between about 16nm and about 36nm. In some embodiments, the distance d2 can be reduced to be substantially the same as the pitch between adjacent first metal layers 322 and / or the pitch between adjacent second metal layers 324.

[0052] According to some embodiments, the third via 330 is formed between the first metal layer 322 adjacent to the cell boundary and the underlying diffusion contact 316a, and the fourth via 332 is formed between the second metal layer 324 adjacent to the cell boundary and the underlying diffusion contact 316e. Each of the third via 330 and the fourth via 332 extends in a third direction and may have substantially the same size and material composition. The third via 330 and the fourth via 332 may include any suitable conductive material, such as copper, tungsten, ruthenium, or molybdenum.

[0053] According to some embodiments, third via 330 and fourth via 332 may be similarly staggered across the cell boundary such that no portion of third via 330 overlaps any portion of fourth via 332 along the first direction. Because third via 330 and fourth via 332 are aligned over the same first metal layer 322 and second metal layer 324 as first via 326 and second via 328, respectively, third via 330 and fourth via 332 have substantially the same distance d2 between their centers along the first direction.

[0054] Figure 3G FIG. 4 shows that after forming an additional signal line (eg, a higher metal layer) and another set of vias to the additional signal line, according to some embodiments, Figure 3FA plan view of the structure shown. A third metal layer 334 extending longitudinally in the first direction may be formed above one or more of the first metal layers 322, and a fourth metal layer 336 extending longitudinally in the first direction may be formed above one or more of the second metal layers 324. Each of the third metal layer 334 and the fourth metal layer 336 may include any suitable conductive material, such as copper, tungsten, ruthenium, or molybdenum. In some embodiments, the third metal layer 334 extends across the cell boundary between the first cell 301a and the second cell 301b, and / or the fourth metal layer 336 extends across the cell boundary between the first cell 301a and the second cell 301b. Thus, the third metal layer 334 and / or the fourth metal layer 336 may extend across the entire width of the gate cutout 320 between the first cell 301a and the second cell 301b (e.g., along the first direction). In some embodiments, the third metal layer 334 extends over at least a portion of one or more of the second metal layers 324, and / or the fourth metal layer 336 extends over at least a portion of one or more of the first metal layers 322.

[0055] According to some embodiments, fifth via 338 is formed between first metal layer 322 and third metal layer 334 adjacent to the cell boundary, and sixth via 340 is formed between second metal layer 324 and fourth metal layer 336 adjacent to the cell boundary. Each of fifth via 338 and sixth via 340 extends in the third direction and may have substantially the same size and material composition. Fifth via 338 and sixth via 340 may include any suitable conductive material, such as copper, tungsten, ruthenium, or molybdenum.

[0056] According to some embodiments, the fifth through hole 338 and the sixth through hole 340 may be similarly staggered across the cell boundary such that no portion of the fifth through hole 338 overlaps any portion of the sixth through hole 340 along the first direction. In some embodiments, the distance d3 between the center of the fifth through hole 338 and the center of the sixth through hole 340 along the second direction is between about 34 nm and about 50 nm. The distance d3 between the center of the fifth through hole 338 and the center of the sixth through hole 340 may extend as wide as the cell width of the first cell 301a or the second cell 301b, so that the fifth through hole 338 and the sixth through hole 340 may be located anywhere along the first metal layer 322 and the second metal layer 324, respectively. Since the fifth through hole 338 and the sixth through hole 340 are aligned over the same first metal layer 322 and the second metal layer 324 as the first through hole 326 and the second through hole 328, respectively, the fifth through hole 338 and the sixth through hole 340 have substantially the same distance d2 between their centers along the first direction.

[0057] Figure 4An example embodiment of a chip package 400 according to an embodiment of the present disclosure is shown. It can be seen that the chip package 400 includes one or more dies 402. The one or more dies 402 may include at least one integrated circuit having a semiconductor device (such as any semiconductor device disclosed herein without a layout arrangement). In some example configurations, the one or more dies 402 may include any other circuits for interfacing with other devices formed on the die or other devices connected to the chip package 400.

[0058] It can also be seen that the chip package 400 includes a housing 404 bonded to a package substrate 406. The housing 404 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 400. One or more dies 402 can be conductively coupled to the package substrate 406 using connections 408, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonding, to name a few examples. The package substrate 406 can be any standard or proprietary package substrate, but in some cases includes a dielectric material having a conductive path (e.g., including conductive vias and lines) that extends through the dielectric material between the faces of the package substrate 406 or between different locations on each face. In some embodiments, the package substrate 406 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 412 can be provided on the opposite side of the package substrate 406 for conductive contact, such as a printed circuit board (PCB). One or more through-holes 410 extend through the thickness of the package substrate 406 to provide a conductive path between one or more connections 408 and one or more contacts 412. For ease of illustration, the through-hole 410 is shown as a single straight column through the package substrate 406, although other configurations may be used (e.g., inlays, dual inlays, through-silicon vias, or interconnect structures that meander through the thickness of the substrate 406 to contact one or more intermediate locations therein). In other embodiments, the through-hole 410 is made of multiple smaller stacked through-holes, or is staggered at different locations across the package substrate 406. In the illustrated embodiment, the contact 412 is a solder ball (e.g., for a bump-based connection or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement). In some embodiments, solder resist is provided between the contacts 412 to inhibit shorting.

[0059] In some embodiments, molding material 414 may be disposed around one or more dies 402 included within housing 404 (e.g., as an underfill material between die 402 and package substrate 406, and as an overfill material between die 402 and housing 404). Although the size and quality of molding material 414 may vary from one embodiment to the next, in some embodiments, molding material 414 has a thickness of less than 1 millimeter. Example materials that may be used for molding material 414 include epoxy molding material, where appropriate. In some cases, molding material 414, in addition to being electrically insulating, is also thermally conductive.

[0060] Methodology Figure 5 A diagram depicting the design and formation of an embodiment according to the present disclosure is shown. Figure 2 5 is a flow chart of a method 500 of implementing an integrated circuit structure.

[0061] In one example, a hardware computer may be used to implement one or more operations of method 500, such as operations 502, 504, 506, and / or 508. The hardware computer may include a hardware processor that is communicatively coupled to a non-transitory computer-readable storage medium that includes an executable instruction set that, when executed, may perform one or more designed operations of method 500. The hardware processor may execute instructions within the computer-readable storage medium to perform operations 502, 504, 506, and / or 508 of method 500. In one example, the hardware processor is a central processing unit (CPU), a graphics processing unit (GPU), a distributed processing system, an application-specific integrated circuit (ASIC), and / or another suitable processor. In one example, the computer-readable storage medium is a suitable storage medium, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a mass storage device (e.g., a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Reference has been made herein to the computer-readable storage medium. Figure 6 Examples of hardware processors and computer-readable storage media are discussed.

[0062] Method 500 includes operation 502, in which a cell library having unit cells is accessed, each unit cell having at least two transistors therein. Suitable integrated circuit design tools, such as EDA (electronic design automation) tools executed in a hardware computer, can be used to form and / or access the cell library and for subsequent design processes. In some examples, each unit cell is substantially the same (e.g., having the same width, height, and number of transistors).

[0063] Method 500 continues with operation 504 where data regarding a circuit to be implemented using the unit is received (eg, via a hardware computer).

[0064] The method 500 continues with operation 506, where an integrated circuit structure is designed having an array of unit cells. The unit cells may be arranged in an array of adjacent rows and columns. It should be understood that the array may also include spaces between any two adjacent cells. Each unit cell of the array may include a substantially identical arrangement of transistor structures (e.g., two transistors, four transistors, or six transistors per unit cell). In one embodiment, a first cell is adjacent to a second cell in a given column, wherein the first cell includes a first gate structure and the second cell includes a second gate structure. Each of the first and second gate structures may extend in a height direction of the cell.

[0065] The method 500 continues with operation 508, where any number of interconnect structures are designed for the integrated circuit structure having the designed unit cell array. The interconnect structure may include any number of metal layers and vias across any number of stacked dielectric layers above the transistor structure. The interconnect structure may be used to route logic signals, power signals, and ground signals to any transistor across any cell in the array.

[0066] According to some embodiments, the interconnect structure includes a first through hole connected between a first gate structure and a first metal layer in an interconnect layer above the transistor, and a second through hole between a second gate structure and a second metal layer in an interconnect layer (or a different interconnect layer) above the transistor. According to some embodiments, the first and second metal layers extend parallel to and adjacent to a cell boundary between the first and second cells, and on opposite sides of the cell boundary. According to some embodiments, the first and second through holes are staggered so that no portion of the first through hole overlaps any portion of the second through hole along the cell height direction. For example, the distance between the center of the first through hole to the center of the second through hole along the cell height direction can be less than about 40nm, less than 30nm, or less than 20nm. In some examples, the distance is between about 16nm and about 36nm.

[0067] Method 500 then proceeds to operation 510, where an integrated circuit having an array of unit cells and an interconnect structure is formed. Figures 3A-3G The integrated circuit may be formed by any of the techniques described.

[0068] Note that for ease of description, the operations in method 500 are shown in a particular order. However, according to some embodiments, one or more of the processes may be performed in a different order, or may not be performed at all (and are therefore optional). Many variations on method 500 and the techniques described herein will be apparent in light of this disclosure.

[0069] Example System Figure 6 is a structure according to some embodiments of the present disclosure using any number of integrated circuits discussed herein (such as, Figure 2 The integrated circuit structure shown in FIG. Figure 5 The design process of the method 500 discussed above is described with reference to a computing system 600. As can be seen, the computing system 600 houses a motherboard 602. The motherboard 602 may include a plurality of components, including but not limited to a processor 604 and at least one communication chip 606, each of which may be physically and electrically coupled to the motherboard 602, or otherwise integrated therein. It should be understood that the motherboard 602 may be, for example, any printed circuit board (PCB), whether a motherboard, a daughterboard mounted on a motherboard, or a sole board of the system 600, etc.

[0070] Depending on its application, the computing system 600 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any component included in the computing system 600 may include one or more integrated circuit structures or devices formed using the disclosed technology according to example embodiments. In some embodiments, multiple functions may be integrated into one or more chips (e.g., such as, note that the communication chip 606 may be part of the processor 604 or otherwise integrated into the processor 604).

[0071] The communication chip 606 implements wireless communication for transmitting data to and from the computing system 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can transmit data by using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not contain any wires, although in some embodiments they may not contain any wires. The communication chip 606 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivative protocols, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing system 600 may include multiple communication chips 606. For example, the first communication chip 606 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 606 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0072] The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented with one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0073] The communication chip 606 may also include an integrated circuit die packaged within the communication chip 606. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described variously herein. It will be appreciated in light of the present disclosure that it is noted that multi-standard wireless capabilities may be integrated directly into the processor 604 (e.g., where the functionality of any chip 606 is integrated into the processor 604, rather than having a separate communication chip). It is also noted that the processor 604 may be a chipset having such wireless capabilities. In short, any number of processors 604 and / or communication chips 606 may be used. Likewise, any one chip or chipset may have multiple functions integrated therein.

[0074] In various implementations, computing system 600 may be a laptop, netbook, notebook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatus, and other structures configured to compute or process information.

[0075] Further example embodiments The following examples relate to further embodiments, from which numerous permutations and configurations will be apparent.

[0076] Example 1 is an integrated circuit structure comprising a first unit having two or more first transistor devices, wherein the two or more first transistor devices include a first gate structure extending in a first direction within the first unit and a second unit adjacent to the first unit in the first direction. The second unit has two or more second transistor devices, wherein the two or more second transistor devices include a second gate structure extending in the first direction within the second unit. The integrated circuit structure also includes a first metal layer extending in a second direction different from the first direction and above the first gate structure, a second metal layer extending in the second direction and above the second gate structure, a first through hole extending in a third direction between the first metal layer and the first gate structure below, and a second through hole extending in the third direction between the second metal layer and the second gate structure below. No portion of the second through hole overlaps any portion of the first through hole along the first direction.

[0077] Example 2 includes the integrated circuit structure of Example 1, further comprising a third metal layer extending along the first direction and over the first metal layer, a fourth metal layer extending along the first direction and over the second metal layer, a third via extending in the third direction between the third metal layer and the first metal layer, and a fourth via extending in the third direction between the fourth metal layer and the second metal layer. No portion of the fourth via overlaps any portion of the third via along the first direction.

[0078] Example 3 includes the integrated circuit structure of Example 2, wherein the third metal layer extends along the first direction over at least a portion of the second metal layer, and wherein the fourth metal layer extends along the first direction over at least a portion of the first metal layer.

[0079] Example 4 includes the integrated circuit structure of Example 2 or 3, further comprising a gate cut extending in the second direction between the first gate structure and the second gate structure.

[0080] Example 5 includes the integrated circuit structure of Example 4, wherein a boundary between the first cell and the second cell extends along the gate cut in the second direction.

[0081] Example 6 includes the integrated circuit structure of Example 4 or 5, wherein the third metal layer extends across a width of the gate cut in the first direction, and wherein the fourth metal layer extends across a width of the gate cut in the first direction.

[0082] Example 7 includes the integrated circuit structure of any of Examples 4-6, wherein the first via is aligned adjacent to a first side of the gate cutout, and the second via is aligned adjacent to a second side of the gate cutout, the second side being opposite to the first side along the first direction.

[0083] Example 8 includes the integrated circuit structure of any of Examples 1-7, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to both the first and second directions.

[0084] Example 9 includes the integrated circuit structure of any of Examples 1-8, wherein a distance between a center of the first via and a center of the second via along the first direction is between about 16 nm and about 36 nm.

[0085] Example 10 is an integrated circuit design system, which includes at least one processor, a non-transitory storage medium storing instructions, and when the instructions are executed by the at least one processor, the system performs a method. The method includes accessing a cell library having unit cells, wherein each unit cell has corresponding two or more transistor devices, receiving data about a circuit to be implemented using the unit cell, designing an array of rows and columns containing unit cells to implement the circuit, and designing a plurality of interconnect structures to implement the circuit. The column of unit cells includes a first unit cell and a second unit cell directly adjacent to the first unit cell. The first unit cell includes a first gate structure extending along a first direction within the first unit cell, and the second unit cell includes a second gate structure extending along the first direction within the second unit cell. The plurality of interconnect structures include a first metal layer extending along a second direction different from the first direction and above the first gate structure, a second metal layer extending along the second direction and above the second gate structure, a first through hole extending in a third direction between the first metal layer and the first gate structure below, and a second through hole extending in the third direction between the second metal layer and the second gate structure below. No portion of the second through hole overlaps any portion of the first through hole along the first direction.

[0086] Example 11 includes the integrated circuit design system of Example 10, wherein the interconnect structure further includes a third metal layer extending along the first direction and over the first metal layer, a fourth metal layer extending along the first direction and over the second metal layer, a third via extending in the third direction between the third metal layer and the first metal layer, and a fourth via extending in the third direction between the fourth metal layer and the second metal layer. No portion of the fourth via overlaps any portion of the third via along the first direction.

[0087] Example 12 includes the integrated circuit design system of Example 11, wherein the third metal layer extends along the first direction over at least a portion of the second metal layer, and wherein the fourth metal layer extends along the first direction over at least a portion of the first metal layer.

[0088] Example 13 includes the integrated circuit design system of Example 11 or 12, wherein the design array further includes a gate cut extending in the second direction between the first gate structure and the second gate structure.

[0089] Example 14 includes the integrated circuit design system of Example 13, wherein a boundary between the first unit cell and the second unit cell extends along the gate cut in the second direction.

[0090] Example 15 includes the integrated circuit design system of Example 13 or 14, wherein the third metal layer extends across the entire width of the gate cut in the first direction, and wherein the fourth metal layer extends across the entire width of the gate cut in the first direction.

[0091] Example 16 includes the integrated circuit design system of any of Examples 13-15, wherein the first via is aligned adjacent to a first side of the gate cutout, and the second via is aligned adjacent to a second side of the gate cutout, the second side being opposite to the first side along the first direction.

[0092] Example 17 includes the integrated circuit design system of any of Examples 10-16, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to both the first and second directions.

[0093] Example 18 is an integrated circuit structure comprising a first transistor device, a second transistor device, a first through hole, and a second through hole. The first transistor device comprises a first source region, a first drain region, a first body comprising a semiconductor material extending from the first source region to the first drain region, and a first gate structure extending above the first body. The first gate structure extends in a first direction above the first body, and the first body extends from the first source region to the first drain region in a second direction different from the first direction. The second transistor device is spaced apart from the first transistor device along the first direction and along the second direction. The second transistor device comprises a second source region, a second drain region, a second body comprising a semiconductor material extending from the second source region to the second drain region in the second direction, and a second gate structure extending above the second body in the first direction. The first through hole is coupled to the first gate structure and extends in a third direction above the first gate structure. The second through hole is coupled to the second gate structure and extends in a third direction above the second gate structure. The distance between the center of the first through hole and the center of the second through hole along the first direction is less than 40nm.

[0094] Example 19 includes the integrated circuit structure of Example 18, wherein the first body includes one or more first semiconductor nanoribbons and the second body includes one or more second semiconductor nanoribbons.

[0095] Example 20 includes the integrated circuit structure of Example 19, wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons include germanium, silicon, or any combination thereof.

[0096] Example 21 includes the integrated circuit structure of any of Examples 18-20, wherein no portion of the second via overlaps any portion of the first via along the first direction.

[0097] Example 22 includes the integrated circuit structure of any one of Examples 18-21, further comprising a first metal layer extending along a second direction and above the first gate structure, such that a first through hole extends from the first metal layer to the first gate structure, and a second metal layer extending along a second direction and above the second gate structure, such that a second through hole extends from the second metal layer to the second gate structure.

[0098] Example 23 includes the integrated circuit structure of Example 22, further comprising a third metal layer extending along the first direction and over the first metal layer, a fourth metal layer extending along the first direction and over the second metal layer, a third via extending in the third direction between the third metal layer and the first metal layer, and a fourth via extending in the third direction between the fourth metal layer and the second metal layer. A distance between a center of the third via and a center of the fourth via along the first direction is less than 40 nm.

[0099] Example 24 includes the integrated circuit structure of Example 23, wherein no portion of the third via overlaps any portion of the fourth via along the first direction.

[0100] Example 25 includes the integrated circuit structure of Example 23 or 24, wherein the third metal layer extends along the first direction over at least a portion of the second metal layer, and wherein the fourth metal layer extends along the first direction over at least a portion of the first metal layer.

[0101] Example 26 includes the integrated circuit structure of any of Examples 18-25, further comprising a gate cut extending in the second direction between the first transistor device and the second transistor device.

[0102] Example 27 includes the integrated circuit structure of Example 26, wherein the first transistor device is a transistor device of a first unit cell and the second transistor device is a transistor device of a second unit cell, wherein a boundary between the first unit cell and the second unit cell extends along the gate cut in a second direction.

[0103] Example 28 includes the integrated circuit structure of Example 26 or 27, wherein the first via is aligned adjacent to a first side of the gate cutout, and the second via is aligned adjacent to a second side of the gate cutout, the second side being opposite to the first side along the first direction.

[0104] Example 29 includes the integrated circuit structure of any of Examples 18-28, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to both the first and second directions.

[0105] Example 30 includes the integrated circuit structure of any of Examples 18-29, wherein a distance between a center of the first via and a center of the second via along the first direction is between about 16 nm and about 36 nm.

[0106] Example 31 is an integrated circuit structure comprising a first unit having two or more first transistor devices, wherein the two or more first transistor devices include a first gate structure extending in a first direction within the first unit and a first contact on a first source or drain region adjacent to the first gate structure, and a second unit adjacent to the first unit in the first direction. The second unit has two or more second transistor devices, wherein the two or more second transistor devices include a second gate structure extending in the first direction within the second unit and a second contact on a second source or drain region adjacent to the second gate structure. The integrated circuit structure also includes a first metal layer extending in a second direction different from the first direction and above the first contact, a second metal layer extending in the second direction and above the second contact, a first through hole extending in a third direction between the first metal layer and the first contact below, and a second through hole extending in the third direction between the second metal layer and the second contact below. No portion of the second through hole overlaps any portion of the first through hole along the first direction.

[0107] Example 32 includes the integrated circuit structure of Example 31, further comprising a third metal layer extending along the first direction and over the first metal layer, a fourth metal layer extending along the first direction and over the second metal layer, a third via extending in the third direction between the third metal layer and the first metal layer, and a fourth via extending in the third direction between the fourth metal layer and the second metal layer. No portion of the fourth via overlaps any portion of the third via along the first direction.

[0108] Example 33 includes the integrated circuit structure of Example 32, wherein the third metal layer extends along the first direction over at least a portion of the second metal layer, and wherein the fourth metal layer extends along the first direction over at least a portion of the first metal layer.

[0109] Example 34 includes the integrated circuit structure of Example 32 or 33, further comprising a gate cut extending in the second direction between the first gate structure and the second gate structure.

[0110] Example 35 includes the integrated circuit structure of Example 34, wherein a boundary between the first cell and the second cell extends along the gate cut in the second direction.

[0111] Example 36 includes the integrated circuit structure of Example 34 or 35, wherein the third metal layer extends across the entire width of the gate cut in the first direction, and wherein the fourth metal layer extends across the entire width of the gate cut in the first direction.

[0112] Example 37 includes the integrated circuit structure of any of Examples 34-36, wherein the first via is aligned adjacent to a first side of the gate cutout, and the second via is aligned adjacent to a second side of the gate cutout, the second side being opposite to the first side along the first direction.

[0113] Example 38 includes the integrated circuit structure of any of Examples 31-37, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to both the first and second directions.

[0114] Example 39 includes the integrated circuit structure of any of Examples 31-38, wherein a distance between a center of the first via and a center of the second via along the first direction is between approximately 16 nm and approximately 36 nm.

[0115] The foregoing description of the exemplary embodiments of the present disclosure has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in light of the present disclosure. It is intended that the scope of the present disclosure is not limited by this detailed description, but rather by the appended claims.

Claims

1. An integrated circuit structure, comprising: a first cell having two or more first transistor devices, the two or more first transistor devices including a first gate structure extending in a first direction within the first cell; a second cell adjacent to the first cell in the first direction, the second cell having two or more second transistor devices, the two or more second transistor devices including a second gate structure extending in the first direction within the second cell; a first metal layer extending in a second direction different from the first direction and over the first gate structure; a second metal layer extending along a second direction and over the second gate structure; a first via extending in a third direction between the first metal layer and an underlying first gate structure; as well as A second via extends in a third direction between the second metal layer and an underlying second gate structure, wherein no portion of the second via overlaps any portion of the first via along the first direction.

2. The integrated circuit structure according to claim 1, further comprising: a third metal layer extending along the first direction and above the first metal layer; a fourth metal layer extending along the first direction and above the second metal layer; a third through hole extending in a third direction between the third metal layer and the first metal layer; as well as A fourth via extending in the third direction between the fourth metal layer and the second metal layer, wherein no portion of the fourth via overlaps any portion of the third via along the first direction. 3 . The integrated circuit structure of claim 2 , wherein the third metal layer extends along the first direction over at least a portion of the second metal layer, and wherein the fourth metal layer extends along the first direction over at least a portion of the first metal layer. 4 . The integrated circuit structure of claim 2 , further comprising a gate cutout extending in the second direction between the first gate structure and the second gate structure. 5 . The integrated circuit structure of claim 4 , wherein a boundary between the first cell and the second cell extends along the gate cut in the second direction.

6. The integrated circuit structure of claim 4, wherein the third metal layer extends across the entire width of the gate cut in the first direction, and wherein the fourth metal layer extends across the entire width of the gate cut in the first direction.

7. The integrated circuit structure of claim 4, wherein the first via is aligned adjacent to a first side of the gate cutout, and the second via is aligned adjacent to a second side of the gate cutout, the second side being opposite to the first side along the first direction.

8. The integrated circuit structure of any one of claims 1 to 3, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to both the first and second directions.

9. The integrated circuit structure of any one of claims 1 to 3, wherein a distance between a center of the first via and a center of the second via along the first direction is between about 16 nm and about 36 nm.

10. An integrated circuit structure comprising: a first transistor device comprising a first source region, a first drain region, a first body comprising a semiconductor material extending from the first source region to the first drain region, and a first gate structure extending over the first body, wherein the first gate structure extends in a first direction over the first body and the first body extends from the first source region to the first drain region in a second direction different from the first direction; a second transistor device spaced apart from the first transistor device along the first direction and along the second direction, the second transistor device comprising a second source region, a second drain region, a second body comprising semiconductor material extending from the second source region to the second drain region in the second direction, and a second gate structure extending over the second body in the first direction; a first through-hole coupled to the first gate structure and extending in a third direction over the first gate structure; as well as A second via is coupled to the second gate structure and extends in a third direction over the second gate structure, wherein a distance between a center of the first via and a center of the second via along the first direction is less than 40 nm. 11 . The integrated circuit structure of claim 10 , wherein the first body comprises one or more first semiconductor nanoribbons and the second body comprises one or more second semiconductor nanoribbons.

12. The integrated circuit structure of claim 11, wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons comprise germanium, silicon, or any combination thereof.

13. The integrated circuit structure of claim 10, wherein no portion of the second via overlaps any portion of the first via along the first direction.

14. The integrated circuit structure of claim 10, further comprising: a first metal layer extending in a second direction and over the first gate structure, such that a first via extends from the first metal layer to the first gate structure; as well as The second metal layer extends along the second direction and over the second gate structure, so that the second via extends from the second metal layer to the second gate structure.

15. The integrated circuit structure of claim 14, further comprising: a third metal layer extending along the first direction and above the first metal layer; a fourth metal layer extending along the first direction and above the second metal layer; a third through hole extending in a third direction between the third metal layer and the first metal layer; as well as A fourth through hole extends in the third direction between the fourth metal layer and the second metal layer, wherein a distance between a center of the third through hole and a center of the fourth through hole along the first direction is less than 40 nm. 16 . The integrated circuit structure of claim 15 , wherein no portion of the third via overlaps any portion of the fourth via along the first direction.

17. The integrated circuit structure of claim 15, wherein the third metal layer extends along the first direction over at least a portion of the second metal layer, and wherein the fourth metal layer extends along the first direction over at least a portion of the first metal layer.

18. The integrated circuit structure of any one of claims 10 to 16, further comprising a gate cut extending in the second direction between the first transistor device and the second transistor device.

19. The integrated circuit structure of claim 18, wherein the first transistor device is a transistor device of a first unit cell and the second transistor device is a transistor device of a second unit cell, wherein a boundary between the first unit cell and the second unit cell extends along the gate cut in the second direction.

20. An integrated circuit structure comprising: a first cell having two or more first transistor devices, the two or more first transistor devices including a first gate structure extending in a first direction within the first cell and a first contact on a first source or drain region adjacent to the first gate structure; a second cell adjacent to the first cell in the first direction, the second cell having two or more second transistor devices, the two or more second transistor devices including a second gate structure extending in the first direction within the second cell and a second contact on a second source or drain region adjacent to the second gate structure; a first metal layer extending in a second direction different from the first direction and over the first contact; a second metal layer extending along a second direction and over the second contact; a first via extending in a third direction between the first metal layer and an underlying first contact; as well as A second via extends in the third direction between the second metal layer and an underlying second contact, wherein no portion of the second via overlaps any portion of the first via along the first direction.

21. The integrated circuit structure of claim 20, further comprising: a third metal layer extending along the first direction and above the first metal layer; a fourth metal layer extending along the first direction and above the second metal layer; a third through hole extending in a third direction between the third metal layer and the first metal layer; as well as A fourth via extending in the third direction between the fourth metal layer and the second metal layer, wherein no portion of the fourth via overlaps any portion of the third via along the first direction.

22. The integrated circuit structure of claim 21, wherein the third metal layer extends along the first direction over at least a portion of the second metal layer, and wherein the fourth metal layer extends along the first direction over at least a portion of the first metal layer.

23. The integrated circuit structure of claim 21, further comprising a gate cutout extending in the second direction between the first gate structure and the second gate structure.

24. The integrated circuit structure of claim 23, wherein a boundary between the first cell and the second cell extends along the gate cut in the second direction.

25. The integrated circuit structure of claim 23 or 24, wherein the third metal layer extends across the entire width of the gate cut in the first direction, and wherein the fourth metal layer extends across the entire width of the gate cut in the first direction.

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