Complementary field effect transistor, semiconductor device and manufacturing method thereof, and electronic equipment

Abstract

The invention provides a complementary field effect transistor. The complementary field effect transistor comprises a first transistor and a second transistor which are stacked on one side of a substrate. Along a first direction parallel to the substrate, the first transistor comprises a plurality of first channels arranged between two first-layer source / drain electrodes, and the peripheries of the first channels are provided with first gate structures; the second transistor comprises a plurality of second channels arranged between two second layer source / drain electrodes, and the peripheries of the second channels are provided with second gate structures; the first gate structure comprises a first work function layer, and the second gate structure comprises a second work function layer; the material of the first work function layer and the material of the second work function layer both comprise indium tin oxide. The thickness of the first gate structure and the second gate structure is smaller, the complementary field effect transistor of a small size can be filled, and the requirement of the complementary field effect transistor of the small size is met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a complementary field effect transistor, a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Complementary Field Effect Transistor (CFET) includes NMOS (N-Metal-Oxide-Semiconductor) transistor and PMOS (P-Metal-Oxide-Semiconductor) transistor, which can significantly enhance the performance of transistors, reduce their size and achieve ultra-high integration. Summary of the invention

[0003] In view of the shortcomings of the existing methods, the present application proposes a complementary field effect transistor, a semiconductor device and a manufacturing method thereof, and an electronic device to solve the technical problems of the existing semiconductor devices including CFET having complex structures or difficult manufacturing.

[0004] In a first aspect, an embodiment of the present application provides a complementary field effect transistor, comprising: a first transistor and a second transistor stacked on one side of a substrate;

[0005] Along a first direction parallel to the substrate, the first transistor includes a plurality of first channels arranged between two first-layer source / drain electrodes, and a first gate structure is arranged around the first channels; the second transistor includes a plurality of second channels arranged between two second-layer source / drain electrodes, and a second gate structure is arranged around the second channels; along a second direction perpendicular to the substrate, any two gate structures among the plurality of the first gate structures and the plurality of the second gate structures are distributed at intervals;

[0006] The first gate structure includes a first work function layer, and the second gate structure includes a second work function layer; the material of the first work function layer and the material of the second work function layer both include indium tin oxide.

[0007] In a second aspect, an embodiment of the present application provides a semiconductor device comprising: a plurality of complementary field effect transistors as described in the first aspect arranged in an array.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, including: the semiconductor device of the second aspect.

[0009] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0010] Manufacturing semiconductor columns arranged in an array on one side of the substrate, wherein the semiconductor columns include channel layers and sacrificial structures alternately stacked along a second direction perpendicular to the substrate, a portion of the channel layers being a first channel of a first transistor, and another portion of the channel layers being a second channel of a second transistor;

[0011] Two first-layer source / drain electrodes insulated from the sacrificial structure are manufactured at both ends of all the first channels along a first direction parallel to the substrate; an insulating layer is manufactured on the side of the first-layer source / drain electrodes away from the substrate; two second-layer source / drain electrodes insulated from the sacrificial structure are manufactured at both ends of all the second channels along the first direction; the second-layer source / drain electrodes, the insulating layer, and the first-layer source / drain electrodes are sequentially close to the substrate;

[0012] Removing each of the sacrificial structures to form a blank area; manufacturing a first gate structure including a first work function layer in the blank area between two adjacent channel layers;

[0013] A first protective layer is covered on the outer side of each first gate structure of the first transistor; under the protection of the first protective layer, the work function of the first work function layer in the first gate structure of the second transistor is adjusted to obtain a second gate structure including a second work function layer.

[0014] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0015] The material of the first work function layer of the first transistor and the material of the second work function layer of the second transistor are set to the same material, so the work function material layers of the first transistor and the second transistor can be deposited at the same time, and then the work function of the work function material layer is adjusted to match the work function of the work function material layer of the first transistor with the conductivity type of the first transistor, and the work function of the work function material layer of the second transistor is matched with the conductivity type of the second transistor. Because the work function material layers of the first transistor and the second transistor can be deposited at the same time, there is no need to set up an additional etching stop layer and a diffusion barrier layer, so the structure of the complementary field effect transistor of the present application is simpler, and the thickness of the first gate structure of the first transistor and the second gate structure of the second transistor can be reduced, and small-sized complementary field effect transistors can be filled to meet the manufacturing requirements of small-sized complementary field effect transistors.

[0016] Moreover, the material of the first work function layer of the first transistor and the material of the second work function layer of the second transistor both include indium tin oxide. The work function of the indium tin oxide of the second work function layer can be adjusted to be different from the work function of the indium tin oxide of the first work function layer, which is beneficial to meeting the work function requirements of the first work function layer and the second work function layer.

[0017] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A schematic cross-sectional view of a complementary field effect transistor along a first direction provided in an embodiment of the present application;

[0020] Figure 2 A cross-sectional schematic diagram of a first gate structure provided in an embodiment of the present application;

[0021] Figure 3 A cross-sectional schematic diagram of a second gate structure provided in an embodiment of the present application;

[0022] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0023] Figures 5 to 18 The present invention provides a schematic cross-sectional view of a semiconductor device manufactured in various expansion methods according to an embodiment of the present application.

[0024] Description of reference numerals:

[0025] 1- substrate;

[0026] 2-first transistor; 21-first gate structure; 211-first work function layer; 22-first source / drain layer; 221-first source; 222-first drain; 23-first channel;

[0027] 3-second transistor; 31-second gate structure; 311-second work function layer; 32-second source / drain; 321-second source; 322-second drain; 33-second channel;

[0028] 41 -interface layer; 42 -gate dielectric layer; 43 -metal filling layer;

[0029] 5-semiconductor column; 51-channel layer; 52-sacrificial structure; 53-blank area;

[0030] 61-channel material layer; 62-sacrificial material layer; 63-fin structure; 64-sacrificial gate; 65-initial semiconductor column; 651-sacrificial layer; 66-internal isolation layer; 67-isolation structure; 68-insulating layer; 681-metal plug;

[0031] 71 - first protective layer; 72 - second protective layer. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0033] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0035] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0036] The present application embodiment provides a complementary field effect transistor. The structural schematic diagram of the complementary field effect transistor is as follows: Figures 1 to 3 As shown, it includes: a first transistor 2 and a second transistor 3 stacked on one side of a substrate 1; the first transistor 2 and the second transistor 3 have opposite conductivity types.

[0037] Along a first direction parallel to the substrate 1, the first transistor 2 includes a plurality of first channels 23 arranged between two first-layer source / drain electrodes 22, and a first gate structure 21 is arranged around the first channel 23; the second transistor 3 includes a plurality of second channels 33 arranged between two second-layer source / drain electrodes 32, and a second gate structure 31 is arranged around the second channel 33; along a second direction perpendicular to the substrate 1, any two gate structures among the plurality of first gate structures 21 and the plurality of second gate structures 31 are distributed at intervals.

[0038] The first gate structure 21 includes a first work function layer 211 , and the second gate structure 31 includes a second work function layer 311 ; the material of the first work function layer 211 and the material of the second work function layer 311 both include indium tin oxide.

[0039] In the related art, the materials of the first work function layer and the second work function layer are different. It is necessary to first manufacture the first work function layer in the first transistor, then remove the first work function layer in the second transistor, and then manufacture the second work function layer in the second transistor. This process requires additional deposition of an etch stop layer and a diffusion barrier layer, which will cause the thickness of the first gate structure of the first transistor and the second gate structure of the second transistor to increase, and cannot meet the manufacturing requirements of small-sized complementary field effect transistors.

[0040] In this embodiment, the material of the first work function layer 211 of the first transistor 2 and the material of the second work function layer 311 of the second transistor 3 are set to be the same material, so the work function material layers of the first transistor 2 and the second transistor 3 can be deposited at the same time, and the work function of the work function material layer is subsequently adjusted to match the work function of the work function material layer of the first transistor 2 with the conductivity type of the first transistor 2, and the work function of the work function material layer of the second transistor 3 with the conductivity type of the second transistor 3. Because the work function material layers of the first transistor 2 and the second transistor 3 can be deposited at the same time, there is no need to set an additional etching stop layer and a diffusion barrier layer, so the structure of the complementary field effect transistor of the present application is simpler, and the thickness of the first gate structure 21 of the first transistor 2 and the second gate structure 31 of the second transistor 3 can be reduced, and a small-sized complementary field effect transistor can be filled, meeting the manufacturing requirements of a small-sized complementary field effect transistor.

[0041] Moreover, the material of the first work function layer 211 of the first transistor 2 and the material of the second work function layer 311 of the second transistor 3 both include indium tin oxide, and different work functions can be obtained by adjusting the ratio of oxygen atoms to indium atoms in the indium tin oxide, which is beneficial to meeting the work function requirements of the first work function layer 211 and the second work function layer 311.

[0042] The atomic ratio described in this application or below can be understood as the ratio of the number of atoms, or the molar ratio, etc.

[0043] refer to Figure 1 A plurality of first channels 23 are arranged between two first-layer source / drain electrodes 22, and a first gate structure 21 is arranged between two adjacent first channels 23. A plurality of second channels 33 are arranged between two second-layer source / drain electrodes 32, and a second gate structure 31 is arranged between two adjacent second channels 33. Figure 1 , a plurality of first gate structures 21 are distributed at intervals, and a plurality of second gate structures 31 are distributed at intervals.

[0044] Optionally, the work function of the first work function layer 211 is not less than 4 electron volts and not more than 4.3 electron volts; the work function of the second work function layer 311 is not less than 4.75 electron volts and not more than 5.2 electron volts.

[0045] In this embodiment, the range of values ​​of the work function of the first work function layer 211 corresponds to an N-type field effect transistor; the range of values ​​of the work function of the second work function layer 311 corresponds to a P-type field effect transistor.

[0046] In order to reduce the threshold voltage of the complementary field effect transistor, the work function of the first work function layer 211 of the first transistor 2 needs to be close to the conduction band bottom of the first channel 23 , and the work function of the second work function layer 311 of the second transistor 3 needs to be close to the valence band top of the second channel 33 .

[0047] Optionally, the ratio of oxygen atoms to indium atoms in the indium tin oxide in the first work function layer 211 is different from the ratio of oxygen atoms to indium atoms in the indium tin oxide in the second work function layer 311 .

[0048] In this embodiment, the ratio of oxygen atoms to indium atoms in indium tin oxide in the first work function layer 211 is different from the ratio of oxygen atoms to indium atoms in indium tin oxide in the second work function layer 311 to obtain different work functions, which is beneficial for the work function of the work function material layer of the first transistor 2 to match the conductivity type of the first transistor 2, and the work function of the work function material layer of the second transistor 3 to match the conductivity type of the second transistor 3.

[0049] Optionally, the ratio of oxygen atoms to indium atoms in the indium tin oxide in the first work function layer 211 is smaller than the ratio of oxygen atoms to indium atoms in the indium tin oxide in the second work function layer 311 .

[0050] In this embodiment, the smaller the ratio of oxygen atoms to indium atoms in indium tin oxide, the smaller the work function. Therefore, the ratio of oxygen atoms to indium atoms in indium tin oxide in the first work function layer 211 is smaller than the ratio of oxygen atoms to indium atoms in indium tin oxide in the second work function layer 311, so that the work function of the first work function layer 211 is smaller than the work function of the second work function layer 311, and the work function of the first work function layer 211 is close to the bottom of the conduction band of the first channel 23, and the work function of the second work function layer 311 is close to the top of the valence band of the second channel 33.

[0051] Optionally, the ratio of oxygen atoms to indium atoms in indium tin oxide in the first work function layer 211 is greater than 0 and not greater than 1.34, and the ratio of oxygen atoms to indium atoms in indium tin oxide in the second work function layer 311 is not less than 1.45.

[0052] In this embodiment, the ratio of oxygen atoms to indium atoms in indium tin oxide in the first work function layer 211 is within the above range, which can satisfy that the work function of the first work function layer 211 is close to the bottom of the conduction band of the first channel 23; the ratio of oxygen atoms to indium atoms in indium tin oxide in the second work function layer 311 is within the above range, which can satisfy that the work function of the second work function layer 311 is close to the top of the valence band of the second channel 33, which is beneficial to reducing the threshold voltage of the semiconductor device.

[0053] Optionally, the first gate structure 21 also includes an interface layer 41, a gate dielectric layer 42 and a metal filling layer 43, the gate dielectric layer 42 is arranged between the interface layer 41 and the first work function layer 211; in the cross-section along the first direction, the cross-section of the interface layer 41, the gate dielectric layer 42 and the first work function layer 211 is annular; the metal filling layer 43 is arranged in the space enclosed by the annular first work function layer 211 and fills the space.

[0054] In this embodiment, reference Figure 1 and 2 In the cross-sectional view along the first direction, the cross-sections of the interface layer 41, the gate dielectric layer 42 and the first work function layer 211 in the first transistor 2 are annular, thereby improving the control capability of the first work function layer 211 over the first transistor 2. The metal filling layer 43 is disposed in the space enclosed by the annular first work function layer 211 and fills the space, which can facilitate the first work function layer 211 to be externally connected to other structures through the metal filling layer 43.

[0055] Optionally, the second gate structure 31 also includes an interface layer 41, a gate dielectric layer 42 and a metal filling layer 43, the gate dielectric layer 42 is arranged between the interface layer 41 and the second work function layer 311; the cross-sections of the interface layer 41, the gate dielectric layer 42 and the second work function layer 311 are annular; the metal filling layer 43 is arranged in the space enclosed by the annular second work function layer 311 and fills the space.

[0056] In this embodiment, reference Figure 1 and Figure 3 In the cross-sectional view along the first direction, the cross-section of the interface layer 41, the gate dielectric layer 42 and the second work function layer 311 in the second transistor 3 is annular, thereby improving the control capability of the second work function layer 311 over the second transistor 3. The metal filling layer 43 is disposed in the space enclosed by the annular second work function layer 311 and fills the space, which can facilitate the second work function layer 311 to be externally connected to other structures through the metal filling layer 43.

[0057] Optionally, the two first-layer source / drain electrodes 22 include a first drain electrode 222 and a first source electrode 221 , and the two second-layer source / drain electrodes 32 include a second drain electrode 322 and a second source electrode 321 .

[0058] The first source electrode 221 and the second source electrode 321 are stacked and insulated, and the first drain electrode 222 and the second drain electrode 322 are stacked and electrically connected.

[0059] In this embodiment, reference Figure 1 The first source electrode 221 and the second source electrode 321 are stacked and insulated, and the first drain electrode 222 and the second drain electrode 322 are stacked and electrically connected. The first drain electrode 222 and the second drain electrode 322 are electrically connected via a metal plug 681 .

[0060] Optionally, the material of the first source 221 and the material of the first drain 222 both include silicon germanium doped with boron atoms; the material of the second source 321 and the material of the second drain 322 both include silicon carbide doped with phosphorus atoms.

[0061] In this embodiment, the material of the first source 221 and the material of the first drain 222 both include silicon germanium doped with boron atoms, and the first source 221 and the first drain 222 correspond to N-type transistors; the material of the second source 321 and the material of the second drain 322 both include silicon carbide doped with phosphorus atoms, and the second source 321 and the second drain 322 correspond to P-type transistors.

[0062] Based on the same inventive concept, the present application embodiment provides a semiconductor device, the structural schematic diagram of the semiconductor device is shown in FIG. Fig.18 , comprising: a plurality of complementary field effect transistors provided by the above embodiments arranged in an array.

[0063] In this embodiment, the semiconductor device includes the complementary field effect transistor provided in the above embodiment, and the beneficial effects of the semiconductor device also include the beneficial effects of the complementary field effect transistor provided in the above embodiment, which will not be repeated here.

[0064] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes the semiconductor device provided by the above embodiment.

[0065] In the embodiments of the present application, since the electronic device adopts any one of the semiconductor devices provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0066] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.

[0067] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any one of the memories provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.

[0068] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a semiconductor device, and the flowchart of the manufacturing method is as follows: Figure 4 As shown, it includes the following steps S1 to S4:

[0069] S1: An array of semiconductor columns 5 is manufactured on one side of a substrate 1. The semiconductor column 5 includes channel layers 51 and sacrificial structures 52 alternately stacked along a second direction perpendicular to the substrate 1. A portion of the channel layer 51 is the first channel 23 of the first transistor 2, and another portion of the channel layer 51 is the second channel 33 of the second transistor 3.

[0070] In this embodiment, reference Fig.12 and Fig.13 The semiconductor column 5 includes alternately stacked channel layers 51 and sacrificial structures 52. A portion of the channel layer 51 can be used as the first channel 23 of the first transistor 2, and another portion of the channel layer 51 can be used as the second channel 33 of the second transistor 3. In this way, the first channel 23 and the second channel 33 can be manufactured at the same time, which is beneficial to shortening the process time and improving the process efficiency. Fig.12 The semiconductor pillars 5 arranged in an array are manufactured on one side of the substrate 1 . The semiconductor pillars 5 include a cross-sectional schematic diagram of channel layers 51 and sacrificial structures 52 alternately stacked along a second direction perpendicular to the substrate 1 .

[0071] Optionally, the material of the first channel 23 and the material of the second channel 33 may both include silicon. The material of the sacrificial structure 52 includes silicon germanium with a superlattice structure, so that the sacrificial structure 52 can be removed later without damaging the channel layer 51 .

[0072] S2: Along the first direction parallel to the substrate 1, two first-layer source and drain electrodes 22 insulated from the sacrificial structure 52 are manufactured at both ends of all the first channels 23; an insulating layer 68 is manufactured on the side of the first-layer source and drain electrodes 22 away from the substrate 1; along the first direction, two second-layer source and drain electrodes 32 insulated from the sacrificial structure 52 are manufactured at both ends of all the second channels 33; the second-layer source and drain electrodes 32, the insulating layer 68, and the first-layer source and drain electrodes 22 are successively approached to the substrate 1.

[0073] In this embodiment, reference Fig.13 A plurality of first channels 23 are arranged between the two first-layer source / drain electrodes 22 , and a plurality of second channels 33 are arranged between the two second-layer source / drain electrodes 32 . Fig.13 Two first-layer source / drain electrodes 22 insulated from the sacrificial structure 52 are manufactured at both ends of all first channels 23 along a first direction parallel to the substrate 1; an insulating layer 68 is manufactured on the side of the first-layer source / drain electrodes 22 away from the substrate 1; two second-layer source / drain electrodes 32 insulated from the sacrificial structure 52 are manufactured at both ends of all second channels 33 along the first direction; and a cross-sectional schematic diagram is obtained after the second-layer source / drain electrodes 32, the insulating layer 68, and the first-layer source / drain electrodes 22 are successively brought close to the substrate 1.

[0074] Optionally, in step S2, two first-layer source / drain electrodes 22 insulated from the sacrificial structure 52 are manufactured at both ends of all the first channels 23 along a first direction parallel to the substrate 1, including:

[0075] Along the first direction, a first drain 222 is epitaxially formed outside one end of all first channels 23 , and a first source 221 is epitaxially formed outside the other end. The two first source / drain layers 22 include a first drain 222 and a first source 221 .

[0076] In this embodiment, reference Fig.13 The two outer sections of each first channel 23 can be respectively formed into a first drain 222 and a first source 221 by epitaxy.

[0077] Optionally, in step S2 , an insulating layer 68 is manufactured on a side of the first source / drain 22 away from the substrate 1 , including: manufacturing an insulating layer 68 on both sides of the first drain 222 and the first source 221 away from the substrate 1 .

[0078] In this embodiment, reference Fig.13 The insulating layer 68 can block the first transistor 2 and the second transistor 3 from causing signal interference.

[0079] Optionally, in step S2, two second-layer source / drain electrodes 32 insulated from the sacrificial structure 52 are manufactured at both ends of all second channels 33 along the first direction, including:

[0080] A plurality of metal vias are fabricated in the insulating layer 68 above the first drain electrode 222, and metal plugs 681 are fabricated in the metal vias. Fig.13 Not shown, please refer to Figure 1 ).

[0081] A second drain 322 is formed epitaxially on the outer side of one end of all the second channels 33, and a second source 321 is formed epitaxially on the outer side of the other end. The two second-layer source / drain electrodes 32 include a second drain 322 and a second source 321, so that the second drain 322 is located on the side of the first drain 222 away from the substrate 1 and is electrically connected to the first drain 222 through the metal plug 681, and the second source 321 is located on the side of the first source 221 away from the substrate 1.

[0082] In this embodiment, reference Fig.13 The second drain 322 and the second source 321 can be formed by epitaxy at both ends of each second channel 33. The first drain 222, the insulating layer and the second drain 322 are stacked, and the first drain 222 and the second drain 322 are electrically connected to each other for signal transmission.

[0083] S3 : removing each sacrificial structure 52 to form a blank area 53 ; manufacturing a first gate structure 21 including a first work function layer 211 in the blank area 53 between two adjacent channel layers 51 .

[0084] In this embodiment, Fig.14 This is a schematic cross-sectional view obtained after removing each sacrificial structure 52 to form a blank area 53 . Fig.15 FIG. 5 is a cross-sectional view of a first gate structure 21 including a first work function layer 211 formed in a blank region 53 between two adjacent channel layers 51 . Fig.14 and 15 After removing each sacrificial structure 52, a blank area 53 is formed between two adjacent channel layers 51, and a first gate structure 21 is manufactured in the blank area 53 between two adjacent channel layers 51 (including two adjacent first channels 23, two adjacent second channels 33, and two adjacent first channels 23 and second channels 33).

[0085] Optionally, in step S3 , a first gate structure 21 including a first work function layer 211 is manufactured in the blank area 53 between two adjacent channel layers 51 , including: sequentially manufacturing an annular interface layer 41 , a gate dielectric layer 42 and a first work function layer 211 in the blank area 53 between two adjacent channel layers 51 .

[0086] In this embodiment, reference Figure 2 and Fig.15 , an annular interface layer 41, a gate dielectric layer 42 and a first work function layer 211 are manufactured between any two adjacent channel layers 51, and the second work function layer 311 is obtained by subsequently adjusting the ratio of oxygen atoms to indium atoms in the indium tin oxide of the first work function layer 211 of the second transistor 3.

[0087] S4: Covering the outer side of each first gate structure 21 of the first transistor 2 with a first protective layer 71 ; under the protection of the first protective layer 71 , adjusting the work function of the first work function layer 211 in the first gate structure 21 of the second transistor 3 to obtain a second gate structure 31 including a second work function layer 311 .

[0088] In this embodiment, under the protection of the first protective layer 71, the work function required by the second work function layer 311 corresponding to the second transistor 3 can be obtained by adjusting the ratio of oxygen atoms to indium atoms in indium tin oxide. This process does not require additional etching of the first work function layer 211 in the second transistor 3. The first gate structure 21 and the second gate structure 31 of the present application have simpler structures and thinner thicknesses, which is conducive to being suitable for small-sized semiconductor devices. Fig.16 It is a schematic cross-sectional view obtained after the outer sides of each first gate structure 21 of the first transistor 2 are covered with a first protection layer 71 .

[0089] Optionally, in step S4, under the protection of the first protective layer 71, the work function of the first work function layer 211 in the first gate structure 21 of the second transistor 3 is adjusted to obtain a second gate structure 31 including a second work function layer 311, including:

[0090] The entire substrate 1 having the first protective layer 71 is annealed in an oxygen-containing atmosphere to adjust the ratio of oxygen atoms to indium atoms in the first work function layer 211 of the second transistor 3 until it is converted into a second work function layer 311, thereby obtaining a second gate structure 31 including the second work function layer 311.

[0091] In this embodiment, the entire substrate 1 is annealed in an oxygen-containing atmosphere, so that the ratio of oxygen atoms to indium atoms in indium tin oxide in the first work function layer 211 is directly converted into the ratio of oxygen atoms to indium atoms required by the second work function layer 311, so as to obtain different work functions, which is conducive to matching the work function of the work function material layer of the first transistor 2 with the conductivity type of the first transistor 2, and matching the work function of the work function material layer of the second transistor 3 with the conductivity type of the second transistor 3. Specifically, the oxygen in the oxygen-containing atmosphere includes ozone.

[0092] Optionally, after step S4 , the method further includes: removing the first protective layer 71 , and manufacturing respective metal filling layers 43 in the space enclosed by the annular first work function layer 211 and the space enclosed by the annular second work function layer 311 .

[0093] In this embodiment, Fig.17 The cross-sectional schematic diagram is obtained by adjusting the work function of the first work function layer 211 in the first gate structure 21 of the second transistor 3 under the protection of the first protection layer 71 to obtain the second gate structure 31 including the second work function layer 311 and removing the first protection layer 71. Fig.18 It is a schematic cross-sectional view obtained after manufacturing respective metal filling layers 43 in the space enclosed by the annular first work function layer 211 and the space enclosed by the annular second work function layer.

[0094] Optionally, before manufacturing the semiconductor pillars 5 arranged in an array on one side of the substrate 1 in step S1, wherein the semiconductor pillars 5 include channel layers 51 and sacrificial structures 52 alternately stacked along a second direction perpendicular to the substrate 1, the method further includes:

[0095] Along a second direction perpendicular to the substrate 1 , alternately arranged channel material layers 61 and sacrificial material layers 62 are manufactured on one side of the substrate 1 ; each channel material layer 61 and each sacrificial material layer 62 is patterned to obtain an array-arranged fin structure 63 .

[0096] A sacrificial gate 64 is formed; along a third direction parallel to the substrate 1 and perpendicular to the first direction, the sacrificial gate 64 covers the fin structures 63 in the same row and the gaps between any two adjacent fin structures 63; along the first direction, the sacrificial gate 64 covers a partial area of ​​the fin structure 63.

[0097] The fin structure 63 exposed outside the sacrificial gate 64 is removed to form initial semiconductor columns 65 arranged in an array. The initial semiconductor columns 65 include stacked channel layers 51 and sacrificial layers 651 .

[0098] In this embodiment, Figure 5 The cross-sectional schematic diagram is obtained after manufacturing the alternately arranged channel material layer 61 and the sacrificial material layer 62 on one side of the substrate 1 along the second direction perpendicular to the substrate 1. The material of the channel material layer 61 may include silicon, and the material of the sacrificial material layer 62 may be silicon germanium with a superlattice structure, which can facilitate the alternating stacking of silicon and silicon germanium without interfering with each other. Figure 6 A cross-sectional schematic diagram is shown after patterning each channel material layer 61 and each sacrificial material layer 62 to obtain an array-arranged fin structure 63 .

[0099] Fig. 9 To form a sacrificial gate 64 ; a cross-sectional schematic diagram is shown after the sacrificial gate 64 covers each fin structure 63 in the same row and the gap between any two adjacent fin structures 63 along a third direction parallel to the substrate 1 and perpendicular to the first direction. Fig.10 1 is a schematic cross-sectional view obtained after the sacrificial gate 64 covers a portion of the fin structure 63 along the first direction. The material of the sacrificial gate 64 may include polysilicon.

[0100] Fig.11 The fin structure 63 exposed outside the sacrificial gate 64 is removed to form an array of initial semiconductor columns 65 . The initial semiconductor columns 65 include a stacked channel layer 51 and a sacrificial layer 651 .

[0101] Optionally, after patterning each channel material layer 61 and each sacrificial material layer 62 to obtain an array-arranged fin structure 63 and before forming the sacrificial gate 64, the method further includes:

[0102] Along the third direction, an isolation structure 67 is manufactured in a gap between two adjacent fin structures 63 and located in the substrate 1 .

[0103] In this embodiment, Figure 7 It is a cross-sectional schematic diagram obtained after manufacturing an isolation structure 67 in a gap between two adjacent fin structures 63 and located in the substrate 1 along the third direction. Figure 8 It is a cross-sectional schematic diagram along the first direction after an isolation structure 67 is manufactured in a gap between two adjacent fin structures 63 and located in the substrate 1 .

[0104] Optionally, after forming the sacrificial gate 64 and before removing the fin structure 63 exposed outside the sacrificial gate 64 and forming the initial semiconductor pillars 65 arranged in an array, the method further includes:

[0105] A second protection layer 72 is formed on both sides of the sacrificial gate 64 along the first direction.

[0106] In this embodiment, reference Fig.10 The second protective layer 72 can prevent a short circuit between the second gate structure 31 and the second source / drain 32 that are subsequently manufactured. The material of the second protective layer 72 can be silicon dioxide or silicon nitride. Fig.10 Schematic cross-sectional view of a second protection layer 72 formed on both sides of the sacrificial gate 64 along the first direction.

[0107] Optionally, in step S1, semiconductor columns 5 arranged in an array are manufactured on one side of the substrate 1, and the semiconductor columns 5 include channel layers 51 and sacrificial structures 52 alternately stacked along a second direction perpendicular to the substrate 1, including:

[0108] Along the first direction, partial structures on both sides of the sacrificial layer 651 are removed to form a sacrificial structure 52 .

[0109] An inner isolation layer 66 is manufactured in the blank areas on both sides of the sacrificial structure 52 to obtain a semiconductor column 5 .

[0110] In this embodiment, Fig.12 A schematic cross-sectional view of the semiconductor column 5 is shown in FIG. 5 , in which a portion of the structure on both sides of the sacrificial layer 651 is removed along the first direction to form a sacrificial structure 52, and an inner isolation layer 66 is manufactured in the blank areas on both sides of the sacrificial structure 52. The inner isolation layer 66 is used to prevent short circuits between the first gate structure 21 and the two first-layer source / drain electrodes 22, and between the second gate structure 31 and the two second-layer source / drain electrodes 32.

[0111] Optionally, the orthographic projections of the sacrificial structure 52 and the inner isolation layer 66 located on both sides of the sacrificial structure 52 on the substrate 1 coincide with the orthographic projection of the channel layer 51 on the substrate 1 .

[0112] Optionally, in step S2, two first-layer source / drain electrodes 22 insulated from the sacrificial structure 52 are manufactured at both ends of all first channels 23 along a first direction parallel to the substrate 1, including:

[0113] Along the first direction, two first-layer source / drain electrodes 22 are manufactured at both ends of each first channel 23 and at both sides of each inner isolation layer 66 adjacent to each first channel 23 away from the sacrificial layer 651 .

[0114] In this embodiment, the first source / drain electrode 22 can cover the first channel 23 and two outer side surfaces of the inner isolation layer 66 along the second direction.

[0115] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0116] 1. In the embodiment of the present application, the material of the first work function layer of the first transistor and the material of the second work function layer of the second transistor are set to the same material, so the work function material layers of the first transistor and the second transistor can be deposited simultaneously, and the work function of the work function material layer is subsequently adjusted to match the work function of the work function material layer of the first transistor with the conductivity type of the first transistor, and the work function of the work function material layer of the second transistor with the conductivity type of the second transistor 3. Because the work function material layers of the first transistor and the second transistor can be deposited simultaneously, there is no need to set an additional etching stop layer and a diffusion barrier layer, so the structure of the complementary field effect transistor of the present application is simpler, and the thickness of the first gate structure of the first transistor and the second gate structure of the second transistor can be reduced, and a small-sized complementary field effect transistor can be filled, meeting the manufacturing requirements of a small-sized complementary field effect transistor.

[0117] 2. In the embodiment of the present application, the material of the first work function layer of the first transistor and the material of the second work function layer of the second transistor both include indium tin oxide. Different work functions can be obtained by adjusting the ratio of oxygen atoms to indium atoms in the indium tin oxide, which is beneficial to meeting the work function requirements of the first work function layer and the second work function layer.

[0118] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0119] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0120] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0121] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0122] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0123] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be executed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0124] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A complementary field effect transistor, characterized in that: include: A first transistor and a second transistor are stacked on one side of the substrate; Along a first direction parallel to the substrate, the first transistor includes a plurality of first channels arranged between two first-layer source / drain electrodes, and a first gate structure is arranged around the first channels; the second transistor includes a plurality of second channels arranged between two second-layer source / drain electrodes, and a second gate structure is arranged around the second channels; along a second direction perpendicular to the substrate, any two gate structures among the plurality of the first gate structures and the plurality of the second gate structures are distributed at intervals; The first gate structure includes a first work function layer, and the second gate structure includes a second work function layer; the material of the first work function layer and the material of the second work function layer both include indium tin oxide.

2. The complementary field effect transistor according to claim 1, characterized in that: The ratio of oxygen atoms to indium atoms in indium tin oxide in the first work function layer is different from the ratio of oxygen atoms to indium atoms in indium tin oxide in the second work function layer.

3. The complementary field effect transistor according to claim 2, characterized in that: The ratio of oxygen atoms to indium atoms in indium tin oxide in the first work function layer is smaller than the ratio of oxygen atoms to indium atoms in indium tin oxide in the second work function layer.

4. The complementary field effect transistor according to claim 1, characterized in that: The first gate structure also includes an interface layer, a gate dielectric layer and a metal filling layer, wherein the gate dielectric layer is arranged between the interface layer and the first work function layer; in the cross-section along the first direction, the cross-sections of the interface layer, the gate dielectric layer and the first work function layer are annular; the metal filling layer is arranged in the space enclosed by the annular first work function layer and fills the space.

5. The complementary field effect transistor according to claim 1, characterized in that: The two first source / drain electrodes include a first drain electrode and a first source electrode, and the two second source / drain electrodes include a second drain electrode and a second source electrode; The first source electrode and the second source electrode are stacked and insulated, and the first drain electrode and the second drain electrode are stacked and electrically connected.

6. The complementary field effect transistor according to claim 5, characterized in that: The material of the first source electrode and the material of the first drain electrode both include silicon germanium doped with boron atoms; the material of the second source electrode and the material of the second drain electrode both include silicon carbide doped with phosphorus atoms.

7. A semiconductor device, characterized in that: The invention comprises a plurality of complementary field effect transistors as claimed in any one of claims 1 to 6 arranged in an array.

8. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 7.

9. A method for manufacturing a semiconductor device, characterized in that: include: Manufacturing semiconductor columns arranged in an array on one side of the substrate, wherein the semiconductor columns include channel layers and sacrificial structures alternately stacked along a second direction perpendicular to the substrate, a portion of the channel layers being a first channel of a first transistor, and another portion of the channel layers being a second channel of a second transistor; Two first-layer source / drain electrodes insulated from the sacrificial structure are manufactured at both ends of all the first channels along a first direction parallel to the substrate; an insulating layer is manufactured on a side of the first-layer source / drain electrodes away from the substrate; Two second-layer source / drain electrodes insulated from the sacrificial structure are manufactured at both ends of all second channels along the first direction; the second-layer source / drain electrodes, the insulating layer, and the first-layer source / drain electrodes are sequentially close to the substrate; Removing each of the sacrificial structures to form a blank area; manufacturing a first gate structure including a first work function layer in the blank area between two adjacent channel layers; A first protective layer is covered on the outer side of each first gate structure of the first transistor; under the protection of the first protective layer, the work function of the first work function layer in the first gate structure of the second transistor is adjusted to obtain a second gate structure including a second work function layer.

10. The manufacturing method according to claim 9, characterized in that: Under the protection of the first protective layer, adjusting the work function of the first work function layer in the first gate structure of the second transistor to obtain a second gate structure including the second work function layer, comprising: The entire substrate having the first protective layer is annealed in an oxygen-containing atmosphere to adjust the ratio of oxygen atoms to indium atoms in the first work function layer of the second transistor until it is converted into a second work function layer, thereby obtaining a second gate structure including the second work function layer.

11. The manufacturing method according to claim 9, characterized in that: A first gate structure including a first work function layer is manufactured in a blank area between two adjacent channel layers, comprising: In a blank area between two adjacent channel layers, a ring-shaped interface layer, a gate dielectric layer and the first work function layer are sequentially manufactured; And, under the protection of the first protective layer, adjusting the work function of the first work function layer in the first gate structure of the second transistor to obtain the second gate structure including the second work function layer, further comprising: The first protective layer is removed, and respective metal filling layers are manufactured in the space enclosed by the annular first work function layer and in the space enclosed by the annular second work function layer.

12. The manufacturing method according to claim 9, characterized in that: Before manufacturing semiconductor columns arranged in an array on one side of the substrate, wherein the semiconductor columns include channel layers and sacrificial structures alternately stacked along a second direction perpendicular to the substrate, the method further includes: Manufacturing alternately arranged channel material layers and sacrificial material layers on one side of the substrate along a second direction perpendicular to the substrate; patterning each of the channel material layers and each of the sacrificial material layers to obtain an array-arranged fin structure; forming a sacrificial gate; along a third direction parallel to the substrate and perpendicular to the first direction, the sacrificial gate covers each of the fin structures in the same row and a gap between any two adjacent fin structures; along the first direction, the sacrificial gate covers a partial area of ​​the fin structure; The fin structure exposed outside the sacrificial gate is removed to form initial semiconductor columns arranged in an array, wherein the initial semiconductor columns include stacked channel layers and sacrificial layers.

13. The manufacturing method according to claim 12, characterized in that: An array of semiconductor columns is manufactured on one side of the substrate, wherein the semiconductor columns include channel layers and sacrificial structures alternately stacked along a second direction perpendicular to the substrate, including: Along the first direction, removing part of the structure on both sides of the sacrificial layer to form the sacrificial structure; An inner isolation layer is manufactured in the blank areas on both sides of the sacrificial structure to obtain the semiconductor column.

14. The manufacturing method according to claim 9, characterized in that: Two first-layer source / drain electrodes insulated from the sacrificial structure are manufactured at both ends of all the first channels along a first direction parallel to the substrate, including: Along the first direction, a first drain is formed by epitaxy at one end of all the first channels, and a first source is formed by epitaxy at the other end, wherein the two first-layer source / drain electrodes include the first drain and the first source; And, manufacturing an insulating layer on a side of the first source / drain layer away from the substrate, comprising: Manufacturing an insulating layer on the first drain and the first source both at a side away from the substrate; And, along the first direction, at both ends of all the second channels, two second-layer source / drain electrodes insulated from the sacrificial structure are manufactured, including: Manufacturing a plurality of metal vias in the insulating layer above the first drain electrode, and manufacturing metal plugs in the metal vias; A second drain is formed epitaxially on the outer side of one end of all the second channels, and a second source is formed epitaxially on the outer side of the other end. The two second-layer source / drain electrodes include the second drain and the second source, so that the second drain is located on the side of the first drain away from the substrate and is electrically connected to the first drain through the metal plug, and the second source is located on the side of the first source away from the substrate.

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