A LDMOS device and a method for manufacturing the same

Abstract

The present invention provides an LDMOS device and a preparation method thereof, the device comprising a first substrate, a gate, a drain, a source and a field plate region; wherein the gate and the field plate region are arranged on the upper surface of the first substrate; a channel region is formed in the first substrate below the gate, and a drift region is formed in the first substrate below the field plate region; the source is arranged in the channel region; the drain is arranged in the drift region; a step-type buried oxide structure is arranged below the channel region and the drift region, and a sawtooth structure is arranged at the contact position between the drift region and the field plate region. The LDMOS device provided by the present invention can regulate the electric field of the LDMOS device by arranging a step-type buried oxide structure below the channel region and the drift region, and arranging a sawtooth structure at the contact position between the drift region and the field plate region, so that the electric field distribution inside the device is more uniform, and at the same time, the electric field peak can be effectively reduced to improve the voltage resistance performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] LDMOS devices are widely used and studied in PMIC (Power Management IC) circuits. The structure of a typical LDMOS device in the 12V~40V range can be found in Figure 1 At present, all the mature LDMOS devices adopt similar structures, including field plate T, polysilicon gate O, P-type channel region M, drift region N and substrate X. When facing different withstand voltage requirements, the LDMOS device structure is generally implemented by adjusting the size, including adjusting the channel length a, the coverage distance b between the field plate T and the polysilicon gate O, and the extension distance c of the field plate. For example, for a 16V LDMOS device, the size of a is generally about 0.5um, the size of b is about 0.7um, and the size of c is about 0.8um.

[0003] However, as the source-drain withstand voltage requirements increase, the distance and size of a, b, and c cannot be increased indefinitely. Moreover, simply increasing the above distances will also lead to a corresponding linear increase in the on-resistance of the source and drain. Therefore, existing LDMOS devices cannot meet the high source-drain withstand voltage requirements. Summary of the invention

[0004] The present invention aims to provide an LDMOS device and a preparation method thereof to solve the above-mentioned technical problems. By setting a stepped buried oxide structure under the channel region and the drift region, and setting a sawtooth structure at the contact position between the drift region and the field plate region, the electric field of the LDMOS device can be regulated, thereby effectively improving the voltage resistance performance of the device.

[0005] In order to solve the above technical problems, the present invention provides an LDMOS device, including a first substrate, a gate, a drain, a source and a field plate region; wherein the gate and the field plate region are arranged on the upper surface of the first substrate; a channel region is formed in the first substrate below the gate, and a drift region is formed in the first substrate below the field plate region; the source is arranged in the channel region; the drain is arranged in the drift region; a stepped buried oxide structure is arranged below the channel region and the drift region, and a sawtooth structure is arranged at the contact position between the drift region and the field plate region.

[0006] The above scheme can regulate the electric field of the LDMOS device by setting a stepped buried oxide structure under the channel region and the drift region, and setting a sawtooth structure at the contact position between the drift region and the field plate region, so that the electric field distribution inside the device is more uniform, and at the same time, it can effectively reduce the electric field peak and improve the voltage resistance performance of the device.

[0007] Furthermore, the stepped buried oxide structure includes a first buried oxide layer and a second buried oxide layer which are connected; the first buried oxide layer is arranged below the channel region, and the second buried oxide layer is arranged below the drift region.

[0008] In the above scheme, the first buried oxide layer is thicker than the second buried oxide layer, and the connecting part of the first buried oxide layer and the second buried oxide layer can have a certain inclination angle, and the typical value of the inclination angle is 45°. Therefore, the transition from the second buried oxide layer to the first buried oxide layer is gradual, that is, the internal electric field distribution is smooth and uniform after power is turned on. This scheme can effectively reduce the electric field peak of the device, so that the device has a higher breakdown voltage and improves the voltage resistance of the device.

[0009] Furthermore, the sawtooth structure includes a plurality of V-shaped grooves with a certain inclination angle, and the depths of the plurality of V-shaped grooves gradually become shallower from the source to the drain. That is, the sawtooth structure is formed by a plurality of V-shaped grooves arranged left and right.

[0010] Furthermore, a first polycrystalline structure is disposed on the gate; and a second polycrystalline structure is disposed on the field plate region.

[0011] In the above scheme, the first polycrystalline structure of the gate plays the role of the channel of the device, and the second polycrystalline structure of the field plate region plays the role of the adjustable field plate of the device, thereby reducing the difficulty of the production process, improving the voltage resistance adjustability of the LDMOS device, and reducing the on-resistance of the device.

[0012] Compared with the existing LDMOS devices with LOCOS field plates and CFP (contact hole field plates) structures, the LDMOS device provided by the above solution has better field plate modulation capability, can obtain lower specific on-resistance and better voltage resistance.

[0013] The present invention provides a method for preparing an LDMOS device, comprising the following steps:

[0014] Determining a first substrate, and providing a stepped buried oxide structure in the first substrate;

[0015] Etching a sawtooth structure on the upper surface of the first substrate;

[0016] forming a drift region at the sawtooth structure, and forming a channel region at a lateral position of the drift region;

[0017] A drain is arranged in the drift region, a source is arranged in the channel region, and a gate and a field plate region are arranged on the upper surface of the first substrate;

[0018] Wherein, the sawtooth structure is arranged at a contact position between the drift region and the field plate region.

[0019] The method provided by the above scheme can quickly, effectively and at low cost prepare an LDMOS device. The device sets a stepped buried oxide structure under the channel region and the drift region, and sets a sawtooth structure at the contact position between the drift region and the field plate region. The electric field of the LDMOS device can be regulated, so that the electric field distribution inside the device is more uniform, and the electric field peak can be effectively reduced, thereby improving the voltage resistance performance of the device.

[0020] Further, the determining of the first substrate and providing a stepped buried oxide structure in the first substrate are specifically:

[0021] Determining a first wafer, and growing an oxide layer on the first wafer;

[0022] Etching the oxide layer to form a stepped buried oxide structure;

[0023] A second wafer is determined, and the second wafer is turned upside down and bonded to the first wafer at the stepped buried oxide structure to form a first substrate.

[0024] The first substrate determination method provided by the above scheme has a simple process and low cost, which can reduce the device preparation cost; and facilitates subsequent ion doping processes and improves the accuracy of doping, that is, it can simply improve the quality of the drift region and the channel region.

[0025] Further, etching a sawtooth structure on the upper surface of the first substrate is specifically:

[0026] A plurality of V-shaped grooves with a certain inclination angle are sequentially etched on the upper surface of the first substrate by dry etching, wherein the depth of the plurality of V-shaped grooves gradually decreases from the source to the drain; and the plurality of V-shaped grooves constitute the sawtooth structure.

[0027] Further, forming a drift region at the sawtooth structure and forming a channel region at a lateral position of the drift region is specifically:

[0028] Performing ion implantation doping at the sawtooth structure layer to form a drift region;

[0029] Performing ion implantation doping in the first substrate and at a lateral position of the drift region to form a channel region;

[0030] Wherein: the channel region is doped with ions having a conductivity type opposite to that of the drift region.

[0031] Furthermore, the gate and field plate regions are provided on the upper surface of the first substrate, specifically:

[0032] forming a field plate thick gate oxide layer on the upper surface of the first substrate;

[0033] Delimiting a thin gate oxide region on the field plate thick gate oxide layer and etching the field plate thick gate oxide layer in the thin gate oxide region to the surface of the first substrate;

[0034] forming a gate thin gate oxide layer in the thin gate oxide region;

[0035] A field plate region is arranged on the field plate thick gate oxide layer, and a gate is arranged on the gate thin gate oxide layer.

[0036] In the above scheme, the gate is independently arranged on the gate thin oxide layer, and has no overlapping part with the field plate region. The structure obtained by this arrangement has a higher gate control capability, so that the device has a lower on-resistance.

[0037] Furthermore, a first polycrystalline structure is disposed on the gate; and a second polycrystalline structure is disposed on the field plate region. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a typical LDMOS device structure provided as the background technology of the present invention;

[0039] Figure 2 A schematic diagram of the structure of an LDMOS device provided by an embodiment of the present invention;

[0040] Figure 3 A schematic flow chart of a method for preparing an LDMOS device provided in one embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the structure of a first LDMOS device provided by an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of the structure of a second LDMOS device provided by an embodiment of the present invention;

[0043] Figure 6 A schematic diagram of a third LDMOS device structure provided by an embodiment of the present invention;

[0044] Figure 7 A schematic diagram of a fourth LDMOS device structure provided by an embodiment of the present invention;

[0045] Figure 8 A schematic diagram of a fifth LDMOS device structure provided by an embodiment of the present invention;

[0046] Fig. 9 A sixth LDMOS device structure schematic diagram provided by an embodiment of the present invention;

[0047] Fig.10 A schematic diagram of a seventh LDMOS device structure provided by an embodiment of the present invention;

[0048] Fig.11 A schematic diagram of the structure of an eighth LDMOS device provided by an embodiment of the present invention;

[0049] Fig.12 A schematic diagram of a simulation structure of an LDMOS device provided by an embodiment of the present invention;

[0050] Fig.13 A schematic diagram of a current path of a simulation structure of an LDMOS device in an off state provided by an embodiment of the present invention;

[0051] Fig.14 A schematic diagram of a current path of a simulation structure of an LDMOS device in an on state provided by an embodiment of the present invention;

[0052] Fig.15 A schematic diagram of a simulation result of electric field distribution of an LDMOS device provided by an embodiment of the present invention;

[0053] Fig.16 A curve diagram of simulation results of an LDMOS device provided by an embodiment of the present invention;

[0054] Fig.17 A schematic diagram of a simulation result of an electric potential below a field plate region of an LDMOS device provided by an embodiment of the present invention;

[0055] Fig.18 A curve diagram of a potential simulation result below a field plate region of an LDMOS device provided by an embodiment of the present invention;

[0056] Among them: 1. first substrate; 101. first wafer; 102. second wafer surface; 103. buried oxide layer; 104. second wafer back; 2. stepped buried oxide structure; 3. channel region; 4. drift region; 5. drain; 6. source; 7. field plate region; 71. second polycrystalline structure; 8. gate; 81. first polycrystalline structure; 9. sawtooth structure; 10. photomask; 11. silicon film; 12. field plate thick gate oxide layer; 13. gate thin gate oxide layer; 14. polycrystalline layer; 15. side wall. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] See also Figure 2The present embodiment provides an LDMOS device, comprising a first substrate 1, a gate 8, a drain 5, a source 6 and a field plate region 7; wherein the gate 8 and the field plate region 7 are arranged on the upper surface of the first substrate 1; a channel region 3 is formed in the first substrate 1 below the gate 8, and a drift region 4 is formed in the first substrate 1 below the field plate region 7; the source 6 is arranged in the channel region 3; the drain 5 is arranged in the drift region 4; a stepped buried oxide structure 2 is arranged below the channel region 3 and the drift region 4, and a sawtooth structure 9 is arranged at the contact position between the drift region 4 and the field plate region 7.

[0059] In this embodiment, by setting a stepped buried oxide structure 2 below the channel region 3 and the drift region 4 and setting a sawtooth structure 9 at the contact position between the drift region 4 and the field plate region 7, the electric field of the LDMOS device can be regulated, so that the electric field distribution inside the device is more uniform, and the electric field peak can be effectively reduced, thereby improving the voltage resistance performance of the device.

[0060] Furthermore, the stepped buried oxide structure 2 includes a first buried oxide layer and a second buried oxide layer which are connected; the first buried oxide layer is arranged below the channel region 3 , and the second buried oxide layer is arranged below the drift region 4 .

[0061] In this embodiment, the first buried oxide layer is thicker than the second buried oxide layer, and the connecting part of the first buried oxide layer and the second buried oxide layer can have a certain inclination angle, and the typical value of the inclination angle is 45°. Therefore, the transition from the second buried oxide layer to the first buried oxide layer is gradual, that is, the internal electric field distribution is smooth and uniform after power is turned on. This scheme can effectively reduce the electric field peak of the device, so that the device has a higher breakdown voltage and improves the voltage resistance performance of the device.

[0062] Furthermore, the sawtooth structure 9 includes a plurality of V-shaped grooves with a certain inclination angle, and the depths of the V-shaped grooves gradually decrease from the source 6 to the drain 5. That is, the sawtooth structure 9 is formed by a plurality of V-shaped grooves arranged left and right.

[0063] Furthermore, a first polycrystalline structure 81 is disposed on the gate 8 , and a second polycrystalline structure 71 is disposed on the field plate region 7 .

[0064] In this embodiment, the first polycrystalline structure 81 of the gate 8 plays the role of a channel of the device, and the second polycrystalline structure 71 of the field plate region 7 plays the role of an adjustable field plate of the device, thereby reducing the difficulty of the production process, improving the voltage resistance adjustability of the LDMOS device, and reducing the on-resistance of the device.

[0065] Compared with the existing LDMOS devices with LOCOS field plates and CFP (contact hole field plates) structures, the LDMOS device provided in this embodiment has better field plate modulation capability, can obtain lower specific on-resistance and better voltage resistance.

[0066] See also Figure 3 This embodiment provides a method for preparing an LDMOS device, comprising the following steps:

[0067] S1: determining a first substrate 1, and providing a stepped buried oxide structure 2 in the first substrate 1;

[0068] S2: etching a sawtooth structure 9 on the upper surface of the first substrate 1;

[0069] S3: forming a drift region 4 at the sawtooth structure 9, and forming a channel region 3 at a lateral position of the drift region 4;

[0070] S4: a drain 5 is provided in the drift region 4 and a source 6 is provided in the channel region 3, and a gate 8 and a field plate region 7 are provided on the upper surface of the first substrate 1;

[0071] The sawtooth structure 9 is disposed at a contact position between the drift region 4 and the field plate region 7 .

[0072] The preparation method provided in this embodiment can prepare an LDMOS device quickly, effectively and at low cost. The device sets a stepped buried oxide structure 2 below the channel region 3 and the drift region 4, and sets a sawtooth structure 9 at the contact position between the drift region 4 and the field plate region 7. The electric field of the LDMOS device can be regulated to make the electric field distribution inside the device more uniform, and the electric field peak can be effectively reduced to improve the voltage resistance performance of the device.

[0073] Furthermore, the first substrate 1 is determined, and a stepped buried oxide structure 2 is provided in the first substrate 1, specifically:

[0074] Determining a first wafer 101, and growing an oxide layer on the first wafer 101;

[0075] Etching the oxide layer to form a stepped buried oxide structure 2;

[0076] A second wafer is determined, and the second wafer is turned upside down and bonded to the first wafer 101 at the stepped buried oxide structure 2 to form a first substrate 1 .

[0077] In this embodiment, the second wafer is preset with a buried oxide layer 103. In the actual bonding process, the second wafer needs to be inverted and peeled off at the interface of the buried oxide layer 103, and then the second wafer surface 102 is bonded to the first wafer 101 surface. After bonding, the buried oxide layer 103 on the surface of the first substrate 1 needs to be cleaned. This method has simple process and low cost, which can reduce the preparation cost of the device; and it is convenient for subsequent processes to perform ion doping and improve the accuracy of doping, that is, it can simply improve the quality of the drift region 4 and the channel region 3.

[0078] Further, the etching of the sawtooth structure 9 on the upper surface of the first substrate 1 is specifically as follows:

[0079] By dry etching, a plurality of V-shaped grooves with a certain inclination angle are sequentially etched on the upper surface of the first substrate 1 , and the depth of the plurality of V-shaped grooves gradually decreases from the source 6 to the drain 5 ; the plurality of V-shaped grooves constitute the sawtooth structure 9 .

[0080] Further, the drift region 4 is formed at the sawtooth structure 9, and the channel region 3 is formed at the lateral position of the drift region 4, specifically:

[0081] Ion implantation is performed at the sawtooth structure 9 to form a drift region 4;

[0082] Performing ion implantation in the first substrate 1 and at a lateral position of the drift region 4 to form a channel region 3;

[0083] Wherein: the channel region 3 is doped with ions having a conductivity type opposite to that of the drift region 4 .

[0084] Furthermore, the gate 8 and the field plate region 7 are provided on the upper surface of the first substrate 1, specifically:

[0085] Forming a field plate thick gate oxide layer 12 on the upper surface of the first substrate 1;

[0086] Delimiting a thin gate oxide region on the field plate thick gate oxide layer 12 and etching the field plate thick gate oxide layer 12 in the thin gate oxide region to the surface of the first substrate 1;

[0087] Forming a gate thin gate oxide layer 13 in the thin gate oxide region;

[0088] A field plate region 7 is disposed on the field plate thick gate oxide layer 12 , and a gate electrode 8 is disposed on the gate thin gate oxide layer 13 .

[0089] In this embodiment, the gate 8 is independently arranged on the gate thin oxide layer 13, and has no overlapping part with the field plate region 7. The structure obtained by this arrangement has a higher gate control capability, so that the device has a lower on-resistance.

[0090] Furthermore, a first polycrystalline structure 81 is disposed on the gate 8 , and a second polycrystalline structure 71 is disposed on the field plate region 7 .

[0091] In this embodiment, the device uses the first polycrystalline structure 81 of the gate 8 to play the channel role of the device, and uses the second polycrystalline structure 71 of the field plate region 7 to play the adjustable field plate role of the device, thereby reducing the difficulty of the production process, improving the voltage resistance adjustability of the LDMOS device, and reducing the on-resistance of the device.

[0092] In order to further illustrate the technical features of the LDMOS device manufacturing process proposed in the present invention and highlight its technical advantages, this embodiment further illustrates its manufacturing process in conjunction with the accompanying drawings.

[0093] Step 1: determine the first wafer 101 and grow an oxide layer (typical value is 10000 Å) on the crystal surface of the first wafer 101 .

[0094] Step 2: Protect the first buried oxide layer region by using the photomask 10, and etch the second buried oxide layer region by using an etching method until the region is etched into an inclination angle of about 2000A, with a typical etching angle of 45 degrees.

[0095] Step 3: See Figure 4 , determine the second wafer (preset with a buried oxide layer 103), invert the second wafer, and partially peel off the second wafer back 104 at the interface of the buried oxide layer 103, and then bond the second wafer surface 102 to the first wafer 101 surface. After bonding, the buried oxide layer 103 on the surface of the first substrate 1 needs to be cleaned (wet cleaning can be used) to form the first substrate 1.

[0096] It should be noted that the materials used to form the first wafer 101 and the second wafer may be single crystal silicon, polycrystalline silicon, amorphous silicon or doped silicon and the like. The material of the first substrate 1 may also be a SiGe first substrate 1, a III-V group element compound first substrate 1, a silicon carbide first substrate 1 or a stacked structure thereof, or a silicon-on-insulator structure. It may also be a diamond first substrate 1 or other semiconductor material first substrate 1 known to those skilled in the art. For example, P atoms may be implanted into single crystal silicon to form an N-type conductive semiconductor first substrate 1, and B atoms may be implanted into single crystal silicon to form a P-type conductive semiconductor first substrate 1, so as to improve the selectivity of the material and its adaptability to the actual production environment.

[0097] Step 4: See Figure 5 After the part of the first substrate 1 that does not need to be etched is protected by the mask 10, the first V-shaped groove is formed by dry etching, and its depth is typically 1500A and its width is typically 0.3um; similarly, a plurality of V-shaped grooves can be obtained to form a sawtooth structure 9.

[0098] It should be noted that when etching the first substrate 1 , a silicon film 11 with a thickness of about 1 um needs to be formed at the etching portion, and an etching operation is performed on the silicon film 11 .

[0099] Step 5: See Figure 6 After forming the sawtooth structure 9, N-doping is performed below the V-shaped groove to form a drift region 4; wherein the typical value of ion implantation is: 2E13cm -2 .

[0100] Step 6: Fill the sawtooth structure 9 and grind the filled part by chemical-mechanical method to ensure that the surface of the filled part is flat.

[0101] Step 7: See Figure 7 A field plate thick gate oxide layer 12 is formed on the surface of the first substrate 1 by thermal oxidation, and the thickness thereof is typically 800 Å.

[0102] Step 8: See Figure 8 A thin gate oxide region is defined in the field plate thick gate oxide layer 12, and the field plate thick gate oxide layer 12 in the thin gate oxide region is etched to the surface of the first substrate 1 by photolithography and etching, and then a gate thin gate oxide layer 13 is formed in the thin gate oxide region by thermal oxidation, and its thickness is a typical value of 150A.

[0103] Step 9: See Fig. 9 , a polycrystalline layer 14 is deposited on the field plate thick gate oxide layer 12 and the gate thin gate oxide layer 13, and at the same time, photolithography and etching are performed, and then 3P- implantation (typical value 5E13cm -2 ), thereby forming a channel region 3.

[0104] Step 10: See Fig.10 The polycrystalline layer 14 is subjected to photolithography and etching processes, so that the polycrystalline structures of the gate 8 and the field plate region 7 are separated to form a first polycrystalline structure 81 and a second polycrystalline structure 71 and form respective electrode terminal interfaces.

[0105] Step 11: See Fig.11 , a side wall 15 is set around the polycrystalline structure using a side wall 15 process.

[0106] Step 12: See Figure 2 , source-drain photolithography and ion implantation are performed in the channel region 3 and the drift region 4 to set the source 6 and the drain 5, thereby realizing the preparation of the LDMOS device.

[0107] The preparation method provided in this embodiment is feasible. By setting a stepped buried oxide structure 2 below the channel region 3 and the drift region 4 and setting a sawtooth structure 9 at the contact position between the drift region 4 and the field plate region 7, the electric field of the LDMOS device can be regulated, so that the electric field distribution inside the device is more uniform, and at the same time, the electric field peak can be effectively reduced, thereby improving the voltage resistance performance of the device.

[0108] In order to illustrate the technical advantages of the LDMOS device proposed in the present invention, this embodiment is described through simulation and corresponding simulation results.

[0109] See also Fig.12 , Fig.12This is a simulation result diagram of the LDMOS device proposed in the present invention, which has two independent polycrystalline structures. Among them, the first polycrystalline structure 81 of the gate 8 plays the role of the channel of the device and is located above the gate thin gate oxide layer 13 and the channel region 3; the second polycrystalline structure 71 of the field plate region 7 plays the role of the adjustable field plate of the device, which is independent of other electrodes and can be independently applied with voltage to better control the field plate; the second polycrystalline structure 71 of the field plate region 7 is arranged above the field plate thick gate oxide layer 12 and the sawtooth structure 9. Since there are two independent polycrystalline structures in the LDMOS device, its simulation results are shown as follows Fig.13 , Fig.14 The situation shown. According to the simulation results, it can be seen that when the device is working in the off state, it needs to withstand a very high withstand voltage. A low potential (typical value is "-5V") can be applied to the electrode FP of the field plate region 7 of the device, so that the drift region 4 below the field plate is depleted, and the depletion region is close to the upper boundary of the buried oxide. The current path can only be from the upper boundary of the buried oxide, thereby obtaining a very high withstand voltage. When the device is working in the on state, a high potential (typical value is "5V") can be applied to the electrode FP of the field plate region 7 of the device, so that the drift region 4 below the field plate accumulates charges under the field plate, and the current path is close to the surface of the drift region 4, thereby obtaining a very low specific on-resistance. Obviously, the setting of two independent polycrystalline structures can improve the voltage withstand adjustability of the LDMOS device and reduce the on-resistance of the device.

[0110] Further, see Fig.12 The LDMOS device provided in this embodiment adopts different buried oxide thicknesses in the channel region 3 and the field plate region 7, that is, a stepped buried oxide structure 2 is set: specifically, a thicker first buried oxide layer is used under the channel region 3, and a thinner second buried oxide layer is used under the drift region 4. The typical values ​​used in the simulation are 1000A and 200A, respectively. A sawtooth structure 9 composed of a number of V-shaped grooves is formed under the field plate region 7 of the LDMOS device. The groove inclination angle can be 45°, and the depth gradually becomes shallower from the source end to the drain end of the device. The groove width is consistent with the groove depth. Due to the presence of the stepped buried oxide structure 2 and the sawtooth structure 9 in the LDMOS device, the simulation results of its electric field distribution can be seen in Fig.15 , Fig.16 As shown. Fig.15 It can be seen that the electric field distribution in the area ① below the sawtooth structure 9 is distributed with multiple lower peaks, while the electric field distribution in the area ② near the stepped buried oxide structure 2 is smooth and uniform. Therefore, the sawtooth structure 9 and the stepped buried oxide structure 2 regulate the electric field one above and one below, so that the electric field distribution can be relatively uniform.

[0111] from Fig.16It can also be seen from the specific curve that the sawtooth structure 9 can reduce the very high electric field peak of the electric field distribution of the traditional device to multiple lower electric field peaks (which can be obtained by comparing the "electric field distribution of the traditional device" curve and the "electric field distribution of region ①" curve). This method can reduce the electric field on the silicon surface, thereby improving the withstand voltage of the device. The electric field distribution of the stepped buried oxide structure 2 is very smooth and uniform, and the peak value is relatively low compared with the electric field distribution of the traditional device (which can be obtained by comparing the "electric field distribution of the traditional device" curve and the "electric field distribution of region ②" curve), which shows that the stepped buried oxide structure 2 can also effectively reduce the electric field peak and improve the withstand voltage performance of the device.

[0112] Further, the potential simulation results of the LDMOS device can be found in Fig.17 , Fig.18 As shown. Wherein, direction ① is the potential distribution below the sawtooth structure 9, and direction ② is the potential distribution away from the sawtooth structure 9. Obviously, the potential distribution below the field plate region 7 is very uniform. Fig.18 It can also be seen from the curve in the middle direction ① that the potential distribution below the sawtooth structure 9 is more uniform, which is conducive to obtaining a higher withstand voltage.

[0113] Based on the above simulation results, it can be known that by setting a stepped buried oxide structure 2 below the channel region 3 and the drift region 4 and setting a sawtooth structure 9 at the contact position between the drift region 4 and the field plate region 7, the electric field of the LDMOS device can be regulated, so that the electric field distribution inside the device is more uniform, and at the same time, the electric field peak can be effectively reduced, thereby improving the voltage resistance performance of the device.

[0114] Specifically, for LDMOS devices, a very important parameter is the relationship between the specific on-resistance and the withstand voltage, that is, the FOM (Figure of Merit) curve. Through simulation, when conventional devices meet the requirements, the converted typical value of the device can reach:

[0115] R on，sp =6.9ohm·mm 2

[0116] BV = 38.9 V

[0117] In general, compared with the traditional LOCOS field plate structure (background description section Figure 1 The LDMOS device provided in this embodiment is improved by more than 60%.

[0118] It should be noted that the doping of the channel region 3 and the drift region 4 can be continuously optimized. Under different doping concentrations, the values ​​of the threshold voltage and saturation current of the device will also be different, which will have better values ​​than the on-resistance and withstand voltage, but overall it will not affect the advantages of this structure.

[0119] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An LDMOS device, comprising a first substrate, a gate, a drain, a source and a field plate region; wherein: The gate and the field plate region are arranged on the upper surface of the first substrate; a channel region is formed in the first substrate below the gate, and a drift region is formed in the first substrate below the field plate region; the source electrode is arranged in the channel region; and the drain electrode is arranged in the drift region; A step-type buried oxide structure is arranged below the channel region and the drift region, the step-type buried oxide structure comprises a first buried oxide layer and a second buried oxide layer connected to each other; the first buried oxide layer is arranged below the channel region, the second buried oxide layer is arranged below the drift region, and a connection portion between the first buried oxide layer and the second buried oxide layer is provided with an inclination angle; a sawtooth structure is arranged at a contact position between the drift region and the field plate region; the sawtooth structure comprises a plurality of V-shaped grooves with a certain inclination angle, and the depths of the plurality of V-shaped grooves gradually become shallower from the source to the drain; A first polycrystalline structure is disposed on the gate; and a second polycrystalline structure is disposed on the field plate region.

2. A method for preparing an LDMOS device, characterized in that: An LDMOS device suitable for use as claimed in claim 1, comprising the following steps: Determine a first substrate, and set a stepped buried oxide structure in the first substrate, specifically: determine a first wafer, and grow an oxide layer on the first wafer; etch the oxide layer to form a stepped buried oxide structure; determine a second wafer, invert the second wafer and bond the first wafer to the stepped buried oxide structure to form a first substrate; Etching a sawtooth structure on the upper surface of the first substrate, wherein the etching of the sawtooth structure on the upper surface of the first substrate is specifically: using dry etching to sequentially etch a plurality of V-shaped grooves with a certain inclination angle on the upper surface of the first substrate, wherein the depths of the plurality of V-shaped grooves are successively shallower from the source to the drain; and the plurality of V-shaped grooves constitute the sawtooth structure; forming a drift region at the sawtooth structure, and forming a channel region at a lateral position of the drift region; A drain is arranged in the drift region, a source is arranged in the channel region, and a gate and a field plate region are arranged on the upper surface of the first substrate; The sawtooth structure is arranged at a contact position between the drift region and the field plate region; a first polycrystalline structure is arranged on the gate; and a second polycrystalline structure is arranged on the field plate region.

3. The method for preparing an LDMOS device according to claim 2, characterized in that: The forming of a drift region at the sawtooth structure and forming a channel region at a lateral position of the drift region is specifically: Performing ion implantation doping at the sawtooth structure layer to form a drift region; Performing ion implantation doping in the first substrate and at a lateral position of the drift region to form a channel region; Wherein: the channel region is doped with ions having a conductivity type opposite to that of the drift region.

4. The method for preparing an LDMOS device according to claim 2, characterized in that: The gate and field plate region are arranged on the upper surface of the first substrate, specifically: forming a field plate thick gate oxide layer on the upper surface of the first substrate; Delimiting a thin gate oxide region on the field plate thick gate oxide layer and etching the field plate thick gate oxide layer in the thin gate oxide region to the surface of the first substrate; forming a gate thin gate oxide layer in the thin gate oxide region; A field plate region is arranged on the field plate thick gate oxide layer, and a gate is arranged on the gate thin gate oxide layer.

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