Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present application discloses a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, and relates to the field of semiconductor technology. The semiconductor device includes a substrate, an epitaxial layer, a gate structure, a source, and a drain. Among them, the epitaxial layer includes a first surface away from the side of the substrate, and the epitaxial layer also includes a well region, a first region, and a second region. The first region is arranged on the first surface, the well region is arranged on the side of the first region away from the first surface, and the second region is arranged on the first surface and is located outside the first region and the well region. The epitaxial layer also includes a first buried layer and a second buried layer. The first buried layer is arranged on the side of the gate structure away from the first surface, and the first buried layer is in electrical contact with the substrate. The second buried layer is arranged on the side of the second region away from the first surface, and the second buried layer is in electrical contact with the second region. By arranging the first buried layer and the second buried layer, the electric field distribution in the semiconductor device is improved, the gate structure is protected, and the device reliability is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In the field of semiconductor technology, trench silicon carbide power devices have the advantages of high current density and small cell size of a single device. However, the high electric field at the bottom and corners of the trench leads to a high electric field in the gate oxide layer, which makes the oxide layer easy to be broken down and has low reliability.

[0003] Under the premise of ensuring device functionality, how to optimize device structure to improve reliability is a current research direction. Summary of the invention

[0004] The embodiment of the present application provides a semiconductor device, including a substrate, an epitaxial layer, a gate structure, a source, and a drain. The epitaxial layer is arranged on the substrate, the epitaxial layer includes a first surface away from the substrate side, the epitaxial layer also includes a well region, a first region, and a second region, the first region is arranged on the first surface, the well region is arranged on the side of the first region away from the first surface, and the second region is arranged on the first surface and extends from the first surface to the epitaxial layer. The gate structure extends from the first surface to the epitaxial layer and passes through the first region and the well region. The source is arranged on the first surface and is electrically connected to the first region and the second region. The drain is arranged on the side of the substrate away from the epitaxial layer. The epitaxial layer also includes a first buried layer and a second buried layer, the first buried layer is arranged on the side of the gate structure away from the first surface, and the first buried layer is electrically in contact with the substrate, and the second buried layer is arranged on the side of the second region away from the first surface, and the second buried layer is electrically in contact with the second region.

[0005] In some embodiments, the first buried layer includes a first portion and a second portion that are connected, the first portion is electrically in contact with the substrate, the second portion is disposed on a side of the first portion away from the substrate, and an orthographic projection of the second portion on the substrate at least partially overlaps with an orthographic projection of the first portion on the substrate.

[0006] In some embodiments, an orthographic projection of the first portion on the substrate is within the range of an orthographic projection of the second portion on the substrate.

[0007] In some embodiments, an orthographic projection of the second portion on the substrate is located within a range of an orthographic projection of the gate structure on the substrate.

[0008] In some embodiments, an orthographic projection of the second buried layer on the substrate covers an orthographic projection of the second region on the substrate.

[0009] In the embodiment of the present application, the epitaxial layer includes a first buried layer and a second buried layer, which are used to improve the electric field distribution in the device and protect the gate structure. The first buried layer is arranged on the side of the gate structure away from the first surface, and the first buried layer is in electrical contact with the substrate. When a positive voltage is applied to the drain, the corresponding potential of the first buried layer increases, the PN junction is in a forward biased state, and the space depletion region is reduced, which is conducive to the increase of the on-state current. The second buried layer is arranged on the side of the second region away from the first surface, and the second buried layer is in electrical contact with the second region. When a positive voltage is applied to the drain, the PN junction is in a reverse biased state, and the space depletion region is increased, which is conducive to improving the withstand voltage characteristics. In addition, the larger the interval between the first buried layer and the second buried layer, the larger the on-state current, the smaller the interval, and the higher the reliability.

[0010] By setting the first buried layer and the second buried layer, the device does not need to set a trench source structure and can also protect the gate structure. At the same time, by eliminating the trench source structure, the contact area between the source metal and the second region is larger, so that the reverse conduction voltage of the device is lower.

[0011] On the other hand, the embodiment of the present application further provides a method for preparing a semiconductor device, comprising the following steps S10 to S70:

[0012] Step S10: forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first buried layer and a second buried layer, and the first buried layer is in electrical contact with the substrate.

[0013] Step S20: forming a well region and a first region in the epitaxial layer, wherein the epitaxial layer includes a first surface away from the substrate, the first region is located on the first surface, and the well region is located on a side of the first region away from the first surface.

[0014] Step S30: forming a gate trench, wherein the gate trench extends from the first surface into the epitaxial layer and penetrates the first region and the well region.

[0015] Step S40: forming a second region in the epitaxial layer, wherein the second region is located on the first surface and extends from the first surface into the epitaxial layer.

[0016] Step S50: forming a gate structure in the gate trench.

[0017] Step S60: forming a source electrode on the first surface, wherein the source electrode is electrically connected to the first region and the second region.

[0018] Step S70: forming a drain electrode, wherein the drain electrode is located on a side of the substrate away from the epitaxial layer.

[0019] In some embodiments, the epitaxial layer includes a first sub-epitaxial layer and a second sub-epitaxial layer, the first buried layer includes a first portion and a second portion, and the step of forming the epitaxial layer further includes steps S11 to S13:

[0020] Step S11: forming a first sub-epitaxial layer on a substrate, wherein the first sub-epitaxial layer comprises a first portion, the first portion is in electrical contact with the substrate, and the first sub-epitaxial layer comprises a second surface away from the substrate.

[0021] Step S12: forming a second portion and a second buried layer in the second surface, wherein the second portion is located on a side of the first portion away from the substrate, and the second portion is connected to the first portion.

[0022] Step S13: forming a second sub-epitaxial layer on a side of the first sub-epitaxial layer away from the substrate.

[0023] The preparation method provided in the embodiment of the present application forms a first buried layer and a second buried layer in the process of forming an epitaxial layer, so as to improve the electric field distribution in the device and protect the gate structure. The first buried layer is arranged on the side of the gate structure away from the first surface, and the first buried layer is in electrical contact with the substrate. When a positive voltage is applied to the drain, the corresponding potential of the first buried layer increases, the PN junction is in a forward biased state, and the space depletion region is reduced, which is conducive to the increase of the on-state current. The second buried layer is arranged on the side of the second region away from the first surface, and the second buried layer is in electrical contact with the second region. When a positive voltage is applied to the drain, the PN junction is in a reverse biased state, and the space depletion region is increased, which is conducive to improving the withstand voltage characteristics. In addition, the larger the interval between the first buried layer and the second buried layer, the larger the on-state current, the smaller the interval, and the higher the reliability.

[0024] Moreover, the preparation method does not require etching of the source trench, and the process is simpler. Moreover, by eliminating the preparation of the source trench, the contact area between the source metal and the second region is larger, and the reverse conduction voltage of the device is lower.

[0025] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to carry the semiconductor device.

[0026] In another aspect, an embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0027] On the other hand, an embodiment of the present application also provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0028] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0031] Figure 2 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0032] Figure 3~Figure 13 A diagram of each step of preparing a semiconductor device provided in an embodiment of the present application;

[0033] Fig.14 A schematic diagram of the structure of a power module provided in an embodiment of the present application;

[0034] Fig.15 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application;

[0035] Fig.16 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0037] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0038] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0039] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0040] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0041] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0042] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0043] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0044] In the field of semiconductor technology, trench-type silicon carbide power devices have the advantages of high current density and small cell size of a single device, but the high electric field at the bottom and corner of the trench leads to a high electric field in the gate oxide layer, which makes the oxide layer easy to be broken down and has low reliability. In order to better protect the gate oxide layer and obtain better reliability, there are currently two main solutions: one is to use a double trench structure, that is, to construct source trenches on both sides of the gate trench and form a trench source structure to shield the electric field at the bottom of the gate trench, but this solution requires additional source trenches to be made, and the process is relatively complicated; the other is to use an asymmetric trench structure, embed a P-type region at the bottom of the gate trench to weaken the electric field at the bottom of the trench, but this solution requires sacrificing half of the conductive trench, so that the on-state current is reduced.

[0045] In view of the above problems, an embodiment of the present application provides a semiconductor device, which may be a silicon carbide MOSFET. Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0046] like Figure 1 As shown, the semiconductor device 10 includes a substrate 101, an epitaxial layer 102, a gate structure 103, a source 104, and a drain 105. The epitaxial layer 102 is disposed on the substrate 101, and the epitaxial layer 102 includes a first surface P1 away from the substrate 101. The epitaxial layer 102 also includes a well region 107, a first region 108, and a second region 109. The first region 108 is disposed on the first surface P1, the well region 107 is disposed on the side of the first region 108 away from the first surface P1, and the second region 109 is disposed on the first surface P1 and extends from the first surface P1 to the epitaxial layer 102. The gate structure 103 extends from the first surface P1 to the epitaxial layer 102 and penetrates the first region 108 and the well region 107. The source 104 is disposed on the first surface P1 and is electrically connected to the first region 108 and the second region 109. The drain 105 is disposed on the side of the substrate 101 away from the epitaxial layer 102.

[0047] For example, Figure 1 As shown, the gate structure 103 includes a gate oxide layer 1031 and a trench gate 1032 . In addition, there is a passivation layer 106 on the first surface P1 . The passivation layer 106 covers the gate structure 103 to perform isolation and protection functions.

[0048] The above-mentioned well region 107 and the second region 109 have the same conductivity type, and are both of the first conductivity type. The substrate 101, the epitaxial layer 102 and the first region 108 have the same conductivity type, and are both of the second conductivity type. For example, P is implanted in both the well region 107 and the second region 109. + ions, the conductivity type of both is P-type, the well region 107 can also be called "P-well region (P-well)", and the second region 109 can also be called "P + The conductivity types of the substrate 101, the epitaxial layer 102 and the first region 108 are all N-type. N + ions, the first region 108 may also be referred to as "N + contact area".

[0049] By transmitting a turn-on voltage to the gate structure 103 , when the semiconductor device 10 is forward-conducting and the operating current is small, the operating current reaches the drain 105 from the source 104 through the first region 108 , the well region 107 , the epitaxial layer 102 and the substrate 101 .

[0050] Since the P-type ion concentration in the second region 109 is higher than that in the well region 107, more PN junctions are formed between the second region 109 and the epitaxial layer 102. When the operating current is large, the operating current flows from the source 104 through the second region 109, the epitaxial layer 102 and the substrate 101 to the drain 105, thereby preventing the large operating current from flowing through the well region 107, thereby protecting the channel in the well region 107.

[0051] The second region 109 penetrates the first region 108 and the well region 107 and extends to the epitaxial layer 102, which can optimize the electric field distribution in the device and protect the gate structure 103. Compared with the related solutions, the solution of the embodiment of the present application does not have a source trench structure, so in the embodiment of the present application, the contact area between the source 104 and the second region 109 is larger, so that the reverse conduction voltage is lower.

[0052] In addition, the epitaxial layer 102 further includes a first buried layer 21 and a second buried layer 22. The first buried layer 21 is disposed on a side of the gate structure 103 away from the first surface P1, and the first buried layer 21 is in electrical contact with the substrate 101. The second buried layer 22 is disposed on a side of the second region 109 away from the first surface P1, and the second buried layer 22 is in electrical contact with the second region 109. The conductivity type of the first buried layer 21 and the second buried layer 22 is the same as the conductivity type of the second region 109, which is also the first conductivity type, and is used to further improve the electric field distribution in the device and protect the gate structure 103. Among them, the first buried layer 21 is disposed on a side of the gate structure 103 away from the first surface P1, and the first buried layer 21 is in electrical contact with the substrate 101. When a positive voltage is applied to the drain 105, the corresponding potential of the first buried layer 21 increases, the PN junction is in a forward biased state, and the spatial depletion region is reduced, which is conducive to the increase of the on-state current. The second buried layer 22 is disposed on a side of the second region 109 away from the first surface P1, and the second buried layer 22 is in electrical contact with the second region 109. When a positive voltage is applied to the drain 105, the PN junction is in a reverse bias state, and the space depletion region increases, which is beneficial to improving the withstand voltage characteristics. In addition, the larger the interval between the first buried layer 21 and the second buried layer 22, the larger the on-state current, and the smaller the interval, the higher the reliability.

[0053] In some embodiments, Figure 1 As shown, the first buried layer 21 includes a first portion 211 and a second portion 212 that are connected, the first portion 211 is in electrical contact with the substrate 101, the second portion 212 is disposed on a side of the first portion 211 away from the substrate 101, and the orthographic projection of the second portion 212 on the substrate 101 at least partially overlaps with the orthographic projection of the first portion 211 on the substrate 101.

[0054] In the embodiment of the present application, the first part 211 is electrically in contact with the substrate 101 , and the second part 212 at least partially overlaps with the orthographic projection of the first part 211 to achieve electrical contact between the second part 212 and the first part 211 , so that the second part 212 can be electrically connected to the substrate 101 through the first part 211 .

[0055] In some embodiments, Figure 1 As shown, the orthographic projection of the first part 211 of the first buried layer 21 on the substrate 101 is located within the range of the orthographic projection of the second part 212 on the substrate 101, so that the contact area between the second part 212 and the first part 211 is maximized, thereby ensuring the contact performance between the second part 212 and the first part 211.

[0056] Exemplarily, the center of the orthographic projection of the first portion 211 on the substrate 101 coincides with the center of the orthographic projection of the second portion 212 on the substrate 101, and at this time, the electric field distribution in the device is more uniform, thereby making the current more uniform, which is beneficial to improving device performance. In addition, the smaller the size of the first portion 211, the more conducive it is to increase the on-state current.

[0057] In some embodiments, Figure 1 As shown, the orthographic projection of the second part 212 on the substrate 101 is located within the range of the orthographic projection of the gate structure 103 on the substrate 101. In this embodiment, the first buried layer 21 is used to optimize the electric field distribution near the bottom of the gate structure 103, and provide protection for the gate structure 103, especially the bottom area of ​​the gate structure 103.

[0058] For example, Figure 1 As shown, along the X direction parallel to the first surface P1, the size of the second portion 212 is equal to half the size of the gate structure 103, which is conducive to forming a larger on-state current while protecting the gate structure 103. Along the Y direction parallel to the first surface P1, the first buried layer 21 can be provided as one or multiple discrete layers.

[0059] In some embodiments, Figure 1 As shown, the orthographic projection of the second buried layer 22 on the substrate 101 covers the orthographic projection of the second region 109 on the substrate 101. The second buried layer 22 and the second region 109 mainly optimize the electric field distribution near the side wall and the groove corner area of ​​the gate structure 103, and provide protection for the gate structure 103, especially the groove corner area of ​​the gate structure 103.

[0060] In some examples, such as Figure 1As shown, the outer boundary of the orthographic projection of the second buried layer 22 exceeds the outer boundary of the orthographic projection of the second region 109, and the area of ​​the orthographic projection of the second buried layer 22 is larger than the area of ​​the orthographic projection of the second region 109, that is, along the X direction parallel to the first surface P1, the size of the second buried layer 22 is larger than the size of the second region 109. At this time, the second buried layer 22 and the second region 109 are used together to improve the electric field distribution near the side wall and the groove corner area of ​​the gate structure 103. In addition, the size setting of the second buried layer 22 makes the interval between it and the first buried layer 21 smaller, which is conducive to improving the reliability of the device. In other examples, the outer boundary of the orthographic projection of the second buried layer 22 can coincide with the outer boundary of the orthographic projection of the second region 109, and the area of ​​the orthographic projection of the second buried layer 22 is equal to the area of ​​the orthographic projection of the second region 109, that is, along the X direction parallel to the first surface P1, the size of the second buried layer 22 is equal to the size of the second region 109, and the second buried layer 22 is equivalent to the further extension of the second region 109 in the Z direction perpendicular to the first surface P1, thereby improving the electric field distribution near the sidewall and the groove corner area of ​​the gate structure 103. In addition, the size of the second buried layer 22 is set so that the interval between it and the first buried layer 21 is large, which is conducive to increasing the on-state current. According to the size of the device, a buried layer area can be added between the first buried layer 21 and the second buried layer 22 as appropriate. The added buried layer area has the same conductivity type as the first buried layer 21 and the second buried layer 22, that is, by adjusting the buried layer interval, the on-state current size and reliability are adjusted to meet the relevant use requirements, which will not be repeated here.

[0061] On the other hand, the present invention also provides a method for preparing a semiconductor device. Figure 2 As shown, Figure 2 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, Figure 3~Figure 13 A diagram of the various steps of preparing a semiconductor device provided in an embodiment of the present application.

[0062] The preparation method provided in the embodiment of the present application includes the following steps S10 to S70:

[0063] Step S10: Figure 3~Figure 5 As shown, an epitaxial layer 102 is formed on a substrate 101 . The epitaxial layer 102 includes a first buried layer 21 and a second buried layer 22 . The first buried layer 21 is in electrical contact with the substrate 101 .

[0064] In some embodiments, the epitaxial layer 102 includes a first sub-epitaxial layer 1021 and a second sub-epitaxial layer 1022, the first buried layer 21 includes a first portion 211 and a second portion 212, and the step of forming the epitaxial layer 102 further includes steps S11 to S13:

[0065] Step S11: Figure 3As shown, a first sub-epitaxial layer 1021 is formed on the substrate 101 , the first sub-epitaxial layer 1021 includes a first portion 211 of the first buried layer 21 , the first portion 211 is in electrical contact with the substrate 101 , and the first sub-epitaxial layer 1021 includes a second surface P2 away from the substrate 101 .

[0066] For example, the conductivity type of the epitaxial layer 102 is N-type, and a mask is formed by a photolithography process to define an ion implantation region and to perform P implantation on the first sub-epitaxial layer 1021. + Ions are implanted to form the first portion 211 .

[0067] Step S12: Figure 4 As shown, a second portion 212 and a second buried layer 22 are formed in the second surface P2 , the second portion 212 is located on a side of the first portion 211 away from the substrate 101 , and the second portion 212 is connected to the first portion 211 .

[0068] Exemplarily, after forming the first portion 211, the mask is removed, and then a mask is formed again by photolithography to define the ion implantation region, and P is again applied to the first sub-epitaxial layer 1021. + Ions are implanted to form the second portion 212 and the second buried layer 22 .

[0069] Step S13: Figure 5 As shown, a second sub-epitaxial layer 1022 is formed on a side of the first sub-epitaxial layer 1021 away from the substrate 101 .

[0070] At this point, the epitaxial layer 102 is formed.

[0071] Step S20: Figure 6 As shown, a well region 107 and a first region 108 are formed in the epitaxial layer 102 . The epitaxial layer 102 includes a first surface P1 away from the substrate 101 . The first region 108 is located on the first surface P1 . The well region 107 is located on a side of the first region 108 away from the first surface P1 .

[0072] Exemplarily, on the first surface P1, a mask is formed by a photolithography process, an ion implantation region is defined, and P + Ion implantation is performed to form a well region 107. After the mask is removed, a mask is formed again through a photolithography process to define the ion implantation area and perform N + Ion implantation is performed to form the first region 108. The implantation energy is controlled to control the ion implantation depth, so that the first region 108 is located on the first surface P1, and the well region 107 is located on a side of the first region 108 away from the first surface P1.

[0073] Step S30: Figure 7As shown, a gate trench T1 is formed, and the gate trench T1 extends from the first surface P1 into the epitaxial layer 102 and penetrates the first region 108 and the well region 107 .

[0074] Compared with related solutions, this process does not require the formation of a source trench, and only the gate trench T1 is etched, that is, the process is simpler.

[0075] Step S40: Figure 8 As shown, a second region 109 is formed in the epitaxial layer 102 . The second region 109 is located on the first surface P1 and extends from the first surface P1 into the epitaxial layer 102 .

[0076] Exemplarily, a mask is formed by a photolithography process, an ion implantation region is defined, and P is performed. + Ion implantation is performed to form the second region 109. The implantation energy is controlled to control the ion implantation depth, so that the second region 109 is electrically connected to the second buried layer 22.

[0077] Step S50: Figure 9~Figure 10 As shown, a gate structure 103 is formed in the gate trench T1 .

[0078] For example, Fig. 9 As shown, a gate oxide layer 1031 is formed by a gate oxide process, and then Fig.10 As shown, polysilicon is deposited in the gate trench T1 and etched to form a trench gate 1032 .

[0079] Afterwards, to isolate and protect the gate structure 103, as shown in FIG. Fig.11 As shown, a passivation layer 106 is deposited on the first surface P1.

[0080] Step S60: Fig.12 As shown, a source 104 is formed on the first surface P1 , and the source 104 is electrically connected to the first region 108 and the second region 109 .

[0081] Exemplarily, aluminum thickening metal is deposited by sputtering or evaporation to form the source 104. Fig.12 As shown, a passivation layer 110 is deposited and a pad window is formed by etching, and an insulating material is spin-coated on the surface of the passivation layer 110 and cured after development and exposure to form an insulating dielectric layer 111. The pad window is used for subsequent electrical connection with other components.

[0082] Step S70: Fig.13 As shown, a drain 105 is formed, and the drain 105 is located on a side of the substrate 101 away from the epitaxial layer 102 .

[0083] Specifically, the substrate 101 is thinned to reduce the thickness of the substrate 101 and form a relatively flat surface, and then metal is deposited and annealed to form an ohmic contact of the drain 105 .

[0084] At this point, the semiconductor device 10 is completed.

[0085] The preparation method provided in the embodiment of the present application forms a first buried layer 21 and a second buried layer 22 in the process of forming the epitaxial layer 102, which is used to improve the electric field distribution in the device and protect the gate structure 103. Among them, the first buried layer 21 is arranged on the side of the gate structure 103 away from the first surface P1, and the first buried layer 21 is in electrical contact with the substrate 101. When a positive voltage is applied to the drain 105, the corresponding potential of the first buried layer 21 increases, the PN junction is in a forward biased state, and the space depletion region is reduced, which is conducive to the increase of the on-state current. The second buried layer 22 is arranged on the side of the second region 109 away from the first surface P1, and the second buried layer 22 is in electrical contact with the second region 109. When a positive voltage is applied to the drain 105, the PN junction is in a reverse biased state, and the space depletion region is increased, which is conducive to improving the withstand voltage characteristics. In addition, the larger the interval between the first buried layer 21 and the second buried layer 22, the larger the on-state current, the smaller the interval, and the higher the reliability.

[0086] Moreover, the preparation method does not require etching of the source trench, and the process is simpler. In addition, by eliminating the preparation of the source trench, the contact area between the source 104 metal and the second region 109 is larger, and the reverse conduction voltage of the device is lower.

[0087] On the other hand, an embodiment of the present application further provides a power module, Fig.14 A schematic diagram of the structure of a power module provided in an embodiment of the present application.

[0088] like Fig.14 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10 .

[0089] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0090] On the other hand, an embodiment of the present application further provides a power conversion circuit, Fig.15 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application.

[0091] like Fig.15 As shown, the power conversion circuit 300 includes a circuit board 301 and a semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0092] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0093] On the other hand, an embodiment of the present application further provides a vehicle, Fig.16 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0094] like Fig.16 As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment, and the power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0095] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate is set to a second conductivity type; An epitaxial layer is arranged on the substrate, and the epitaxial layer is set to the second conductivity type; the epitaxial layer includes a first surface away from the substrate, the epitaxial layer also includes a well region set to the first conductivity type, a first region set to the second conductivity type, and a second region set to the first conductivity type, the first region is arranged on the first surface, the well region is arranged on a side of the first region away from the first surface, and the second region is arranged on the first surface and extends from the first surface into the epitaxial layer; a gate structure extending from the first surface into the epitaxial layer and penetrating the first region and the well region; A source electrode, disposed on the first surface and electrically connected to the first region and the second region; A drain electrode is arranged on a side of the substrate away from the epitaxial layer; The epitaxial layer further includes a first buried layer and a second buried layer, both of which are set to be of the first conductivity type; the first buried layer is arranged on a side of the gate structure away from the first surface, the first buried layer is separated from the gate structure by a portion of the epitaxial layer, and the first buried layer is in electrical contact with the substrate; The second buried layer is disposed on a side of the second region away from the first surface, and the second buried layer is in electrical contact with the second region.

2. The semiconductor device according to claim 1, wherein: The first buried layer comprises a first portion and a second portion connected to each other, the first portion is in electrical contact with the substrate, and the second portion is disposed on a side of the first portion away from the substrate; An orthographic projection of the second portion on the substrate at least partially overlaps with an orthographic projection of the first portion on the substrate.

3. The semiconductor device according to claim 2, characterized in that The orthographic projection of the first portion on the substrate is located within the range of the orthographic projection of the second portion on the substrate.

4. The semiconductor device according to claim 2 or 3, characterized in that: An orthographic projection of the second portion on the substrate is located within a range of an orthographic projection of the gate structure on the substrate.

5. The semiconductor device according to claim 1, wherein: The orthographic projection of the second buried layer on the substrate covers the orthographic projection of the second region on the substrate.

6. A method for preparing a semiconductor device, characterized in that: include: forming an epitaxial layer on a substrate, wherein both the substrate and the epitaxial layer are set to be of a second conductivity type; the epitaxial layer comprises a first buried layer and a second buried layer, wherein the first buried layer is in electrical contact with the substrate; A well region and a first region are formed in the epitaxial layer, the well region is set to a first conductivity type, and the first region is set to a second conductivity type; the epitaxial layer includes a first surface away from a side of the substrate, the first region is located on the first surface, and the well region is located on a side of the first region away from the first surface; forming a gate trench, the gate trench extending from the first surface into the epitaxial layer and penetrating the first region and the well region; the gate trench is located on a side of the first buried layer away from the substrate, and the gate trench is separated from the first buried layer by a portion of the epitaxial layer; forming a second region in the epitaxial layer, wherein the second region is set to a first conductivity type; The second region is located on the first surface and extends from the first surface into the epitaxial layer; The second region is located on a side of the second buried layer away from the substrate, and the second region is in electrical contact with the second buried layer; forming a gate structure in the gate trench; forming a source electrode on the first surface, wherein the source electrode is electrically connected to the first region and the second region; A drain is formed, wherein the drain is located on a side of the substrate away from the epitaxial layer.

7. The preparation method according to claim 6, characterized in that: The epitaxial layer includes a first sub-epitaxial layer and a second sub-epitaxial layer, the first buried layer includes a first portion and a second portion, and forming the epitaxial layer includes: forming a first sub-epitaxial layer on the substrate, wherein the first sub-epitaxial layer includes the first portion, the first portion is in electrical contact with the substrate; and the first sub-epitaxial layer includes a second surface away from the substrate; forming the second portion and the second buried layer in the second surface, wherein the second portion is located on a side of the first portion away from the substrate, and the second portion is connected to the first portion; The second sub-epitaxial layer is formed on a side of the first sub-epitaxial layer away from the substrate.

8. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 5; A substrate is used to carry the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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