Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present application discloses a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, and relates to the field of semiconductor technology. The semiconductor body of the semiconductor device is set to a first conductivity type, and the semiconductor body includes a first region set to the first conductivity type, a well region of the second conductivity type and a second region of the second conductivity type. The second region and at least part of the first surface are connected to the source of the semiconductor device to form a Schottky contact. The semiconductor device also includes a plurality of first structures set to the second conductivity type. The Schottky contact reduces the on-state voltage drop, reverse recovery time and reverse recovery energy consumption of the semiconductor device. During the freewheeling process, the problem of holes entering the drift layer does not occur, reducing the risk of double-click degradation of the device and avoiding external freewheeling diodes. In addition, the plurality of first structures improve the overall reverse characteristics and gate oxide reliability of the device, thereby ensuring the long-term reliability of the device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In SiC Metal-Oxide-SemiconductorField-EffectTransistor (SiC MOSFET), the body diode freewheeling often occurs in actual applications. However, due to the material characteristics of SiC, the body diode has a too high turn-on voltage, which will cause large losses. Therefore, in specific semiconductor application fields such as photovoltaic inverters, motor drives, and DCDC conversion, it is usually necessary to connect a diode in parallel in the module as a reverse recovery diode to form a complete circuit. However, parallel diodes will cause additional costs and are limited by the module packaging form.

[0003] In addition, due to the characteristics of silicon carbide crystal materials, taking N-type substrate transistors as an example, the P + The area is shallow, and the drain current is relatively large when the device is turned off and used in a high-temperature environment. In addition, there is an electric field concentration effect at the corners of the gate trench, which can easily cause the gate oxide layer to break down prematurely. Summary of the invention

[0004] The embodiment of the present application provides a semiconductor device, including a semiconductor body, a gate structure, a source and a drain. The semiconductor body is set to a first conductivity type and includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a gate trench, the gate trench extends from the first surface to the semiconductor body, and the gate structure is located in the gate trench. The semiconductor body also includes a first region set to the first conductivity type, the first region is arranged on the first surface. The semiconductor body also includes a well region set to the second conductivity type, the well region is arranged on the side of the first region away from the first surface. The semiconductor body also includes a second region set to the second conductivity type, the second region extends from the first surface to the semiconductor body. In addition, the source is located on the first surface, and the second region and at least part of the first surface are connected to the source to form a Schottky contact. The drain is located on the second surface. In addition, the semiconductor device also includes a plurality of first structures, the plurality of first structures are set to the second conductivity type, and the semiconductor body also includes a first interface between the gate structure and the second surface, and the plurality of first structures are arranged on the side of the first interface close to the second surface.

[0005] In some embodiments, the semiconductor body includes a substrate, a first epitaxial layer, and a second epitaxial layer stacked in sequence, the surface of the second epitaxial layer away from the substrate is the first surface, the surface of the substrate away from the second epitaxial layer is the second surface, and the surface of the first epitaxial layer away from the substrate is the first interface. The plurality of first structures extend from the first interface into the first epitaxial layer.

[0006] In some embodiments, the semiconductor body further includes a third epitaxial layer located between the substrate and the first epitaxial layer, and a surface of the third epitaxial layer away from the substrate is a second interface. Among the plurality of first structures, a portion of the first structures extends from the first interface to the first epitaxial layer, and another portion of the first structures extends from the second interface to the third epitaxial layer.

[0007] In some embodiments, the first region and the second region are arranged along a first direction, and the first direction is parallel to the first surface. A plurality of first structures are arranged at intervals along the first direction, and each first structure extends along a second direction, and the second direction is parallel to the first surface and intersects with the first direction. Alternatively, the plurality of first structures include a plurality of rows and a plurality of columns, and the first structures in each row are arranged at intervals along the first direction, and the first structures in each column are arranged at intervals along the second direction.

[0008] In some embodiments, the first area and the second area are arranged along a first direction, the first direction is parallel to the first surface, the plurality of first structures include a plurality of first linear structures and a plurality of second linear structures, each of the first linear structures extends along the first direction, and each of the second linear structures extends along the second direction. The second direction is parallel to the first surface and intersects with the first direction, and the plurality of first linear structures and the plurality of second linear structures are interwoven into a network.

[0009] In some embodiments, a distance between two adjacent first structures ranges from 1 μm to 8 μm.

[0010] In some embodiments, along a direction perpendicular to the first interface, a depth of the first structure ranges from 1 μm to 5 μm.

[0011] In some embodiments, the first surface is further provided with a source trench, and the source trench extends from the first surface into the semiconductor body. The semiconductor body also includes a third region that is set to the second conductivity type, and the third region is arranged on the surface of the source trench. The semiconductor device also includes a source trench structure, and the source trench structure is located in the source trench. The above-mentioned multiple first structures are also located on one side of the third region close to the second surface.

[0012] In some embodiments, along a direction perpendicular to the first interface, a distance between the first interface and the third region ranges from 1 μm to 3 μm.

[0013] In an embodiment of the present application, the semiconductor body is set to a first conductivity type, and the semiconductor body also includes a first region set to the first conductivity type, a well region set to the second conductivity type, and a second region set to the second conductivity type. The second region forms a PN junction with the semiconductor body, and the second region and at least a portion of the first surface are connected to the source to form a Schottky contact. Based on this, the problem of holes entering the drift layer will not occur during the freewheeling process, thereby reducing the risk of double-click degradation of the device, reducing the on-state voltage drop and reverse recovery time of the semiconductor device, reducing the reverse recovery energy consumption, enhancing the conduction performance and surge current resistance of the body diode, and avoiding an external freewheeling diode, thereby reducing the complexity of circuit design and system cost, and improving the reliability of silicon carbide MOSFET devices.

[0014] In addition, the semiconductor device also includes a plurality of first structures set to the second conductivity type. When a reverse bias is applied, the depletion layer will gradually extend below the drift region as the reverse bias increases. When the depletion layer extends to the first structure, a new peak electric field will be formed at the first structure, forming a new depletion shielding layer to improve the overall reverse characteristics and gate oxide reliability of the device, thereby ensuring the long-term reliability of the device.

[0015] On the other hand, the embodiment of the present application further provides a method for preparing a semiconductor device, comprising the following steps S10 to S80:

[0016] Step S10: forming a first epitaxial layer on a substrate, wherein the first epitaxial layer is set to be of a first conductivity type and comprises a first interface away from a side of the substrate.

[0017] Step S20: forming a plurality of first structures at the first interface, wherein the first structures are set to be of the second conductivity type and extend from the first interface into the first epitaxial layer.

[0018] Step S30: forming a second epitaxial layer, wherein the second epitaxial layer is set to the first conductivity type and is located on a side of the first epitaxial layer away from the substrate, the second epitaxial layer includes a first surface away from the substrate, and the substrate includes a second surface away from the second epitaxial layer.

[0019] Step S40: forming a first region, a well region and a gate trench. The first region is located on the first surface and is set to the first conductivity type. The well region is located on a side of the first region away from the first surface and is set to the second conductivity type. The gate trench extends from the first surface into the second epitaxial layer.

[0020] Step S50: forming a second region, where the second region extends from the first surface into the second epitaxial layer and is set to be of a second conductivity type.

[0021] Step S60: forming a gate structure in the gate trench.

[0022] Step S70: forming a source electrode on the first surface, and connecting the second region and at least a portion of the first surface to the source electrode to form a Schottky contact.

[0023] Step S80: forming a drain electrode, wherein the drain electrode is located on a side of the substrate away from the first epitaxial layer.

[0024] In some embodiments, in the process of forming the gate trench, a source trench is also formed on the first surface, and the source trench extends from the first surface to the second epitaxial layer. In the process of forming the second region, a third region is also formed on the surface of the source trench, and the third region is set to the second conductivity type, and the plurality of first structures are also located on a side of the third region close to the second surface. In the process of forming the gate structure in the gate trench, a source trench structure is also formed in the source trench.

[0025] According to the preparation method provided in the embodiment of the present application, multiple first structures are formed in the process of preparing the semiconductor device. The preparation method is relatively simple and does not increase additional production costs. Multiple first structures can be used to improve the overall reverse characteristics and gate oxide reliability of the device, thereby ensuring the long-term reliability of the device. In addition, in the process of preparing the semiconductor device, a second region is also formed on the semiconductor body, and the second region and at least part of the first surface of the semiconductor body are connected to the source to form a Schottky contact. The preparation method is relatively simple. The semiconductor device prepared by the preparation method provided in the above embodiment can reduce the conduction voltage drop and reverse recovery time of the semiconductor device through the Schottky contact formed by connecting the second region and at least part of the first surface of the semiconductor body to the source, reduce the reverse recovery energy consumption, enhance the conduction performance and surge current resistance of the body diode, and in addition, the problem of holes entering the drift layer will not occur during the freewheeling process, reducing the risk of double-click degradation of the device, avoiding external freewheeling diodes, thereby reducing the complexity of circuit design and system cost, and improving the reliability of silicon carbide MOSFET devices.

[0026] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to carry the semiconductor device.

[0027] In another aspect, an embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0028] On the other hand, an embodiment of the present application also provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0029] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0031] Figure 1 A schematic diagram of a semiconductor device structure provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of another semiconductor device structure provided in an embodiment of the present application;

[0033] Figure 3 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0034] Figure 4 to Figure 17 A diagram of each step of preparing a semiconductor device provided in an embodiment of the present application;

[0035] Fig.18 A schematic diagram of the structure of a power module provided in an embodiment of the present application;

[0036] Fig.19 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application;

[0037] Fig. 20 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0042] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0043] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0044] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0045] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0046] In the field of semiconductor technology, silicon carbide materials have attracted extensive attention and research due to their superior physical properties. Its high-temperature and high-power electronic devices have the advantages of high input impedance, fast switching speed, high operating frequency, high temperature and high pressure resistance, and have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0047] Since MOSFET devices often have body diode freewheeling in actual applications, and the body diode has a too high turn-on voltage due to the characteristics of silicon carbide materials, it will cause large losses. Therefore, in specific semiconductor application fields such as photovoltaic inverters, motor drives, and DCDC conversion, it is often necessary to connect diodes in parallel in the module as reverse recovery diodes to form a complete circuit. However, connecting diodes in parallel will cause additional costs and is limited by the module packaging form.

[0048] In addition, due to the characteristics of silicon carbide crystal materials, taking N-type substrate transistors as an example, the P+ region formed by trench structure injection is shallow, and the drain current is relatively large when the device is turned off and used in a high-temperature environment. In addition, there is an electric field concentration effect at the corners of the gate trench, which can cause the gate oxide layer to easily break down prematurely.

[0049] In view of the above problems, the present invention provides a semiconductor device, such as Figure 1 As shown, Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0050] like Figure 1 As shown, the semiconductor device 10 includes a semiconductor body 101, a gate structure 102, a source 103, and a drain 104. The semiconductor body 101 is set to a first conductivity type, and includes a first surface P1 and a second surface P2 opposite to each other. The first surface P1 is provided with a gate trench T1, and the gate trench T1 extends from the first surface P1 to the semiconductor body 101. The gate structure 102 is located in the gate trench T1. A first insulating layer 105 is also formed in the gate trench T1 to protect the gate structure 102. A gate isolation dielectric layer 106 is also provided on the first surface P1. The gate isolation dielectric layer 106 covers the gate structure 102 and is used to isolate and protect the gate structure 102.

[0051] The source 103 is located on the first surface P1 , and the drain 104 is located on the second surface P2 .

[0052] In addition, the semiconductor body 101 further includes a first region 107 set to a first conductivity type, a well region 108 set to a second conductivity type, and a second region 109 set to a second conductivity type, wherein the first region 107 is set on the first surface P1, the well region 108 is set on a side of the first region 107 away from the first surface P1, and the second region 109 extends from the first surface P1 into the semiconductor body 101. Moreover, the second region 109 and at least a portion of the first surface P1 are connected to the source 103 to form a Schottky contact. For example, a Schottky contact layer 110 is set between the first surface P1 and the source 103, and the Schottky contact layer 110 is electrically connected to the second region 109.

[0053] In addition, the semiconductor device 10 also includes multiple first structures 11, which are set to the second conductivity type. The semiconductor body 101 also includes a first interface P3 located between the gate structure 102 and the second surface P2, and the multiple first structures 11 are arranged on the side of the first interface P3 close to the second surface P2.

[0054] In the embodiment of the present application, the semiconductor body 101 and the first region 107 are both of the first conductivity type, the well region 108 and the second region 109 are both of the second conductivity type, illustratively, the first conductivity type is N type, and the second conductivity type is P type, based on which, the first region 107, the well region 108 and the semiconductor body 101 form an NPN junction, and the second region 109 and the semiconductor body 101 form a PN junction. The gate structure 102, the source 103, and the drain 104 constitute three electrodes of the semiconductor device 10.

[0055] Since the second region 109 and at least part of the first surface P1 are connected to the source 103 to form a Schottky contact, a Schottky barrier is formed there, and the Schottky barrier has an asymmetric current-voltage characteristic, allowing current to pass easily when forward biased, and preventing current from flowing when reverse biased. The second region 109 is used to improve the electric field distribution and reduce the edge effect, thereby reducing the leakage current under reverse bias. By optimizing the structural design of the second region 109, it is helpful to optimize the electric field distribution to prevent failure caused by electric field concentration, and the stability and reliability of the Schottky contact in long-term operation can be improved.

[0056] The on-state voltage drop of Schottky contact is low. When switching from the forward conduction state to the reverse blocking state, it does not need to go through the process of charge storage and depletion, and can quickly reverse recovery, reducing the reverse recovery time. In addition, since the reverse recovery time of Schottky contact is short, less charge is stored in the process of switching from the on state to the off state, so less energy is consumed in the reverse recovery process, reducing the reverse recovery energy consumption and helping to improve the efficiency of the circuit.

[0057] In summary, the Schottky contact formed by connecting the second region 109 and at least part of the first surface P1 to the source 103 reduces the on-state voltage drop and reverse recovery time of the semiconductor device 10, reduces the reverse recovery energy consumption, enhances the conduction performance and surge current resistance of the body diode, and in addition, the problem of holes entering the drift layer will not occur during the freewheeling process, reducing the risk of double-click degradation of the device, and no external freewheeling diode is required, thereby reducing the complexity of circuit design and system cost, and improving the reliability of silicon carbide MOSFET devices. In the application process of photovoltaic inverter, motor drive, DCDC conversion and other related fields, parallel diodes are no longer required, which reduces costs and avoids the limitations of module packaging.

[0058] In addition, the semiconductor device 10 also includes a plurality of first structures 11 set to the second conductivity type. The plurality of first structures 11 are arranged on the side of the first interface P3 close to the second surface P2. When a reverse bias is applied, the depletion layer will gradually extend below the drift region as the reverse bias increases. When the depletion layer extends to the first structure 11, a new peak electric field will be formed at the first structure 11, forming a new depletion shielding layer to improve the overall reverse characteristics and gate oxide reliability of the device, avoid breakdown of the first insulating layer 105, and thus ensure the long-term reliability of the device.

[0059] In some embodiments, Figure 1 As shown, the semiconductor body 101 at the top includes a substrate 1011, a first epitaxial layer 1012, and a second epitaxial layer 1013 stacked in sequence. The surface of the second epitaxial layer 1013 away from the substrate 1011 is the first surface P1, the surface of the substrate 1011 away from the second epitaxial layer 1013 is the second surface P2, and the surface of the first epitaxial layer 1012 away from the substrate 1011 is the first interface P3. The plurality of first structures 11 extend from the first interface P3 to the first epitaxial layer 1012.

[0060] The first structure 11 is used to improve the electric field concentration problem at the bottom and corners of the gate trench, protect the gate structure 102, and prevent the first insulating layer 105 from being broken down prematurely. By optimizing the arrangement positions of multiple first structures 11, it is helpful to optimize the electric field distribution and ensure the current conduction effect.

[0061] In some embodiments, Figure 2 As shown, Figure 2 Another schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application, the semiconductor body 101 further includes a third epitaxial layer 1014 located between the substrate 1011 and the first epitaxial layer 1012, and the surface of the third epitaxial layer 1014 away from the substrate 101 is the second interface P4. Among the plurality of first structures 11, a portion of the first structures 11 extends from the first interface P3 to the first epitaxial layer 1012, and another portion of the first structures 11 extends from the second interface P4 to the third epitaxial layer 1014.

[0062] That is, in the direction Z perpendicular to the second surface P2, the first structure 11 is arranged in layers, and the layered first structure 11 is used to optimize the electric field distribution, while ensuring the current conduction effect, improving the electric field concentration problem at the bottom and corners of the gate trench, protecting the gate structure 102, and preventing the first insulating layer 105 from being broken down prematurely.

[0063] In some embodiments, Figure 1As shown, the first region 107 and the second region 109 are arranged along the first direction X, and the first direction X is parallel to the first surface P1. A plurality of first structures 11 are arranged at intervals along the first direction X, and each first structure 11 extends along the second direction Y, and the second direction Y is parallel to the first surface P1 and intersects with the first direction X. That is, on a plane parallel to the first surface P1, a plurality of first structures 11 are arranged discretely in a track shape. The interval between two adjacent first structures 11 is used to ensure the current conduction effect, and a plurality of first structures 11 arranged discretely in a track shape are used to optimize the electric field distribution, protect the gate structure 102, and prevent the first insulating layer 105 from being broken down prematurely.

[0064] Alternatively, the plurality of first structures 11 include a plurality of rows and a plurality of columns, the first structures 11 in each row are arranged at intervals along the first direction X, and the first structures 11 in each column are arranged at intervals along the second direction Y. That is, on a plane parallel to the first surface P1, the plurality of first structures 11 are discretely arranged in an array. The interval between two adjacent first structures 11 is used to ensure the current conduction effect, and the plurality of first structures 11 discretely arranged in an array are used to optimize the electric field distribution, protect the gate structure 102, and prevent the first insulating layer 105 from being broken down prematurely.

[0065] In some embodiments, Figure 1 As shown, the first area 107 and the second area 109 are arranged along a first direction X, the first direction X is parallel to the first surface P1, and the plurality of first structures 11 include a plurality of first linear structures and a plurality of second linear structures, each of the first linear structures extends along the first direction X, and each of the second linear structures extends along the second direction Y. The second direction Y is parallel to the first surface P1 and intersects with the first direction X, and the plurality of first linear structures and the plurality of second linear structures are interwoven into a network.

[0066] That is, on a plane parallel to the first surface P1, the first structure 11 is arranged in a mesh shape. The mesh is used to ensure the current conduction effect, and the mesh-shaped first structure 11 is used to optimize the electric field distribution, protect the gate structure 102, and prevent the first insulating layer 105 from being broken down in advance.

[0067] In some embodiments, Figure 1 As shown, the interval between two adjacent first structures 11 ranges from 1 μm to 8 μm, for example, 1 μm, 2 μm, 3 μm, 5 μm, or 8 μm.

[0068] In some embodiments, Figure 1 As shown, along the direction Z perpendicular to the first interface P3 , the depth of the first structure 11 is in the range of 1 μm to 5 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, and 5 μm.

[0069] The size and spacing of the first structure 11 affect the pressure bearing capacity of the device. If the spacing is not set properly, the reverse characteristics will be affected. The first structure 11 is reasonably set within the above range to ensure that the semiconductor device 10 has good reverse characteristics and high reliability.

[0070] In some embodiments, Figure 1 As shown, the first surface P1 is also provided with a source trench T2, and the source trench T2 extends from the first surface P1 into the semiconductor body 101. The semiconductor body 101 also includes a third region 111 that is set to the second conductivity type, and the third region 111 is arranged on the surface of the source trench T2. The semiconductor device 10 also includes a source trench structure 112, and the source trench structure 112 is located in the source trench T2. The above-mentioned multiple first structures 11 are also located on one side of the third region 111 close to the second surface P2.

[0071] For example, Figure 1 As shown, a second insulating layer 113 is also formed in the source trench T2 to protect the source trench structure 112. An ohmic contact layer 114 is also provided on the first surface P1. The ohmic contact layer 114 can be provided in the same layer as the Schottky contact layer 110. The ohmic contact layer 114 covers the third region 111 and the source trench structure 112. The ohmic contact layer 114 can be made of at least one of titanium (Ti) or molybdenum (Mo).

[0072] The ohmic contact layer 114 is disposed between the semiconductor body 101 and the source 103 to form an ohmic contact. The ohmic contact is based on good electron exchange between metal and semiconductor to form a low-impedance connection, and its current-voltage characteristic is symmetrical, that is, current is allowed to pass regardless of forward or reverse bias.

[0073] The third region 111 has the same conductivity type as the well region 108, both of which are the second conductivity type. For example, the first conductivity type is N-type and the second conductivity type is P-type. Figure 1 In the semiconductor device 10 shown, the outlet of the vertical channel of the trench MOSFET device is directly connected to the open drift region, and the junction field effect (JEFT effect) is completely eliminated. Compared with the planar MOSFET device, it has the advantages of smaller on-resistance and on-voltage drop, and higher integration. The second region 109 and the third region 111 can both optimize the electric field distribution in the semiconductor body 101, thereby protecting the gate structure 102 and preventing the first insulating layer 105 from being broken down at the corner of the trench.

[0074] The plurality of first structures 11 are also located between the third region 111 and the second surface P2, further optimizing the electric field distribution, preventing the first insulating layer 105 from being broken down at the trench corners, improving the reverse characteristics and gate oxide reliability, and thus ensuring the long-term reliability of the device.

[0075] In some embodiments, Figure 1 As shown, along the direction Z perpendicular to the first interface P3 , the distance between the first interface P3 and the third region 111 ranges from 1 μm to 3 μm, for example, 1 μm, 1.5 μm, 2 μm, 2.5 μm, and 3 μm.

[0076] Since the plurality of first structures 11 are located within the third surface P3, by reasonably setting the distance between the third surface P3 and the second region 109, the spacing between the first structure 11 and the second region 109 along the direction Z can be optimized, and both can optimize the electric field distribution within the semiconductor body 101, thereby protecting the gate structure 102 and preventing the first insulating layer 105 from being broken down at the corner of the trench. By reasonably setting the spacing between the two, it is beneficial to further improve the overall reverse characteristics and gate oxide reliability of the device, thereby ensuring the long-term reliability of the device.

[0077] On the other hand, the present invention also provides a method for preparing a semiconductor device. Figure 3 As shown, Figure 3 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, Figure 4~Figure 14 A diagram of the various steps of preparing a semiconductor device provided in an embodiment of the present application.

[0078] like Figure 3 As shown, the preparation method includes the following steps S10 to S80:

[0079] Step S10: Figure 4 As shown, a first epitaxial layer 1012 is formed on a substrate 1011 , and the first epitaxial layer 1012 is set to be of a first conductivity type. The first epitaxial layer 1012 includes a first interface P3 away from a side of the substrate 1011 .

[0080] Step S20: Figure 5 As shown, a plurality of first structures 11 are formed at the first interface P3 , and the first structures 11 are set to be of the second conductivity type. The plurality of first structures 11 extend from the first interface P3 into the first epitaxial layer 1012 .

[0081] Exemplarily, the conductivity type of the first epitaxial layer 1012 is N-type, and a mask is formed by a photolithography process, an ion implantation region is defined, and a P + Ion implantation is performed to form the first structure 11. The implantation depth can be adjusted by controlling the implantation energy during the ion implantation process. The spacing and width of the plurality of first structures 11 can be adjusted by adjusting the morphology of the mask. For example, the spacing between two adjacent first structures 11 ranges from 1 μm to 8 μm.

[0082] Step S30: Figure 6As shown, a second epitaxial layer 1013 is formed, the second epitaxial layer 1013 is set to the first conductive type, and the second epitaxial layer 1013 is located on the side of the first epitaxial layer 1012 away from the substrate 1011, the second epitaxial layer 1013 includes a first surface P1 away from the side of the substrate 1011, and the substrate 1011 includes a second surface P2 away from the side of the second epitaxial layer 1013.

[0083] Exemplarily, a secondary epitaxial growth is performed on a side of the first epitaxial layer 1012 away from the substrate 1011 , with a growth thickness of 2 μm to 4 μm, thereby forming the second epitaxial layer 1013 .

[0084] Step S40: Figure 7~Figure 8 As shown, a first region 107, a well region 108 and a gate trench T1 are formed. The first region 107 is located on the first surface P1 and is set to the first conductivity type. The well region 108 is located on a side of the first region 107 away from the first surface P1 and is set to the second conductivity type. The gate trench T1 extends from the first surface P1 to the second epitaxial layer 1013.

[0085] In some embodiments, during the process of forming the gate trench T1 , a source trench T2 is also formed on the first surface P1 , and the source trench T2 extends from the first surface P1 into the second epitaxial layer 1013 .

[0086] For example, Figure 7 As shown, the conductivity type of the second epitaxial layer 1013 is also N-type. On the first surface P1 of the second epitaxial layer 1013, a mask is formed by a photolithography process to define an ion implantation area and perform P + Ion implantation is performed to form a well region 108. After the mask is removed, a mask is formed again through a photolithography process to define the ion implantation area and perform N + Ion implantation is performed to form the first region 107. The implantation energy is controlled to control the ion implantation depth, so that the first region 107 is located on the first surface P1, and the well region 108 is located on a side of the first region 107 away from the first surface P1.

[0087] Afterwards, if Figure 8 As shown, the gate trench T1 and the source trench T2 are formed by an etching process.

[0088] Step S50: Fig. 9 As shown, a second region 109 is formed, the second region 109 extends from the first surface P1 into the second epitaxial layer 1013 and is set to the second conductivity type.

[0089] In some embodiments, during the formation of the second region 109 , a third region 111 is also formed on the surface of the source trench T2 . The third region 111 is set to the second conductivity type, and the plurality of first structures 11 are also located on one side of the third region 111 close to the second surface P2 .

[0090] For example, Fig. 9 As shown, the ion implantation area is defined and a mask is formed to perform the ion implantation process, and finally the second area 109 and the third area 111 are formed. The ion implantation process can be performed multiple times, and the implantation energy can be adjusted according to the implantation depth. For example, P can be performed 4 to 5 times. + For ion implantation, the implantation energy ranges from 40 to 1200 keV, and the total dose ranges from 1E15 to 4E15, depending on the trench depth.

[0091] In some embodiments, after forming the second region 109 and the third region 111, a field limiting ring or a junction terminal is defined in the terminal region and ion implantation is completed. The field limiting ring is used to limit the distribution of the electric field to control the concentration of the electric field and prevent the electric field from being excessively concentrated at the edge of the device, thereby reducing the risk of edge breakdown and enhancing the stability and reliability of the device. The junction terminal is used to reduce the electric field strength in the region and reduce the concentration of the electric field at the PN junction terminal, thereby increasing the reverse breakdown voltage of the device. According to the device function and related needs, the above two structures can be set at the same time, or only one of them can be set.

[0092] After that, a carbon film is deposited on the device surface and activated by high-temperature annealing, and then removed after the annealing activation is completed. This process helps to activate the doped ions and repair the lattice defects caused by processes such as ion implantation, which is beneficial to improving the yield and reliability of the device.

[0093] Step S60: Figure 10~Figure 12 As shown, a gate structure 102 is formed in the gate trench T1 .

[0094] In some embodiments, during the process of forming the gate structure 102 in the gate trench T1 , a source trench structure 112 is also formed in the source trench T2 .

[0095] For example, Fig.10As shown, the gate oxide dielectric on the sidewall and the bottom is first grown by thermal oxidation in the trench through a high-temperature gate oxide process, that is, a first insulating layer 105 is formed in the gate trench T1, and a second insulating layer 113 is formed in the source trench T2. The first insulating layer 105 and the second insulating layer 113 are usually silicon dioxide, which are used to provide good electrical insulation performance and prevent current leakage. The first insulating layer 105 can also protect the gate structure 102. The third region 111 formed above can play a reverse shielding role, alleviate the electric field concentration problem of the gate structure 102 at the bottom of the trench, and prevent the first insulating layer 105 from being broken down at the corner of the trench.

[0096] Then, Fig.11 As shown, polysilicon is deposited and the excess portion is removed, and the deposited polysilicon material is patterned into a specific shape, that is, a gate structure 102 is finally formed in the gate trench T1, and a source trench structure 112 is formed in the source trench T2.

[0097] For subsequent processes such as Fig.12 As shown, a gate isolation dielectric layer 106 is formed, and the gate isolation dielectric layer 106 covers the gate structure 102 to isolate and protect the gate structure 102 .

[0098] Step S70: Figure 13~Figure 14 As shown, a source 103 is formed on the first surface P1 , and the second region 109 and at least a portion of the first surface P1 are connected to the source 103 to form a Schottky contact.

[0099] like Fig.13 As shown, a mask patterning process is first performed to define a source metal window, and metal is deposited using the mask as a shield, and finally the required ohmic contact layer 114 is formed on the first surface P1. Exemplarily, the ohmic contact layer 114 is metal nickel.

[0100] Then, if Fig.14 As shown, after removing the mask, a new mask is formed and patterned to define a Schottky window, and the mask is used as a shield to deposit Schottky metal, and finally a Schottky contact layer 110 is formed on the first surface P1. Exemplarily, the Schottky metal is titanium.

[0101] Then, if Fig.15 As shown, a source electrode 103 is formed on the first surface P1 . The source electrode 103 is located on a side of the Schottky contact layer 110 away from the semiconductor body 101 , and is electrically connected to the Schottky contact layer 110 and the ohmic contact layer 114 .

[0102] For example, in some embodiments, Fig.15 As shown, aluminum thickening metal is deposited by sputtering or evaporation to form the source 103 .

[0103] Afterwards, if Fig.16 As shown, a passivation layer 115 is deposited and a pad window V1 is formed by etching, and an insulating material is spin-coated on the surface of the passivation layer 115 and cured after development and exposure to form an insulating dielectric layer 116. The pad window V1 is used for subsequent electrical connection with other components.

[0104] Step S80: Fig.17 As shown, a drain 104 is formed, and the drain 104 is located on a side of the substrate 1011 away from the first epitaxial layer 1012. Specifically, the substrate 1011 is thinned to reduce the thickness of the semiconductor body 101 and form a relatively flat surface, and then metal is deposited and annealed to form an ohmic contact of the drain 104.

[0105] At this point, the semiconductor device 10 is completed.

[0106] In the above-mentioned preparation method, in the process of forming each structure of the semiconductor device 10, a plurality of first structures 11 are also formed. The preparation method is relatively simple and does not increase additional production costs. The plurality of first structures 11 can be used to improve the overall reverse characteristics and gate oxide reliability of the device, thereby ensuring the long-term reliability of the device.

[0107] In addition, in the above preparation method, the second region 109 and at least part of the first surface P1 are connected to the source 103 to form a Schottky contact. The process is relatively simple and does not increase additional production costs. The Schottky contact makes the on-state voltage drop and reverse recovery time of the semiconductor device 10 lower, reduces the reverse recovery energy consumption, and enhances the conduction performance and surge current resistance of the body diode. In addition, the problem of holes entering the drift layer will not occur during the freewheeling process, reducing the risk of double-click degradation of the device, and no external freewheeling diode is required, thereby improving the device integration. In the application process of photovoltaic inverter, motor drive, DCDC conversion and other related fields, no additional parallel diode is required, thereby reducing the application cost of related fields, and the semiconductor device 10 prepared by this method has a high degree of integration and is less restricted by the packaging form.

[0108] On the other hand, an embodiment of the present application further provides a power module, Fig.18 A schematic diagram of the structure of a power module provided in an embodiment of the present application.

[0109] like Fig.18 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10 .

[0110] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0111] On the other hand, an embodiment of the present application further provides a power conversion circuit, Fig.19 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application.

[0112] like Fig.19 As shown, the power conversion circuit 300 includes a circuit board 301 and a semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0113] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0114] On the other hand, an embodiment of the present application further provides a vehicle, Fig. 20 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0115] like Fig. 20 As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment, and the power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0116] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, which is set to a first conductivity type, includes a first surface and a second surface which are arranged opposite to each other, wherein the first surface is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body; the semiconductor body also includes a first region which is set to the first conductivity type, and the first region is arranged on the first surface; the semiconductor body also includes a well region which is set to the second conductivity type, and the well region is arranged on a side of the first region away from the first surface; the semiconductor body also includes a second region which is set to the second conductivity type, and the second region extends from the first surface into the semiconductor body; A gate structure, disposed in the gate trench; A source electrode, disposed on the first surface; The second region and at least a portion of the first surface are connected to the source electrode to form a Schottky contact; A drain electrode is disposed on the second surface; A plurality of first structures are set to a second conductivity type; the semiconductor body further comprises a first interface between the gate structure and the second surface, and the plurality of first structures are arranged on a side of the first interface close to the second surface; the semiconductor body comprises a substrate, a first epitaxial layer, and a second epitaxial layer stacked in sequence, a surface of the second epitaxial layer away from the substrate is the first surface, and a surface of the substrate away from the second epitaxial layer is the second surface; a surface of the first epitaxial layer away from the substrate is the first interface; The plurality of first structures extend from the first interface into the first epitaxial layer.

2. The semiconductor device according to claim 1, wherein: The semiconductor body further includes a third epitaxial layer located between the substrate and the first epitaxial layer, and a surface of the third epitaxial layer away from the substrate is a second interface; Among the plurality of first structures, a portion of the first structures extends from the first interface into the first epitaxial layer, and another portion of the first structures extends from the second interface into the third epitaxial layer.

3. The semiconductor device according to claim 1, wherein: The first region and the second region are arranged along a first direction, and the first direction is parallel to the first surface; The plurality of first structures are arranged at intervals along the first direction, and each first structure extends along a second direction; the second direction is parallel to the first surface and intersects with the first direction; or, The plurality of first structures include a plurality of rows and a plurality of columns. The first structures in each row are arranged at intervals along the first direction, and the first structures in each column are arranged at intervals along the second direction.

4. The semiconductor device according to claim 1, wherein: The first region and the second region are arranged along a first direction, and the first direction is parallel to the first surface; The plurality of first structures include a plurality of first linear structures and a plurality of second linear structures, each of the first linear structures extends along the first direction, and each of the second linear structures extends along a second direction; the second direction is parallel to the first surface and intersects with the first direction; The plurality of first linear structures and the plurality of second linear structures are interwoven into a network.

5. The semiconductor device according to claim 1, wherein: The interval between two adjacent first structures ranges from 1 μm to 8 μm.

6. The semiconductor device according to claim 1, wherein: Along a direction perpendicular to the first interface, a depth of the first structure ranges from 1 μm to 5 μm.

7. The semiconductor device according to claim 1, wherein: The first surface is also provided with a source trench, and the source trench extends from the first surface into the semiconductor body; The semiconductor body further includes a third region which is set to a second conductivity type, and the third region is arranged on the surface of the source trench; the semiconductor device further includes a source trench structure, and the source trench structure is located in the source trench; The plurality of first structures are also located on a side of the third region close to the second surface.

8. The semiconductor device according to claim 7, characterized in that Along a direction perpendicular to the first interface, a distance between the first interface and the third region ranges from 1 μm to 3 μm.

9. A method for preparing a semiconductor device, characterized in that: include: forming a first epitaxial layer on a substrate, wherein the first epitaxial layer is set to be a first conductivity type; The first epitaxial layer comprises a first interface away from a side of the substrate; forming a plurality of first structures at the first interface, wherein the first structures are set to be of the second conductivity type; and the plurality of first structures extend from the first interface into the first epitaxial layer; forming a second epitaxial layer, wherein the second epitaxial layer is set to be of the first conductivity type; the second epitaxial layer is located on a side of the first epitaxial layer away from the substrate, the second epitaxial layer includes a first surface away from the substrate, and the substrate includes a second surface away from the second epitaxial layer; forming a first region, a well region and a gate trench, wherein the first region is located on the first surface and is set to be of a first conductivity type; The well region is located on a side of the first region away from the first surface and is set to be of the second conductivity type; the gate trench extends from the first surface into the second epitaxial layer; forming a second region, the second region extending from the first surface into the second epitaxial layer and being set to a second conductivity type; forming a gate structure in the gate trench; A source electrode is formed on the first surface, and the second region and at least a portion of the first surface are connected to the source electrode to form a Schottky contact; A drain is formed, where the drain is located on a side of the substrate away from the first epitaxial layer.

10. The preparation method according to claim 9, characterized in that: In the process of forming the gate trench, a source trench is also formed on the first surface, wherein the source trench extends from the first surface into the second epitaxial layer; In the process of forming the second region, a third region is also formed on the surface of the source trench, and the third region is set to be of the second conductivity type; the plurality of first structures are also located on a side of the third region close to the second surface; During the process of forming the gate structure in the gate trench, a source trench structure is also formed in the source trench.

11. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 8; A substrate is used to carry the semiconductor device.

12. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 12, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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