Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a preparation method thereof, and relates to the technical field of integrated circuits, wherein a source electrode is located on a substrate; a dielectric core is located on a side of the source electrode away from the substrate; a channel layer is located between the dielectric core and the source electrode, and covers a bottom surface and a sidewall of the dielectric core, a top surface of the channel layer is higher than a top surface of the dielectric core and forms a groove above the dielectric core; a conductive plug is at least partially located in the groove, and a bottom surface of the conductive plug is lower than the top surface of the channel layer; a drain electrode is located between the channel layer and the conductive plug, and a sidewall of the drain electrode is partially covered by the conductive plug, so that the performance and reliability of the semiconductor device can be improved without increasing the volume of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the rapid development of semiconductor technology, the market has increasingly high requirements for the integration, performance and reliability of integrated circuits. The market has increasingly high requirements for the number of integrated transistors per unit area, and requires smaller transistor structures and more compact design layouts, which brings challenges to the improvement of the performance and reliability of semiconductor devices.

[0003] Therefore, how to improve the performance and reliability of the preparation of semiconductor devices without increasing the volume of the transistor structure has become one of the technical problems to be solved. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor device and a preparation method thereof to at least ensure that the volume of the semiconductor device is not increased, and the performance and reliability of the semiconductor device are improved.

[0005] According to various embodiments of the present disclosure, the first aspect of the present disclosure provides a semiconductor device, comprising a substrate, a source, a dielectric core, a channel layer, a conductive plug and a drain, the source is located on the substrate; the dielectric core is located on the side of the source away from the substrate; the channel layer is located between the dielectric core and the source, and covers the bottom surface and the sidewall of the dielectric core, the top surface of the channel layer is higher than the top surface of the dielectric core and forms a groove above the dielectric core; the conductive plug is at least partially located in the groove, and the bottom surface of the conductive plug is lower than the top surface of the channel layer; the drain is located between the channel layer and the conductive plug, and the sidewall of the drain is covered by part of the conductive plug.

[0006] The semiconductor device in the above embodiment, by setting the source on the substrate, the dielectric core on the side of the source away from the substrate, the channel layer between the dielectric core and the source, and covering the bottom surface and the sidewall of the dielectric core, forming a U-shaped channel layer, the top surface of the channel layer is higher than the top surface of the dielectric core and forms a groove above the dielectric core, so as to set the conductive plug at least partially in the groove, so that the bottom surface of the conductive plug is lower than the top surface of the channel layer, and the drain is set between the channel layer and the conductive plug, so that the sidewall of the drain is covered by part of the conductive plug, the contact area of the drain and the conductive plug is increased without increasing the volume of the semiconductor device, the volume of the conductive plug is relatively increased, the connection impedance between the conductive plug and the drain is reduced, and the performance and reliability of the semiconductor device are improved.

[0007] In some embodiments, the longitudinal section of the conductive plug is "T" shaped, and the bottom surface of the conductive plug contacts the top surface of the dielectric core, such that the conductive plug is partially located in a groove formed on the top surface of the channel layer above the dielectric core, thereby relatively increasing the volume of the conductive plug without increasing the volume of the semiconductor device; this facilitates the formation of a drain electrode partially covered by the conductive plug on the sidewall of the groove, further increasing the contact area between the conductive plug and the drain electrode.

[0008] In some embodiments, the conductive plug further includes a first portion located within the groove and a second portion located above the first portion; the semiconductor device further includes an interconnect pillar located on the top surface of the second portion, with the vertical center line of the second portion situated between the vertical center line of the first portion and the vertical center line of the interconnect pillar, which facilitates setting the specific position of the interconnect pillar on the conductive plug according to the actual needs of integrated circuit fabrication, thereby meeting the integration requirements of integrated circuits while reducing the complexity and cost of the fabrication process.

[0009] In some embodiments, the thickness of the drains on both sides of the conductive plug is equal, so that the size and performance of the drains on both sides of the conductive plug are as consistent as possible, thereby improving the performance and reliability of the semiconductor device.

[0010] In some embodiments, the bottom surface of the conductive plug is lower than the bottom surface of the drain and extends into the dielectric core, thereby increasing the volume of the conductive plug without increasing the volume of the semiconductor device, thereby reducing the connection impedance between the conductive plug and the drain; furthermore, the extension of the conductive plug into the dielectric core can also reduce the complexity and cost of the fabrication process in practical applications.

[0011] In some embodiments, the semiconductor device further includes a gate dielectric layer and a gate conductive layer, the gate conductive layer being located on the outer wall of the channel layer; the gate dielectric layer being located between the gate conductive layer and the channel layer, the top surface of the gate dielectric layer being higher than the bottom surface of the conductive plug.

[0012] In some embodiments, a second aspect of this disclosure provides a method for fabricating a semiconductor device, comprising:

[0013] A substrate is provided, on which a source electrode is included;

[0014] An intermediate layer is formed on the side of the source electrode away from the substrate, and the intermediate layer includes a trench that exposes part of the source electrode.

[0015] Forming a channel layer that covers the sidewalls of the trench and the exposed source electrode;

[0016] A dielectric core is formed within the trench, and the top surface of the trench layer is higher than the top surface of the dielectric core, forming a groove located above the dielectric core;

[0017] A drain electrode is formed on the sidewall of the groove;

[0018] forming a conductive plug at least partially in the trench, a bottom surface of the conductive plug being lower than a top surface of the channel layer, the sidewall of the drain being partially covered by the conductive plug.

[0019] In some embodiments, forming the drain on the sidewall of the trench comprises:

[0020] forming a drain covering the sidewall of the trench and the top surface of the dielectric core.

[0021] In some embodiments, forming the drain on the sidewall of the trench comprises:

[0022] forming a layer of drain material, the layer of drain material conformally covering the sidewall of the trench and the top surface of the dielectric core;

[0023] removing the layer of drain material from at least the top surface of the dielectric core, leaving the layer of drain material on the sidewall of the trench to form the drain.

[0024] In some embodiments, during the removing of the layer of drain material from the top surface of the dielectric core, over-etching forms a recess towards the dielectric core; the conductive plug is partially in the recess, which further increases the volume of the conductive plug without increasing the volume of the semiconductor device, thereby reducing the connection impedance between the conductive plug and the drain; and, in the actual process, during the removing of the layer of drain material from the top surface of the dielectric core, over-etching forms a recess towards the dielectric core, which ensures that the layer of drain material on the top surface of the dielectric core is completely removed, so that the drains on both sides of the conductive plug are isolated.

[0025] In some embodiments, forming the conductive plug at least partially in the trench comprises:

[0026] forming a barrier layer covering the top surface of the dielectric core and the drain;

[0027] forming a conductive layer filling the trench; the barrier layer and the conductive layer are used to jointly form the conductive plug.

[0028] In the above embodiments, after forming the barrier layer covering the top surface of the dielectric core and the drain, the conductive layer filling the trench is formed, which avoids metal ions between the conductive layers from entering the dielectric core to form a current leakage channel, thereby improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0030] Figure 1A flowchart of a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0031] Figure 2 A longitudinal cross-sectional structure of a semiconductor structure obtained in step S20 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0032] Figure 3 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming a gate conductive part in step S40 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0033] Figure 4 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming an intermediate layer and an isolation layer in step S40 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0034] Figure 5 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming a gate conductive layer in step S40 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0035] Figure 6 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming a gate dielectric layer in step S40 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0036] Figure 7 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming a trench in step S40 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0037] Figure 8 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming an initial channel layer and a dielectric core in step S80 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0038] Figure 9 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming a drain material layer in step S100 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0039] Figure 10 A longitudinal cross-sectional structure of a semiconductor structure obtained after forming a drain in step S100 in a semiconductor device manufacturing method is shown in an embodiment of the present disclosure;

[0040] Figure 11A longitudinal sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in a semiconductor device preparation method provided by an embodiment of the present disclosure, after the conductive plug is formed in step S110, a longitudinal sectional structure diagram of the obtained semiconductor structure is shown;

[0041] Figure 12 A longitudinal sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in a semiconductor device preparation method provided by an embodiment of the present disclosure, after the isolation structure is formed, a longitudinal sectional structure diagram of the obtained semiconductor structure is shown;

[0042] Figure 13 A longitudinal sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in a semiconductor device preparation method provided by an embodiment of the present disclosure, after the interconnection column is formed, a longitudinal sectional structure diagram of the obtained semiconductor structure is shown;

[0043] Figure 14a A longitudinal sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in a semiconductor device preparation method provided by an embodiment of the present disclosure, after the interconnection column is formed, a longitudinal sectional structure diagram of the obtained semiconductor structure is shown;

[0044] Figure 14b A longitudinal sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in a semiconductor device preparation method provided by an embodiment of the present disclosure, after the interconnection column is formed, a longitudinal sectional structure diagram of the obtained semiconductor structure is shown;

[0045] Figure 15 A longitudinal sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in a semiconductor device preparation method provided by an embodiment of the present disclosure, after the interconnection column is formed, a longitudinal sectional structure diagram of the obtained semiconductor structure is shown;

[0046] Figure 16 A longitudinal sectional structure diagram of a semiconductor device provided by an embodiment of the present disclosure is shown in a semiconductor device preparation method provided by an embodiment of the present disclosure, after the interconnection column is formed, a longitudinal sectional structure diagram of the obtained semiconductor structure is shown.

[0047] Legend of reference signs:

[0048] 100, substrate; 1, first metal layer; 2, first barrier layer; 1211, gate conductive material layer; 10, source electrode; 1000, stack; 20, dielectric core; 31, initial channel layer; 30, channel layer; 23, groove; 231, recess; 40, conductive plug; 41, first part; 42, second part; 401, barrier layer; 402, conductive layer; 403, isolation groove; 101, initial trench; 11, trench; 61, gate dielectric layer; 62, gate conductive layer; 51, drain material layer; 50, drain electrode; 60, gate electrode; 80, interlayer dielectric layer; 110, isolation structure; 111, first dielectric layer; 112, second dielectric layer; 90, interconnection column; 12, intermediate layer; 13, isolation layer; 121, gate conductive part; 122, isolation part. DETAILED DESCRIPTION

[0049] For the purposes of the present disclosure, certain terms will now be defined, summarized below. These preferred embodiments of the present disclosure are shown in the attached drawings, which are made a part hereof, and specific language is used herein for the purpose of describing particular embodiments. But the disclosure made herein is not intended to be limited to the described embodiments, but is to be accorded the full scope consistent with the scope of the claims, wherein reference to a particular embodiment includes not only that embodiment but also the equivalent embodiment.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for describing particular embodiments only and is not intended to be limiting of the disclosure.

[0051] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.

[0052] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0054] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

[0055] It is to be understood that the above description and the embodiments described therein are merely exemplary of the inventive concepts described herein, and that a wide variety of alternative embodiments incorporating the principles described herein will be apparent to those of ordinary skill in the art from the information provided herein.

[0056] Reference will now be made to the drawings, wherein Figure 1In some embodiments, a semiconductor device manufacturing method is provided, comprising steps S20-S110, wherein:

[0057] Step S20: providing a substrate, the substrate comprising a source electrode thereon;

[0058] Step S40: forming an intermediate layer on a side of the source electrode away from the substrate, the intermediate layer comprising a trench exposing a portion of the source electrode;

[0059] Step S60: forming a channel layer covering the sidewall of the trench and the exposed source electrode;

[0060] Step S80: forming a dielectric core in the trench, the top surface of the channel layer being higher than the top surface of the dielectric core and forming a recess above the dielectric core;

[0061] Step S100: forming a drain electrode on the sidewall of the recess;

[0062] Step S110: forming a conductive plug at least partially in the recess, the bottom surface of the conductive plug being lower than the top surface of the channel layer, and the sidewall of the drain electrode being partially covered by the conductive plug.

[0063] In some embodiments, referring to Figure 2 The material of the substrate 100 provided in step S20 can include, but is not limited to, a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 100 is a semiconductor structure that provides mechanical support and electrical performance for the semiconductor device. The substrate 100 can be a single-layer structure or a multi-layer structure. For example, the substrate 100 can be a III / V semiconductor substrate or a II / VI semiconductor substrate. Those skilled in the art can select the type of substrate 100 according to the type of transistor formed on the substrate 100, and therefore the type of substrate 100 should not limit the scope of protection of the present disclosure.

[0064] As an example, referring to Figure 2The first metal layer 1, the first barrier layer 2, the source electrode 10, the interlayer dielectric layer 80, and the gate conductive material layer 1211 can be sequentially formed on the substrate 100 in a direction away from the substrate 100, for example, the OY direction, by using a chemical vapor deposition or a physical vapor deposition (PVD) process. The chemical vapor deposition process can include, but is not limited to, one or more of an atmospheric-pressure CVD (APCVD), a low-pressure CVD (LPCVD), or a plasma-enhanced CVD (PECVD) process. For example, the LPCVD process has good step coverage, and can improve the deposition rate and output, and reduce the process cost. In addition, the LPCVD process does not need a carrier gas, and can reduce particle pollution.

[0065] As an example, please continue to refer to Figure 2 The material of the first metal layer 1 can include, but is not limited to, at least one of titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, etc. The material of the first barrier layer 2 can include, but is not limited to, at least one of a titanium nitride layer, a cobalt layer, a platinum layer, and a titanium tungsten layer, etc. The material of the source electrode 10 can include, but is not limited to, at least one of a semiconductor material, a metal, a metal silicide, etc. The material of the interlayer dielectric layer 80 can include, but is not limited to, at least one of silicon dioxide, silicon nitride, silicon oxynitride, amorphous carbon, etc. The material of the gate conductive material layer 1211 can include, but is not limited to, at least one of indium tin oxide, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, titanium nitride, tantalum nitride, etc.

[0066] In some embodiments, please refer to Figure 3 The forming of the intermediate layer 12 in step S40 can include: patterning the gate conductive material layer 1211 to obtain a plurality of gate conductive portions 121 arranged at intervals along the OX direction. The patterning can include a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0067] In some embodiments, please refer to Figure 4In step S40, forming the intermediate layer 12 can include: forming isolation portions 122 in gaps between the gate conductive portions 121 adjacent along the OX direction, and the gate conductive portions 121 and the isolation portions 122 arranged alternately along the OX direction are used to jointly form the intermediate layer 12. For example, the isolation portions 122 between the gate conductive portions 121 adjacent along the OX direction can be formed by using a deposition process or a spin on glass (SOG) process. The material of the isolation portions 122 can include, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), etc.

[0068] In some embodiments, please continue to refer to Figure 4 After forming the isolation portions 122, the isolation layer 13 covering the intermediate layer 12 can be formed by using a deposition process. The material of the isolation layer 13 can include, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), etc.

[0069] In some embodiments, please refer to Figure 5 In step S40, forming the intermediate layer 12 can include: forming a plurality of initial grooves 101 penetrating through the isolation layer 13 and the plurality of gate conductive portions 121 along a direction perpendicular to the substrate 100, for example, the OY direction, and the remaining gate conductive portions 121 form gate conductive layers 62 arranged at intervals along the OX direction; and the initial grooves 101 are located between the gate conductive layers 62 adjacent along the OX direction. For example, a patterned photoresist layer (not shown) can be formed on the top surface of the isolation layer 13, and the patterned photoresist layer includes an opening pattern (not shown) used to define the initial grooves 101; then, the isolation layer 13 and the gate conductive portions 121 are etched by using the patterned photoresist layer as a mask, so as to obtain a plurality of initial grooves 101 penetrating through the isolation layer 13 and the plurality of gate conductive portions 121 along the OY direction, and the remaining gate conductive portions 121 form gate conductive layers 62 arranged at intervals along the OX direction.

[0070] In some embodiments, please refer to Figure 6 After forming the initial grooves 101 and before forming the channel layer, the method further includes: forming a gate dielectric material layer (not shown) covering the top surface of the remaining isolation layer 13 and the sidewall and bottom surface of the initial grooves 101 by using a deposition process; and removing the gate dielectric material layer located on the top surface of the remaining isolation layer 13 and the bottom surface of the initial grooves 101 by using a dry etching process, and the remaining gate dielectric material layer is used to form the gate dielectric layer 61.

[0071] In some embodiments, please refer to Figure 7After forming the gate dielectric layer 61 and before forming the channel layer, a dry etching process can be performed to remove the ILD layer 80 exposed by the plurality of initial trenches 101 and located between the gate dielectric layers 61 along the OX direction, to obtain a plurality of trenches 11 spaced along the OX direction and exposing part of the source 10.

[0072] In some embodiments, referring to Figure 8 forming the channel layer 30 covering the sidewalls of the trenches 11 and the exposed source 10 in step S60 can include forming an initial channel layer 31 covering the top surface of the remaining isolation layer 13, the sidewalls of the trenches 11, and the exposed source 10 by a deposition process.

[0073] In some embodiments, referring to Figure 8 forming the dielectric core 20 in the trenches 11 in step S80 can include forming a dielectric material (not shown) filling the trenches 11 by a deposition process or a Spin On Glass (SOG) coating process; and etching back the dielectric material to obtain the dielectric core 20 with a top surface flush with the top surface of the gate conductive layer 62 and the recess 23 located above the dielectric core 20. The material of the dielectric core 20 can include, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0074] In some embodiments, referring to Figure 9 forming the drain 50 in the recess 23 in step S100 can include forming a drain material layer 51 conformally covering the exposed surface of the initial channel layer 31 and the top surface of the dielectric core 20 by an ALD deposition process. The material of the drain material layer 51 can include, but is not limited to, at least one of a semiconductor material, a metal, a metal silicide, etc.

[0075] In some embodiments, referring to Figure 10 a dry etching process can be performed to remove at least the drain material layer 51 located on the top surface of the remaining isolation layer 13 to obtain the drain 50 located in the recess 23.

[0076] In some embodiments, referring to Figure 10 the initial channel layer 31 located on the top surface of the remaining isolation layer 13 can be removed simultaneously in the process of removing the drain material layer 51 located on the top surface of the remaining isolation layer 13 to obtain the channel layer 30 and the drain 50 covering the sidewalls of the recess 23 and the top surface of the dielectric core 20, thereby reducing the complexity and cost of the fabrication process.

[0077] In some embodiments, referring to Figure 10The remaining portions of the drain material layer 51 on the top surface of the dielectric core 20 and the remaining isolation layer 13 can be removed simultaneously, and the portions of the drain material layer 51 remaining in the recess 23 and on the sidewall of the channel layer 30 are used to form the drain 50.

[0078] In some embodiments, referring to Figure 10 The over-etching can form a recess 231 towards the dielectric core 20 during the removal of the drain material layer 51 on the top surface of the dielectric core 20 and the remaining isolation layer 13, so that the subsequently prepared portions of the conductive plug 40 are located in the recess 231, thereby further increasing the volume of the conductive plug 40 without increasing the volume of the semiconductor device, and thus reducing the connection impedance between the conductive plug 40 and the drain.

[0079] In some embodiments, referring to Figure 11 The forming of the conductive plug 40 at least partially in the recess 23 in step S110 includes: forming a barrier material layer (not shown) covering the top surface of the remaining isolation layer 13, the sidewall of the drain 50, and the top surface of the dielectric core 20 by using a deposition process, and then forming a conductive material layer (not shown) on the exposed surface of the barrier material layer, the conductive material layer and the barrier material layer at least filling the remaining gap of the recess 23; after planarizing the top surface of the conductive material layer, removing the portions of the conductive material layer and the barrier material layer on the top surface of the remaining isolation layer 13 by using a photolithography and etching process, the remaining conductive material layer being used to form the conductive layer 402, and the remaining barrier material layer being used to form the barrier layer 401, the barrier layer 401 and the conductive layer 402 being used to form the conductive plug 40, thereby obtaining the conductive plug 40 and the isolation recess 403 alternately arranged along the OX direction. The barrier material layer can prevent the metal ions from entering the dielectric core 20 during the formation of the conductive material layer to form a current leakage channel, thereby improving the performance and reliability of the semiconductor device.

[0080] Please continue to refer to Figure 11 The gate conductive layer 62 is located on the outer sidewall of the channel layer 30, and the gate dielectric layer 61 is located between the gate conductive layer 62 and the channel layer 30, the top surface of the gate dielectric layer 61 being higher than the bottom surface of the conductive plug 40, the gate dielectric layer 61 and the gate conductive layer 62 being used to jointly form the gate 60.

[0081] In some embodiments, please continue to refer to Figure 11 The gate 60 can partially surround the channel layer 30 to relatively increase the contact area between the gate 60 and the channel layer 30, thereby improving the performance and reliability of the device.

[0082] In some embodiments, the gate can circumferentially surround the channel layer to form a ring gate structure, thereby further increasing the contact area between the gate and the channel layer, and improving the performance and reliability of the device.

[0083] In some embodiments, referring to Figure 12 , a first dielectric layer 111 is formed on the sidewall of the isolation recess 403, and then a second dielectric layer 112 is formed in the isolation recess 403, the first dielectric layer 111 and the second dielectric layer 112 are used to jointly form an isolation structure 110, the isolation structure 110 at least fills the isolation recess 403. A planarization process can be used to make the top surface of the isolation structure 110 flush with the top surface of the conductive plug 40. The material of the first dielectric layer 111 includes but is not limited to silicon nitride. The material of the second dielectric layer 112 includes but is not limited to silicon oxide. The isolation structure formed by the silicon nitride and the silicon oxide can alleviate the warping stress generated by the adjacent conductive plug 40 on the substrate 100.

[0084] In some embodiments, referring to Figure 13 , the conductive plug 40 further includes a first part 41 located in the recess 23, and a second part 42 located above the first part 41; the semiconductor device further includes an interconnection column 90 located on the top surface of the second part 42, and the vertical center line 42a of the second part 42 is between the vertical center line 41a of the first part 41 and the vertical center line 90a of the interconnection column 90, which facilitates setting the specific position of the interconnection column 90 on the conductive plug 40 according to the actual needs of preparing the integrated circuit, and meets the integrated degree requirement of the integrated circuit while reducing the complexity and cost of the preparation process.

[0085] In some embodiments, referring to Figure 13 , an Atomic Layer Deposition (ALD) process is used to form a conformal covering of the exposed surface of the initial channel layer 31 and the top surface of the dielectric core 20, and a drain material layer 51, so that the thickness of the drain 50 located on both sides of the conductive plug 40 is equal, and the size and performance of the drain 50 on both sides of the conductive plug 40 are kept as consistent as possible, thereby improving the performance and reliability of the semiconductor device.

[0086] In some embodiments, referring to Figure 14a , a semiconductor device is provided, including a substrate 100, a source 10, a dielectric core 20, a channel layer 30, a conductive plug 40, and a drain, the source 10 is located on the substrate 100; the dielectric core 20 is located on the side of the source 10 away from the substrate 100; the channel layer 30 is located between the dielectric core 20 and the source 10, and covers the bottom surface and the sidewall of the dielectric core 20, the top surface of the channel layer 30 is higher than the top surface of the dielectric core 20 and forms a recess 23 above the dielectric core 20; the conductive plug 40 is at least partially located in the recess 23, and the bottom surface of the conductive plug 40 is lower than the top surface of the channel layer 30; the drain is located between the channel layer 30 and the conductive plug 40, and the sidewall of the drain is partially covered by the conductive plug 40.

[0087] For example, referring to Figure 14a, by setting the source electrode 10 on the substrate 100, the dielectric core 20 on the side of the source electrode 10 away from the substrate 100, the channel layer 30 between the dielectric core 20 and the source electrode 10, and the channel layer 30 covering the bottom surface and the sidewall of the dielectric core 20, forming a U-shaped channel layer 30, the top surface of the channel layer 30 being higher than the top surface of the dielectric core 20 and forming a groove 23 above the dielectric core 20, and setting the conductive plug 40 at least partially in the groove 23, so that the bottom surface of the conductive plug 40 is lower than the top surface of the channel layer 30, and the drain electrode 50 is set between the channel layer 30 and the conductive plug 40, so that the sidewall of the drain electrode 50 is partially covered by the conductive plug 40.

[0088] In some embodiments, please refer to Figure 14a , the longitudinal section of the conductive plug 40 is in the shape of "T", and the bottom surface of the conductive plug 40 contacts the top surface of the dielectric core 20, so that the conductive plug 40 is partially in the groove 23 above the dielectric core 20 formed by the top surface of the channel layer 30, and the volume of the conductive plug 40 is relatively increased without increasing the volume of the semiconductor device; it is convenient to form the drain electrode covered by the conductive plug 40 on the sidewall of the groove 23, further increasing the contact area between the conductive plug 40 and the drain electrode.

[0089] In some embodiments, please refer to Figure 14a , the conductive plug 40 further includes a first part 41 in the groove 23 and a second part 42 above the first part 41; the semiconductor device further includes an interconnection column 90 on the top surface of the second part 42, and the vertical center line 42a of the second part 42 is between the vertical center line 41a of the first part 41 and the vertical center line 90a of the interconnection column 90, which facilitates setting the specific position of the interconnection column 90 on the conductive plug 40 according to the actual needs of preparing integrated circuits, meeting the integration requirements of integrated circuits while reducing the complexity and cost of the preparation process.

[0090] In some embodiments, please refer to Figure 14b , Figure 14a , Figure 14b The differences include: Figure 14a In the first aspect, the bottom surface of the conductive plug 40 contacts the top surface of the dielectric core 20, and the drain electrode 50 is located on the outer sidewall of the conductive plug 40; Figure 14b In the second aspect, the drain electrode 50 includes a first part 50a between the bottom surface of the conductive plug 40 and the source electrode 10, and a second part 50b on the outer sidewall of the conductive plug 40. Figure 14b Compared with Figure 14a , the contact area between the conductive plug 40 and the drain electrode 50 is increased, which can reduce the connection impedance between the conductive plug 40 and the drain electrode 50.

[0091] In some embodiments, please refer to Figure 15The bottom surface of the conductive plug 40 is lower than the bottom surface of the drain 50 and extends into the dielectric core 20, thereby increasing the volume of the conductive plug 40 without increasing the volume of the semiconductor device, thus reducing the connection impedance between the conductive plug 40 and the drain. Furthermore, the extension of the conductive plug 40 into the dielectric core 20 can also reduce the complexity and cost of the fabrication process in practical applications.

[0092] In some embodiments, please continue reading Figure 14a , Figure 14b or Figure 15 The thickness of the drains 50 on both sides of the conductive plug 40 is equal, so that the size and performance of the drains on both sides of the conductive plug 40 are kept as consistent as possible, thereby improving the performance and reliability of the semiconductor device.

[0093] In some embodiments, please continue reading Figure 14a , Figure 14b or Figure 15 The semiconductor device also includes a gate dielectric layer 61 and a gate conductive layer 62. The gate conductive layer 62 is located on the outer wall of the channel layer 30. The gate dielectric layer 61 is located between the gate conductive layer 62 and the channel layer 30, and the top surface of the gate dielectric layer 61 is higher than the bottom surface of the conductive plug 40. The gate dielectric layer 61 and the gate conductive layer 62 are used together to form the gate 60.

[0094] In some embodiments, the gate may partially surround the channel layer to relatively increase the contact area between the gate and the channel layer, thereby improving the performance and reliability of the device.

[0095] In some embodiments, the gate can circumferentially surround the channel layer to form a gate ring structure, further increasing the contact area between the gate and the channel layer and improving the performance and reliability of the device.

[0096] Please continue reading. Figure 15 , Figure 16 , Figure 16 and Figure 15 The differences include: Figure 16 The intermediate drain 50 is located outside the recess 23 and between the bottom surface of the conductive plug 40 and the top surface of the channel layer 30. Relative to... Figure 16 , Figure 15 The method achieves at least the following: without increasing the size of the semiconductor device, it increases the contact area between the drain 50 and the conductive plug 40, relatively increases the volume of the conductive plug 40, reduces the connection impedance between the conductive plug 40 and the drain 50, and improves the performance and reliability of the semiconductor device.

[0097] In some embodiments, a memory is provided, including the semiconductor device in any embodiment of this application.

[0098] In some embodiments, a memory is provided, comprising a memory prepared by the semiconductor device preparation method of any of the embodiments of the present application.

[0099] In some embodiments, an electronic device is provided, comprising the semiconductor device of any of the embodiments of the present application.

[0100] In some embodiments, an electronic device is provided, comprising the memory of any of the embodiments of the present application.

[0101] The aforementioned electronic device is, for example but not limited to, a consumer electronic product, a home electronic product, a vehicle electronic product, a financial terminal product, and the like. The consumer electronic product is, for example, a mobile phone, a tablet computer, a notebook computer, a desktop display, an all-in-one computer, and the like. The home electronic product is, for example, a smart door lock, a television, a refrigerator, a wearable device, and the like. The vehicle electronic product is, for example, a vehicle navigation device, a vehicle DVD, and the like. The financial terminal product is, for example, an ATM machine, a self-service terminal, and the like.

[0102] Please note that, for the sake of brevity of the description, in the structural schematic diagrams of the following embodiments, unless a corresponding cross-sectional structural schematic diagram is separately given, the structural schematic diagrams of different perspectives of the structures related to the inventive points of the embodiments of the present application can be referred to each other.

[0103] The technical features of the above embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they shall be considered as within the scope of the present application.

[0104] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor device, characterized by, A semiconductor device comprising: a substrate; a source on the substrate; a dielectric core on a side of the source facing away from the substrate; a channel layer between the dielectric core and the source, covering a bottom surface and a sidewall of the dielectric core, a top surface of the channel layer being higher than a top surface of the dielectric core and forming a recess above the dielectric core; a conductive plug at least partially in the recess, a bottom surface of the conductive plug being lower than the top surface of the channel layer; a drain between the channel layer and the conductive plug, a sidewall of the drain being partially covered by the conductive plug; the bottom surface of the conductive plug contacting the top surface of the dielectric core.

2. The semiconductor device according to claim 1, wherein a longitudinal cross-section of the conductive plug is in a "T" shape.

3. The semiconductor device of claim 1, wherein thicknesses of the drain on both sides of the conductive plug are equal.

4. A semiconductor device, characterized by A semiconductor device comprising: a substrate; a source on the substrate; a dielectric core on a side of the source facing away from the substrate; a channel layer between the dielectric core and the source, covering a bottom surface and a sidewall of the dielectric core, a top surface of the channel layer being higher than a top surface of the dielectric core and forming a recess above the dielectric core; a conductive plug at least partially in the recess, a bottom surface of the conductive plug being lower than the top surface of the channel layer; a drain between the channel layer and the conductive plug; wherein the conductive plug further comprises a first portion in the recess and a second portion above the first portion; the semiconductor device further comprises: an interconnection pillar on a top surface of the second portion, a vertical centerline of the second portion being between a vertical centerline of the first portion and a vertical centerline of the interconnection pillar.

5. A semiconductor device, characterized by, A semiconductor device comprising: a substrate; a source on the substrate; a dielectric core on a side of the source facing away from the substrate; a channel layer between the dielectric core and the source, covering a bottom surface and a sidewall of the dielectric core, a top surface of the channel layer being higher than a top surface of the dielectric core and forming a recess above the dielectric core; a conductive plug at least partially in the recess, a bottom surface of the conductive plug being lower than the top surface of the channel layer; a drain between the channel layer and the conductive plug; wherein the bottom surface of the conductive plug is lower than a bottom surface of the drain and extends into the dielectric core.

6. The semiconductor device according to claim 5, wherein further comprising: a gate conductive layer on an outer sidewall of the channel layer; a gate dielectric layer between the gate conductive layer and the channel layer, a top surface of the gate dielectric layer being higher than the bottom surface of the conductive plug.

7. A method of fabricating a semiconductor device, characterized by, A semiconductor device comprising: providing a substrate, the substrate comprising a source thereon; forming an intermediate layer on a side of the source facing away from the substrate, the intermediate layer comprising a trench exposing a portion of the source; forming a channel layer covering a sidewall of the trench and the exposed source; forming a dielectric core in the trench, a top surface of the channel layer being higher than a top surface of the dielectric core and forming a recess above the dielectric core; forming a drain on a sidewall of the recess; forming a conductive plug at least partially in the recess, a bottom surface of the conductive plug being lower than the top surface of the channel layer, a sidewall of the drain being partially covered by the conductive plug, the bottom surface of the conductive plug contacting the top surface of the dielectric core.

8. The method of fabricating a semiconductor device according to claim 7, wherein forming a drain on a sidewall of the recess, comprising: forming a drain covering sidewalls of the recess and a top surface of the dielectric core.

9. The method of fabricating a semiconductor device according to claim 8, wherein over-etching during removal of the drain material layer from the top surface of the dielectric core forms a recess toward the dielectric core; the conductive plug portion is located within the recess.

10. The method of fabricating a semiconductor device of claim 7, wherein, forming a conductive plug at least partially located within the recess, including: forming a barrier layer covering the top surface of the dielectric core and the drain; forming a conductive layer filling the recess; the barrier layer and the conductive layer are configured to collectively constitute the conductive plug.

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