A driving circuit for accurately controlling conversion rate and a driving method thereof

Abstract

The present invention discloses a driving circuit and a driving method for accurately controlling a conversion rate, comprising a logic control module, a driving module, a power tube Vth compensation module, an auxiliary driving module, a current source I1, a current source I2, a PMOS tube M3, an NMOS tube M2, a resistor R1, a capacitor C1 and a power tube M1. The logic control module generates four control signals according to a PWM input signal and controls the driving module, the auxiliary driving module and the power tube Vth compensation module by a combination of the four signals. The power tube Vth compensation module can offset the influence of the power tube PVT. The auxiliary driving module can quickly increase or decrease the gate voltage of the power tube to Vth, so that the power tube enters the saturation zone faster. At this time, the output conversion rate parameter is only related to the capacitance and the current size, so that the output increase and decrease conversion rate can be accurately controlled.

Description

Technical Field

[0001] The present invention relates to a driving circuit and a driving method thereof, in particular to a driving circuit and a driving method thereof for accurately controlling a conversion rate, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] The drive circuit is a circuit that drives the power stage transistor according to the control signal PWM. The traditional drive circuit is Fig. 9 As shown, the PWM signal is directly input to the drive module after passing through the inverter to control the opening and closing of the power tube. The conversion rate parameters of the output node are determined by the switching MOS tubes M21 and M22, resistors R4 and R5, and the parasitic capacitance of the power tube to GND. These parameters are affected by the process, voltage, and temperature (PVT) and have a large floating range.

[0003] When the power tube switches too quickly, there will be noise caused by electromagnetic interference (EMI). When the power tube switches too slowly, its rise / fall time is unnecessarily extended, making the entire system respond slowly. Traditional drive circuits cannot take into account both minimizing EMI and meeting certain rise / fall time requirements. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a driving circuit and a driving method thereof for accurately controlling the conversion rate, thereby improving the conversion rate and reducing EMI.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A driving circuit for accurately controlling a conversion rate comprises a logic control module, a driving module, a power tube Vth compensation module, an auxiliary driving module, a current source I1, a current source I2, a PMOS tube M3, an NMOS tube M2, a resistor R1, a capacitor C1 and a power tube M1, wherein an input end of the logic control module is connected to a PWM input signal, a first output end of the logic control module is connected to a second input end of the power tube Vth compensation module and a second input end of the driving module and generates a control signal sw, a second output end of the logic control module is connected to a third input end of the power tube Vth compensation module, a third input end of the driving module, a gate of the PMOS tube M3 and a gate of the NMOS tube M2 and generates a control signal swb, a third output end of the logic control module is connected to a third input end of the auxiliary driving module and generates a control signal swb_delay, and a fourth output end of the logic control module is connected to a power tube Vth compensation module. The first input end of the Vth compensation module is connected to the second input end of the auxiliary driving module and generates a control signal pulse, the source of the PMOS tube M3 is connected to one end of the current source I1, the other end of the current source I1 is connected to the power supply VCC, the source of the NMOS tube M2 is connected to one end of the current source I2, the other end of the current source I2 is grounded, the output end of the power tube Vth compensation module is connected to the first input end of the driving module, the first input end of the auxiliary driving module, the drain of the PMOS tube M3, the drain of the NMOS tube M2 and one end of the resistor R1 and generates a control signal Pre_gate, the output end of the driving module is connected to the output end of the auxiliary driving module and the gate of the power tube M1 and generates a control signal gate, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the resistor C1 is connected to the drain of the power tube M1 and generates an output signal OUT, and the source of the power tube M1 is grounded.

[0007] Further, the driving module includes a PMOS tube M13, a PMOS tube M11, a NNMOS tube M12, an NMOS tube M10 and a resistor R3, the source of the PMOS tube M13 is connected to the power supply VCC, the gate of the PMOS tube M13 serves as the second input end of the driving module and is connected to the control signal sw, the drain of the PMOS tube M13 is connected to the drain of the NMOS tube M12, the gate of the NMOS tube M12 is connected to the gate of the PMOS tube M11 and serves as the first input end of the driving module to connect the control signal Pre_gate, the source of the NMOS tube M12 is connected to the source of the PMOS tube M11 and one end of the resistor R3 and serves as the output end of the driving module to generate the control signal gate, the drain of the PMOS tube M11 is connected to the drain of the NMOS tube M10, the gate of the NMOS tube M10 serves as the third input end of the driving module and is connected to the control signal swb, and the source of the NMOS tube M10 and the other end of the resistor R3 are grounded.

[0008] Furthermore, the PMOS transistor M13 , the PMOS transistor M11 , the NNMOS transistor M12 , and the NMOS transistor M10 form a source follower structure.

[0009] Further, the power tube Vth compensation module includes a current source I3, an NMOS tube M5, an NMOS tube M4, an NMOS tube M8, an NMOS tube M9, an NMOS tube M6 and an NMOS tube M7, one end of the current source I3 is connected to the power supply VCC, the other end of the current source I3 is connected to the drain of the NMOS tube M5, the gate of the NMOS tube M5 and the drain of the NMOS tube M8, the source of the NMOS tube M5 is connected to the drain of the NMOS tube M4, the gate of the NMOS tube M4 and the drain of the NMOS tube M6, the source of the NMOS tube M4 is grounded, and the gate of the NMOS tube M8 serves as the power tube Vth compensation The second input end of the module is connected to the control signal sw, the source of the NMOS tube M8 is connected to the drain of the NMOS tube M9, the gate of the NMOS tube M9 is connected to the gate of the NMOS tube M7 and serves as the third input end of the power tube Vth compensation module to connect the control signal pulse, the source of the NMOS tube M9 is connected to the source of the NMOS tube M7 and serves as the output end of the power tube Vth compensation module to generate the control signal Pre_gate, the gate of the NMOS tube M6 serves as the third input end of the power tube Vth compensation module and is connected to the control signal swb, and the source of the NMOS tube M6 is connected to the drain of the NMOS tube M7.

[0010] Further, the auxiliary driving module includes an NMOS tube M14, an NMOS tube M15, an NMOS tube M16, an NMOS tube M17, an NMOS tube M20, a PMOS tube M18 and a PMOS tube M19, the gate of the NMOS tube M14 is connected to the drain of the NMOS tube M14, the source of the NMOS tube M16 and the gate of the PMOS tube M18 and are connected as the first input end of the auxiliary driving module to the control signal Pre_gate, the source of the NMOS tube M14 is connected to the drain of the NMOS tube M15, the gate of the NMOS tube M16 is connected to the drain of the NMOS tube M16 and the drain of the NMOS tube M17, and the NMOS tube M The gate of the NMOS tube M15 is connected to the gate of the NMOS tube M17 and is connected to the control signal pulse as the second input end of the auxiliary driving module. The source of the NMOS tube M15 is connected to the source of the NMOS tube M17, the source of the PMOS tube M18, and the source of the PMOS tube M19 and is connected to the output end of the auxiliary driving module to generate the control signal gate. The drain of the PMOS tube M18 is connected to the drain of the PMOS tube M19 and the drain of the NMOS tube M20. The gate of the PMOS tube M19 is connected to the gate of the NMOS tube M20 and is connected to the control signal swb_delay as the third input end of the auxiliary driving module. The gate of the NMOS tube M20 is grounded.

[0011] Further, the logic control module comprises an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an NOR gate NOR1, a resistor R2 and a capacitor C2, the input end of the inverter INV1 is connected to the PWM input signal, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the input end of the inverter INV3 and serves as the first output end of the logic control module to generate a control signal sw, the output end of the inverter INV3 is connected to the input end of the inverter INV4 and the NOR gate NOR1, the resistor R2 and the ... The first input terminal of NOR1 is connected and serves as the second output terminal of the logic control module to generate a control signal swb, the output terminal of the inverter INV4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the capacitor C2 and the input terminal of the inverter INV5, the other end of the capacitor C2 is grounded, the output terminal of the inverter INV5 is connected to the second input terminal of the NOR gate NOR1 and serves as the third output terminal of the logic control module to generate a control signal swb_delay, and the output terminal of the NOR gate NOR1 serves as the fourth output terminal of the logic control module to generate a control signal pulse.

[0012] A driving method for a driving circuit for accurately controlling a conversion rate comprises the following steps:

[0013] Working status 1:

[0014] When the PWM input signal changes from low to high, the control signal sw changes from low to high, the control signal swb changes from high to low, the control signal pulse generates a short pulse signal, the control signal Pre_gate is at a low level, the PMOS tube M3 is turned on, the current source I1 charges the first input terminal of the driving module, and at the same time, the NMOS tube M8 in the power tube Vth compensation module is turned on, and the NMOS tube M9 is turned on briefly, so that the voltage of the control signal Pre_gate rises quickly to Vth4+Vth5, where Vth4 is the threshold voltage of the NMOS tube M4, Vth5 is the threshold voltage of the NMOS tube M5, and the threshold voltage Vth4 of the NMOS tube M4 is the same as the threshold voltage Vth1 of the power tube M1, which offsets the PVT effect of the threshold voltage Vth1 of the power tube M1;

[0015] At this time, the control signal gate is at a low level, while the control signal Pre_gate voltage is high. The NMOS tube M15 in the auxiliary driving module is turned on briefly, forming a path between the two signal nodes of the control signal gate and the control signal Pre_gate. The control signal gate is pulled up to Vth4 through the auxiliary driving module, so that it quickly enters the saturation region.

[0016] As the voltage of the control signal gate continues to rise, the current of the power tube M1 increases, the voltage of the output signal OUT decreases, and the current flowing through the capacitor C1 increases. When the current flowing through the capacitor C1 is equal to the current of the current source I1, the control signal Pre_gate stabilizes at a fixed level, and the output signal OUT decreases at a constant rate.

[0017] As the voltage of the output signal OUT continues to decrease, the power tube M1 is in the linear region, the control signal Pre_gate breaks away from the fixed level and rises rapidly, the current flowing through the capacitor C1 decreases, and the voltage of the output signal OUT drops to GND;

[0018] Working status 2:

[0019] When the PWM input signal changes from high to low, the control signal sw changes from high to low, the control signal swb changes from low to high, the control signal pulse generates a short pulse signal, and the control signal Pre_gate is at a high level; the NMOS tube M2 is turned on, and the current source I2 discharges to the first input terminal of the driving module. At the same time, the NMOS tube M6 in the power tube Vth compensation module is turned on, and the NMOS tube M7 is turned on briefly, so that the voltage of the control signal Pre_gate drops rapidly to Vth4, wherein the threshold voltage Vth4 of the NMOS tube M4 offsets the PVT influence of the threshold voltage Vth1 of the power tube M1;

[0020] At this time, the control signal gate is at a high level, while the control signal Pre_gate voltage is low. The NMOS tube M17 in the auxiliary driving module is turned on briefly, forming a path between the two signal nodes of the control signal gate and the control signal Pre_gate. The control signal gate is pulled down to Vth4 through the auxiliary driving module, so that it quickly enters the saturation region from the linear region.

[0021] As the voltage of the control signal gate continues to decrease, the current of the power tube M1 decreases, the output signal OUT increases, and the current flowing through the capacitor C1 increases. The direction of the current flowing through the capacitor C1 is opposite to the direction of the current flowing through the capacitor C1 in the working state 1. When the current flowing through the capacitor C1 is equal to the current of the current source I2, the control signal Pre_gate stabilizes at a fixed level, and the output signal OUT increases at a constant rate.

[0022] As the voltage of the output signal OUT continues to rise to the highest voltage, the current flowing through the capacitor C1 decreases, the control signal Pre_gate is pulled down to GND by the current source I2, and the power tube M1 is turned off.

[0023] Compared with the prior art, the present invention has the following advantages and effects:

[0024] 1. The driving module structure of the present invention adopts a source follower structure, which isolates the capacitor feedback node and the gate end of the power tube. The current source only flows through the feedback capacitor, shielding the influence of the parasitic capacitance of the power tube, making the control of the conversion rate more accurate;

[0025] 2. The auxiliary drive module of the present invention provides a feed-forward path for the power tube gate, so that the gate can be quickly pulled up or down to V th , compared with only the driver module, the response time of the power tube is shortened;

[0026] 3. The power tube Vth compensation module of the present invention provides a bias voltage consistent with the power tube Vth, and cooperates with the auxiliary drive module to enable the power tube gate to be accurately pulled up or down to Vth, thereby ensuring that the output node will not generate spikes when PWM is flipped. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a driving circuit for accurately controlling the conversion rate of the present invention.

[0028] Figure 2 is a circuit diagram of a driving module of the present invention.

[0029] Figure 3 It is a circuit diagram of the power tube Vth compensation module of the present invention.

[0030] Figure 4 is a circuit diagram of the auxiliary drive module of the present invention.

[0031] Figure 5 It is a circuit diagram of the logic control module of the present invention.

[0032] Figure 6 3 is a waveform diagram of each control signal of the present invention.

[0033] Figure 7 It is a schematic diagram of simulation waveforms of working state 1 of the driving method for accurately controlling the conversion rate of the present invention.

[0034] Figure 8 It is a schematic diagram of simulation waveforms of working state 2 of the driving method for accurately controlling the conversion rate of the present invention.

[0035] Fig. 9 is a schematic diagram of a driving circuit in the prior art. DETAILED DESCRIPTION

[0036] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0037] like Figure 1 As shown, a driving circuit for accurately controlling the conversion rate of the present invention comprises a logic control module, a driving module, a power tube Vth compensation module, an auxiliary driving module, a current source I1, a current source I2, a PMOS tube M3, an NMOS tube M2, a resistor R1, a capacitor C1 and a power tube M1, an input end of the logic control module is connected to a PWM input signal, a first output end of the logic control module is connected to a second input end of the power tube Vth compensation module and a second input end of the driving module and generates a control signal sw, a second output end of the logic control module is connected to a third input end of the power tube Vth compensation module, a third input end of the driving module, a gate of the PMOS tube M3 and a gate of the NMOS tube M2 and generates a control signal swb, a third output end of the logic control module is connected to a third input end of the auxiliary driving module and generates a control signal swb_delay, a fourth output end of the logic control module is connected to a power tube Vth compensation module, and a fourth output end of the logic control module is connected to a power tube M3. The first input end of the rate tube Vth compensation module is connected to the second input end of the auxiliary driving module and generates a control signal pulse, the source of the PMOS tube M3 is connected to one end of the current source I1, the other end of the current source I1 is connected to the power supply VCC, the source of the NMOS tube M2 is connected to one end of the current source I2, the other end of the current source I2 is grounded, the output end of the power tube Vth compensation module is connected to the first input end of the driving module, the first input end of the auxiliary driving module, the drain of the PMOS tube M3, the drain of the NMOS tube M2 and one end of the resistor R1 and generates a control signal Pre_gate, the output end of the driving module is connected to the output end of the auxiliary driving module and the gate of the power tube M1 and generates a control signal gate, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the resistor C1 is connected to the drain of the power tube M1 and generates an output signal OUT, and the source of the power tube M1 is grounded.

[0038] The driving module is used to drive the power tube M1. The logic control module generates four control signals sw, swb, pulse and swb_delay according to the PWM input signal. The combination of the four signals controls the driving module, the auxiliary driving module and the power tube Vth compensation module. The power tube Vth compensation module can offset the influence of the PVT of the power tube M1. The auxiliary driving module can quickly increase or decrease the gate voltage of the power tube M1 to Vth, so that the power tube M1 enters the saturation zone faster. At this time, the output conversion rate parameter is only related to the capacitor C1 and the current size, so that the output increase and decrease conversion rate can be accurately controlled.

[0039] When the output signal OUT changes from high to low, the current flowing through the capacitor C1 increases until it is equal to the current source I1, and the output signal OUT starts to decrease at a constant rate; when the output signal OUT changes from low to high, the current flowing through the capacitor C1 increases, but the direction is opposite to that when it decreases, until it is equal to the current source I2, and the output signal OUT starts to increase at a constant rate.

[0040] like Figure 2 As shown, the driving module includes a PMOS tube M13, a PMOS tube M11, a NNMOS tube M12, an NMOS tube M10 and a resistor R3, the source of the PMOS tube M13 is connected to the power supply VCC, the gate of the PMOS tube M13 serves as the second input end of the driving module and is connected to the control signal sw, the drain of the PMOS tube M13 is connected to the drain of the NMOS tube M12, the gate of the NMOS tube M12 is connected to the gate of the PMOS tube M11 and serves as the first input end of the driving module to connect the control signal Pre_gate, the source of the NMOS tube M12 is connected to the source of the PMOS tube M11 and one end of the resistor R3 and serves as the output end of the driving module to generate the control signal gate, the drain of the PMOS tube M11 is connected to the drain of the NMOS tube M10, the gate of the NMOS tube M10 serves as the third input end of the driving module and is connected to the control signal swb, and the source of the NMOS tube M10 and the other end of the resistor R3 are grounded.

[0041] Among them, the PMOS tube M13, the PMOS tube M11, the NNMOS tube M12 and the NMOS tube M10 form a source follower structure. The driving module converts the control signal Pre_gate into the control signal gate through source following to control the on and off of the power tube M1. When the level of the control signal gate is pulled down to Vth11 by the PMOS tube M11, the resistor R3 can continue to pull down the level of the control signal gate so that the node can be pulled down to GND. The advantage of this structure is that when the power tube M1 rises to Vth and enters the saturation region, the driving module can isolate the capacitor feedback node and the gate node of the power tube M1 by using the source follower structure. Only the current of the feedback capacitor flows through the current source I1 or the current source I2, and the parasitic capacitance current of the power tube M1 flows to the driving module, thereby shielding the influence of the parasitic capacitance of the power tube M1, and achieving the purpose of accurately controlling the conversion rate.

[0042] like Figure 3 As shown, the power tube Vth compensation module includes a current source I3, an NMOS tube M5, an NMOS tube M4, an NMOS tube M8, an NMOS tube M9, an NMOS tube M6 and an NMOS tube M7. One end of the current source I3 is connected to the power supply VCC, and the other end of the current source I3 is connected to the drain of the NMOS tube M5, the gate of the NMOS tube M5 and the drain of the NMOS tube M8. The source of the NMOS tube M5 is connected to the drain of the NMOS tube M4, the gate of the NMOS tube M4 and the drain of the NMOS tube M6. The source of the NMOS tube M4 is grounded, and the gate of the NMOS tube M8 serves as the power tube Vth compensation module. The second input terminal of the power tube Vth compensation module is connected to the control signal sw, the source of the NMOS tube M8 is connected to the drain of the NMOS tube M9, the gate of the NMOS tube M9 is connected to the gate of the NMOS tube M7 and serves as the first input terminal of the power tube Vth compensation module to connect the control signal pulse, the source of the NMOS tube M9 is connected to the source of the NMOS tube M7 and serves as the output terminal of the power tube Vth compensation module to generate the control signal Pre_gate, the gate of the NMOS tube M6 serves as the third input terminal of the power tube Vth compensation module and is connected to the control signal swb, and the source of the NMOS tube M6 is connected to the drain of the NMOS tube M7.

[0043] When the output signal OUT changes from high to low, the power tube Vth compensation module is controlled by logic to temporarily provide a bias voltage of Vth4+Vth5 to the node of the control signal Pre_gate, so that the control signal gate of the power tube M1 can quickly get rid of the 0 level; when the output signal OUT changes from low to high, the power tube Vth compensation module is controlled by logic to temporarily provide a bias voltage of Vth4 to the node of the control signal Pre_gate, so that the control signal gate of the power tube M1 can quickly drop from the highest level to a lower level; and the Vth of the NMOS tube M4 is the same as that of the power tube M1, which can offset the PVT effect of the Vth of the power tube M1.

[0044] like Figure 4 As shown, the auxiliary driving module includes NMOS tube M14, NMOS tube M15, NMOS tube M16, NMOS tube M17, NMOS tube M20, PMOS tube M18 and PMOS tube M19. The gate of NMOS tube M14 is connected to the drain of NMOS tube M14, the source of NMOS tube M16 and the gate of PMOS tube M18 and is connected to the control signal Pre_gate as the first input end of the auxiliary driving module. The source of NMOS tube M14 is connected to the drain of NMOS tube M15, the gate of NMOS tube M16 is connected to the drain of NMOS tube M16 and the drain of NMOS tube M17, and the gate of NMOS tube M15 is connected to the drain of NMOS tube M16 and the drain of NMOS tube M17. The gate of the NMOS tube M15 is connected to the gate of the NMOS tube M17 and is connected to the control signal pulse as the second input terminal of the auxiliary driving module. The source of the NMOS tube M15 is connected to the source of the NMOS tube M17, the source of the PMOS tube M18, and the source of the PMOS tube M19 and is used as the output terminal of the auxiliary driving module to generate the control signal gate. The drain of the PMOS tube M18 is connected to the drain of the PMOS tube M19 and the drain of the NMOS tube M20. The gate of the PMOS tube M19 is connected to the gate of the NMOS tube M20 and is connected to the control signal swb_delay as the third input terminal of the auxiliary driving module. The gate of the NMOS tube M20 is grounded.

[0045] When the output signal OUT changes from high to low, only the NMOS tube M14 is turned on, and the NMOS tube M15 is turned on briefly under the control of the control signal pulse, forming a path between the control signal Pre_gate node and the control signal gate node of the power tube M1, so that the control signal gate rises rapidly; when the output signal OUT changes from low to high, the NMOS tube M16 is turned on, and the NMOS tube M17 is turned on briefly under the control of the control signal pulse, during this period of time when the NMOS tube M17 is turned on, the control signal gate drops rapidly; if the control signal gate is still at a level higher than Vth, it will be quickly pulled down by the PMOS tube M18, PMOS tube M19, and NMOS tube M20, so that the control signal gate drops to Vth.

[0046] like Figure 5 As shown, the logic control module includes an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an NOR gate NOR1, a resistor R2 and a capacitor C2, the input end of the inverter INV1 is connected to the PWM input signal, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the input end of the inverter INV3 and serves as the first output end of the logic control module to generate a control signal sw, the output end of the inverter INV3 is connected to the input end of the inverter INV4 and the NOR gate NO The first input terminal of R1 is connected and serves as the second output terminal of the logic control module to generate a control signal swb, the output terminal of the inverter INV4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the capacitor C2 and the input terminal of the inverter INV5, the other end of the capacitor C2 is grounded, the output terminal of the inverter INV5 is connected to the second input terminal of the NOR gate NOR1 and serves as the third output terminal of the logic control module to generate a control signal swb_delay, and the output terminal of the NOR gate NOR1 serves as the fourth output terminal of the logic control module to generate a control signal pulse.

[0047] like Figure 6 As shown, when the PWM input signal changes from low to high, the control signal sw changes from low to high, the control signal swb changes from high to low, and the control signal pulse generates a short pulse signal; when the PWM input signal changes from high to low, the control signal sw changes from high to low, the control signal swb changes from low to high, and the control signal pulse generates a short pulse signal.

[0048] A driving method for a driving circuit for accurately controlling a conversion rate comprises the following steps:

[0049] Working status 1:

[0050] When the PWM input signal changes from low to high, the control signal sw changes from low to high, the control signal swb changes from high to low, the control signal pulse generates a short pulse signal, the control signal Pre_gate is at a low level, the PMOS tube M3 is turned on, the current source I1 charges the first input terminal of the driving module, and at the same time, the NMOS tube M8 in the power tube Vth compensation module is turned on, and the NMOS tube M9 is turned on briefly, so that the voltage of the control signal Pre_gate rises quickly to Vth4+Vth5, wherein Vth4 is the threshold voltage of the NMOS tube M4, and Vth5 is the threshold voltage of the NMOS tube M5. The threshold voltage Vth4 of the NMOS tube M4 is the same as the threshold voltage Vth1 of the power tube M1, which offsets the PVT effect of the threshold voltage Vth1 of the power tube M1.

[0051] At this time, the control signal gate is at a low level, while the control signal Pre_gate voltage is high. The NMOS tube M15 in the auxiliary driving module is briefly turned on, forming a path between the two signal nodes of the control signal gate and the control signal Pre_gate. The control signal gate is pulled up to Vth4 through the auxiliary driving module, so that it quickly enters the saturation region.

[0052] As the voltage of the control signal gate continues to rise, the current of the power tube M1 increases, the voltage of the output signal OUT decreases, and the current flowing through the capacitor C1 increases. When the current flowing through the capacitor C1 is equal to the current of the current source I1, the control signal Pre_gate stabilizes at a fixed level, and the output signal OUT decreases at a constant rate.

[0053] As the voltage of the output signal OUT continues to decrease, the power tube M1 is in the linear region, the control signal Pre_gate breaks away from the fixed level and rises rapidly, the current flowing through the capacitor C1 decreases, and the voltage of the output signal OUT drops to GND.

[0054] like Figure 7 As shown, when the current flowing through capacitor C1 is equal to the current source I1, the output signal OUT decreases at a constant rate. From the current-voltage relationship of capacitor C1, we can get:

[0055]

[0056] That is, the conversion rate of the output signal OUT falling is: , where the capacitor C1 is 1.84pF, the current of the current source I1 is 1.6uA, and the conversion rate of the output signal OUT falling is 869kv / s, which is consistent with the simulation results.

[0057] Working status 2:

[0058] When the PWM input signal changes from high to low, the control signal sw changes from high to low, the control signal swb changes from low to high, the control signal pulse generates a short pulse signal, and the control signal Pre_gate is at a high level; the NMOS tube M2 is turned on, and the current source I2 discharges to the first input terminal of the driving module. At the same time, the NMOS tube M6 in the power tube Vth compensation module is turned on, and the NMOS tube M7 is turned on briefly, so that the voltage of the control signal Pre_gate drops rapidly to Vth4, wherein the threshold voltage Vth4 of the NMOS tube M4 offsets the PVT influence of the threshold voltage Vth1 of the power tube M1.

[0059] At this time, the control signal gate is at a high level, while the control signal Pre_gate voltage is low. The NMOS tube M17 in the auxiliary driving module is briefly turned on, forming a path between the two signal nodes of the control signal gate and the control signal Pre_gate. The control signal gate is pulled down to Vth4 through the auxiliary driving module, so that it quickly enters the saturation region from the linear region.

[0060] As the voltage of the control signal gate continues to drop, the current of the power tube M1 decreases, the output signal OUT rises, the current flowing through the capacitor C1 increases, and the direction of the current flowing through the capacitor C1 is opposite to the direction of the current flowing through the capacitor C1 in the working state 1. When the current flowing through the capacitor C1 is equal to the current of the current source I2, the control signal Pre_gate stabilizes at a fixed level, and the output signal OUT rises at a constant rate.

[0061] As the voltage of the output signal OUT continues to rise to the highest voltage, the current flowing through the capacitor C1 decreases, the control signal Pre_gate is pulled down to GND by the current source I2, and the power tube M1 is turned off.

[0062] like Figure 8 As shown, when the current flowing through capacitor C1 is equal to the current source I2, the output signal OUT rises at a constant rate. From the current-voltage relationship of capacitor C1, we can get:

[0063]

[0064] That is, the conversion rate of the output signal OUT falling is: , where the capacitor C1 is 1.84pF, and the current of the current source I2 is 1.6uA, the conversion rate of the output signal OUT rising is 869kv / s, which is consistent with the simulation results.

[0065] like Fig. 9 As shown in the schematic diagram of the traditional drive circuit, the PWM signal is directly input to the drive module after passing through the inverter to control the opening and closing of the power tube. The conversion rate of the output node is determined by the switch MOS tubes M21 and M22, the resistors R4 and R5, and the parasitic capacitance of the power tube to GND. These parameters are affected by the process, voltage, and temperature (PVT), and have a large floating range, resulting in a slew rate that is too fast or too slow. Under the premise of ensuring the conversion rate, the peak current and the noise caused by electromagnetic interference (EMI) cannot be reduced.

[0066] The driving module structure of the present invention adopts a source follower structure, which isolates the capacitor feedback node and the gate end of the power tube. The current source only flows through the feedback capacitor, shielding the influence of the parasitic capacitance of the power tube, making the control of the conversion rate more accurate; the auxiliary driving module of the present invention provides a feedforward path for the gate of the power tube, so that its gate can be quickly pulled up or down to V th Compared with only the driving module, the response time of the power tube is shortened; the power tube Vth compensation module of the present invention provides a bias voltage consistent with the Vth of the power tube, and cooperates with the auxiliary driving module to enable the power tube gate to be accurately pulled up or down to Vth, thereby ensuring that the output node will not generate spikes when PWM is flipped.

[0067] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A driving circuit for accurately controlling a conversion rate, characterized in that: The invention comprises a logic control module, a driving module, a power tube Vth compensation module, an auxiliary driving module, a current source I1, a current source I2, a PMOS tube M3, an NMOS tube M2, a resistor R1, a capacitor C1 and a power tube M1, wherein an input end of the logic control module is connected to a PWM input signal, a first output end of the logic control module is connected to a second input end of the power tube Vth compensation module and a second input end of the driving module and generates a control signal sw, a second output end of the logic control module is connected to a third input end of the power tube Vth compensation module, a third input end of the driving module, a gate of the PMOS tube M3 and a gate of the NMOS tube M2 and generates a control signal swb, a third output end of the logic control module is connected to a third input end of the auxiliary driving module and generates a control signal swb_delay, a fourth output end of the logic control module is connected to a first input end of the power tube Vth compensation module and a second input end of the driving module and generates a control signal swb_delay. An input end is connected to the second input end of the auxiliary driving module and generates a control signal pulse, a source of the PMOS tube M3 is connected to one end of the current source I1, the other end of the current source I1 is connected to the power supply VCC, a source of the NMOS tube M2 is connected to one end of the current source I2, the other end of the current source I2 is grounded, an output end of the power tube Vth compensation module is connected to the first input end of the driving module, the first input end of the auxiliary driving module, the drain of the PMOS tube M3, the drain of the NMOS tube M2 and one end of the resistor R1 and generates a control signal Pre_gate, an output end of the driving module is connected to the output end of the auxiliary driving module and the gate of the power tube M1 and generates a control signal gate, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the resistor C1 is connected to the drain of the power tube M1 and generates an output signal OUT, and the source of the power tube M1 is grounded; The auxiliary driving module comprises an NMOS tube M14, an NMOS tube M15, an NMOS tube M16, an NMOS tube M17, an NMOS tube M20, a PMOS tube M18 and a PMOS tube M19. The gate of the NMOS tube M14 is connected to the drain of the NMOS tube M14, the source of the NMOS tube M16 and the gate of the PMOS tube M18 and are connected to the control signal Pre_gate as the first input end of the auxiliary driving module. The source of the NMOS tube M14 is connected to the drain of the NMOS tube M15, the gate of the NMOS tube M16 is connected to the drain of the NMOS tube M16 and the drain of the NMOS tube M17, and the NMOS tube M15 is connected to the gate of the PMOS tube M18. The gate of the NMOS tube M15 is connected to the gate of the NMOS tube M17 and is connected to the control signal pulse as the second input terminal of the auxiliary driving module. The source of the NMOS tube M15 is connected to the source of the NMOS tube M17, the source of the PMOS tube M18, and the source of the PMOS tube M19 and is used as the output terminal of the auxiliary driving module to generate the control signal gate. The drain of the PMOS tube M18 is connected to the drain of the PMOS tube M19 and the drain of the NMOS tube M20. The gate of the PMOS tube M19 is connected to the gate of the NMOS tube M20 and is connected to the control signal swb_delay as the third input terminal of the auxiliary driving module. The gate of the NMOS tube M20 is grounded.

2. A driving circuit for accurately controlling conversion rate according to claim 1, characterized in that: The driving module includes a PMOS tube M13, a PMOS tube M11, a NNMOS tube M12, an NMOS tube M10 and a resistor R3, the source of the PMOS tube M13 is connected to the power supply VCC, the gate of the PMOS tube M13 serves as the second input end of the driving module and is connected to the control signal sw, the drain of the PMOS tube M13 is connected to the drain of the NMOS tube M12, the gate of the NMOS tube M12 is connected to the gate of the PMOS tube M11 and serves as the first input end of the driving module to connect the control signal Pre_gate, the source of the NMOS tube M12 is connected to the source of the PMOS tube M11 and one end of the resistor R3 and serves as the output end of the driving module to generate the control signal gate, the drain of the PMOS tube M11 is connected to the drain of the NMOS tube M10, the gate of the NMOS tube M10 serves as the third input end of the driving module and is connected to the control signal swb, and the source of the NMOS tube M10 and the other end of the resistor R3 are grounded.

3. A driving circuit for accurately controlling conversion rate according to claim 2, characterized in that: The PMOS transistor M13 , the PMOS transistor M11 , the NNMOS transistor M12 , and the NMOS transistor M10 form a source follower structure.

4. The driving circuit for accurately controlling the conversion rate according to claim 1, characterized in that: The power tube Vth compensation module comprises a current source I3, an NMOS tube M5, an NMOS tube M4, an NMOS tube M8, an NMOS tube M9, an NMOS tube M6 and an NMOS tube M7. One end of the current source I3 is connected to a power source VCC, and the other end of the current source I3 is connected to a drain of the NMOS tube M5, a gate of the NMOS tube M5 and a drain of the NMOS tube M8. The source of the NMOS tube M5 is connected to a drain of the NMOS tube M4, a gate of the NMOS tube M4 and a drain of the NMOS tube M6. The source of the NMOS tube M4 is grounded, and the gate of the NMOS tube M8 serves as the Vth compensation module of the power tube. The second input terminal is connected to the control signal sw, the source of the NMOS tube M8 is connected to the drain of the NMOS tube M9, the gate of the NMOS tube M9 is connected to the gate of the NMOS tube M7 and serves as the third input terminal of the power tube Vth compensation module to connect the control signal pulse, the source of the NMOS tube M9 is connected to the source of the NMOS tube M7 and serves as the output terminal of the power tube Vth compensation module to generate the control signal Pre_gate, the gate of the NMOS tube M6 serves as the third input terminal of the power tube Vth compensation module and is connected to the control signal swb, and the source of the NMOS tube M6 is connected to the drain of the NMOS tube M7.

5. The driving circuit for accurately controlling the conversion rate according to claim 1, characterized in that: The logic control module comprises an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an NOR gate NOR1, a resistor R2 and a capacitor C2, an input end of the inverter INV1 is connected to a PWM input signal, an output end of the inverter INV1 is connected to an input end of the inverter INV2, an output end of the inverter INV2 is connected to an input end of the inverter INV3 and serves as a first output end of the logic control module to generate a control signal sw, an output end of the inverter INV3 is connected to an input end of the inverter INV4 and an NOR gate NOR1, a resistor R2 and a capacitor C2, an input end of the inverter INV1 is connected to a PWM input signal, an output end of the inverter INV1 is connected to an input end of the inverter INV2, an output end of the inverter INV2 is connected to an input end of the inverter INV3 and serves as a first output end of the logic control module to generate a control signal sw, and an output end of the inverter INV3 is connected to an input end of the inverter INV4 and an NOR gate NOR1. The first input terminal of R1 is connected and serves as the second output terminal of the logic control module to generate a control signal swb, the output terminal of the inverter INV4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the capacitor C2 and the input terminal of the inverter INV5, the other end of the capacitor C2 is grounded, the output terminal of the inverter INV5 is connected to the second input terminal of the NOR gate NOR1 and serves as the third output terminal of the logic control module to generate a control signal swb_delay, and the output terminal of the NOR gate NOR1 serves as the fourth output terminal of the logic control module to generate a control signal pulse.

6. A driving method for a driving circuit for accurately controlling a conversion rate according to any one of claims 1 to 5, characterized in that The following steps are involved: Working status 1: When the PWM input signal changes from low to high, the control signal sw changes from low to high, the control signal swb changes from high to low, the control signal pulse generates a short pulse signal, the control signal Pre_gate is at a low level, the PMOS tube M3 is turned on, the current source I1 charges the first input terminal of the driving module, and at the same time, the NMOS tube M8 in the power tube Vth compensation module is turned on, and the NMOS tube M9 is turned on briefly, so that the voltage of the control signal Pre_gate rises quickly to Vth4+Vth5, where Vth4 is the threshold voltage of the NMOS tube M4, Vth5 is the threshold voltage of the NMOS tube M5, and the threshold voltage Vth4 of the NMOS tube M4 is the same as the threshold voltage Vth1 of the power tube M1, which offsets the PVT effect of the threshold voltage Vth1 of the power tube M1; At this time, the control signal gate is at a low level, while the control signal Pre_gate voltage is high. The NMOS tube M15 in the auxiliary driving module is turned on briefly, forming a path between the two signal nodes of the control signal gate and the control signal Pre_gate. The control signal gate is pulled up to Vth4 through the auxiliary driving module, so that it quickly enters the saturation region. As the voltage of the control signal gate continues to rise, the current of the power tube M1 increases, the voltage of the output signal OUT decreases, and the current flowing through the capacitor C1 increases. When the current flowing through the capacitor C1 is equal to the current of the current source I1, the control signal Pre_gate stabilizes at a fixed level, and the output signal OUT decreases at a constant rate. As the voltage of the output signal OUT continues to decrease, the power tube M1 is in the linear region, the control signal Pre_gate breaks away from the fixed level and rises rapidly, the current flowing through the capacitor C1 decreases, and the voltage of the output signal OUT drops to GND; Working status 2: When the PWM input signal changes from high to low, the control signal sw changes from high to low, the control signal swb changes from low to high, the control signal pulse generates a short pulse signal, and the control signal Pre_gate is at a high level; the NMOS tube M2 is turned on, and the current source I2 discharges to the first input terminal of the driving module. At the same time, the NMOS tube M6 in the power tube Vth compensation module is turned on, and the NMOS tube M7 is turned on briefly, so that the voltage of the control signal Pre_gate drops rapidly to Vth4, wherein the threshold voltage Vth4 of the NMOS tube M4 offsets the PVT influence of the threshold voltage Vth1 of the power tube M1; At this time, the control signal gate is at a high level, while the control signal Pre_gate voltage is low. The NMOS tube M17 in the auxiliary driving module is turned on briefly, forming a path between the two signal nodes of the control signal gate and the control signal Pre_gate. The control signal gate is pulled down to Vth4 through the auxiliary driving module, so that it quickly enters the saturation region from the linear region. As the voltage of the control signal gate continues to decrease, the current of the power tube M1 decreases, the output signal OUT increases, and the current flowing through the capacitor C1 increases. The direction of the current flowing through the capacitor C1 is opposite to the direction of the current flowing through the capacitor C1 in the working state 1. When the current flowing through the capacitor C1 is equal to the current of the current source I2, the control signal Pre_gate stabilizes at a fixed level, and the output signal OUT increases at a constant rate. As the voltage of the output signal OUT continues to rise to the highest voltage, the current flowing through the capacitor C1 decreases, the control signal Pre_gate is pulled down to GND by the current source I2, and the power tube M1 is turned off.

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