Power failure holding circuit and power input protection circuit

Abstract

The invention relates to a power failure holding circuit and a power input protection circuit, and belongs to the field of industrial control. The power failure holding circuit comprises a voltage input loop used for being connected to the positive electrode and the negative electrode of the input side of a power supply module; the voltage input loop comprises a first capacitor branch used for charging the first capacitor during power-on and providing a discharge loop for the first capacitor during power-off, and a switch branch used for being switched on when the voltage of the first capacitor reaches a starting threshold value and switched off during power-off. The second capacitor branch circuit is used for charging the second capacitor when the switch branch circuit is switched on and providing a temporary power supply for the power supply module when the power is off; the first capacitor branch is connected in parallel between the positive and negative electrodes of the voltage input loop; the on-off end of the switch branch is connected in series with the negative electrode line of the voltage input loop. The second capacitor branch is connected in parallel with the anode and cathode of the input side of the power supply module. According to the invention, the impact current can be reduced during power-on, and the stability of system operation is improved.

Description

Technical Field

[0001] The invention relates to a power-off holding circuit and a power input protection circuit, belonging to the field of industrial control. Background Art

[0002] The power input protection circuit is an indispensable part of modern electronic equipment. Its main purpose is to ensure that the power system can operate safely and prevent damage caused by external or internal abnormal conditions.

[0003] During the operation of electronic equipment, the external input power supply often fails. When the external power supply fails, some important data needs to be saved to the hard disk. Therefore, there are certain requirements for the power-off retention time of the internal power module of the electronic equipment. In order to improve the power-off retention time of the internal power module of the electronic equipment, a power-off retention circuit is usually set. You can refer to Figure 1 .

[0004] Figure 1 It is a structural diagram of an existing power-off holding circuit, such as Figure 1 As shown, a diode D11 is connected in series on the positive input end of the power module to prevent reverse connection, a capacitor C11 is connected in parallel between the positive input end of the power module behind the diode D11 and the negative input end of the power module to provide power to the power module when power is off, and a capacitor C12 is connected in parallel between the positive output end of the power module and the negative output end of the power module. When power is on, the capacitor C11 stores power; when power is off, the capacitor C11 releases power to the power module, allowing the power module to continue to work for a period of time, so that the digital circuit at the back of the power module can save important data; when reversely connected, the power module does not work because the diode D11 is reversely cut off.

[0005] However, the existing power-off holding circuit has the following problems: when the electronic equipment is started, since the capacitor C11 is close to a short circuit when powered on and has a large capacitance, the surge current in the voltage input circuit will be very large and last for a long time, which will often cause the external circuit breaker to trip incorrectly, resulting in unstable system operation. Summary of the invention

[0006] The purpose of the present invention is to provide a power-off holding circuit and a power input protection circuit to solve the problem in the prior art that when power is on, the impact current is large, which often causes the external circuit breaker to trip incorrectly, resulting in unstable system operation.

[0007] To achieve the above object, the solution of the present invention includes: A power-off holding circuit of the present invention comprises: a voltage input circuit for connecting to both ends of the positive and negative electrodes of the input side of a power module; The voltage input circuit includes: a first capacitor branch for charging the first capacitor when powered on and providing a discharge circuit for the first capacitor when powered off, a switch branch for turning on when the voltage of the first capacitor reaches a start threshold and turning off when powered off, and a second capacitor branch for charging the second capacitor when the switch branch is turned on and providing a temporary power supply for the power module when powered off; The first capacitor branch is connected in parallel between the positive and negative electrodes of the voltage input loop; the on-off end of the switch branch is connected in series to the negative electrode line of the voltage input loop; the second capacitor branch is connected in parallel to both ends of the positive and negative electrodes on the input side of the power module.

[0008] Furthermore, the voltage input circuit also includes: a third capacitor connected in parallel at both ends of the positive and negative electrodes of the power module for charging when the switch branch is turned on, and after being fully charged, for stabilizing the voltage of the power module when the external power supply is unstable.

[0009] Further, the first capacitor branch includes: a first current limiting resistor, a first diode and a first capacitor connected in series in sequence, the other end of the first current limiting resistor is connected to the positive electrode of the voltage input loop, and the other end of the first capacitor is connected to the negative electrode of the voltage input loop; It also includes a PNP transistor whose collector and emitter are connected in parallel at both ends of the first capacitor, the base of the PNP transistor is connected between the first current limiting resistor and the first diode, and the emitter of the PNP transistor is connected between the first diode and the first capacitor.

[0010] Further, the switch branch includes: a first MOS tube; The gate of the first MOS tube is connected to the anode of the first diode, the source of the first MOS tube is connected to one end of the first capacitor for connecting to the negative electrode of the voltage input loop, and the drain of the first MOS tube is connected to the negative electrode of the input side of the power module.

[0011] Furthermore, the switch branch further includes: a second current limiting resistor connected in series between the first diode and the gate of the first MOS tube.

[0012] Furthermore, the second capacitor branch includes: a second capacitor and a third current limiting resistor connected in series with the second capacitor; the other end of the third current limiting resistor is connected to the positive electrode of the power module input side, and the other end of the second capacitor is connected to the negative electrode of the power module input side.

[0013] Furthermore, the second capacitor branch also includes: a second diode connected in parallel at both ends of the third current limiting resistor and with its conduction direction pointing to the positive electrode of the input side of the power module.

[0014] Furthermore, the voltage input loop also includes: a fourth current limiting resistor connected in parallel to the source and drain of the first MOS tube and used for charging the second capacitor branch when the switch branch is turned off during power-on.

[0015] Furthermore, the voltage input loop also includes: a bias resistor having one end connected to the connection point between the first current limiting resistor and the base of the PNP transistor and the other end connected to the negative electrode of the voltage input loop, for providing a bias voltage for the first switch tube; Furthermore, the voltage input loop also includes: a voltage stabilizing diode connected in parallel across the bias resistor for stabilizing the bias voltage, and the conduction direction of the voltage stabilizing diode points to the positive pole of the voltage input loop.

[0016] Furthermore, the voltage input circuit also includes: a second MOS tube for cutting off the voltage input circuit when the external power supply is reversely connected; The source and drain of the second MOS tube are connected in series between one end of the bias resistor connected to the negative electrode of the voltage input loop and the negative electrode of the voltage input loop; the gate of the second MOS tube is connected to one end of the bias resistor used for connecting to the first current limiting resistor; the source of the second MOS tube is connected to one end of the bias resistor used for connecting to the negative electrode of the voltage input loop.

[0017] Furthermore, the voltage input loop further includes: a fifth current limiting resistor connected in series between the gate of the second MOS tube and the bias resistor.

[0018] Furthermore, the voltage input circuit further comprises: a fourth diode for cutting off the voltage input circuit when the external power supply is reversely connected; The cathode of the fourth diode is connected to the negative electrode of the voltage input loop, and the anode of the fourth diode is connected to the connection point between the bias resistor and the negative electrode of the voltage input loop.

[0019] A power input protection circuit of the present invention comprises: a power module and the above-mentioned power-off holding circuit.

[0020] The beneficial effects of the present invention are as follows: as a pioneering invention, the present invention allows the first capacitor branch to be connected in parallel at the positive and negative ends of the voltage input circuit of the power module, and uses the charging characteristics of the first capacitor to control the conduction and cutoff of the switch branch, thereby delaying the conduction time of the switch branch and reducing the impact current; allowing the second capacitor branch to start charging after the switch branch is turned on, which can delay the time for the second capacitor to start charging and reduce the impact current; when the power is off, the second capacitor can provide temporary power to the power module, so that the system can maintain normal operation for a period of time after the power is off, so that the digital circuit behind the power module can save data without causing data loss. Since the impact current in the voltage input circuit becomes smaller and lasts for a short time, it will not cause the external circuit breaker to trip incorrectly, and the stability of the system operation can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of an existing power-off holding circuit; Figure 2 It is a structural schematic diagram of a power-off holding circuit provided by an embodiment of the present invention; Figure 3 It is a structural schematic diagram of another power-off holding circuit provided by an embodiment of the present invention; Figure 4 It is a schematic structural diagram of another power-off holding circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0023] The present invention is conceived to add a first capacitor branch, a switch branch, and a second capacitor branch, so that when power is on, the charging characteristics of the first capacitor are used to extend the time to reach the size of the start threshold voltage of the switch branch conduction, thereby reducing the impact current. The second capacitor is charged only when the switch branch is turned on, delaying the conduction time of the second capacitor, thereby reducing the impact current. When the power is off, the second capacitor provides a temporary power supply for the power module, so that the system can maintain normal operation for a period of time after the power is off, so that the digital circuit behind the power module can save data without causing data loss.

[0024] An embodiment of a power-off holding circuit: Embodiment 1: Figure 2 is a schematic diagram of a power-off holding circuit provided by an embodiment of the present invention, such as Figure 2 As shown, the power-off holding circuit includes: a voltage input circuit for connecting to the positive and negative terminals of the input side of the power module 10, the voltage input circuit includes: a first capacitor branch 20 for charging the first capacitor C1 when powered on and providing a discharge circuit for the first capacitor C1 when powered off, a switch branch 30 for turning on when the voltage of the first capacitor C1 reaches a start threshold and turning off when powered off, and a second capacitor branch 40 for charging the second capacitor C2 when the switch branch 30 is turned on and providing a temporary power supply for the power module 10 when powered off.

[0025] Specifically, the first capacitor branch 20 is connected in parallel between the positive and negative poles of the voltage input loop; the on-off end of the switch branch 30 is connected in series to the negative pole line of the voltage input loop; the second capacitor branch 40 is connected in parallel at both ends of the positive and negative poles on the input side of the power module 10.

[0026] Among them, the first capacitor branch 20 includes: a first current limiting resistor R1, a first diode D1 and a first capacitor C1 connected in series in sequence, the other end of the first current limiting resistor R1 is connected to the positive electrode IN+ of the voltage input loop, and the other end of the first capacitor C1 is connected to the negative electrode IN- of the voltage input loop; it also includes a PNP transistor Q3 whose collector and emitter are connected in parallel at both ends of the first capacitor C1, the base of the PNP transistor Q3 is connected between the first current limiting resistor R1 and the first diode D1, and the emitter of the PNP transistor Q3 is connected between the first diode D1 and the first capacitor C1.

[0027] The switch branch 30 includes: a first metal-oxide-semiconductor field-effect transistor (MOSFET) tube Q1 and a second current-limiting resistor R2; the gate of the first MOS tube Q1 is connected to the anode of the first diode D1, the source of the first MOS tube Q1 is connected to the first capacitor C1 for connecting to one end of the negative electrode IN- of the voltage input loop, the drain of the first MOS tube Q1 is connected to the negative electrode of the input side of the power module 10, and the second current-limiting resistor R2 is connected in series between the first diode D1 and the gate of the first MOS tube.

[0028] Among them, the second capacitor branch 40 includes: a second capacitor C2, a third current limiting resistor R3 connected in series with the second capacitor, and a second diode D2 connected in parallel at both ends of the third current limiting resistor R3; the other end of the third current limiting resistor R3 is connected to the positive electrode on the input side of the power module 10, the other end of the second capacitor C2 is connected to the negative electrode on the input side of the power module 10, and the conduction direction of the second diode D2 points to the positive electrode on the input side of the power module 10.

[0029] The first MOS transistor Q1 is a MOS transistor including a body diode, and the type of the first MOS transistor Q1 can be a P-type MOS transistor or an N-type MOS transistor, which is not particularly limited in the present invention, and the following explanation is given by taking the first MOS transistor Q1 as an N-type MOS transistor as an example. The second diode D2 is a Schottky diode.

[0030] When the voltage input loop includes the first current limiting resistor R1, the first diode D1, the first capacitor C1, the PNP transistor Q3, the first MOS transistor, the third current limiting resistor R3, the second diode D2 and the second capacitor C2, the working principle of the power-off holding circuit is: When the external input power supply is powered on, the external power supply voltage is in the process of voltage climbing, and the external power supply voltage charges the first capacitor C1 through the first current limiting resistor R1 and the first diode D1, and the PNP transistor Q3 is in the cut-off state. At this time, the first capacitor branch 20 limits the climbing speed of the start threshold Vgs1 of the first MOS tube Q1, and the voltage Vgs across the first MOS tube Q1 is less than the start threshold Vgs1, and the first MOS tube Q1 is in the cut-off state.

[0031] When the external power supply voltage rises to a certain level, the voltage across the first capacitor C1 rises to a voltage Vgs across the first MOS tube that is greater than the start threshold Vgs1, and the first MOS tube Q1 is turned on. After the first MOS tube Q1 is turned on, the external power supply voltage can charge the second capacitor C2 through the third current limiting resistor R3 and the first MOS tube Q1.

[0032] After power-on is completed, the power module 10 operates normally. Due to the current limiting effect of the third current limiting resistor R3, the voltage across the second capacitor C2 has not yet reached the external power supply voltage and will continue to charge.

[0033] When the external power supply is powered off, the external power supply voltage drops rapidly. Due to the reverse cutoff effect of the first diode D1, the charge on the first capacitor C1 cannot be released immediately. Due to the rapid drop of the external power supply voltage, the voltage of the base of the PNP transistor Q3 will also drop rapidly. At this time, the voltage at the base of the PNP transistor Q3 is less than the voltage at the emitter of the PNP transistor Q3, and the PNP transistor Q3 is turned on. After the PNP transistor Q3 is turned on, the charge on the first capacitor C1 is quickly released. At this time, the Vgs of the first MOS tube Q1 also drops rapidly, and the first MOS tube Q1 is quickly turned off. The rapid cutoff of the first MOS tube Q1 can reduce the occurrence of the situation where the power module 10 is repeatedly started at the starting critical point when the external power supply is powered off. The charge on the second capacitor C2 is provided to the power module through the second diode D2, which is used for the power module 10 to continue working for a certain period of time, so as to facilitate the digital circuit of the later stage to save important data.

[0034] For those skilled in the art, after knowing the conduction principle when the first MOS tube is an N-type MOS tube, when the first MOS tube is replaced with a P-type MOS tube, the conduction principle of the power-off holding circuit can be easily thought of, and will not be repeated here.

[0035] In order to reduce the damage to the first MOS transistor caused by excessive current, as an optional implementation, a second current limiting resistor R2 is connected in series between the anode of the first diode D1 and the gate of the first MOS transistor Q1.

[0036] In order to enable the first MOS tube to be stably turned on or off, as an optional implementation, the voltage input loop further includes: a bias resistor Rp, and the bias resistor Rp is used to provide a bias voltage for the first MOS tube.

[0037] One end of the bias resistor Rp is connected to the connection point of the first current limiting resistor R1 and the base of the PNP transistor Q3 , and the other end of the bias resistor Rp is connected to the negative electrode IN- of the voltage input loop.

[0038] In order to make the bias voltage more stable, as an optional implementation, the voltage input loop further includes a voltage zener diode D3 connected in parallel across the bias resistor Rp, and the conduction direction of the voltage zener diode D3 points to the positive pole of the voltage input loop.

[0039] In order to enable the voltage across the second capacitor C2 to reach the external power supply voltage as quickly as possible, as an optional implementation, the voltage input loop further includes a fourth current limiting resistor R4 connected in parallel across the source and drain of the first MOS tube.

[0040] In order to prevent the unstable supply voltage of the power supply module 10 caused by the external power supply voltage fluctuation from having an adverse effect on the subsequent circuit, as an optional implementation, the voltage input circuit also includes a third capacitor C3 connected in parallel to the positive and negative terminals of the input side of the power supply module. The third capacitor C3 is used to supply power to the power supply module in time when the external power supply voltage fluctuates.

[0041] The capacitance of the second capacitor C2 is greater than the capacitance of the third capacitor C3.

[0042] When the voltage input loop further includes a second current limiting resistor R2, a bias resistor Rp, a voltage stabilizing diode D3, and a third capacitor C3, the working principle of the power-off holding circuit is as follows: When the external input power supply is powered on, the external power supply voltage is in the process of voltage climbing. The external power supply voltage charges the first capacitor C1 through the first current limiting resistor R1 and the first diode D1, and the PNP transistor Q3 is in the cut-off state. At this time, the first capacitor branch 20 limits the climbing speed of the start threshold Vgs1 of the first MOS tube Q1, the voltage Vgs across the first MOS tube is less than the start threshold Vgs1, and the first MOS tube Q1 is in the cut-off state.

[0043] The external power supply voltage charges the second capacitor C2 through the third current limiting resistor R3 and the fourth current limiting resistor R4, and also charges the third capacitor C3 through the fourth current limiting resistor R4. The third current limiting resistor R3 and the fourth current limiting resistor R4 limit the charging current of the second capacitor C2 when powered on, and the fourth current limiting resistor R4 limits the charging current of the third capacitor C3.

[0044] The voltage division on the bias resistor Rp determines whether the first MOS tube is turned on or not. When the external power supply is powered on, the voltage division on the bias resistor Rp is greater than the start threshold value Vgs1 of the first MOS tube Q1, which means that the voltage across the first capacitor C1 is also greater than the start threshold value Vgs1 of the first MOS tube Q1, and the first MOS tube Q1 is fully turned on, and the fourth current limiting resistor R4 is short-circuited. At this time, the third capacitor C3 is fully charged, and the voltage across the third capacitor C3 is equal to the input voltage of the external power supply. The second capacitor C2 is charged slowly due to the current limiting effect of the third current limiting resistor R3. The voltage across the second capacitor C2 has not yet reached the external power supply voltage, and the second capacitor C2 continues to charge.

[0045] When the external power supply is powered off, the external power supply voltage drops rapidly. Due to the reverse cutoff effect of the first diode D1, the charge on the first capacitor C1 cannot be released immediately. Due to the rapid drop of the external power supply voltage, the voltage of the base of the PNP transistor Q3 will also drop rapidly. At this time, the voltage at the base of the PNP transistor Q3 is less than the voltage at the emitter of the PNP transistor Q3, and the PNP transistor Q3 is turned on. After the PNP transistor Q3 is turned on, the charge on the first capacitor C1 is quickly released. At this time, the start threshold Vgs of the first MOS tube Q1 also drops rapidly, and the first MOS tube Q1 is quickly turned off. The rapid cutoff of the first MOS tube Q1 can reduce the occurrence of the situation where the power module 10 is repeatedly started at the start critical point when the external power supply is powered off. The charge on the second capacitor C2 is provided to the power module through the second diode D2, which is used for the power module 10 to continue working for a certain period of time, so as to facilitate the digital circuit of the later stage to save important data. The third capacitor C3 is used to supply power to the power module 10 in time when the external power supply voltage fluctuates to prevent the output voltage from fluctuating.

[0046] For those skilled in the art, after knowing the conduction principle when the first MOS tube is an N-type MOS tube, when the first MOS tube is replaced with a P-type MOS tube, the conduction principle of the power-off holding circuit can be easily thought of, and will not be repeated here.

[0047] A power-off holding circuit provided by an embodiment of the present invention allows a first capacitor branch to be connected in parallel to the positive and negative terminals of the voltage input circuit of the power module, and uses the charging characteristics of the first capacitor to control the on and off of the switch branch, thereby delaying the on time of the switch branch and reducing the impact current; allowing the second capacitor branch to start charging after the switch branch is turned on, thereby delaying the time for the second capacitor to start charging and reducing the impact current; when the power is off, the second capacitor can provide temporary power to the power module, so that the system can maintain normal operation for a period of time after the power is off, so that the digital circuit behind the power module can save data without causing data loss. Since the impact current in the voltage input circuit becomes smaller and the duration is short, it will not cause the external circuit breaker to trip incorrectly, and the stability of the system operation can be improved.

[0048] Embodiment 2: The difference between Example 2 and Example 1 is that an anti-reverse connection branch including a second MOS tube is added to the voltage input circuit, and other components and connection relationships remain unchanged.

[0049] Combine the following Figure 3 , illustrating the connection relationship and conduction principle of the power-off holding circuit provided in Example 2.

[0050] Here, it is only explained how to connect the second MOS transistor Q2 in the voltage input circuit when the anti-reverse connection branch including the second MOS transistor Q2 is added to the voltage input circuit. For other components and their connection relationships, reference can be made to the relevant descriptions in Example 1, which will not be repeated here.

[0051] Figure 3 is a schematic diagram of the structure of another power-off holding circuit provided by an embodiment of the present invention, such as Figure 3 As shown, the connection relationship of the second MOS tube Q2 in the voltage input loop is specifically as follows: the gate of the second MOS tube Q2 is connected to one end of the bias resistor Rp used for connecting to the first current limiting resistor R1; the drain of the second MOS tube Q2 is connected to the negative electrode IN- of the voltage input loop, and the source of the second MOS tube Q2 is connected to one end of the bias resistor Rp used for connecting to the negative electrode IN- of the voltage input loop.

[0052] The second MOS tube Q2 is a MOS tube including a body diode. The type of the second MOS tube may be a P-type MOS tube or an N-type MOS tube, and the present invention does not specifically limit this. The selection of the second MOS tube Q2 should be consistent with that of the first MOS tube Q1, that is, when the first MOS tube Q1 is an N-type MOS tube, the second MOS tube Q2 is also an N-type MOS tube, and when the first MOS tube Q1 is a P-type MOS tube, the second MOS tube Q2 is also a P-type MOS tube. The following takes the second MOS tube Q2 being an N-type MOS tube as an example for exemplary description.

[0053] In order to reduce the damage to the second MOS transistor Q2 caused by the excessive current, as an optional implementation, a fifth current limiting resistor R5 is connected in series between the gate of the second MOS transistor Q2 and the first current limiting resistor R1.

[0054] The following explains Figure 3 The working principle of the power-off holding circuit provided: When the external input power source is powered on, the external power source voltage is in the process of voltage climbing, and the external power source voltage charges the first capacitor C1 through the first current limiting resistor R1, the first diode D1 and the body diode of the second MOS tube Q2, and the PNP transistor Q3 is in the cut-off state. At this time, the first capacitor branch 20 limits the climbing speed of the Vgs of the first MOS tube Q1, and also limits the climbing speed of the Vgs of the second MOS tube Q2. The Vgs voltage of the first MOS tube Q1 is less than the start threshold Vgs1, and the first MOS tube Q1 is in the cut-off state. The Vgs voltage of the second MOS tube Q2 is less than the start threshold Vgs1, and the second MOS tube Q2 is in the cut-off state.

[0055] The external power supply voltage charges the second capacitor C2 through the third current limiting resistor R3, the fourth current limiting resistor R4 and the body diode of the second MOS transistor Q2, and also charges the third capacitor C3 through the fourth current limiting resistor R4 and the body diode of the second MOS transistor Q2. The third current limiting resistor R3 and the fourth current limiting resistor R4 jointly limit the charging current of the second capacitor C2 when power is on, and the fourth current limiting resistor R4 limits the charging current of the third capacitor C3.

[0056] The magnitude of the voltage division of the bias resistor Rp determines whether the first MOS tube Q1 and the second MOS tube Q2 are turned on or not. When the external power supply is powered on, the voltage division on the bias resistor Rp is greater than the start threshold value Vgs2 of the second MOS tube Q2, and the second MOS tube Q2 is fully turned on. When the voltage division on the bias resistor Rp is greater than the start threshold value Vgs1 of the first MOS tube Q1, it means that the voltage across the first capacitor C1 is also greater than the start threshold value Vgs1 of the first MOS tube Q1, and the first MOS tube Q1 is fully turned on. When the first MOS tube Q1 is turned on, the fourth current limiting resistor R4 is short-circuited. At this time, the third capacitor C3 is fully charged, and the voltage across the third capacitor C3 is equal to the input voltage of the external power supply. Due to the current limiting effect of the third current limiting resistor R3, the second capacitor C2 is charged slowly. The voltage across the second capacitor C2 has not yet reached the external power supply voltage, and the second capacitor C2 continues to charge.

[0057] When the external power supply is powered off, the external power supply voltage drops rapidly. Due to the reverse cutoff effect of the first diode D1, the charge on the first capacitor C1 cannot be released immediately. The rapid drop of the external power supply voltage will cause the voltage of the base of the PNP transistor Q3 to drop rapidly. At this time, the voltage at the base of the PNP transistor Q3 is less than the voltage at the emitter of the PNP transistor Q3, and the PNP transistor Q3 is turned on. After the PNP transistor Q3 is turned on, the charge on the first capacitor C1 is quickly released. At this time, the Vgs voltage of the first MOS tube Q1 and the second MOS tube Q2 also drops rapidly, and the first MOS tube Q1 and the second MOS tube Q2 are quickly turned off. The rapid cutoff of the first MOS tube Q1 and the second MOS tube Q2 can reduce the occurrence of the situation where the power module 10 is repeatedly started at the starting critical point when the external power supply is powered off. The charge on the second capacitor C2 is provided to the power module through the second diode D2, which is used for the power module 10 to continue working for a certain period of time, so as to facilitate the digital circuit of the later stage to save important data. The third capacitor C3 is used to supply power to the power module 10 in time when the external power supply voltage fluctuates, so as to prevent the output voltage from fluctuating.

[0058] When the external power supply is reversely connected, the body diode of the first MOS transistor Q1 is reversely cut off, no voltage is distributed between the gate and source of the first MOS transistor Q1 and the second MOS transistor Q2, the first MOS transistor Q1 and the second MOS transistor Q2 are both cut off, and the power module 10 does not start.

[0059] For those skilled in the art, after knowing the conduction principle when the first MOS tube is an N-type MOS tube and the second MOS tube is an N-type MOS tube, when the first MOS tube is replaced with a P-type MOS tube and the second MOS tube is replaced with a P-type MOS tube, the conduction principle of the power-off holding circuit can be easily thought of, and will not be repeated here.

[0060] A power-off holding circuit provided by an embodiment of the present invention, by allowing a first capacitor branch to be connected in parallel to the positive and negative ends of the voltage input circuit of the power module, and using the charging characteristics of the first capacitor to control the conduction and cutoff of the switch branch, the conduction time of the switch branch can be delayed to reduce the impact current; the second capacitor branch is allowed to start charging after the switch branch is turned on, and the time for the second capacitor to start charging can be delayed to reduce the impact current; when the power is off, the second capacitor can provide temporary power to the power module, so that the system can maintain normal operation for a period of time after the power is off, so that the digital circuit behind the power module can save data without causing data loss; when the external power supply is reversed, the voltage input circuit can be cut off, so that the power module does not work, protecting the power module and the rear-stage circuit of the rear power module. Since the impact current in the voltage input circuit becomes smaller and the duration is short, it will not cause the external circuit breaker to trip incorrectly, and the stability of the system operation can be improved. In the case of a heavy load on the power module, since the second MOS tube in the anti-reverse connection branch has a small power loss and a small heat generation, it is not easy to be damaged, and the service life of the power-off holding circuit can be improved.

[0061] Embodiment 3: The difference between Example 3 and Example 1 is that an anti-reverse connection branch including a fourth diode D4 is added to the voltage input loop, and other components and connection relationships remain unchanged.

[0062] Combine the following Figure 4 , illustrating the connection relationship and conduction principle of the power-off holding circuit provided in Example 3.

[0063] Here, it is only explained how the fourth diode D4 is connected in the voltage input circuit when an anti-reverse connection branch including the fourth diode D4 is added to the voltage input circuit. For other components and their connection relationships, please refer to the relevant description in Example 1, which will not be repeated here.

[0064] Figure 4 FIG. 1 is a schematic diagram of another power-off holding circuit provided by an embodiment of the present invention. Figure 4 As shown, the connection relationship of the fourth diode D4 in the voltage input loop is specifically: the cathode of the fourth diode D4 is connected to the negative electrode IN- of the voltage input loop, and the anode of the fourth diode D4 is connected to the connection between the bias resistor Rp and the negative electrode IN- of the voltage input loop.

[0065] When the fourth diode D4 is also included in the voltage loop, the working principle of the power-off holding circuit is: When the external input power source is powered on, the external power source voltage is in the process of voltage climbing, and the external power source voltage charges the first capacitor C1 through the first current limiting resistor R1, the first diode D1 and the fourth diode D4, and the P-type transistor Q3 is in the cut-off state. At this time, the first capacitor branch 20 limits the climbing speed of the Vgs of the first MOS tube Q1, the Vgs voltage of the first MOS tube is less than the start threshold Vgs1, and the first MOS tube Q1 is in the cut-off state.

[0066] The external power supply voltage charges the second capacitor C2 through the third current limiting resistor R3, the fourth current limiting resistor R4 and the fourth diode D4, and also charges the third capacitor C3 through the fourth current limiting resistor R4 and the fourth diode D4. The third current limiting resistor R3 and the fourth current limiting resistor R4 jointly limit the charging current of the second capacitor C2 when power is turned on, and the fourth current limiting resistor R4 limits the charging current of the third capacitor C3.

[0067] The voltage division on the bias resistor Rp determines whether the first MOS tube is turned on or not. When the external power supply is powered on, the voltage division on the bias resistor Rp is greater than the start threshold value Vgs1 of the first MOS tube Q1, which means that the voltage across the first capacitor C1 is also greater than the start threshold value Vgs1 of the first MOS tube Q1, and the first MOS tube Q1 is fully turned on, and the fourth current limiting resistor R4 is short-circuited. At this time, the third capacitor C3 is fully charged, and the voltage across the third capacitor C3 is equal to the input voltage of the external power supply. The second capacitor C2 is charged slowly due to the current limiting effect of the third current limiting resistor R3. The voltage across the second capacitor C2 has not yet reached the external power supply voltage, and the second capacitor C2 continues to charge.

[0068] When the external power supply is powered off, the external power supply voltage drops rapidly. Due to the reverse cutoff effect of the first diode D1, the charge on the first capacitor C1 cannot be released immediately. Due to the rapid drop of the external power supply voltage, the voltage of the base of the PNP transistor Q3 will also drop rapidly. At this time, the voltage at the base of the PNP transistor Q3 is less than the voltage at the emitter of the PNP transistor Q3, and the PNP transistor Q3 is turned on. After the PNP transistor Q3 is turned on, the charge on the first capacitor C1 is quickly released. At this time, the Vgs of the first MOS tube Q1 also drops rapidly, and the first MOS tube Q1 is quickly turned off. The rapid cutoff of the first MOS tube Q1 can reduce the occurrence of the situation that the power module 10 is repeatedly started at the starting critical point when the external power supply is powered off. The charge on the second capacitor C2 is provided to the power module through the second diode D2, which is used for the power module 10 to continue working for a certain period of time, so as to facilitate the digital circuit of the later stage to save important data. The third capacitor C3 is used to supply power to the power module 10 in time when the external power supply voltage fluctuates to prevent the output voltage from fluctuating.

[0069] When the external power supply is reversely connected, the fourth diode D4 is reversely cut off, no voltage is distributed between the gate and the source of the first MOS transistor Q1, the first MOS transistor Q1 is cut off, and the power module 10 does not start.

[0070] For those skilled in the art, after knowing the conduction principle when the first MOS tube is an N-type MOS tube, when the first MOS tube is replaced with a P-type MOS tube, the conduction principle of the power-off holding circuit can be easily thought of, and will not be repeated here.

[0071] A power-off holding circuit provided by an embodiment of the present invention allows a first capacitor branch to be connected in parallel to the positive and negative ends of the voltage input circuit of the power module, and uses the charging characteristics of the first capacitor to control the conduction and cutoff of the switch branch, so that the conduction time of the switch branch can be delayed to reduce the impact current; the second capacitor branch is allowed to start charging after the switch branch is turned on, which can delay the time when the second capacitor starts charging, and can reduce the impact current; when the power is off, the second capacitor can provide temporary power to the power module, so that the system can maintain normal operation for a period of time after the power is off, so that the digital circuit behind the power module can save data without causing data loss; when the external power supply is reversed, the voltage input circuit can be cut off, so that the power module does not work, protecting the power module and the subsequent circuit of the power module. Since the impact current in the voltage input circuit becomes smaller and the duration is short, it will not cause the false tripping of the external circuit breaker, and the stability of the system operation can be improved. When the power module is heavily loaded, the fourth diode in the anti-reverse connection branch has low power loss and low heat generation, so it is not easy to be damaged, which can increase the service life of the power-off holding circuit. At the same time, since the fourth diode is relatively cheap and easy to obtain, the production cost of the power-off holding circuit can also be reduced.

[0072] An embodiment of a power input protection circuit: A power input protection circuit provided in an embodiment of the present invention includes a power module 10 and a power-off holding circuit in any of the above embodiments.

[0073] Regarding the connection relationship and working principle between the power module 10 and the power-off holding circuit in the power input protection circuit, reference may be made to the relevant description of the power-off holding circuit in any of the above embodiments, which will not be repeated here.

[0074] A power input protection circuit provided in an embodiment of the present invention can achieve the same beneficial effects as the power-off holding circuit in any of the aforementioned embodiments, which will not be described in detail here.

Claims

1. A power-off holding circuit, characterized in that: include: Used for connecting the voltage input circuit at the positive and negative ends of the input side of the power module; The voltage input circuit includes: a first capacitor branch for charging the first capacitor when powered on and providing a discharge circuit for the first capacitor when powered off, a switch branch for turning on when the voltage of the first capacitor reaches a start threshold and turning off when powered off, and a second capacitor branch for charging the second capacitor when the switch branch is turned on and providing a temporary power supply for the power module when powered off; The first capacitor branch is connected in parallel between the positive and negative poles of the voltage input loop; the on-off end of the switch branch is connected in series to the negative pole line of the voltage input loop; the second capacitor branch is connected in parallel at both ends of the positive and negative poles on the input side of the power module.

2. The power-off holding circuit according to claim 1, characterized in that: The voltage input circuit also includes: a third capacitor connected in parallel at the positive and negative terminals of the power module for charging when the switch branch is turned on, and after being fully charged, for stabilizing the voltage of the power module when the external power supply is unstable.

3. The power-off holding circuit according to claim 1, characterized in that: The first capacitor branch comprises: a first current limiting resistor, a first diode and the first capacitor which are connected in series in sequence, the other end of the first current limiting resistor is connected to the positive electrode of the voltage input loop, and the other end of the first capacitor is connected to the negative electrode of the voltage input loop; It also includes a PNP transistor whose collector and emitter are connected in parallel at both ends of the first capacitor, the base of the PNP transistor is connected between the first current limiting resistor and the first diode, and the emitter of the PNP transistor is connected between the first diode and the first capacitor.

4. The power-off holding circuit according to claim 3, characterized in that: The switch branch includes: a first MOS tube; The gate of the first MOS transistor is connected to the anode of the first diode, the source of the first MOS transistor is connected to one end of the first capacitor used to connect to the negative electrode of the voltage input loop, and the drain of the first MOS transistor is connected to the negative electrode of the input side of the power module; It also includes: a second current limiting resistor connected in series between the first diode and the gate of the first MOS tube.

5. The power-off holding circuit according to claim 4, characterized in that: The second capacitor branch includes: the second capacitor and a third current limiting resistor connected in series with the second capacitor; the other end of the third current limiting resistor is connected to the positive electrode of the input side of the power module, and the other end of the second capacitor is connected to the negative electrode of the input side of the power module; It also includes: a second diode connected in parallel at both ends of the third current limiting resistor and with its conduction direction pointing to the positive electrode of the input side of the power module.

6. The power-off holding circuit according to claim 5, characterized in that: The voltage input loop also includes: a fourth current limiting resistor connected in parallel to the source and drain of the first MOS tube and used to charge the second capacitor branch when the switch branch is turned off during power-on.

7. The power-off holding circuit according to any one of claims 4 to 6, characterized in that: The voltage input loop also includes: a bias resistor having one end connected to the connection point between the first current limiting resistor and the base of the PNP transistor and the other end connected to the negative electrode of the voltage input loop, for providing a bias voltage for the first switch tube; The voltage input loop also includes: a voltage stabilizing diode connected in parallel at both ends of the bias resistor for stabilizing the bias voltage, and the conducting direction of the voltage stabilizing diode points to the positive pole of the voltage input loop.

8. The power-off holding circuit according to claim 7, characterized in that: The voltage input loop further includes: a second MOS tube for cutting off the voltage input loop when the external power supply is reversely connected; The source and drain of the second MOS transistor are connected in series between one end of the bias resistor connected to the negative electrode of the voltage input loop and the negative electrode of the voltage input loop; the gate of the second MOS transistor is connected to one end of the bias resistor used for connecting to the first current limiting resistor; the source of the second MOS transistor is connected to one end of the bias resistor used for connecting to the negative electrode of the voltage input loop; The voltage input loop further includes: a fifth current limiting resistor connected in series between the gate of the second MOS tube and the bias resistor.

9. The power-off holding circuit according to claim 7, characterized in that: The voltage input loop further includes: a fourth diode for cutting off the voltage input loop when the external power supply is reversely connected; The cathode of the fourth diode is connected to the negative electrode of the voltage input loop, and the anode of the fourth diode is connected to the connection point between the bias resistor and the negative electrode of the voltage input loop.

10. A power input protection circuit, characterized in that: include: A power supply module and a power-off holding circuit as described in any one of claims 1 to 9.

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