Voltage conversion circuit, multiphase switching converter and control method thereof

Abstract

The embodiment of the invention relates to a voltage conversion circuit, a multi-phase switching converter and a control method of the multi-phase switching converter. A plurality of voltage conversion circuits can be cascaded to form a multi-phase converter, one is a host, and the others are slaves. The voltage conversion circuit comprises a mode pin, a current sharing pin and a phase cutting control circuit. The mode pin is used for setting a host or a slave; the current-sharing pins are coupled together so as to generate current-sharing voltage signals at the current-sharing pins; the phase cutting control circuit generates an enable signal according to the mode selection signal, the current sharing voltage signal and the current sampling signal. When the output current is greater than a preset value, the voltage conversion circuit works; and when the output current is smaller than the preset value and serves as a slave, the enable signal controls the voltage conversion circuit serving as the slave to stop working. According to the scheme, the phase cutting control of the multiphase switching converter can be realized, the phase number of the multiphase switching converter can be flexibly set according to load application, the power consumption is low, and the efficiency is high.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and more particularly to a voltage conversion circuit, a multi-phase switching converter and a control method thereof. Background Art

[0002] With the development of electronic technology, more and more high-performance modules (such as central processing units in servers, communication equipment, etc.) require higher current and lower voltage power supply. This puts higher requirements on the design of switching converters.

[0003] Multiphase switching converters are widely used in power solutions for high-performance central processing units due to their superior performance. Multiphase switching converters can adopt an architecture mode in which each switching converter is controlled individually, or an architecture mode in which a master-slave cascade control is adopted. For the architecture mode in which a master-slave cascade control is adopted, the total number of phases of the multiphase switch can be easily adjusted according to the needs of the specific application, and there is no need to adjust the control circuit logic and structure of each phase circuit. It has good scalability and is therefore widely used in multiphase switching converters. How to implement the master-slave cascade control of multiphase switching converters more efficiently and concisely is also a focus of industry research. Summary of the invention

[0004] The purpose of the present invention is to solve the above problems in the prior art and to provide a voltage conversion circuit, a multi-phase switching converter and a control method thereof.

[0005] According to one aspect of the present invention, a voltage conversion circuit is provided, wherein a plurality of voltage conversion circuits can be cascaded to form a multi-phase switching converter, wherein one voltage conversion circuit serves as a host and the other voltage conversion circuits serve as slaves. The voltage conversion circuit comprises: a mode pin, providing a mode selection signal for setting the voltage conversion circuit as a host or a slave; a current sharing pin, wherein the current sharing pins of all hosts and slaves are coupled together, and a current sharing voltage signal representing the average output current of the plurality of voltage conversion circuits is generated at the current sharing pin; a phase cutting control circuit, receiving the mode selection signal, the current sharing voltage signal and the current sampling signal, and generating an enable signal according to the mode selection signal, the current sharing voltage signal and the current sampling signal, wherein the current sampling signal represents the output current of the voltage conversion circuit; when the output current of the voltage conversion circuit is greater than a preset value, the voltage conversion circuit works; when the output current of the voltage conversion circuit is less than a preset value and the voltage conversion circuit serves as a slave, the enable signal controls the voltage conversion circuit serving as a slave to stop working.

[0006] According to another aspect of the present invention, a multi-phase switching converter is provided, comprising: a first voltage conversion circuit; a second voltage conversion circuit, the second voltage conversion circuit is exactly the same as the first voltage conversion circuit, the first voltage conversion circuit and the second voltage conversion circuit comprise a synchronous input pin, a synchronous output pin, a mode pin and a current equalizing pin; wherein, the synchronous input pin of the second voltage conversion circuit is coupled to the synchronous output pin of the first voltage conversion circuit; the current equalizing pin of the second voltage conversion circuit is coupled to the current equalizing pin of the first voltage conversion circuit; the voltage on the current equalizing pin can represent the average output current of the first voltage conversion circuit and the second voltage conversion circuit; when the output current of the first voltage conversion circuit is greater than a preset value, the first voltage conversion circuit works, and controls the second voltage conversion circuit to work through the current equalizing pin; when the output current of the first voltage conversion circuit is less than a preset value, the first voltage conversion circuit works, and controls the second voltage conversion circuit to stop working through the current equalizing pin.

[0007] According to another aspect of the present invention, a control method for a multi-phase switching converter is provided, the multi-phase switching converter includes a plurality of identical voltage conversion circuits, each voltage conversion circuit includes a synchronous input pin, a synchronous output pin, a mode pin and a current sharing pin. The control method includes: setting one of the voltage conversion circuits as a host through a mode pin, and setting the other voltage conversion circuits as slaves; coupling the synchronous output pin of the host with the synchronous input pin of the slave, and sequentially connecting the synchronous output pin of the slave with the synchronous input pin of the next-level slave; sampling the output current of each voltage conversion circuit, and coupling all the current sharing pins together to generate a current sharing voltage signal on the current sharing pin, wherein the current sharing voltage signal can represent the average output current of multiple voltage conversion circuits; the host determines whether its output current is greater than a preset value; when the output current of the host is less than the preset value, the host works and controls all slaves to stop working through the current sharing pin; when the output current of the host is greater than the preset value, the host works and controls all slaves to work through the current sharing pin.

[0008] By using the embodiments of the present disclosure, phase-cutting control of a multi-phase switching converter can be implemented, and the number of phases of the multi-phase switching converter can be flexibly set according to load applications, with low power consumption and high efficiency, achieving the desired technical effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a circuit diagram of a multi-phase switching converter cascade system 100 according to an embodiment of the present invention;

[0010] Figure 2 FIG. 1 is a schematic diagram of the internal circuit structure of a voltage conversion circuit 1N according to an embodiment of the present invention;

[0011] Figure 3It is a waveform diagram of relevant parameters of a two-phase switching converter cascade system according to an embodiment of the present invention;

[0012] Figure 4 The figure shows a circuit schematic diagram of a phase cutting control circuit 21 according to an embodiment of the present invention;

[0013] Figure 5 The figure shows a circuit schematic diagram of a phase cutting control circuit 21 according to another embodiment of the present invention;

[0014] Figure 6 FIG. 1 is a flow chart of a control method for a multi-phase switching converter according to an embodiment of the present invention.

[0015] As shown in the accompanying drawings, the same reference numerals refer to the same parts in all the different views. The accompanying drawings provided herein are for the purpose of illustrating embodiments, principles, concepts, etc., and are not drawn to scale. DETAILED DESCRIPTION

[0016] Next, a non-restrictive description of the specific embodiments of the present invention will be made in conjunction with the accompanying drawings. References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment. The verbs "include" and "have" are used as open restrictions in this article, which neither exclude nor require the existence of undescribed features. Unless otherwise clearly stated, the features recorded in the dependent claims can be freely combined with each other. The elements defined by "one" or "one" (i.e., singular form) throughout the document do not exclude the possibility of multiple elements. Further, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connection" is used to specify the direct electrical connection between circuit elements, while the term "coupling" is used to specify the electrical connection between circuit elements that can be direct or can be via one or more other elements. On the contrary, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" as used herein includes any and all combinations of one or more related listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and a reference potential (usually ground). In addition, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of a logic signal may correspond to a voltage or current that may not be completely constant in a high or low state.

[0017] Figure 1 FIG. 1 is a circuit diagram of a multi-phase switching converter cascade system 100 according to an embodiment of the present invention. Figure 1 In the illustrated embodiment, the switching converter cascade system 100 includes N parallel voltage conversion circuits, which are respectively indicated as 11, 12, ..., 1N, for providing the same output voltage VOUT, and each voltage conversion circuit serves as a phase circuit of the multi-phase switching converter cascade system 100. Wherein, N is an integer greater than or equal to 2. In one embodiment, the N parallel voltage conversion circuits are indicated as integrated circuit chips with the same structure and function. Those skilled in the art can understand that the N parallel voltage conversion circuits may not be integrated circuits but circuits constructed by discrete devices.

[0018] In one embodiment, the N voltage conversion circuits 11, 12, ..., 1N are configured in a master-slave cascade operation mode, wherein one phase circuit is configured as a master and the remaining phase circuits are configured as slaves. Figure 1 In the embodiment shown, the voltage conversion circuit 11 is set as a master, and the remaining voltage conversion circuits 12, ..., 1N are set as slaves. Figure 1 In the illustrated embodiment, each voltage conversion circuit includes a plurality of pins. For the sake of simplicity and clarity, only the pins used for illustration are shown. Figure 1 The pins of the working principle of the embodiment are shown, and other pins are not shown. Figure 1 In the illustrated embodiment, these pins include an input pin IN, a switch pin SW, a feedback pin FB, a mode pin MODE, a synchronous input pin SYNIN, a synchronous output pin SYNO, and a current sharing pin ICS.

[0019] like Figure 1 As shown, the input pin IN receives the input voltage VIN of the switching converter cascade system 100 , the switch pin SW is coupled to the output end of the switching converter cascade system 100 through a corresponding inductor, and the feedback pin FB is used to receive a feedback signal VFB.

[0020] The mode pin MODE is used to determine the master and slave in the N voltage conversion circuits. In one embodiment, the mode pin MODE is connected to the reference ground through a resistor, and then a mode selection signal is generated on the pin to determine the working mode of each phase circuit. The mode selection signal usually has two signal modes of logic high and low levels. For example, a logic high level represents that the phase circuit is the master, and a logic low level represents that the phase circuit is the slave.

[0021] The synchronous input pin SYNIN is used to receive the synchronous signal provided by the previous stage, and the synchronous output pin SYNO is used to provide the synchronous signal to the next stage. Figure 1 As shown, the synchronous output pin SYNO of the voltage conversion circuit 11 is connected to the synchronous input pin SYNIN of the voltage conversion circuit 12; the synchronous output pin SYNO of the voltage conversion circuit 12 will be connected to the synchronous input pin SYNIN of the next voltage conversion circuit. Similarly, the synchronous input pin SYNIN of the voltage conversion circuit 1N is connected to the synchronous output pin SYNO of the voltage conversion circuit 1(N-1).

[0022] The current sharing pins of all hosts and slaves are coupled together, and a current sharing voltage signal that can characterize the average output current of multiple phase circuits is generated at the current sharing pin ICS; the current sharing pins ICS of all phase circuits are coupled together. Each phase circuit performs phase cutting control according to the voltage on its current sharing pin ICS, the mode selection signal on the mode pin MODE, and the current sampling signal inside the phase circuit. In the embodiment shown in the present invention, phase cutting control refers to controlling the phase circuit as a slave to work or not work, thereby controlling the number of phase circuits working in the entire switching converter cascade system 100, and switching between phase circuits with different working numbers. In one embodiment, when the output current of the host is greater than a preset value, the host works and controls all slaves to work through the current sharing pin ICS; when the output current of the host is less than the preset value, the host works and controls all slaves to stop working through the current sharing pin. It can be understood that in another embodiment, the slave stops working and the power switch in the slave stops switching on and off.

[0023] Each voltage conversion circuit includes a power unit, and the power unit may have different structures according to the different topologies selected by the voltage conversion circuit. In the following description, the power unit in the voltage conversion circuit 1N is described as a BUCK type topology structure. Therefore, the power unit of the voltage conversion circuit includes an upper switch tube and a lower switch tube. The common node of the upper switch tube and the lower switch tube is the switch pin SW.

[0024] exist Figure 1 In the illustrated embodiment, the switching converter cascade system 100 further includes N output inductors, an output capacitor Cout, and a feedback circuit. Specifically, the output inductor L1 is coupled between the pin SW of the voltage conversion circuit 11 and the output end of the switching converter cascade system 100; the output inductor L2 is coupled between the pin SW of the voltage conversion circuit 12 and the output end of the switching converter cascade system 100. Similarly, the output inductor LN is coupled between the pin SW of the voltage conversion circuit 1N and the output end of the switching converter cascade system 100. The output capacitor Cout is coupled between the output end of the switching converter cascade system 100 and the reference ground. The feedback circuit is coupled between the output end of the switching converter cascade system 100 and the reference ground to generate a feedback signal VFB. In one embodiment, the feedback signal VFB is sent to the feedback pin FB of the voltage conversion circuit, and the feedback circuit includes a voltage divider composed of resistors R1 and R2. The feedback signal VFB is a voltage feedback signal, representing the output voltage VOUT of the switching converter cascade system 100.

[0025] Those skilled in the art will understand that Figure 1In the illustrated embodiments, the inductor is shown as being outside the voltage conversion circuit. In other embodiments, the inductor may be integrated inside the voltage conversion circuit as a part of the power unit. That is, the power unit includes the inductor in addition to the upper switch tube and the lower switch tube. Figure 1 In the illustrated embodiment, N phase circuits are shown to work in a cascade control manner, but each phase circuit has an independent control circuit and power unit, so in some other embodiments, even if no other phase circuit exists, each phase circuit can also work independently as a single-phase circuit. Next, the working principle of the multi-phase switching converter cascade system 100 will be described in detail in conjunction with more specific embodiments.

[0026] Figure 2 FIG. 1 is a schematic diagram of the internal circuit structure of a voltage conversion circuit 1N according to an embodiment of the present invention. Figure 2 In the illustrated embodiment, the power unit in the voltage conversion circuit 1N includes an upper switch tube HS and a lower switch tube LS. The upper switch tube HS and the lower switch tube LS are connected in series between the input pin IN and the reference ground, and their common node is coupled to the switch pin SW. By controlling the on and off switching of the upper switch tube HS and the lower switch tube LS, the input voltage VIN received by the voltage conversion circuit is converted into the final output voltage VOUT.

[0027] exist Figure 2 In the illustrated embodiment, the upper switch tube HS and the lower switch tube LS are both illustrated as metal semiconductor field effect transistors (MOSFET), but those skilled in the art can understand that the upper switch tube HS and the lower switch tube LS can also be other suitable controllable semiconductor power switch devices. At the same time, the power unit may not be a BUCK topology, but other suitable types of isolated or non-isolated topologies, such as BOOST topology, BUCK-BOOST topology, Z-type topology, CUK topology, FLYBACK topology, etc.

[0028] exist Figure 2In the illustrated embodiment, each voltage conversion circuit 1N includes a phase-cut control circuit 21. The phase-cut control circuit 21 receives a mode selection signal Vmode, a current-sharing voltage signal Vavg, and a current sampling signal Isen. The phase-cut control circuit 21 generates an enable signal EN according to the mode selection signal Vmode, the current-sharing voltage signal Vavg, and the current sampling signal Isen. The enable signal EN is used to control the slave to work or stop working, wherein the current sampling signal Isen represents the output current of the voltage conversion circuit 1N. In one embodiment, the output current of the voltage conversion circuit 1N includes a peak value, a valley value, or an average value of the output current. That is, the current sampling signal Isen can represent the peak value, the valley value, or the average value of the current output by the voltage conversion circuit 1N.

[0029] In one embodiment, the enable signal EN has a first logic state (e.g., logic high) and a second logic state (e.g., logic low). The phase-cutting control circuit 21 of the host controls the enable signal EN of the slave to change from the second logic state (e.g., logic low) to the first logic state (e.g., logic high) by pulling the current-sharing voltage signal Vavg down to the reference ground, thereby controlling the upper switch tube HS and the lower switch tube LS to turn off and thereby controlling the slave to stop working.

[0030] Continue to see Figure 2 In one embodiment, the voltage conversion circuit 1N further includes a synchronization signal generating circuit 22 , a control unit 23 and a logic circuit 24 .

[0031] The synchronization signal generating circuit 22 receives the first synchronization signal SET(N-1) at the synchronization input pin SYNIN, and outputs the synchronization signal as the second synchronization signal SET(N) at the synchronization output pin SYNO after phase shifting.

[0032] In one embodiment, when the voltage conversion circuit 1N is the host, the synchronization signal generating circuit 22 can receive the first synchronization signal SET (N-1) provided externally from the synchronization input pin SYNIN, and generate the second synchronization signal SET (N) after phase shifting the first synchronization signal SET (N-1), and provide the second synchronization signal SET (N) to the next-level slave connected thereto through its synchronization output pin SYNO. The phase shift angle between the first synchronization signal SET (N-1) and the second synchronization signal SET (N) is related to the number of phase circuits of the switching converter cascade system, which is 360° / N. In another embodiment, the synchronization signal generating circuit 22 can generate the synchronization signal by itself. For example, the voltage conversion circuit 1N also includes a frequency setting pin, and the host 11 generates the first synchronization signal SET (N-1) through its frequency setting pin, and generates the second synchronization signal SET (N) after phase shifting the first synchronization signal SET (N-1), and provides it to the slave connected to its synchronization output pin SYNO. At this time, the synchronization input pin SYNIN of the host 11 can be grounded through a resistor.

[0033] When the voltage conversion circuit 1N is a slave, the synchronization signal generating circuit 22 only receives the synchronization signal provided by the synchronization output pin SYNO of the previous voltage conversion circuit from its synchronization input pin SYNIN, and after shifting the phase of the received synchronization signal again, provides it to the next slave connected to it through its synchronization output pin SYNO. In one embodiment, the synchronization output pin SYNO of the last slave can be floating. In another embodiment, the synchronization output pin SYNO of the last slave can be connected to the host to send a cycle end signal to the host.

[0034] In one embodiment, the first synchronization signal SET(N-1) and the second synchronization signal SET(N) are both logic signals with logic high and low levels, including multiple high and low pulses. In one embodiment, each logic high level of the synchronization signal is used as a pulse; in other embodiments, the synchronization signal may also use each logic low level as a pulse. In one embodiment, the synchronization signal may include a clock signal. Figure 3 According to an embodiment of the present invention, a schematic diagram of waveforms of relevant parameters of a two-phase switching converter cascade system is illustrated, in which the first synchronization signal Set1, the second synchronization signal Set2, the pulse width modulation signal PWM1 of the first phase circuit, and the pulse width modulation signal PWM2 of the second phase circuit are illustrated from top to bottom. As shown in the figure, the phase shift angle between the first synchronization signal Set1 and the second synchronization signal Set2 is 180°.

[0035] Continue to see Figure 2The control unit 23 receives the feedback signal VFB and the first synchronization signal SET(N-1), and generates a pulse width modulation signal PWM according to the feedback signal VFB and the first synchronization signal SET(N-1).

[0036] Continue to see Figure 2 The logic circuit 24 receives the enable signal EN and the pulse width modulation signal PWM, and generates a control signal CTL according to the enable signal EN and the pulse width modulation signal PWM. The control signal CTL is used to adjust the on time and off time of the upper switch tube HS and the lower switch tube LS, thereby converting the input voltage VIN received by the voltage conversion circuit into the output voltage VOUT.

[0037] In one embodiment, the voltage conversion circuit 1N also includes a current balancing circuit 25. The current balancing circuit 25 receives the current balancing voltage signal Vavg and the current sampling signal Isen, and generates a current balancing adjustment signal Ireg according to the current balancing voltage signal Vavg and the current sampling signal Isen. The current balancing adjustment signal Ireg can adjust the duty cycle of the pulse width modulation signal PWM, and then adjust the on time and off time of the upper switch tube HS and the lower switch tube LS, so that the output current of each voltage conversion circuit is equal to achieve the effect of current balancing. At this time, the control unit 23 further receives the current balancing adjustment signal Ireg, and generates a pulse width modulation signal PWM according to the feedback signal VFB, the first synchronization signal SET (N-1) and the current balancing adjustment signal Ireg.

[0038] In one embodiment, the voltage conversion circuit 1N further includes a driving circuit 26 , which receives a control signal CTL and generates a driving signal according to the control signal CTL for driving the upper switch tube HS and the lower switch tube LS to turn on and off.

[0039] Figure 4 According to an embodiment of the present invention, a circuit diagram of a phase-cut control circuit 21 is shown. Figure 4 The illustrated embodiment shows a voltage conversion circuit 11 as a master and a phase control circuit 21 in a voltage conversion circuit 12 as a slave.

[0040] like Figure 4 As shown, each phase-cut control circuit 21 includes a first voltage generating circuit 41 , a second voltage generating circuit 42 , a first comparing unit 43 , a second comparing unit 44 , a first logic unit 45 , a second logic unit 46 and a phase-cut switch 47 .

[0041] The first voltage generating circuit 41 has a first end and a second end. The first end of the first voltage generating circuit 41 receives the current sampling signal Isen1 / Isen2. The second end of the first voltage generating circuit 41 is coupled to the current balancing pin ICS. The first voltage generating circuit 41 generates a current balancing voltage signal Vavg at its second end according to the current sampling signal. The current sampling signal of the host 11 is indicated as Isen1, and the current sampling signal of the slave 12 is indicated as Isen2.

[0042] In one embodiment, the first voltage generating circuit 41 includes a first resistor R1 and an operational amplifier OP. The first resistor R1 has a first end and a second end, and the first end of the first resistor R1 is coupled to the current balancing pin ICS. The operational amplifier OP has a first input end, a second input end, and an output end, and the first input end of the operational amplifier OP receives the voltage reference value Vref3, and the second input end of the operational amplifier OP is coupled to the second end of the first resistor R1. The current sampling signal Isen1 / Isen2 is sent to the first end of the first resistor R1 and the current balancing pin ICS. Therefore, the current sampling signal Isen1 flows through the first resistor R1 of the host 11, and flows through the first resistor R1 of the slave 12 through the current balancing pin ICS; the current sampling signal Isen2 flows through the first resistor R1 of the slave 12, and flows through the first resistor R1 of the host 11 through the current balancing pin ICS. Therefore, the voltage on the current balancing pin ICS, that is, the current balancing voltage signal Vavg=Vref3+1 / 2×R1×(Isen1+Isen2), can represent the average output current of the host 11 and the slave 12.

[0043] The second voltage generating circuit 42 has a first end and a second end. The first end of the second voltage generating circuit 42 receives the current sampling signal Isen1 / Isen2 , and the second voltage generating circuit 42 generates an equivalent voltage signal Vsen1 / Vsen2 at its second end according to the current sampling signal Isen1 / Isen2 .

[0044] In one embodiment, the second voltage generating circuit 42 includes a second resistor R2. The second resistor R2 has a first end and a second end, the first end of the second resistor R2 receives the current sampling signal Isen1 / Isen2, and the second end of the second resistor R2 is connected to the reference ground. The current sampling signal Isen1 / Isen2 flows through the second resistor R2 and generates an equivalent voltage signal Vsen1 / Vsen2 at the first end of the second resistor R2, wherein Vsen1=R2×Isen1, Vsen1=R2×Isen2. It can be understood that after the voltage conversion circuit 11 and the voltage conversion circuit 12 are processed by current balancing, Isen1=Isen2. In another embodiment, the second voltage generating circuit 42 may further include a filtering circuit 421, which is used to filter the voltage on the second resistor R2 and calculate the average value before generating the equivalent voltage signal Vsen1 / Vsen2. In one embodiment, the value of the current balancing voltage signal Vavg and the equivalent voltage signal Vsen1 / Vsen2 is related to the resistance value of the first resistor R1, the resistance value of the second resistor R2, and the value of the voltage reference value Vref3. The value of the current-sharing voltage signal Vavg may also be set to be equal to the value of the equivalent voltage signal Vsen1 / Vsen2 .

[0045] The first comparison unit 43 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the first comparison unit 43 is coupled to the current balancing pin ICS. The second input terminal of the first comparison unit 43 receives the voltage reference value Vref1. The first comparison unit 43 compares the voltage on the current balancing pin ICS with the voltage reference value Vref1 and outputs a first comparison signal at the output terminal. In one embodiment, the value of the current balancing voltage signal Vavg is greater than the voltage reference value Vref1. In one embodiment, the voltage reference value Vref3 is greater than the voltage reference value Vref1.

[0046] The second comparison unit 44 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the second comparison unit 44 receives the equivalent voltage signal Vsen1 / Vsen2, and the second input terminal of the second comparison unit 44 receives the voltage reference value Vref2. The second comparison unit 44 compares the equivalent voltage signal Vsen1 / Vsen2 with the voltage reference value Vref2 and outputs a second comparison signal at the output terminal.

[0047] The first logic unit 45 receives the first comparison signal and the mode selection signal Vmode, and performs a logic operation on the first comparison signal and the mode selection signal Vmode to output an enable signal EN. It can be understood that in this embodiment, the mode selection signal Vmode of the host 11 and the mode selection signal Vmode of the slave 12 are logic complementary signals. Usually, the mode selection signal Vmode of the host 11 is a logic high level and the mode selection signal Vmode of the slave 12 is a logic low level.

[0048] The second logic unit 46 receives the second comparison signal and the mode selection signal Vmode, performs a logic operation on the second comparison signal and the mode selection signal Vmode, and outputs a slave control signal S_slv.

[0049] The phase switch 47 has a first end, a second end and a control end. The first end of the phase switch 47 is coupled to the current sharing pin, the second end of the phase switch 47 is electrically connected to the reference ground, and the control end of the phase switch 47 receives the slave control signal S_slv.

[0050] Next, we will combine Figure 4 In the specific embodiment shown, the working principle of the phase-cutting control circuit 21 is described as follows.

[0051] When the current sampling signal Isen1 / Isen2 of the phase circuit (which can characterize the load current of the multi-phase switch converter cascade system) is less than the preset value, it means that the load current demand is not high, and the equivalent voltage signal Vsen1 / Vsen2 output by the second voltage generating circuit 42 is less than the voltage reference value Vref2, so the second comparison signal output by the second comparison unit 44 becomes a logic high level. At this time, because the voltage conversion circuit 11 is the host, the value of the mode selection signal Vmode is also a logic high level, so that the slave control signal S_slv output by the second logic unit 46 of the host 11 is a logic high level, the phase switch 47 of the host 11 is turned on, and the current sharing pin ICS1 of the host 11 and the current sharing pin ICS2 of the slave 12 are both pulled down to the reference ground. The first comparison unit 43 outputs a logic high level. Since the mode selection signal Vmode of the host is a logic high level, the enable signal EN output by the first logic unit 45 in the host 11 is a logic low level, the power switch in the host 11 is switched normally, and the host works normally. At the same time, because the voltage conversion circuit 12 is a slave, the value of the mode selection signal Vmode is a logic low level, so the slave control signal S_slv output by the second logic unit 46 in the slave 12 is a logic low level, and the phase switch 47 in the slave 12 is still turned on, but because the current sharing pin ICS2 of the slave 12 is connected to the current sharing pin ICS1 of the host 11, it is also pulled down to the reference ground. The first comparison unit 43 in the slave 12 outputs a logic high level, but the mode selection signal Vmode of the slave 12 is a logic low level, so the enable signal EN output by the first logic unit 45 in the slave 12 is a logic high level, and the power switch in the slave 12 stops switching on and off, and the slave 12 does not work and only the host 11 works, so as to reduce the loss of the cascade system and improve efficiency.

[0052] When the current sampling signal Isen1 / Isen2 of the phase circuit (which can represent the load current of the multi-phase switching converter cascade system) is greater than the preset value, it means that the load current demand is high, and the equivalent voltage signal Vsen1 output by the second voltage generating circuit 42 is greater than the voltage reference value Vref2, so the second comparison signal output by the second comparison unit 44 becomes a logic low level. At this time, because the voltage conversion circuit 11 is the host, the value of the mode selection signal Vmode is a logic high level, the slave control signal S_slv output by the second logic unit 46 of the host 11 is a logic low level, and the phase switch 47 of the host 11 remains disconnected. The first comparison unit 43 compares the value of the current-sharing voltage signal Vavg with the voltage reference value Vref1. Since the voltage reference value Vref3 is set greater than the voltage reference value Vref1 in both the host 11 and the slave 12, the value of the current-sharing voltage signal Vavg must be greater than the voltage reference value Vref1, and the first comparison unit 43 will output a logic low level. At this time, regardless of whether the mode selection signal Vmode is a logic high level or a logic low level, the enable signal EN output by the first logic unit 45 is a logic low level, and the power switches in the host 11 and the slave 12 are turned on and off normally, and both the host and the slave 12 work to provide a larger output current.

[0053] In some applications, when only the master is working and the slaves are stopped, the master needs to provide a larger output current than when it is one phase in a multi-phase circuit. Figure 5 According to another embodiment of the present invention, a circuit schematic diagram of a phase cutting control circuit 21 is provided. Figure 4 The phase cutting control circuit in the embodiment, Figure 5 The voltage reference value Vref2 received by the second comparison unit 44 in the disclosed phase-cut control circuit 21 is adjustable. Figure 5 As shown, the second comparison unit 44 includes a transmission gate module 441 and a comparator 442 .

[0054] The transmission gate module 441 has a first input terminal, a second input terminal, a first control terminal, a second control terminal and an output terminal. The first input terminal of the transmission gate module 441 receives the fourth voltage reference value Vref4; the second input terminal of the transmission gate module 441 receives the fifth voltage reference value Vref5; the first control terminal of the transmission gate module 441 receives the slave control signal S_slv; the second control terminal of the transmission gate module 441 receives the inverted signal of the slave control signal S_slv; the transmission gate module 441 selects the fourth voltage reference value Vref4 or the fifth voltage reference value Vref5 as the second voltage reference value Vref2 and outputs it at its output terminal according to different logic states of the slave control signal S_slv. The values ​​of the fourth voltage reference value Vref4 and the fifth voltage reference value Vref5 are not equal. For example, in one embodiment, assuming that Vref4>Vref5, when the slave control signal S_slv is in the first logic state (e.g., logic high), the transmission gate module 441 selects the fourth voltage reference value Vref4 as the second voltage reference value Vref2 to be output at its output end; when the slave control signal S_slv is in the second logic state (e.g., logic low), the transmission gate module 441 selects the fifth voltage reference value Vref5 as the second voltage reference value Vref2 to be output at its output end.

[0055] The comparator 442 has a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal of the comparator 442 is coupled to the output terminal of the transmission gate module 441 to receive the second voltage reference value Vref2. The inverting input terminal of the comparator 442 receives the equivalent voltage signal. The comparator 442 compares the equivalent voltage signal with the second voltage reference value Vref2 and outputs a second comparison signal at the output terminal.

[0056] Continue to see Figure 5 In some embodiments, in order to prevent the current of the phase circuit from being too large, the second logic unit 46 further receives the current limiting indication signal Peak, and the second logic unit 46 performs a logic operation on the second comparison signal, the mode selection signal Vmode and the current limiting indication signal Peak and outputs the slave control signal S_slv, wherein the current limiting indication signal Peak is used to indicate whether the output current of the phase circuit has reached the current limit. For example, when the output current of the host reaches the current limit, the current limiting indication signal Peak becomes a logic high level state, the slave control signal S_slv becomes a logic low level state, and all slaves work to prevent the host output current from being too large. In one embodiment, the slave control signal S_slv of the host controls the slave to stop working by pulling down the voltage on the current sharing pin ICS to the reference ground.

[0057] Figure 6 FIG. 1 is a flow chart of a control method for a multi-phase switching converter according to an embodiment of the present invention. The method includes the following steps S1-S6.

[0058] Step S1, setting one of the voltage conversion circuits as a master and the other voltage conversion circuits as slaves through the mode pin MODE.

[0059] Step S2, coupling the synchronous output pin SYNO of the host to the synchronous input pin SYNIN of the slave, and sequentially coupling the synchronous output pin SYNO of the slave to the synchronous input pin SYNIN of the next-stage slave.

[0060] Step S3, sampling the output current of each voltage conversion circuit and coupling all the current balancing pins ICS together, and generating a current balancing voltage signal Vavg on the current balancing pin ICS, wherein the current balancing voltage signal Vavg can represent the average output current of the multiple voltage conversion circuits.

[0061] Step S4: The host determines whether its output current is greater than a preset value. If yes, go to step S5; otherwise, go to step S6.

[0062] Step S5, when the output current is greater than the preset value, the host operates and controls the slave to operate via the current sharing pin ICS.

[0063] Step S6, when the output current is less than the preset value, the host operates and controls all slaves to stop operating through the current sharing pin ICS. In one embodiment, the host controls the slaves to stop operating by pulling down the voltage on the current sharing pin ICS to the reference ground.

[0064] Although the present invention has been described above with reference to several typical embodiments, it should be understood by those skilled in the art that the terms used in the disclosed embodiments of the present invention are illustrative and exemplary, rather than restrictive, and are only used to describe specific embodiments, and are not intended to limit the present invention. In addition, various modifications in form and details made by those skilled in the art to the embodiments disclosed in the present invention without departing from the principles and concepts of the present invention and without creative efforts, all of which fall within the scope of protection defined by the claims of the present application or their equivalents.

Claims

1. A voltage conversion circuit, characterized in that: A plurality of the voltage conversion circuits can be cascaded to form a multi-phase switching converter, wherein one voltage conversion circuit serves as a master and the other voltage conversion circuits serve as slaves, and the voltage conversion circuits include: A mode pin, providing a mode selection signal, wherein the mode selection signal is used to set the voltage conversion circuit as a master or a slave; A current sharing pin, the current sharing pins of all hosts and slaves are coupled together, and a current sharing voltage signal that can represent the average output current of multiple voltage conversion circuits is generated at the current sharing pin; A phase-cutting control circuit receives a mode selection signal, a current-sharing voltage signal and a current sampling signal, and generates an enable signal according to the mode selection signal, the current-sharing voltage signal and the current sampling signal, wherein the current sampling signal represents an output current of the voltage conversion circuit; When the output current of the voltage conversion circuit is greater than a preset value, the voltage conversion circuit works; When the output current of the voltage conversion circuit is less than a preset value and the voltage conversion circuit acts as a slave, the enable signal controls the voltage conversion circuit acting as a slave to stop working.

2. The voltage conversion circuit according to claim 1, characterized in that: The enable signal has a first logic state and a second logic state. When the voltage conversion circuit acts as a host, the phase-cutting control circuit of the host controls the enable signal in the voltage conversion circuit acting as a slave to change from the second logic state to the first logic state by pulling down the current-sharing voltage signal to the reference ground, thereby controlling the voltage conversion circuit acting as a slave to stop working.

3. The voltage conversion circuit according to claim 1, characterized in that: Further including: Synchronous input pin; Synchronous output pins, wherein the synchronous output pin of each voltage conversion circuit is connected to the synchronous input pin of the next voltage conversion circuit in cascade connection; A synchronization signal generating circuit receives a first synchronization signal at a synchronization input pin, and outputs the first synchronization signal as a second synchronization signal at a synchronization output pin after phase shifting; Power switch; a control unit, receiving a feedback signal and a first synchronization signal, and generating a pulse width modulation signal according to the feedback signal and the first synchronization signal, wherein the feedback signal represents an output voltage of the voltage conversion circuit; and The logic circuit receives the enable signal and the pulse width modulation signal, and generates a control signal according to the enable signal and the pulse width modulation signal, wherein the control signal is used to adjust the on time and off time of the power switch, thereby converting the input voltage received by the voltage conversion circuit into an output voltage.

4. The voltage conversion circuit according to claim 3, characterized in that: Further including: A current sharing circuit receives a current sharing voltage signal and a current sampling signal, and generates a current sharing adjustment signal according to the current sharing voltage signal and the current sampling signal; The control unit further receives a current sharing regulation signal, and generates the pulse width modulation signal according to the feedback signal, the first synchronization signal and the current sharing regulation signal.

5. The voltage conversion circuit according to claim 1, characterized in that: Further including: The output current of the voltage conversion circuit includes a peak value, a valley value or an average value of the output current.

6. The voltage conversion circuit according to claim 1, characterized in that: The phase cutting control circuit comprises: A first voltage generating circuit has a first end and a second end, the first end of the first voltage generating circuit receives a current sampling signal, the second end of the first voltage generating circuit is coupled to a current balancing pin, and the first voltage generating circuit generates a current balancing voltage signal at its second end according to the current sampling signal; A second voltage generating circuit has a first end and a second end, the first end of the second voltage generating circuit receives a current sampling signal, and the second voltage generating circuit generates an equivalent voltage signal at its second end according to the current sampling signal; A first comparison unit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the first comparison unit is coupled to the current balancing pin, the second input terminal of the first comparison unit receives a first voltage reference value, the first comparison unit compares the voltage on the current balancing pin with the first voltage reference value, and outputs a first comparison signal at the output terminal; A second comparison unit has a first input terminal, a second input terminal and an output terminal, the first input terminal of the second comparison unit receives the equivalent voltage signal, the second input terminal of the second comparison unit receives the second voltage reference value, the second comparison unit compares the equivalent voltage signal with the second voltage reference value, and outputs a second comparison signal at the output terminal; A first logic unit receives a first comparison signal and a mode selection signal, performs a logic operation on the first comparison signal and the mode selection signal, and outputs an enable signal; A second logic unit receives a second comparison signal and a mode selection signal, performs a logic operation on the second comparison signal and the mode selection signal, and outputs a slave control signal; The phase-cutting switch has a first end, a second end and a control end. The first end of the phase-cutting switch is coupled to the current-sharing pin, the second end of the phase-cutting switch is electrically connected to the reference ground, and the control end of the phase-cutting switch receives a slave control signal.

7. The voltage conversion circuit according to claim 6, characterized in that: The first voltage generating circuit comprises: The first resistor has a first end and a second end, and the first end of the first resistor is coupled to the current balancing pin. An operational amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the operational amplifier receives a third voltage reference value, and the second input terminal of the operational amplifier is coupled to the second terminal of the first resistor, wherein the third voltage reference value is greater than the first voltage reference value; The current sampling signal is sent to the first end of the first resistor and the current sharing pin.

8. The voltage conversion circuit according to claim 6, characterized in that: The second comparison unit comprises: A transmission gate module having a first input terminal, a second input terminal, a first control terminal, a second control terminal and an output terminal, wherein the first input terminal of the transmission gate module receives a fourth voltage reference value; the second input terminal of the transmission gate module receives a fifth voltage reference value; the first control terminal of the transmission gate module receives a slave control signal; the second control terminal of the transmission gate module receives an inverted signal of the slave control signal; the transmission gate module selects the fourth voltage reference value or the fifth voltage reference value as a second voltage reference value and outputs it at its output terminal according to different logic states of the slave control signal; and The comparator has a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal of the comparator is coupled to the output terminal of the transmission gate module to receive a second voltage reference value. The inverting input terminal of the comparator receives an equivalent voltage signal. The comparator compares the equivalent voltage signal with the second voltage reference value and outputs a second comparison signal at the output terminal.

9. The voltage conversion circuit according to claim 6, characterized in that: The second logic unit further receives a current limiting indication signal, performs a logic operation on the second comparison signal, the mode selection signal and the current limiting indication signal, and outputs a slave control signal, wherein the current limiting indication signal is used to indicate whether the output current reaches the current limit.

10. A multi-phase switching converter, characterized in that: include: a first voltage conversion circuit; A second voltage conversion circuit, wherein the second voltage conversion circuit is identical to the first voltage conversion circuit, and the first voltage conversion circuit and the second voltage conversion circuit include a synchronous input pin, a synchronous output pin, a mode pin, and a current sharing pin; Wherein, the synchronous input pin of the second voltage conversion circuit is coupled to the synchronous output pin of the first voltage conversion circuit; The current equalizing pin of the second voltage conversion circuit is coupled to the current equalizing pin of the first voltage conversion circuit; the voltage on the current equalizing pin can represent the average output current of the first voltage conversion circuit and the second voltage conversion circuit; the mode pin is used to set the first voltage conversion circuit as the host and the second voltage conversion circuit as the slave; when the output current of the first voltage conversion circuit is greater than a preset value, the first voltage conversion circuit works, and controls the second voltage conversion circuit to work through the current equalizing pin; when the output current of the first voltage conversion circuit is less than a preset value, the first voltage conversion circuit works, and controls the second voltage conversion circuit to stop working through the current equalizing pin.

11. A control method for a multi-phase switching converter, characterized in that: The multi-phase switching converter includes a plurality of identical voltage conversion circuits, each of which includes a synchronous input pin, a synchronous output pin, a mode pin and a current sharing pin, and the control method includes: One of the voltage conversion circuits is set as the master through the mode pin, and the other voltage conversion circuits are set as slaves; The synchronous output pin of the host is coupled to the synchronous input pin of the slave, and the synchronous output pin of the slave is connected to the synchronous input pin of the next slave in turn; Sampling the output current of each voltage conversion circuit, and coupling all current sharing pins together to generate a current sharing voltage signal on the current sharing pin, wherein the current sharing voltage signal can represent the average output current of the multiple voltage conversion circuits; The host determines whether its output current is greater than a preset value; When the output current of the host is less than the preset value, the host works and controls all slaves to stop working through the current sharing pin; When the output current of the host is greater than the preset value, the host works and controls all slaves to work through the current sharing pin.

12. The control method according to claim 11, characterized in that: The steps of "when the output current of the host is less than the preset value, the host works and controls all slaves to stop working through the current sharing pin" include: The host controls all slaves to stop working by pulling the voltage on the current sharing pin down to the reference ground.

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