Electronic circuit

Abstract

An electronic circuit includes a reference clock signal generator block and a functional module. In response to a fault detected on a signal originating from a reference frequency generator of the reference clock signal generator block, only the reference frequency generator of the reference clock signal generator block is reset without resetting the functional module.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority of French Patent Application No. 2306702, filed on June 27, 2023, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits. Background Art

[0004] For the internal processes of electronic circuits, they generally include a reference oscillator in the form of a quartz oscillator whose crystal, when powered, delivers a signal having a frequency which is used as a reference to generate a time sequence such as a clock signal.

[0005] Reference oscillators may be sensitive to, for example, power supply variations or to environmental parameters external to the circuit, which may result in transient or permanent failures. The impact of these failures on general circuit operation raises questions.

[0006] It is desirable to have an electronic circuit that reduces the effects of malfunction of a reference oscillator.

[0007] There is a need to overcome all or some of the disadvantages of known electronic circuits. Summary of the invention

[0008] One embodiment provides an electronic circuit comprising a reference clock signal generator circuit and a functional circuit; the electronic circuit is configured to reset the reference clock signal generator circuit only when a fault is detected on a signal originating from a reference frequency generator of the reference clock signal generator circuit.

[0009] An embodiment provides a method of controlling an electronic circuit including a reference clock signal generator circuit and a functional circuit, the method comprising the steps of resetting the reference clock signal generator circuit only when a fault on a signal originating from a reference frequency generator of the reference clock signal generator circuit is detected.

[0010] In an embodiment, the electronic circuit further comprises a control circuit configured to generate a signal for resetting the reference frequency generator when a fault on the signal originating from the reference frequency generator is detected, the signal being different from a reset signal common to the functional circuit and to the reference clock signal generator circuit.

[0011] In an embodiment, the reference clock signal generator circuit comprises a detection circuit configured to detect whether the signal originating from the reference frequency generator fails and to generate a failure status signal at an output of the detection circuit according to a result of the detection.

[0012] In one embodiment, the reference clock signal generator circuit includes a flip-flop having a clock input coupled to the output of the detection circuit and a reset input coupled to a first logic circuit module, the first logic circuit module being configured to perform an AND type logic function between the inverse of a signal for resetting the reference frequency generator and a reset signal common to the functional circuit and the reference clock signal generator circuit.

[0013] In one embodiment, the reference clock generator circuit includes a control element having a reset input coupled to a second logic circuit, the second logic circuit being configured to perform an AND-type logic function between a signal present at the inverting output of the flip-flop and the reset signal common to the functional circuit and to the reference clock signal generator circuit.

[0014] In an embodiment, the control element comprises an oscillator output configured to transmit a signal for controlling the reference frequency generator.

[0015] In an embodiment, the signal for controlling the reference frequency generator is configured to stop the reference frequency generator when a reset input of the control element is enabled.

[0016] In one embodiment, the control element comprises: a clock output configured to transmit a reference clock signal having a reference frequency; and a clock input configured to receive the signal originating from a reference frequency generator; the control element is configured such that the clock output transmits the reference clock signal based on the signal originating from the reference frequency generator after a given number of cycles have been verified.

[0017] In one embodiment, the flip-flop is coupled to the output of the detection circuit via a third logic circuit module, the third logic circuit module being configured to perform an AND-type logic function between the fault status signal and a signal for enabling the detection circuit.

[0018] In one embodiment, a flip-flop includes a data input that is set to state one.

[0019] In one embodiment, the flip-flop is a D-type flip-flop.

[0020] In one embodiment, the inverting output of the flip-flop is configured to be reset when the reset input is enabled.

[0021] In one embodiment, the reset input of the flip-flop is enabled when it receives a signal at zero.

[0022] In one embodiment, the reset input of the control element is enabled when it receives a signal at zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0024] Figure 1 Examples of integrated circuits are shown very schematically in the form of circuit modules;

[0025] Figure 2 The circuit module is shown very schematically. Figure 1 A circuit module of an integrated circuit; and

[0026] Figure 3 The control is shown very schematically in the form of a flow chart Figure 2 Circuit method. DETAILED DESCRIPTION

[0027] In the various drawings, the same features have been indicated with the same reference numerals. Specifically, common structural and / or functional features in various embodiments may have the same reference numerals and may be arranged with the same structure, size and material properties.

[0028] For clarity, only the steps and elements that are helpful for understanding the described embodiments are illustrated and described in detail.

[0029] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or coupled via one or more other elements.

[0030] In the following description, when referring to terms defining absolute positions (such as terms "edge", "rear / back", "top", "bottom", "left", "right", etc.), or terms defining relative positions (such as terms "above", "below", "upper", "lower", etc.), or terms defining directions (such as terms "horizontal", "vertical", etc.), unless otherwise specified, they refer to the orientation of the drawings.

[0031] Unless otherwise specified, the expressions "around", "approximately", "substantially" and "about" mean plus or minus 10%, preferably plus or minus 5%.

[0032] Figure 1 An example of an integrated circuit 100 is shown very schematically in the form of a circuit module.

[0033] Circuit 100 includes, for example, a processing circuit block 104 (CTRL) including one or more processors, for example under the control of instructions stored in an instruction memory (not shown).

[0034] The circuit 100 further includes a clock circuit module 106 (REF) having a reference clock signal generating circuit including an oscillator generating a reference frequency.

[0035] The device 100 may integrate other circuits for implementing other functions, such as one or more volatile and / or non-volatile memories, other processing units, input / output interfaces (I / O), etc. Figure 1 1 is represented by a functional circuit module 102 (FCT).

[0036] Circuit modules 102 , 104 , and 106 are coupled to each other and / or to the rest of integrated circuit 100 , for example, via a bus 108 that carries the necessary signals.

[0037] The circuit modules 102 and / or 104 and / or 106 further include other functional circuits. The reference clock signal generation circuit module and the functional circuits are configured to be reset by at least one reset signal common to the functional circuits and the reference clock signal generation circuit module.

[0038] The present description relates more particularly to a clock circuit module 106 that generates a reference clock signal that is used, for example, in processes implemented by other circuit modules 102 , 104 .

[0039] The reference oscillator of the reference clock signal generator circuit module may be sensitive to, for example, power supply variations or to environmental parameters external to the circuit 100, which may lead to transient or permanent failures. In the current embodiment, these failures cause a total restart of the circuit 100.

[0040] In the described embodiment, circuit module 106 is configured to reset the reference clock signal generator circuit module only upon detection of a fault on the signal originating from the reference frequency generator oscillator. This allows a complete restart of circuit 100 to be avoided when the fault may be only momentary, for example.

[0041] Figure 2 The circuit module is shown very schematically. Figure 1 A circuit module of the integrated circuit 100.

[0042] More specifically, Figure 2 A reference clock signal generator circuit block 106 is depicted along with other functional circuits, such as circuit blocks 102 , 104 (other circuit blocks) external to the circuit block 106 or other functional circuit blocks 240 internal or external to the circuit block 106 .

[0043] The reference clock signal generator circuit module 106 includes a reference frequency generator 202 (oscillator), which is, for example, a crystal oscillator, such as a quartz crystal oscillator oscillating at 32,768 kHz. For example, under the action of a signal applied to input 202a, the reference frequency generator 202 generates a clock signal (OscClk) having a reference frequency at output 202b.

[0044] In the example shown, the reference clock signal generator circuit module further includes a clock detection circuit 204 (clock detector), whose input 204c is coupled to (preferably connected to) the output 202b of the generator 202 at a node 220. The detection circuit 204 is configured to detect whether the signal OscClk originating from the reference frequency generator 202 exhibits a fault, for example, whether a time period is lost or the expected frequency is not observed, and to generate an alarm signal (ClkFail) at the output 204a of the detection circuit, the state of which is modified according to the detection result, for example, when no fault is detected, it is state 0, and when a fault is detected, it switches to state 1 with a rising edge. In an example, the detection circuit 204 is a state machine. For example, the signal ClkFail can also be accessed in a register, and can send an event to the control unit 270 (such as, for example, the circuit module 104) to indicate to the control unit 270 that a fault has occurred and to record an error.

[0045] In the example shown, activation and deactivation of the detection circuit 204 is controlled, for example, by an enable control signal (ClkDetEn).

[0046] The detection circuit output 204a and the detection circuit control signal ClkDetEn are coupled to the input of the logic circuit module 212, which is configured to perform an AND logic function based on its inputs.

[0047] In the example shown, the output of the logic circuit module 212 is coupled (preferably connected) to a clock input 210b (generally referred to as CP input) of a flip-flop 210 (FF, memory element), which is, for example, a D-type flip-flop, for example, with falling or rising edge detection. In the example shown, the flip-flop is provided with rising edge detection and further includes a reset input 210a (resetbar), a data input 210c (D) (for example, set to 1) and an inverting output 210d (Qn) generally referred to as Qbar. Figure 2In the example of , the enabling of the input 210a is performed by falling edge detection when the signal switches to 0. The reset input 210a of the flip-flop 210 is coupled (preferably connected) to the output of the logic circuit module 214, which is configured to perform an AND-type function based on a reset signal (resetn) common to the functional circuit modules 102 and / or 104 and / or 240 and to the reference clock generator circuit module 106 and based on the inverse of the signal (ClkReArm) for resetting the reference frequency generator circuit module. The reset signal (resetn) common to the functional circuit modules 102 and / or 104 and / or 240 is, for example, at 0 when no reset is applied, and is set to 1 with a rising edge when, for example, the overall reset of the circuit 100 is controlled by the circuit module 104.

[0048] The logic circuit module 214 is implemented based on, for example, combinational logic and sequential logic. The signal ClkReArm for resetting the reference frequency generator circuit module includes, for example, a pulse controlled by a program (eg, implemented by the circuit module 104).

[0049] In the example shown, the reference clock signal generator circuit module 106 includes another logic circuit module 222, which is configured to perform an "AND" function based on the output signal 210d of the trigger 210 and a reset signal (resetn) common to the functional circuit modules 102 and / or 104 and / or 240 and the reference clock generator circuit module 106.

[0050] In the example shown, the reference clock generator circuit module 106 includes a control circuit element 224 (start control). The circuit module 224 is, for example, a digital circuit module based on a counter. The reset input 224a (resetbar) of the control element 224 is configured to receive an output signal (ClkOK) from the logic circuit module 222. When the input 224a receives a signal passing through 0, the control element 224 is reset. The clock input 224b (ClkIn) of the control element 224 is configured to receive a signal (OscClk) originating from a reference frequency generator. The oscillator control output 224c (SrcEn) of the control element 224 is coupled (preferably connected) to the logic circuit module 208 of the reference clock generator circuit module 106. The logic circuit module 208 is configured to perform an AND function based on the signal presented at the oscillator control output 224c and based on the signal (OscEn) for enabling the oscillator (which, for example, corresponds to a parameter determined by a user). The oscillator enable signal OscEn includes one or more bits assigned, for example, by a user to enable or disable the reference frequency generator 202. The output of the logic circuit module 208 is configured to transmit a control signal to the reference frequency generator 202 at its input 202a.

[0051] The control element 224 further includes an output 260, which transmits a signal (Ready) indicating whether the reference clock signal is ready to be transmitted by applying a delay equal to or greater than the oscillator stabilization time, for example. For example, the delay can be obtained by counting N cycles of the clock signal, N is greater than 100, for example, equal to 4096.

[0052] When the clock signal has been verified, the output 250 of the control element 224 provides a reference clock signal (ClkOut) having a reference frequency. This signal ClkOut is used, for example, by a security circuit module storing the time 230 (RTC, Real Time Clock), or can be used by other circuit modules to generate time sequences, for example (timers).

[0053] Resetting the control element 224 by means of the common reset signal resetn or by means of the reset signal ClkReArm comprises, for example, stopping the signal ClkOut and setting the output 224c to 0, which stops the reference frequency generator 202. When the input 224a is at 0, the control element 224 is reset. As long as the input 224a is at 0, the control element 224 will remain stopped. When the input 224a switches to 1, the circuit module 224 is again operable.

[0054] In operation, when detection circuit 204 is enabled by control bit ClkDetEn, which is set to 1, for example, in operation, detection circuit 204 detects whether there is a fault on the signal originating from reference frequency generator 202, such as, for example, no signal or wrong frequency.

[0055] When a fault is detected, the signal ClkFail changes, for example switches to a high level, and generates a rising edge. The output of the logic circuit module 212 then comprises a high level signal with a rising edge applied to the flip-flop 210 at the clock input 210b. The output 210d is then in state 0. The common reset signal resetn is at 1 by default, whereby the input 224a resetbar is set to 0, which triggers the reset of the control element 224.

[0056] At this stage, only a complete restart of the circuit (power-on) or a modification of the signal resetn or the signal ClkReArm enables the oscillator to be restarted. However, both the power-on of the circuit and the modification of the signal resetn may result in a reset of all functional circuit modules 102, 104 and may also result in a rewriting of the security key from the memory. This leads to delays in the use of the circuit and may also lead to security problems. Therefore, depending on the type of fault (temporary or permanent), a reset of the different functional circuit modules 102, 104 (in the case of a reset by modifying resetn) or a reset of only the circuit module 106 (in the case of a reset by modifying ClkReArm) may be preferred.

[0057] The control unit 270 which has received the bit ClkFail set to 1 modifies the state of the signal ClkReArm or resetn. The selection of the signal to be modified is performed, for example, according to the type of transient or permanent fault.

[0058] A first way to determine if a fault is a transient fault is to count the number of times signal ClkFail switches to 1 over the time counted using RTC module 230. This provides a fault rate that is compared to a threshold.

[0059] A second approach is to check whether the power mode of circuit 100 has been modified, for example by switching from active mode to very low power mode, when signal ClkFail switches to 1. In fact, this may generate oscillator power supply disturbances and potential faults that are related to this change and are therefore a priori instantaneous.

[0060] In order to reset only the circuit module 106, thereby avoiding the need to reset multiple functional circuit modules outside the circuit module 106, the signal ClkReArm for resetting the reference frequency generator circuit module is then set to a high level with a rising edge or pulse form. In this case, the signal resetn remains at 1 or a high level. The signal ClkReArm is inverted before the "AND" function of the logic circuit module 214, and the reset input 210a of the flip-flop 210 receives a falling edge passing through 0, which enables the flip-flop 210 to be reset and its Qn output 210d to switch to 1. Because resetn remains at 1, the output signal ClkOK of the logic circuit module 222 is at 1 (or high). Thus, the reset of the control element 224 is disabled because the control element 224 is only active when a signal at 0 is applied to the input 224a.

[0061] In order to also reset a plurality of functional circuit modules outside the circuit module 106, for example because there is no signal originating from the oscillator or the detected error rate is above a threshold value, the common reset signal resetn is then set to 0 or a low level with a falling edge. In this case, the signal ClkReArm remains at 0 or a low level. The reset input 210a of the flip-flop 210 thus receives a falling edge passing through 0, which enables the flip-flop 210 to be reset and its Qn output 210d to be switched to 1. Since resetn is at 0, the output signal ClkOK of the logic circuit module 222 is at 1. The reset 224a of the control element 224 is then disabled, since it is only active when the input 224a is at 0.

[0062] Figure 3 The control is shown very schematically in the form of a flow chart Figure 2 Circuit method.

[0063] At step 302 (Clock Failure Detected), a failure on a signal originating from reference frequency generator 202 is detected by detection circuit 204 .

[0064] Then, the two steps 304 (calculate failure rate) and 303 (failure occurs when power mode is changed?) may be performed in parallel, or only one of them, or one after the other, to estimate whether the failure is transient or permanent.

[0065] At step 303, if the fault is detected when the power mode of circuit 100 has changed (e.g., when transitioning from active mode to very low power mode), then the fault may be considered transient. In this case, branch "Y" toward step 308 (disabling the clock detector) is followed. In the opposite case (branch "N"), steps 316 (disabling the clock detector) or 326 (resetting the entire system) are implemented, or step 304 (which is the case in Figure 3 not shown).

[0066] During step 304, the error rate is determined, for example, by analyzing the number of times the signal ClkFail has switched to 1 according to the time of the clock circuit module 230. The time provided by the clock circuit module 230 is used, for example, to determine the failure rate per time unit by determining the relative time between two failures. Since the clock of the circuit module 230 is stopped when a failure is detected, this relative time is counted, for example, by a time counter or another reference clock different from the reference clock of the clock circuit module 230.

[0067] After step 304, at step 306 (Ratio Below Threshold), the error rate determined at step 304 is compared to a predetermined threshold. If the error rate is below the threshold (branch "yes"), then step 308 is implemented. If not, then steps 316 or 326 are implemented.

[0068] Step 308 comprises disabling the detection circuit 204, for example, by changing the state of the bit(s) ClkDetEn and by, for example, switching it to 0 if it was at 1 and vice versa. The signal ClkFail is then reset to its default value at 0.

[0069] Then, step 310 (re-arming the oscillator) is implemented, in which only the signal ClkReArm is modified (set to 1 by a rising edge), the signal resetn remains at 1. The input 210a of the flip-flop 210 is then set to 0. The output 210d is 1. The input 224a of the control element 224 switches to 1, which restarts the control element 224. The signal SrcEn at the output 224c switches to 1 and the oscillator 202 is re-enabled.

[0070] Next, step 312 (Oscillator Ready?) is performed. In this step, the reference signal OscClk, which is again generated and present at the input 224b of the control element 224, is verified by the control element 224 over a large number of cycles (e.g. 4096 cycles). If the oscillator has stabilized and no errors are detected, the signal Ready is set to a state indicating that the reference frequency generator 202 is ready (branch "yes"). The reference clock signal ClkOut is then available at the output 250. Next, step 314 (Enable Clock Detector) is implemented.

[0071] During a step 314 , the detection circuit 204 is re-enabled, for example by switching the state of the bit ClkDetEn to a high state or in the form of a pulse.

[0072] The following step 315 (end process) corresponds to the end of the process.

[0073] At step 312, in case the signal Ready on output 260 is not detected or is not detected within a given time (timeout), the reference frequency generator 202 is considered not ready (branch "No"), and one of steps 316 (disabling the clock detector) or 326 (resetting the entire system) is implemented.

[0074] When following the "NO" branches of steps 306 and 312, one of steps 316 or 326 may be implemented.

[0075] Step 316 includes disabling the detection circuit 204 , eg, similar to step 308 .

[0076] Then, step 318 is performed (selecting a less accurate backup clock for temporary use). At step 318, a substitute clock signal is selected for use in other subsequent processes in subsequent step 340 (next process step). This substitute clock signal is derived, for example, from an internal backup low frequency oscillator, which enables compensation of a fault in the reference frequency generator for a limited time period.

[0077] Step 340 (the next process step) includes other processes to be carried out. These other processes are, for example: re-adjusting the time of the circuit module 230, or protecting the confidentiality of the circuit if it is estimated that the fault may be an attack, or in addition requesting power-on by sending the bit "resetn", and if the oscillator is not restarted, then confidentiality (such as encryption keys) can be erased.

[0078] Step 326 includes completely resetting the various functional circuit blocks by modifying bit resetn (e.g., by setting it to 0), and then restarting and resetting them at step 328 (reinitializing the entire system). During step 328, the security key may have to be copied from the memory into the security register.

[0079] At the following step 330 (Re-enable oscillator), the reference frequency generator 202 is restarted by modifying the bits SrcEn and OscEn, wherein the bit OscEn returns to 0, which corresponds to a switched-off oscillator.

[0080] Then, after step 330, a step 332 (Oscillator Ready?) similar to step 312 is performed. At this step, if the signal Ready is set to a state indicating that the reference frequency generator 202 is ready (branch "Yes"), a step 334 (Enable Clock Detector) is implemented. At step 334, the detection circuit 204 is re-enabled, for example, by switching the state of the bit ClkDetEn to a high state or in the form of a pulse.

[0081] Otherwise, the reference frequency generator 202 is considered not ready (branch “NO”), and step 340 is implemented.

[0082] A number of embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0083] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of those skilled in the art. In particular, with respect to the input 224a of the control element 224, if the logic circuit module 222 is a NAND logic circuit module, then the input can be enabled by a signal at 1 or a high level.

[0084] In another example, if the logic circuit module 214 does not include an inverter at the input, then the signal ClkReArm may be set to 0 when it is necessary to restart the circuit module 106 .

Claims

1. An electronic circuit comprising: a reference clock signal generator circuit including a reference frequency generator and a detection circuit configured to detect a fault on a signal originating from the reference frequency generator; Functional circuit; and A control circuit is configured to generate a first reset signal in response to a fault detected on a signal originating from a reference frequency generator, the first reset signal causing a reset of the reference frequency generator, wherein the first reset signal is different from a second reset signal used to cause a common reset of the functional circuit and the reference clock signal generator circuit.

2. The circuit according to claim 1, further comprising: a trigger clocked by a signal derived from a fault detected on a signal originating from a reference frequency generator; a first logic circuit configured to logically combine a first reset signal and a second reset signal; the flip-flop having a reset input coupled to the output of the first flip-flop; a second logic circuit configured to logically combine the output of the flip-flop with the second reset signal to generate a clock state signal; as well as The enable control circuit is configured to control the enablement of the reference frequency generator in response to the clock state signal.

3. The circuit of claim 1, wherein the detection circuit is configured to detect whether the signal originating from the reference frequency generator exhibits a fault, and to generate a fault status signal at the output of the detection circuit in dependence on a result of the detection.

4. The circuit of claim 3, wherein the reference clock signal generator circuit further comprises a flip-flop, the flip-flop having: a clock input coupled to the output of the detection circuit; and A reset input is coupled to the first logic block, the first logic block being configured to perform a logical AND of the inverse of the first reset signal and the second reset signal.

5. The circuit of claim 4 , wherein the reference clock signal generator circuit further comprises a control circuit having a reset input coupled to a second logic block, the second logic block being configured to perform a logical AND of a signal present at the inverting output of the flip-flop and the second reset signal.

6. The circuit of claim 5, wherein the inverting output of the flip-flop is configured to be reset when the reset input is enabled.

7. The circuit of claim 5, wherein the reset input of the flip-flop is enabled when it receives a signal at logic 0.

8. The circuit of claim 5, wherein the control circuit comprises an oscillator output configured to transmit a signal for controlling a reference frequency generator.

9. The circuit of claim 8, wherein the signal for controlling the reference frequency generator is configured to stop the reference frequency generator when a reset input of the control circuit is enabled.

10. The circuit of claim 5, wherein the control circuit comprises: a clock output configured to transmit a reference clock signal having a reference frequency; as well as a clock input configured to receive said signal originating from a reference frequency generator; Wherein the control circuit is configured to transmit a reference clock signal at the clock output based on said signal originating from the reference frequency generator after a given number of cycles have been verified.

11. The circuit according to claim 4, wherein: The flip-flop is coupled to the output of the detection circuit via a third logic block, and the third logic block is configured to perform a logical AND on the fault status signal and a signal for enabling the detection circuit.

12. The circuit of claim 4, wherein the flip-flop includes a data input that is set to a logic 1 state.

13. The circuit of claim 4, wherein the flip-flop is a D-type flip-flop.

14. A circuit comprising: an oscillator circuit having an enable input and a clock output; a detection circuit coupled to the clock output and configured to detect a failure of the oscillator circuit; a flip-flop circuit having a clock input coupled to receive the clock failure signal output by the detection circuit; a first logic circuit configured to logically combine a first reset signal indicating a reset of the circuit module and a second reset signal indicating a reset of only the reference frequency generator; wherein a reset input of the flip-flop is coupled to an output of the first logic circuit; a second logic circuit configured to logically combine the output of the flip-flop with a second reset signal to generate a clock state signal; as well as A control circuit is configured to receive the clock state signal and to control a logic state of an enable signal applied to an enable input of the oscillator circuit.

15. The circuit of claim 14 , wherein the detection circuit further comprises an enable input configured to receive a detector enable signal, and further comprises a third logic circuit configured to logically combine the detector enable signal and a clock failure signal output by the detection circuit to generate a signal applied to a clock input of the flip-flop.

16. The circuit of claim 14, further comprising a fourth logic circuit configured to logically combine the oscillator enable signal and the oscillator control signal generated by the control circuit to generate an enable signal applied to an enable input of the oscillator circuit.

17. The circuit according to claim 14, wherein the oscillator circuit, the detection circuit, the trigger circuit, the first logic circuit, the second logic circuit and the control circuit are circuit components of a reference clock signal generator circuit module, the circuit further includes one or more functional circuit modules, wherein each functional circuit module is reset in response to the first reset signal, and wherein the reference clock signal generator circuit module and the one or more functional circuit modules are coupled via a circuit bus.

Images