Millimeter wave broadband high-gain low-noise amplifier based on CMOS (complementary metal oxide semiconductor) process

Abstract

The invention discloses a millimeter wave broadband high-gain low-noise amplifier based on a CMOS (Complementary Metal Oxide Semiconductor) process. The millimeter wave broadband high-gain low-noise amplifier comprises an input broadband balun transformer network, a first-stage gain circuit, a symmetric MCR interstage matching network, a second-stage linearization circuit and an output broadband transformer network, the first-stage gain circuit provides large gain for the whole amplifier and inhibits noise by using a differential common-source structure, and a source degeneration inductor uses an 8-shaped drawing scheme to reduce parasitic parameters; a derivative overlapping technology is used in a second-stage linearization circuit, so that the signal linearity is improved, and the signal is gained to a certain extent; the input broadband balun transformer network, the symmetric MCR inter-stage matching network and the output broadband transformer network all use an MCR broadband impedance matching method to carry out matching network design, so that the broadband characteristic of the circuit is ensured; the antenna can normally work in a temperature range from low temperature (-40 DEG C) to high temperature (125 DEG C), and achieves high gain and broadband characteristics in a working frequency band.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a millimeter wave broadband high-gain low-noise amplifier based on CMOS technology. Background Art

[0002] With the rapid development of wireless communication technology, the fifth generation of communication technology (5G) has emerged, and the millimeter wave band has entered people's field of vision. Compared with the crowded sub 6GHz band, the millimeter wave band can more conveniently achieve the goal of high bandwidth. Under the same relative bandwidth, high-frequency millimeter waves naturally have a wider absolute bandwidth; RF integrated circuits, as key modules in wireless communication systems, have become a current research hotspot. Low noise amplifiers (Low Noise Amplifiers, LNA) are one of the most important parts of wireless communication systems. They are located at the front end of the RF receiver, and their performance has a crucial impact on the overall performance of the RF receiver. In the entire receiver system, the noise size of the LNA determines the overall noise of the link, and the gain of the LNA needs to be large enough to reduce the impact of the subsequent circuit modules on the noise performance indicators of the entire system. In addition, since broadband communication has the advantages of high frequency utilization and high transmission rate, it has good application prospects in fields such as satellite communications. At present, achieving high gain, low noise and high linearity under millimeter wave broadband conditions and being able to achieve good input matching and output matching is a technical difficulty in LNA design, which needs to be broken through urgently.

[0003] In the prior art, the invention with publication number CN111371412A discloses "a CMOS millimeter-wave broadband low-noise amplifier operating at 66 to 88 GHz", which performs inter-stage matching through a transformer and adjusts the resonance point to achieve a broadband effect. However, its linearity is low and cannot meet the application scenarios with high linearity requirements.

[0004] In the prior art, the invention with publication number CN115549601A discloses "a Ka-band broadband low-noise amplifier", which improves the bandwidth by using the Arm and Branch structure and introduces an inter-stage matching network to improve the -3dB bandwidth to achieve a broadband effect, but its gain is low and the noise coefficient is large. Summary of the invention

[0005] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a millimeter-wave broadband high-gain low-noise amplifier based on CMOS technology, which improves the overall gain of the circuit and reduces the noise coefficient by using a differential common-source stage circuit in the first-stage circuit; reduces the third-order nonlinearity by using the derivative overlap technology in the second-stage circuit to improve the linearity of the circuit; adopts a transformer-based matching method between each stage of the circuit, and uses a broadband impedance matching method based on MCR (magnetically coupled resonator) to design a matching network to obtain broadband gain characteristics; by merging the two source degeneration inductors in the first-stage gain circuit and grounding the middle tap, the coupling coefficient between the transformer surrounding it can be minimized; the present invention as a whole works in the frequency range of 24GHz to 27GHz with good performance.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A millimeter-wave broadband high-gain low-noise amplifier based on CMOS technology, comprising an input broadband balun transformer network 1a, a first-stage gain circuit 2, a symmetrical MCR inter-stage matching network 1b, a second-stage linearization circuit 3, and an output broadband transformer network 1c; wherein the input broadband balun transformer network 1a is used to convert the RF signal from a single-ended signal u se Converted into differential signal u diff , and achieve broadband impedance matching; the first-stage gain circuit 2 provides a larger gain for the low-noise amplifier as a whole and suppresses noise, achieving the differential signal u diff After processing, the gain differential signal u is obtained diff '; Symmetrical MCR inter-stage matching network 1b is used for signal transmission and broadband impedance matching between the first-stage gain circuit 2 and the second-stage linearization circuit 3, and converts the gain differential signal u diff 'Convert to single-ended signal u se ' and input to the second-stage linearization circuit 3; the second-stage linearization circuit 3 is used to improve the linearity of the signal and the single-ended signal u se 'Apply a certain gain to obtain the signal u se "; The output broadband transformer network 1c performs broadband impedance matching and matches the output impedance to the load impedance, while the signal u se ” is converted into RF output signal u se ”' and output it.

[0008] Furthermore, the input broadband balun transformer network 1a includes a first capacitor C1, a first transformer primary coil Ta1, a first transformer secondary coil Ta2, and a second capacitor C2; the RF signal input end is connected to one end of a parallel network composed of the first capacitor C1 and the first transformer primary coil Ta1, and the other end of the parallel network composed of the first capacitor C1 and the first transformer primary coil Ta1 is grounded; one end of the first transformer secondary coil Ta2 is respectively connected to the first end of the second capacitor C2 and the first end of the first impedance tuning inductor L1A in the first-stage gain circuit 2, and the other end of the first transformer secondary coil Ta2 is respectively connected to the second end of the second capacitor C2 and the first end of the second impedance tuning inductor L1B in the first-stage gain circuit 2, and the middle tap of the first transformer secondary coil Ta2 is connected to the bias voltage VDC; the first transformer primary coil Ta1 is magnetically coupled to the first transformer secondary coil Ta2.

[0009] Furthermore, the first-stage gain circuit 2 is used to achieve the gain output of the input signal and lower signal noise, and includes a first impedance tuning inductor L1A, a second impedance tuning inductor L1B, a first source degeneration inductor L2A, a second source degeneration inductor L2B and a differential common-source amplifier with a neutralizing capacitor, wherein the differential common-source amplifier with a neutralizing capacitor is composed of a first MOS tube M1A, a second MOS tube M1B, a first neutralizing capacitor C3A and a second neutralizing capacitor C3B, and a bias voltage VDC is supplied from the middle tap of the secondary winding Ta2 of the first transformer to the gate of the first MOS tube M1A, and at the same time, the gate of the first MOS tube M1A is connected to the second end of the first impedance tuning inductor L1A, and the source of the first MOS tube M1A is connected to the second end of the first source degeneration inductor L2A. ; The first end of the first source degeneration inductor L2A and the first end of the second source degeneration inductor L2B are connected and grounded together; the bias voltage VDC is supplied from the middle tap of the secondary winding Ta2 of the first transformer to the gate of the second MOS tube M1B, and the gate of the second MOS tube M1B is connected to the second end of the second impedance tuning inductor L1B, and the source of the second MOS tube M1B is connected to the second end of the second source degeneration inductor L2B; the first end of the first neutralization capacitor C3A is connected to the gate of the first MOS tube M1A, and the second end of the first neutralization capacitor C3A is connected to the drain of the second MOS tube M1B; the first end of the second neutralization capacitor C3B is connected to the gate of the second MOS tube M1B, and the second end of the second neutralization capacitor C3B is connected to the drain of the first MOS tube M1A.

[0010] Furthermore, the symmetrical MCR inter-stage matching network 1b includes a third capacitor C4A, a fourth capacitor C4B, a second transformer primary coil Tb1 and a second transformer secondary coil Tb2; the first end of the third capacitor C4A is respectively connected to the drain of the first MOS tube M1A and the first end of the second transformer primary coil Tb1, the second end of the third capacitor C4A is connected to the second end of the fourth capacitor C4B, the first end of the fourth capacitor C4B is respectively connected to the drain of the second MOS tube M1B and the second end of the second transformer primary coil Tb1, and the middle tap of the second transformer primary coil Tb1 is connected to the power supply voltage VDD; the first end of the second transformer secondary coil Tb2 is connected to the input end of the second-stage linearization circuit 3, and the second end of the second transformer secondary coil Tb2 is connected to the bias voltage VB1; the second transformer primary coil Tb1 is magnetically coupled to the second transformer secondary coil Tb2.

[0011] Further, the second-stage linearization circuit 3 includes a third MOS tube M2, a third source degeneration inductor L3, a fifth capacitor C5, a first resistor R1, a fourth MOS tube M3, and a fourth source degeneration inductor L4; the gate of the third MOS tube M2 is respectively connected to the first end of the second transformer secondary coil Tb2 and the first end of the fifth capacitor C5, the drain of the third MOS tube M2 is connected to the input end of the output broadband transformer network 1c, the source of the third MOS tube M2 is connected to the first end of the third source degeneration inductor L3, and the second end of the third source degeneration inductor L3 is grounded; the gate of the fourth MOS tube M3 is respectively connected to the second end of the fifth capacitor C5 and the first end of the first resistor R1, the drain of the fourth MOS tube M3 is connected to the input end of the output broadband transformer network 1c, the source of the fourth MOS tube M3 is connected to the first end of the fourth source degeneration inductor L4, and the second end of the fourth source degeneration inductor L4 is grounded; the second end of the first resistor R1 is connected to the bias voltage VB2.

[0012] Furthermore, the output broadband transformer network 1c includes a sixth capacitor C6, a third transformer primary coil Tc1, a third transformer secondary coil Tc2, and a seventh capacitor C7; the first end of the sixth capacitor C6 is respectively connected to the drain of the third MOS tube M2, the drain of the fourth MOS tube M3 and the first end of the third transformer primary coil Tc1, and the second end of the sixth capacitor C6 is grounded; the second end of the third transformer primary coil Tc1 is connected to the power supply voltage VDD; the first end of the third transformer secondary coil Tc2 is respectively connected to the first end of the seventh capacitor C7 and the RF signal output port, the second end of the third transformer secondary coil Tc2 is connected to the second end of the seventh capacitor C7, and the second end of the third transformer secondary coil Tc2 is grounded; the third transformer primary coil Tc1 is magnetically coupled to the third transformer secondary coil Tc2.

[0013] Furthermore, the input broadband balun transformer network 1a, the symmetrical MCR inter-stage matching network 1b, and the output broadband transformer network 1c all use an MCR-based broadband impedance matching method to calculate the corresponding initial inductance and capacitance values, and design the matching network through iterative optimization.

[0014] Furthermore, the first source degeneration inductor L2A and the second source degeneration inductor L2B in the first-stage gain circuit 2 are combined into one inductor in the layout drawing and the middle tap is grounded, and the drawing uses an 8-shaped inductor solution.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] First, in the present invention, the input broadband balun transformer network 1a, the symmetrical MCR interstage matching network 1b, and the output broadband transformer network 1c all use the MCR-based broadband impedance matching method to design the matching network, thereby ensuring that broadband characteristics can be obtained.

[0017] Second, in the present invention, after the differential common source structure is used in the first-stage gain circuit 2 to ensure the gain, the derivative overlap technology is used in the second-stage linearization circuit 3, and two MOS tubes M2 and M3 working at different bias voltages are connected in parallel to offset the third-order derivative component of the current to the voltage, thereby reducing the third-order nonlinearity; in addition, the source degeneration inductors L3 and L4 are added to further improve the second-stage linearity.

[0018] 3. In the layout drawing of the first-stage gain circuit 2, the present invention combines the two source degeneration inductors L2A and L2B together, and the middle tap is grounded. In order to minimize the coupling coefficient between the transformers Tb1 and Tb2 surrounding them, an 8-shaped inductor drawing scheme is used, so that the coupling coefficient between the two can be ignored, which greatly reduces the layout routing length and reduces parasitic parameters.

[0019] Fourthly, the present invention adjusts the circuit parameters so that the low noise amplifier can work normally at -40°C to 125°C, and the performance indicators do not have a large deviation.

[0020] In summary, the gain and linearity of the present invention are high, and the use of magnetic coupling technology (MCR) can make the circuit have better broadband characteristics. By adjusting the circuit parameters, the circuit can work normally in a large temperature range of -40°C to 125°C, and the layout drawing method using an 8-shaped inductor greatly reduces the layout area and parasitic effects, thereby optimizing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a schematic diagram of a structure of a millimeter-wave broadband high-gain low-noise amplifier based on CMOS technology provided in an embodiment of the present invention.

[0022] Figure 2 Schematic diagram of the second-stage linearization circuit 3 provided in an embodiment of the present invention.

[0023] FIG. 3( a ) is a schematic diagram of magnetic coupling resonance in an embodiment of the present invention.

[0024] Figure 3(b) is a schematic diagram of the principle of a magnetically coupled resonator.

[0025] Figure 4 It is a schematic diagram of an 8-shaped layout of source degeneration inductors L2A and L2B of the first-stage gain circuit 2 provided by an embodiment of the present invention.

[0026] Figure 5 It is a schematic diagram of the principle of the low coupling coefficient of the figure-8 inductor in an embodiment of the present invention.

[0027] FIG. 6( a ) is a schematic diagram of a simulation result of a 1 dB compression point at -40° C. input provided by an embodiment of the present invention.

[0028] FIG6( b ) is a schematic diagram of a simulation result of a 1 dB compression point at 25° C. input provided by an embodiment of the present invention.

[0029] FIG6( c ) is a schematic diagram of simulation results of a 125° C. input 1 dB compression point provided by an embodiment of the present invention.

[0030] Figure 7 It is a schematic diagram of input matching simulation provided by an embodiment of the present invention.

[0031] Figure 8 It is a schematic diagram of output matching simulation provided by an embodiment of the present invention.

[0032] Fig. 9 It is a schematic diagram of circuit gain simulation provided by an embodiment of the present invention.

[0033] Fig.10 It is a schematic diagram of noise coefficient simulation provided by an embodiment of the present invention.

[0034] Fig.11 It is a schematic diagram of stability factor simulation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments, but the embodiments of the present invention are not limited thereto.

[0036] See also Figure 1The present application provides a millimeter-wave broadband high-gain low-noise amplifier based on CMOS technology, comprising an input broadband balun transformer network 1a, a first-stage gain circuit 2, a symmetrical MCR interstage matching network 1b, a second-stage linearization circuit 3, and an output broadband transformer network 1c; the output end of the input broadband balun transformer network (1a) is connected to the input end of the first-stage gain circuit (2), the output end of the first-stage gain circuit (2) is connected to the input end of the second-stage linearization circuit (3) through the symmetrical MCR interstage matching network (1b), and the output end of the second-stage linearization circuit (3) is connected to the input end of the output broadband transformer network (1c).

[0037] The input broadband balun transformer network 1a is used to convert the RF signal from a single-ended signal u se Converted into differential signal u diff , and achieve broadband impedance matching; the first-stage gain circuit 2 provides a larger gain for the low-noise amplifier as a whole and suppresses noise, achieving the differential signal u diff After processing, the gain differential signal u is obtained diff '; Symmetrical MCR inter-stage matching network 1b is used for signal transmission and broadband impedance matching between the first-stage gain circuit 2 and the second-stage linearization circuit 3, and converts the gain differential signal u diff 'Convert to single-ended signal u se ' and input to the second-stage linearization circuit 3; the second-stage linearization circuit 3 is used to improve the linearity of the signal and the single-ended signal u se 'Apply a certain gain to obtain the signal u se "; The output broadband transformer network 1c performs broadband impedance matching and matches the output impedance to the load impedance, while the signal u se ” is converted into RF output signal u se ”' and output it.

[0038] In the first embodiment of the present application, the input broadband balun transformer network 1a includes a first capacitor C1, a first transformer primary coil Ta1, a first transformer secondary coil Ta2, and a second capacitor C2; the RF signal input end is connected to one end of the parallel network composed of the first capacitor C1 and the first transformer primary coil Ta1, and the other end of the parallel network composed of the first capacitor C1 and the first transformer primary coil Ta1 is grounded; one end of the first transformer secondary coil Ta2 is respectively connected to the first end of the second capacitor C2 and the first end of the first impedance tuning inductor L1A in the first-stage gain circuit 2, and the other end of the first transformer secondary coil Ta2 is respectively connected to the second end of the second capacitor C2 and the first end of the second impedance tuning inductor L1B in the first-stage gain circuit 2, and the middle tap of the first transformer secondary coil Ta2 is connected to the bias voltage VDC; the first transformer primary coil Ta1 is magnetically coupled to the first transformer secondary coil Ta2.

[0039] See also Figure 1 In the first step, the value of the input impedance is measured through the test platform using a simulation method. In the second step, a first resonant circuit is formed by the first capacitor C1 and the first transformer primary coil Ta1, and a second resonant circuit is formed by the second capacitor C2 and the first transformer secondary coil Ta2. In the third step, the corresponding capacitance and inductance values ​​in the corresponding circuit are designed using a symmetrical MCR design method. It should be noted that in the process of input impedance matching, gate tuning inductors L1A and L1B are used to adjust the Q value (network quality factor) in the right resonant network (i.e., the resonant network composed of the first transformer secondary coil Ta2 and the equivalent parallel capacitor and the equivalent parallel resistor), so that the difference between the impedance value when the input impedance is converted from series to parallel and the source impedance can be reduced, and the matching difficulty can be reduced to achieve the impedance transformation between the 50Ω impedance value and the conjugate value of the input impedance. The method introduced below is a detailed description of the matching network method.

[0040] In the first embodiment of the present application, the input broadband balun transformer network 1a, the symmetrical MCR interstage matching network 1b, and the output broadband transformer network 1c all use the MCR-based broadband impedance matching method to design the matching network to ensure that broadband characteristics can be obtained.

[0041] See also Figure 3(a) to Figure 3(b), when designing, it is necessary to convert the differential impedance at the input end of the first-stage gain circuit into a single-ended impedance before designing. Figure 3(a) is a schematic diagram of a symmetrical MCR, which includes two magnetically coupled resonant circuits (i.e., the first capacitor C1 and the first transformer primary coil Ta1 constitute the first resonant circuit, and the second capacitor C2 and the first transformer secondary coil Ta2 constitute the second resonant circuit). These two resonant circuits belong to a fourth-order matching network and have a double pole with adjustable frequency; Figure 3(b) is a simplified schematic diagram of the MCR, which consists of two inductors, two capacitors and two resistors. There is coupling between the inductors. Seven parameters are sufficient to describe this simplified MCR, which are L1, C1 and R1 of the left resonator, L2, C2 and R2 of the right resonator, and the coupling coefficient K between them; we can also use the angular frequency w, quality factor Q and peak impedance R P A new set of parameters is used to describe the MCR. These parameters are more convenient to use when the peak impedance at both ends of the matching network is fixed (such as the output matching network of a PA, i.e., a power amplifier). For the uncoupled slots on each side of the MCR, the conversion between the two sets of parameters can be performed using the following formulas (1) to (3):

[0042]

[0043] R P =R#(3)

[0044] In formula (1) to formula (3), w is the angular frequency, L is the inductance of the resonant network, C is the capacitance of the resonant network, R is the value of the peak impedance, and R P is the peak impedance of the resonant network, and Q is the quality factor.

[0045] w, Q and R P It can be estimated from the amplitude response of the uncoupled resonant cavity; with the new parameter set, we also have seven parameters to describe the MCR: w1, Q1 and R of the uncoupled cavity on the left P1 , w2, Q2 and R of the uncoupled cavity on the right P2 and the coupling K between them. These seven parameters are used in the two-port network model to analyze MCR, Z of MCR 21 The complete formula for calculating is (4), where s = jw.

[0046]

[0047] In formula (4) and formula (5), Z 21 It is the parameter in the two-port network Z parameter that represents the control effect of the input current on the output voltage, and w0 is the unified resonant frequency of the two resonant networks.

[0048] When using the broadband impedance matching method, there are two cases: symmetrical MCR and asymmetrical MCR. In this application, symmetrical MCR is used, so only the symmetrical MCR method is introduced. Consider the case of symmetrical MCR, where w1=w2=w0, Q1=Q2=Q(R P1 and R P2 do not need to be equal to each other), then, Z in formula (4) 21 is simplified to formula (5); from formulas (4) and (5), we can see that R P1 and R P2 The bandwidth characteristic is not affected by the peak impedance as it appears only as a constant factor in the equation.

[0049] At the pole frequency of the MCR, Z 21 The phase should be 0° or ±180°, which means that Z 21 The imaginary part of is zero, we can calculate the two pole frequencies by making the real part of the denominator of (5) equal to zero, assuming 2Q 2 >>1-k 2 , where Q is the quality factor and the two pole frequencies are w H and w L The calculation is shown in formulas (6) to (7):

[0050]

[0051] In formula (6) and formula (7), w H is the high frequency pole frequency, w L is the low frequency pole frequency.

[0052] From the above equation, we can see that a larger k will move the frequencies of the two poles away from each other.

[0053] In order to make the gain flat, the no gain ripple condition needs to be met:

[0054] k 2 (1+Q 2 )=1#(8)

[0055] In formula (8), k is the coupling coefficient and Q is the quality factor.

[0056] The central operating frequency w C is determined, and the Q value is calculated using the following formula

[0057]

[0058] α=w C R S (C S Ten C P )#(10)

[0059] In formula (9) and formula (10), Q is the quality factor, α is the symbol of the algebraic expression, and C P is the parasitic capacitance of the primary coil, w C is the central operating angular frequency, R S is the real part of the optimal load impedance conjugate, C S is the imaginary part of the conjugate of the optimal load impedance.

[0060] After calculating the Q value, the coupling coefficient k is calculated according to the condition of no gain ripple, and then L1 is calculated according to formula (11):

[0061]

[0062] In formula (11), L1 is the inductance value of the left resonant network.

[0063] From the symmetrical MCR conditions of w1=w2 and Q1=Q2, it can be seen that the inductance ratio on both sides of the MCR must be equal to the resistance ratio:

[0064]

[0065] In formula (12) and formula (13), C1 is the capacitance value of the left resonant network, C2 is the capacitance value of the right resonant network, L1 is the inductance value of the left resonant network, L2 is the inductance value of the right resonant network, and R S is the real part of the optimal load impedance conjugate, R L is the load impedance.

[0066] According to the above formula, the transformer inductance value that satisfies the designed broadband matching and the capacitance value that resonates with the coil to provide a broadband frequency response can be obtained, while load matching is achieved.

[0067] In the first embodiment of the present application, the first-stage gain circuit 2 is used to achieve the gain output of the input signal and lower signal noise, which includes a first impedance tuning inductor L1A, a second impedance tuning inductor L1B, a first source degeneration inductor L2A, a second source degeneration inductor L2B and a differential common-source amplifier with a neutralizing capacitor. The differential common-source amplifier with a neutralizing capacitor is composed of a first MOS tube M1A, a second MOS tube M1B, a first neutralizing capacitor C3A and a second neutralizing capacitor C3B. The bias voltage VDC is supplied from the middle tap of the secondary winding Ta2 of the first transformer to the gate of the first MOS tube M1A. At the same time, the gate of the first MOS tube M1A is connected to the second end of the first impedance tuning inductor L1A, and the source of the first MOS tube M1A is connected to the second end of the first source degeneration inductor L2A. The first end of the first source degeneration inductor L2A and the first end of the second source degeneration inductor L2B are connected and grounded together; the bias voltage VDC is supplied from the middle tap of the secondary winding Ta2 of the first transformer to the gate of the second MOS tube M1B, and the gate of the second MOS tube M1B is connected to the second end of the second impedance tuning inductor L1B, and the source of the second MOS tube M1B is connected to the second end of the second source degeneration inductor L2B; the first end of the first neutralization capacitor C3A is connected to the gate of the first MOS tube M1A, and the second end of the first neutralization capacitor C3A is connected to the drain of the second MOS tube M1B; the first end of the second neutralization capacitor C3B is connected to the gate of the second MOS tube M1B, and the second end of the second neutralization capacitor C3B is connected to the drain of the first MOS tube M1A.

[0068] See also Figure 4 In actual RF circuits, there may be a large number of inductors. When there are many inductors, a lot of layout area will be consumed. In order to maintain the spacing between the inductors, the routing of other components will be lengthened. This part of the routing will introduce additional parasitics and affect the circuit performance. In order to reduce the coupling between the inductors, the inductors should be kept at a sufficiently large spacing. In order to reduce the coupling between the inductors, the present invention can use an 8-shaped inductor.

[0069] See also Figure 5 , the figure-8 inductor can be regarded as a twisted octagonal spiral inductor, and the upper and lower coils are symmetrical, so the magnetic coupling effect can be measured as shown in formula (14):

[0070]

[0071] In formula (14), M 21 is the mutual inductance of Ind2 and Ind1 (Ind1 is an 8-shaped inductor, Ind2 is another circular inductor), R1 and R2 are the inner diameters of the coils of Ind1 and Ind2 respectively, D1 and D2 are the electric displacement vectors of the two coils of the 8-shaped inductor, and μ0 is the magnetic permeability.

[0072] It can be seen from the equation that even at a close distance, the mutual inductance between the figure-8 inductor and any square or octagonal inductor whose center is located at the common tangent is approximately zero. The figure-8 inductor solution makes the coupling coefficient between the transformers Tb1, Tb2 surrounding it and the source degeneration inductors L2A, L2B negligible. The use of the figure-8 inductor can greatly reduce its coupling with other inductors, so it can be placed in a position close to other inductors without worrying about coupling with other inductors, greatly reducing the routing length and layout area, and reducing parasitic parameters.

[0073] In the first embodiment of the present application, the symmetrical MCR inter-stage matching network 1b includes a third capacitor C4A, a fourth capacitor C4B, a second transformer primary coil Tb1 and a second transformer secondary coil Tb2; the first end of the third capacitor C4A is respectively connected to the drain of the first MOS tube M1A and the first end of the second transformer primary coil Tb1, the second end of the third capacitor C4A is connected to the second end of the fourth capacitor C4B, the first end of the fourth capacitor C4B is respectively connected to the drain of the second MOS tube M1B and the second end of the second transformer primary coil Tb1, and the middle of the second transformer primary coil Tb1 is tapped to the power supply voltage VDD; the first end of the second transformer secondary coil Tb2 is connected to the input end of the second-stage linearization circuit 3, and the second end of the second transformer secondary coil Tb2 is connected to the bias voltage VB1; the second transformer primary coil Tb1 is magnetically coupled to the second transformer secondary coil Tb2.

[0074] In the first embodiment of the present application, the second-stage linearization circuit 3 includes a third MOS transistor M2, a third source degeneration inductor L3, a fifth capacitor C5, a first resistor R1, a fourth MOS transistor M3, and a fourth source degeneration inductor L4; the gate of the third MOS transistor M2 is respectively connected to the first end of the second transformer secondary coil Tb2 and the first end of the fifth capacitor C5, the drain of the third MOS transistor M2 is connected to the input end of the output broadband transformer network 1c, the source of the third MOS transistor M2 is connected to the first end of the third source degeneration inductor L3, and the second end of the third source degeneration inductor L3 is grounded; the gate of the fourth MOS transistor M3 is respectively connected to the second end of the fifth capacitor C5 and the first end of the first resistor R1, the drain of the fourth MOS transistor M3 is connected to the input end of the output broadband transformer network 1c, the source of the fourth MOS transistor M3 is connected to the first end of the fourth source degeneration inductor L4, and the second end of the fourth source degeneration inductor L4 is grounded; the second end of the first resistor R1 is connected to the bias voltage VB2.

[0075] See also Figure 2An ideal single-frequency input signal will generate various harmonic components through a nonlinear system, wherein the third-order nonlinearity of the system will affect the gain of the baseband signal, and the third-order nonlinearity will cause the gain to be compressed when the input signal amplitude is large. The 1dB compression point of the system can be improved by reducing the third-order nonlinearity of the system, that is, improving the linearity of the circuit. The key to reducing the third-order nonlinearity is to reduce the third-order nonlinearity of the transistor transmission characteristics. The present invention uses a derivative overlap method to improve and reduce the third-order nonlinearity in the circuit, and biases two NMOS tubes with different bias voltages respectively, so that the sum of the second-order derivatives of the transconductance of the two NMOS tubes to the bias voltage is 0, which can better improve the third-order nonlinearity caused by the nonlinear transmission characteristics of the transistor and improve the input 1dB compression point of the low-noise amplifier.

[0076] In the first embodiment of the present application, the output broadband transformer network 1c includes a sixth capacitor C6, a third transformer primary coil Tc1, a third transformer secondary coil Tc2, and a seventh capacitor C7; the first end of the sixth capacitor C6 is respectively connected to the drain of the third MOS tube M2, the drain of the fourth MOS tube M3 and the first end of the third transformer primary coil Tc1, and the second end of the sixth capacitor C6 is grounded; the second end of the third transformer primary coil Tc1 is connected to the power supply voltage VDD; the first end of the third transformer secondary coil Tc2 is respectively connected to the first end of the seventh capacitor C7 and the RF signal output port, the second end of the third transformer secondary coil Tc2 is connected to the second end of the seventh capacitor C7, and the second end of the third transformer secondary coil Tc2 is grounded; the third transformer primary coil Tc1 is magnetically coupled to the third transformer secondary coil Tc2.

[0077] The technical effect of the first embodiment of the present invention can be further illustrated by simulation experiments:

[0078] 1. Simulation conditions:

[0079] In the frequency band of 24 to 27 GHz, the present invention Figure 1 The circuit shown adopts the SMIC 40nm CMOS process model and is simulated using the Cadence simulation tool under the condition that the power supply voltage VDD is 1.1V.

[0080] 2. Simulation content:

[0081] See also Figure 7 Under the above conditions, the input matching of the circuit of the present invention is simulated and tested. The present invention achieves good input matching. At three temperatures in the simulation frequency band of 24 GHz to 27 GHz, S11 is less than -15 dB, which proves that good input impedance matching is achieved.

[0082] See also Figure 8Under the above conditions, the output matching of the circuit of the present invention was simulated and tested 2 times. The present invention achieved good output matching. At three temperatures in the simulation frequency band of 24 GHz to 27 GHz, S22 was less than -10 dB, proving that good output impedance matching was achieved.

[0083] See also Fig. 9 Under the above conditions, the gain of the circuit of the present invention is simulated and tested for 3 times. The present invention achieves good gain and has good broadband characteristics. The gain in the range of 24GHz to 27GHz is greater than 12dB at low temperature and room temperature, and the minimum gain is about 11.18dB at high temperature. The gain flatness is less than 1.5dB at three temperatures.

[0084] See also Fig.10 Under the above conditions, the noise coefficient of the circuit of the present invention is simulated and tested 4 times. The present invention achieves a relatively low noise coefficient, and the noise coefficients at three temperatures are all less than 7dB. The maximum value of the noise coefficient does not exceed 5.7dB, and the flatness of the noise coefficient within the frequency band is less than 1dB.

[0085] See also Fig.11 Under the above conditions, the stability factor of the circuit of the present invention was simulated and tested for 5 times. The simulation results show that the stability factor Kf within 24 GHz to 27 GHz at three temperatures is greater than 1, and the circuit is unconditionally stable.

[0086] See also Figure 6(a) to Figure 6(c) Under the above conditions, the 1dB compression point of the circuit of the present invention is simulated and tested 6 times, wherein the red line represents the ideal linear gain, the circuit has good linearity, the input 1dB compression points at room temperature (25°C) and high temperature (125°C) are both higher than -7dBm; the input 1dB compression point at low temperature (-40°C) is -7.082dBm.

[0087] The working principle of the present invention is as follows:

[0088] When the RF signal is input, the single-ended signal u is converted into se Converted into differential signal u diff , and achieve broadband impedance matching; the first-stage gain circuit 2 provides a larger gain for the low-noise amplifier as a whole and suppresses noise, achieving the differential signal u diff After processing, the gain differential signal u is obtained diff '; Symmetrical MCR inter-stage matching network 1b is used for signal transmission and broadband impedance matching between the first-stage gain circuit 2 and the second-stage linearization circuit 3, and converts the gain differential signal u diff' Converted to single-ended signal u se 'Input to the second-stage linearization circuit 3; the second-stage linearization circuit 3 is used to improve the linearity of the signal and the single-ended signal use 'Apply a certain gain to obtain the signal u se "; The output broadband transformer network 1c performs broadband impedance matching to match the output impedance to the load impedance and at the same time se ” is converted into RF output signal u se ”' and output it.

Claims

1. A millimeter-wave broadband high-gain low-noise amplifier based on CMOS technology, characterized in that: The invention comprises an input broadband balun transformer network (1a), a first-stage gain circuit (2), a symmetrical MCR inter-stage matching network (1b), a second-stage linearization circuit (3), and an output broadband transformer network (1c); wherein the input broadband balun transformer network (1a) is used to convert a radio frequency signal from a single-ended signal u se Converted into differential signal u diff , and realize broadband impedance matching; the first-stage gain circuit (2) provides a large gain for the low-noise amplifier as a whole and suppresses noise, realizing the differential signal u diff After processing, the gain differential signal u is obtained diff The symmetrical MCR inter-stage matching network (1b) is used for signal transmission and broadband impedance matching between the first-stage gain circuit (2) and the second-stage linearization circuit (3), and converts the gain differential signal u diff 'Convert to single-ended signal u se ' and input to the circuit of the second-stage linearization circuit (3); the second-stage linearization circuit (3) is used to improve the linearity of the signal and at the same time to the single-ended signal u se 'Apply a certain gain to obtain the signal u se "; The output broadband transformer network (1c) performs broadband impedance matching and matches the output impedance to the load impedance, while the signal u se ” is converted into RF output signal u se ”' and output it.

2. The high-gain low-noise amplifier according to claim 1, characterized in that: The input broadband balun transformer network (1a) comprises a first capacitor C1, a first transformer primary coil Ta1, a first transformer secondary coil Ta2, and a second capacitor C2; a radio frequency signal input end is connected to one end of a parallel network consisting of the first capacitor C1 and the first transformer primary coil Ta1, and the other end of the parallel network consisting of the first capacitor C1 and the first transformer primary coil Ta1 is grounded; one end of the first transformer secondary coil Ta2 is respectively connected to the first end of the second capacitor C2 and the first end of the first impedance tuning inductor L1A in the first-stage gain circuit (2), and the other end of the first transformer secondary coil Ta2 is respectively connected to the second end of the second capacitor C2 and the first end of the second impedance tuning inductor L1B in the first-stage gain circuit (2), and the middle tap of the first transformer secondary coil Ta2 is connected to a bias voltage VDC; the first transformer primary coil Ta1 is magnetically coupled to the first transformer secondary coil Ta2.

3. The high-gain low-noise amplifier according to claim 1, characterized in that: The first-stage gain circuit (2) is used to achieve the gain output of the input signal and lower signal noise, and comprises a first impedance tuning inductor L1A, a second impedance tuning inductor L1B, a first source degeneration inductor L2A, a second source degeneration inductor L2B and a differential common-source amplifier with a neutralizing capacitor, wherein the differential common-source amplifier with a neutralizing capacitor is composed of a first MOS transistor M1A, a second MOS transistor M1B, a first neutralizing capacitor C3A and a second neutralizing capacitor C3B, and a bias voltage VDC is supplied from the middle tap of the secondary winding Ta2 of the first transformer to the gate of the first MOS transistor M1A, and the gate of the first MOS transistor M1A is connected to the second end of the first impedance tuning inductor L1A, and the source of the first MOS transistor M1A is connected to the second end of the first source degeneration inductor L2A; The first end of the first source degeneration inductor L2A and the first end of the second source degeneration inductor L2B are connected and grounded together; the bias voltage VDC is supplied from the middle tap of the secondary winding Ta2 of the first transformer to the gate of the second MOS transistor M1B, and the gate of the second MOS transistor M1B is connected to the second end of the second impedance tuning inductor L1B, and the source of the second MOS transistor M1B is connected to the second end of the second source degeneration inductor L2B; the first end of the first neutralization capacitor C3A is connected to the gate of the first MOS transistor M1A, and the second end of the first neutralization capacitor C3A is connected to the drain of the second MOS transistor M1B; the first end of the second neutralization capacitor C3B is connected to the gate of the second MOS transistor M1B, and the second end of the second neutralization capacitor C3B is connected to the drain of the first MOS transistor M1A.

4. The high-gain low-noise amplifier according to claim 1, characterized in that: The symmetrical MCR inter-stage matching network (1b) comprises a third capacitor C4A, a fourth capacitor C4B, a second transformer primary coil Tb1 and a second transformer secondary coil Tb2; the first end of the third capacitor C4A is respectively connected to the drain of the first MOS transistor M1A and the first end of the second transformer primary coil Tb1, the second end of the third capacitor C4A is connected to the second end of the fourth capacitor C4B, the first end of the fourth capacitor C4B is respectively connected to the drain of the second MOS transistor M1B and the second end of the second transformer primary coil Tb1, and the middle tap of the second transformer primary coil Tb1 is connected to the power supply voltage VDD; the first end of the second transformer secondary coil Tb2 is connected to the input end of the second-stage linearization circuit (3), and the second end of the second transformer secondary coil Tb2 is connected to the bias voltage VB1; the second transformer primary coil Tb1 is magnetically coupled to the second transformer secondary coil Tb2.

5. The high-gain low-noise amplifier according to claim 1, characterized in that: The second-stage linearization circuit (3) comprises a third MOS tube M2, a third source degeneration inductor L3, a fifth capacitor C5, a first resistor R1, a fourth MOS tube M3, and a fourth source degeneration inductor L4; the gate of the third MOS tube M2 is respectively connected to the first end of the second transformer secondary coil Tb2 and the first end of the fifth capacitor C5, the drain of the third MOS tube M2 is connected to the input end of the output broadband transformer network (1c), the source of the third MOS tube M2 is connected to the first end of the third source degeneration inductor L3, and the second end of the third source degeneration inductor L3 is grounded; the gate of the fourth MOS tube M3 is respectively connected to the second end of the fifth capacitor C5 and the first end of the first resistor R1, the drain of the fourth MOS tube M3 is connected to the input end of the output broadband transformer network (1c), the source of the fourth MOS tube M3 is connected to the first end of the fourth source degeneration inductor L4, and the second end of the fourth source degeneration inductor L4 is grounded; the second end of the first resistor R1 is connected to the bias voltage VB2.

6. The high-gain low-noise amplifier according to claim 1, characterized in that: The output broadband transformer network (1c) comprises a sixth capacitor C6, a third transformer primary coil Tc1, a third transformer secondary coil Tc2, and a seventh capacitor C7; the first end of the sixth capacitor C6 is respectively connected to the drain of the third MOS transistor M2, the drain of the fourth MOS transistor M3, and the first end of the third transformer primary coil Tc1, and the second end of the sixth capacitor C6 is grounded; the second end of the third transformer primary coil Tc1 is connected to the power supply voltage VDD; the first end of the third transformer secondary coil Tc2 is respectively connected to the first end of the seventh capacitor C7 and the radio frequency signal output port, the second end of the third transformer secondary coil Tc2 is connected to the second end of the seventh capacitor C7, and the second end of the third transformer secondary coil Tc2 is grounded; the third transformer primary coil Tc1 is magnetically coupled to the third transformer secondary coil Tc2.

7. The high-gain low-noise amplifier according to claim 1, characterized in that: The input broadband balun transformer network (1a), the symmetrical MCR inter-stage matching network (1b), and the output broadband transformer network (1c) all use an MCR-based broadband impedance matching method to calculate the corresponding initial inductance values ​​and capacitance values, and the matching network is designed through iterative optimization.

8. The high-gain low-noise amplifier according to claim 3, characterized in that: The first source degeneration inductor L2A and the second source degeneration inductor L2B in the first-stage gain circuit (2) are combined into one inductor in the layout drawing and the middle tap is grounded, and the drawing adopts the scheme of figure 8 inductor.

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