A clock control circuit, a power supply control circuit, and an integrated circuit with high anti-interference ability

Abstract

The present invention relates to the technical field of clock control, and discloses a clock control circuit, a power supply control circuit and an integrated circuit with high anti-interference performance. The clock control circuit includes a voltage detection unit, a NOR gate, an AND gate, a plurality of serially connected TFF flip-flops, a latch LAT and an OR gate; in actual use, the present invention detects the fluctuation of the power supply voltage through the voltage detection unit. When the power supply voltage changes upward or downward, the changed high-voltage detection signal or low-voltage detection signal will cause the latch LAT to stop outputting the clock signal through the serially connected TFF flip-flops. After the power supply voltage returns to normal, the serially connected TFF flip-flops will cause the latch LAT to continue outputting the clock signal after timing, so as to avoid generating abnormal clock signals by stopping the clock signal when the power supply voltage is abnormal, thereby improving the anti-interference performance of the clock control circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of clock control, and particularly relates to a clock control circuit, a power supply control circuit and an integrated circuit with high anti-interference ability. Background Art

[0002] In an integrated circuit system, the stability of the clock signal is crucial for the reliable operation of the integrated circuit system. The stability of the clock signal is related to the power supply voltage. The more stable the power supply voltage is, the more stable the clock signal is.

[0003] Currently, most of the interference elimination is achieved by filtering the power supply voltage through a filter circuit. However, when there is a large-amplitude high-frequency interference in the power supply voltage of the circuit system, the filter circuit itself will also be affected by the voltage fluctuation and generate glitch signals, and the generated glitch signals will also affect the stability of the clock signal.

[0004] In the existing circuit system, the anti-interference ability of the circuit system in the sleep state is very strong. At this time, the clock is stopped, and the logic circuit that determines the operating state of the circuit system is composed of a large number of flip-flops, latches and gate circuits;

[0005] Among them, the flip-flop and the latch itself have a built-in latch structure and have strong anti-interference ability. As long as the states of the flip-flop and the latch are not affected by interference, the output result of the combinational logic gate circuit will not change;

[0006] In addition, the flip-flop and the latch are clock-sensitive circuits and have certain requirements for the setup time and hold time of the input. Therefore, the clock cannot have glitches and unstable jitters. Summary of the Invention

[0007] In view of the deficiencies of the background art, the present invention provides a clock control circuit, a power supply control circuit and an integrated circuit with high anti-interference ability. The technical problem to be solved is that the clock in the existing integrated circuit system has glitches due to the influence of power supply voltage fluctuations.

[0008] To solve the above technical problems, in the first aspect, the present invention provides the following technical solution: A clock control circuit with high anti-interference ability, comprising:

[0009] A voltage detection unit that generates a high-voltage detection signal and a low-voltage detection signal based on the change of the power supply voltage;

[0010] A NOR gate for performing a NOR operation on the high-voltage detection signal and the low-voltage detection signal;

[0011] An AND gate, one input terminal of which is electrically connected to the output terminal of the NOR gate, and the other input terminal is used for inputting a reset signal;

[0012] Multiple cascaded TFF flip - flops, where the cascading means that the QN output terminal of the previous - stage TFF flip - flop is electrically connected to the clock terminal of the next - stage TFF flip - flop; the output terminal of the AND gate is electrically connected to the reset terminal of each TFF flip - flop;

[0013] The Q output terminal of the last TFF flip - flop is respectively electrically connected to the clock terminal of the latch LAT and one input terminal of the OR gate, for outputting the latch control signal CLK_LAT;

[0014] The other input terminal of the OR gate and the D input terminal of the latch LAT are used for inputting the clock signal CLKIN.

[0015] In a certain implementation manner of the first aspect, the number of cascaded TFF flip - flops is four.

[0016] In a certain implementation manner of the first aspect, the voltage detection unit includes a resistor R1, a capacitor C1, a first inverter, and a second inverter;

[0017] One end of the resistor R1, the power supply terminal of the first inverter, and the input terminal of the second inverter are respectively used for inputting the power supply voltage. The other end of the resistor R1 is electrically connected to the input terminal of the first inverter and the power supply terminal of the second inverter, and is grounded through the capacitor C1;

[0018] The output terminal of the first inverter is used for outputting the high - voltage detection signal, and the output terminal of the second inverter is used for outputting the low - voltage detection signal.

[0019] In a certain implementation manner of the first aspect, the first inverter includes a MOS transistor P1 and a MOS transistor N1. The source of the MOS transistor P1 is the power supply terminal of the first inverter. The drain of the MOS transistor P1 is electrically connected to the drain of the MOS transistor N1, which is the output terminal of the first inverter. The gate of the MOS transistor P1 is electrically connected to the gate of the MOS transistor N1, which is the input terminal of the first inverter. The source of the MOS transistor N1 is grounded;

[0020] The second inverter includes a MOS transistor P2 and a MOS transistor N2. The source of the MOS transistor P2 is the power supply terminal of the second inverter. The drain of the MOS transistor P2 is electrically connected to the drain of the MOS transistor N2, which is the output terminal of the second inverter. The gate of the MOS transistor P2 is electrically connected to the gate of the MOS transistor N2, which is the input terminal of the second inverter. The source of the MOS transistor N2 is grounded.

[0021] In a certain implementation manner of the first aspect, the size of the MOS transistor P1 is the same as the size of the MOS transistor P2, and the size of the MOS transistor N1 is the same as the size of the MOS transistor N2.

[0022] In a certain implementation manner of the first aspect, the width - to - length ratio of the MOS transistor P1 is greater than the width - to - length ratio of the MOS transistor N1.

[0023] In a certain implementation of the first aspect, the sizes of the resistor R1, capacitor C1, MOS transistor P1, MOS transistor N1, MOS transistor P2, and MOS transistor N2 are adjustable to match different detection sensitivities.

[0024] In a second aspect, the present invention provides a power control circuit, which includes the above-mentioned high anti-interference clock control circuit, and also includes a transmission gate, a resistor R2, and a capacitor C2. One end of the resistor R2 and the input end of the transmission gate are respectively used to input the power supply voltage. The other end of the resistor R2 is electrically connected to the output end of the transmission gate and one end of the capacitor C2, and the other end of the capacitor C2 is grounded;

[0025] One control end of the transmission gate inputs the latch control signal CLK_LAT, and the other control end inputs the transmission control signal CLK_LAT_N, and the latch control signal CLK_LAT and the transmission control signal are two opposite signals;

[0026] The transmission gate is turned on when the latch control signal CLK_LAT is at a high level and turned off when the latch control signal CLK_LAT is at a low level.

[0027] In a certain implementation of the second aspect, the transmission gate includes a MOS transistor P3 and a MOS transistor N3. The source electrode of the MOS transistor P3 is electrically connected to the drain electrode of the MOS transistor N3, which is the input end of the transmission gate. The drain electrode of the MOS transistor P3 is electrically connected to the source electrode of the MOS transistor N3, which is the output end of the transmission gate. The gate electrode of the MOS transistor N3 is used to input the latch control signal CLK_LAT, and the gate electrode of the MOS transistor P3 is used to input the transmission control signal CLK_LAT_N.

[0028] In a third aspect, the present invention provides an integrated circuit, which includes the above-mentioned power control circuit, and also includes a digital circuit. The output end of the transmission gate is electrically connected to the digital circuit to provide a working voltage for the digital circuit, and the Q output end of the latch LAT is electrically connected to the digital circuit to provide an output clock CLKOUT for the digital circuit.

[0029] The beneficial effects of the present invention compared with the prior art are as follows: In actual use, the present invention detects the fluctuation of the power supply voltage through the voltage detection unit. When the power supply voltage changes upward or downward, the changed high-voltage detection signal or low-voltage detection signal will cause the latch LAT to stop outputting the clock signal through the series-connected TFF flip-flops. When the power supply voltage returns to normal, the series-connected TFF flip-flops will cause the latch LAT to continue to output the clock signal after timing, so as to avoid generating abnormal clock signals by stopping the clock signal when the power supply voltage is abnormal, thereby improving the anti-interference ability of the clock control circuit. Description of the Drawings

[0030] Figure 1 It is a schematic structural diagram of the present invention in Embodiment 1;

[0031] Figure 2 It is a circuit diagram of the voltage detection unit in Embodiment 1;

[0032] Figure 3 It is a relevant signal waveform diagram of the clock control circuit when the power supply voltage is normal;

[0033] Figure 4 It is a relevant signal waveform diagram of the clock control circuit when the power supply voltage is abnormally high;

[0034] Figure 5 It is a relevant signal waveform diagram of the clock control circuit when the power supply voltage is abnormally low;

[0035] Figure 6 It is a circuit diagram of resistor R2, capacitor C2 and transmission gate in Embodiment 2;

[0036] Figure 7 It is a schematic structural diagram of the integrated circuit in Embodiment 3. Detailed Embodiments

[0037] Now, the present invention will be further described in detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present invention in a schematic manner, so they only show the components related to the present invention.

[0038] Embodiment 1

[0039] As Figure 1 shown, a clock control circuit with high anti-interference includes:

[0040] A voltage detection unit 1 that generates a high-voltage detection signal and a low-voltage detection signal based on the change of the power supply voltage VDD;

[0041] A NOR gate NOR1 for performing NOR processing on the high-voltage detection signal and the low-voltage detection signal;

[0042] An AND gate AND1, one input terminal is electrically connected to the output terminal of the NOR gate NOR1, and the other input terminal is used to input a reset signal RST_N;

[0043] Multiple serially connected TFF flip-flops, serially connected such that the QN output terminal of the previous-stage TFF flip-flop is electrically connected to the clock terminal of the next-stage TFF flip-flop; the output terminal of the AND gate AND1 is electrically connected to the reset terminal of each TFF flip-flop;

[0044] The Q output terminals of the terminal TFF flip-flops are respectively electrically connected to the clock terminal of the latch LAT and one input terminal of the OR gate OR1, and are used to output a latch control signal CLK_LAT;

[0045] The other input terminal of the OR gate OR1 and the D input terminal of the latch LAT are used to input a clock signal CLKIN.

[0046] In actual use, the present invention uses the voltage detection unit 1 to detect the fluctuation of the power supply voltage VDD. When the power supply voltage VDD changes upward or downward, the changed high-voltage detection signal or low-voltage detection signal will cause the latch LAT to stop outputting the clock signal CLKIN through the series-connected TFF flip-flops. When the power supply voltage VDD returns to normal, the series-connected TFF flip-flops will cause the latch LAT to continue outputting the clock signal after timing, so as to avoid generating abnormal clock signals by stopping the clock signal CLKIN when the power supply voltage VDD is abnormal, thereby improving the anti-interference ability of the clock control circuit.

[0047] Specifically, in this embodiment, the number of series-connected TFF flip-flops is four. In a certain implementation manner, the number of the remaining TFF flip-flops can be set to set different durations of the clock signal recovery time.

[0048] Specifically, in this embodiment, as Figure 2 shown, the voltage detection unit 1 includes a resistor R1, a capacitor C1, a first inverter 10, and a second inverter 11;

[0049] One end of the resistor R1, the power supply terminal of the first inverter 10, and the input terminal of the second inverter 11 are respectively used to input the power supply voltage VDD. The other end of the resistor R1 is respectively electrically connected to the input terminal of the first inverter 10 and the power supply terminal of the second inverter 11, and is grounded through the capacitor C1;

[0050] The output terminal of the first inverter 10 is used to output a high-voltage detection signal, and the output terminal of the second inverter 11 is used to output a low-voltage detection signal.

[0051] More specifically, in Figure 1 it, the first inverter 10 includes a MOS transistor P1 and a MOS transistor N1. The source electrode of the MOS transistor P1 is the power supply terminal of the first inverter 10. The drain electrode of the MOS transistor P1 is electrically connected to the drain electrode of the MOS transistor N1, which is the output terminal of the first inverter 10. The gate electrode of the MOS transistor P1 is electrically connected to the gate electrode of the MOS transistor N1, which is the input terminal of the first inverter 10. The source electrode of the MOS transistor N1 is grounded;

[0052] The second inverter 11 includes MOS transistor P2 and MOS transistor N2. The source of MOS transistor P2 is the power supply terminal of the second inverter 11. The drain of MOS transistor P2 is electrically connected to the drain of MOS transistor N2, which is the output terminal of the second inverter 11. The gate of MOS transistor P2 is electrically connected to the gate of MOS transistor N2, which is the input terminal of the second inverter 11. The source of MOS transistor N2 is grounded.

[0053] Among them, the size of MOS transistor P1 is the same as that of MOS transistor P2, and the size of MOS transistor N1 is the same as that of MOS transistor N2. In addition, the width-to-length ratio of MOS transistor P1 is greater than that of MOS transistor N1.

[0054] Exemplarily, the widths of MOS transistor P1 and MOS transistor P2 can be 5um, the lengths of MOS transistor P1 and MOS transistor P2 are 1um, and they are both PMOS transistors;

[0055] The widths of MOS transistor N1 and MOS transistor N2 can be 1um, the lengths of MOS transistor N1 and MOS transistor N2 are 20um, and they are both NMOS transistors;

[0056] In addition, the resistance value of resistor R1 can be 5000Ω, and the capacitance value of capacitor C1 is 10pf.

[0057] Specifically, in this embodiment, the sizes of resistor R1, capacitor C1, MOS transistor P1, MOS transistor N1, MOS transistor P2, and MOS transistor N2 are adjustable to match different detection sensitivities, where the detection sensitivity refers to the change trend of the power supply voltage VDD that can be detected.

[0058] For Figure 1 and Figure 2 the circuit shown is analyzed as follows:

[0059] First is the voltage detection unit 1, and its working process is as follows:

[0060] According to the MOS transistor source-drain on-resistance formula , where u is the majority carrier mobility, Cox is the MOS transistor gate oxide capacitance, and Vth is the MOS transistor threshold voltage, all of which are only related to the process; when the source-drain voltage Vgs is fixed, the larger the width-to-length ratio W / L, the smaller the on-resistance Ron, and vice versa Ron is larger.

[0061] Since the power supply voltage VDD passes through a relatively large resistor R1 and capacitor C1 to generate voltage VDDR, the voltage VDDR and the power supply voltage VDD enable the two first inverters 10 and the second inverter 11 to detect the power supply voltage rise and the power supply voltage drop through different connection methods. The first inverter 10 outputs a high-voltage detection signal, and the second inverter 11 outputs a low-voltage detection signal;

[0062] MOS transistors P1 and P2 are PMOS transistors with a large W / L (width-to-length ratio), and MOS transistors N1 and N2 are NMOS transistors with a small W / L. When the W / L is large, the MOS transistor has a strong conduction ability and a small impedance; when the W / L is small, the MOS transistor has a weak conduction ability and a large impedance. Therefore, the conduction abilities of MOS transistors P1 and P2 are stronger than those of MOS transistors N1 and N2;

[0063] When the power supply voltage VDD is stable or changes slowly, the first inverter 10 and the second inverter 11 output low-level signals, that is, both the high-voltage detection signal and the low-voltage detection signal are low level;

[0064] When the power supply voltage VDD rises rapidly, there will be a delay in the voltage VDDR due to the RC resistor-capacitor output. The voltage VDDR rises more slowly than the power supply voltage VDD. At this time, when the power supply voltage VDD is greater than the turn-on voltage Vt of a MOS transistor P1 by one MOS transistor P1, the MOS transistor P1 conducts, and the impedance of the MOS transistor P1 is much smaller than that of the MOS transistor N1. At this time, a pulse signal will be generated for the high-voltage detection signal;

[0065] When the power supply voltage VDD drops rapidly, there will be a delay in the voltage VDDR due to the RC resistor-capacitor output. The voltage VDDR drops more slowly than the power supply voltage VDD. At this time, when the voltage VDDR is greater than the power supply voltage VDD by the turn-on voltage Vt of a MOS transistor P2, the MOS transistor P2 conducts, and the impedance of the MOS transistor P2 is much smaller than that of the MOS transistor N2. At this time, a pulse signal will be generated for the low-voltage detection signal.

[0066] In a certain implementation, other circuits that output a pulse signal according to the difference between the power supply voltage VDD and the voltage VDDR when the power supply voltage VDD changes to indicate that the power supply voltage VDD changes too fast can also be understood as the first inverter 10 or the second inverter 11 in the present invention.

[0067] For components such as TFF flip-flops, the specific process is as follows:

[0068] During normal operation:

[0069] When the reset signal RST_N is at a low level, the circuit is in a reset state, the latch control signal CLK_LAT is at a low level, the latch LAT is in a closed state, and the output clock CLKOUT does not change with the clock signal CLKIN;

[0070] When the reset signal RST_N is released to high, after the TFF flip-flop receives 8 clocks through the clock signal CLKIN, the latch control signal CLK_LAT becomes high, the latch LAT is opened, the output clock CLKOUT follows the change of the clock signal CLKIN, and the clock is normally output. At the same time, the latch control signal CLK_LAT shields the clock input of the first-stage TFF flip-flop through the OR gate OR1, so that the TFF flip-flop stops counting. At this time, the latch control signal CLK_LAT remains high; at this time, the timing diagram of the power supply voltage VDD without interference is as Figure 3 shown.

[0071] When there is high-frequency interference in the power supply voltage VDD:

[0072] If there is a rapid drop or rise in the power supply voltage VDD, the high-voltage detection signal or low-voltage detection signal output by the voltage detection unit 1 will generate a short pulse. The pulse signal passes through the NOR gate NOR1 and performs an AND operation with the AND gate AND1 connected to the reset signal RST_N, so that the AND gate AND1 outputs a short low level. The short low level resets the TFF flip-flop, and the latch control signal CLK_LAT is reset to low. At this time, the latch LAT is closed and the output clock CLKOUT stops outputting, and the output clock CLKOUT will maintain the current level;

[0073] At the same time, the clock control of the first stage of the TFF flip-flop is released (CLK_LAT = 0); when the power supply voltage VDD returns to stability, the reset signal of the TFF flip-flop will be released. After the TFF flip-flop receives 8 clocks through the clock signal CLKIN, the latch control signal CLK_LAT becomes high, the latch LAT is opened, the output clock CLKOUT follows the change of the clock signal CLKIN, and the clock is normally output; at the same time, the latch control signal CLK_LAT shields the clock input of the first-stage TFF flip-flop through the OR gate OR1 so that the TFF flip-flop stops counting. At this time, the latch control signal CLK_LAT always remains high; among them, the timing diagram of the power supply voltage VDD rising interference is as Figure 4 shown, and the timing diagram of the power supply voltage VDD falling interference is as Figure 5 shown.

[0074] Embodiment 2

[0075] This embodiment provides a power control circuit, including the above-mentioned high-immunity clock control circuit, as Figure 6 shown, and also includes a transmission gate TG1, a resistor R2, and a capacitor C2. One end of the resistor R2 and the input end of the transmission gate TG1 are respectively used to input the power supply voltage VDD. The other end of the resistor R2 is electrically connected to the output end of the transmission gate TG1 and one end of the capacitor C2 respectively, and the other end of the capacitor C2 is grounded;

[0076] One control terminal of the transmission gate TG1 inputs the latch control signal CLK_LAT, and the other control terminal inputs the transmission control signal CLK_LAT_N. The latch control signal CLK_LAT and the transmission control signal CLK_LAT_N are two opposite signals. Among them, the latch control signal CLK_LAT outputs the transmission control signal CLK_LAT_N through an inverter.

[0077] The transmission gate TG1 is turned on when the latch control signal CLK_LAT is at a high level and turned off when the latch control signal CLK_LAT is at a low level.

[0078] Specifically, in Figure 6 , the transmission gate TG1 includes the MOS transistor P3 and the MOS transistor N3. The source of the MOS transistor P3 and the drain of the MOS transistor N3 are electrically connected as the input terminal of the transmission gate TG1. The drain of the MOS transistor P3 and the source of the MOS transistor N3 are electrically connected as the output terminal of the transmission gate TG1. The gate of the MOS transistor N3 is used to input the latch control signal CLK_LAT, and the gate of the MOS transistor P3 is used to input the transmission control signal CLK_LAT_N.

[0079] In this embodiment, the MOS transistor P3 can be a PMOS transistor with a width of 200um and a length of 0.6um. The MOS transistor N3 can be an NMOS transistor with a width of 100um and a length of 0.6um. The resistance value of the resistor R2 can be 1000Ω, and the capacitance value of the capacitor C2 can be 100pf.

[0080] For Figure 6 circuit analysis, it is as follows:

[0081] During normal operation:

[0082] The latch control signal CLK_LAT is at a high level, the transmission control signal CLK_LAT_N is at a low level, the transmission gate TG1 is in an on state, and the W / L ratio is very large and the on-resistance is very small. Therefore, the voltage DVDD is approximately generated by the power supply voltage VDD through a very small resistor, and the voltage DVDD during operation is approximately equal to the power supply voltage VDD.

[0083] When there is high-frequency interference in the power supply voltage VDD:

[0084] The latch control signal CLK_LAT is at a low level, the transmission control signal CLK_LAT_N is at a high level, and the transmission gate TG1 is in a closed state;

[0085] The power supply voltage VDD will generate the voltage DVDD through the resistor R2. Due to the RC filter composed of the resistor R2 and the capacitor C2, the high-frequency interference on the power supply voltage VDD will be filtered to obtain the voltage DVDD.

[0086] Embodiment 3

[0087] As Figure 7 shown, this embodiment provides an integrated circuit, which includes the power control circuit in Embodiment 2, and further includes a digital circuit 3. The output end of the transmission gate TG1 is electrically connected to the digital circuit 3 to provide a working voltage for the digital circuit 3. The Q output end of the latch LAT is electrically connected to the digital circuit 3 to provide an output clock CLKOUT for the digital circuit.

[0088] In actual use, when the power supply voltage VDD is normal, the transmission gate TG1 is turned on, and the voltage DVDD is input to the digital circuit 3 for power supply. The output clock CLKOUT is input to the digital circuit 3, and the digital circuit 3 works normally.

[0089] When the power supply voltage VDD is abnormal, the output clock CLKOUT stops outputting, and the digital circuit 3 stops working. The power consumption is approximately 0. Therefore, there will be no voltage drop between the voltage DVDD and the power supply voltage VDD, and the voltage DVDD of the digital circuit 4 can be kept clean and stable. The timing circuit in the digital circuit 4 is improved in anti-interference and maintains the current state. When the interference of the power supply voltage VDD disappears, the transmission gate TG1 will be turned on again, and the voltage DVDD obtains a stronger driving ability to continue to supply power to the digital circuit 3. The output clock CLKOUT starts the digital circuit 3, and the digital circuit 3 continues to work from the state maintained before.

[0090] In addition, it should be noted that the digital circuit 3 is an existing digital circuit and does not involve the inventive point of this application.

[0091] Based on the inspiration of the present invention, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A clock control circuit with high noise immunity, characterized in that: include: A voltage detection unit, generating a high voltage detection signal and a low voltage detection signal based on a change in a power supply voltage; A NOR gate, used for performing NOR processing on the high voltage detection signal and the low voltage detection signal; An AND gate, one input end of which is electrically connected to the output end of the NOR gate, and the other input end of which is used to input a reset signal; A plurality of TFF triggers connected in series, wherein the series connection is that the QN output end of the preceding TFF trigger is electrically connected to the clock end of the succeeding TFF trigger; the output end of the AND gate is electrically connected to the reset end of each TFF trigger; The Q output terminal of the terminal TFF trigger is electrically connected to the clock terminal of the latch LAT and an input terminal of the OR gate respectively, and is used to output a latch control signal CLK_LAT; The other input terminal of the OR gate and the D input terminal of the latch LAT are used to input the clock signal CLKIN; The voltage detection unit includes a resistor R1, a capacitor C1, a first inverter and a second inverter; One end of the resistor R1, the power supply end of the first inverter and the input end of the second inverter are respectively used to input the power supply voltage, and the other end of the resistor R1 is respectively electrically connected to the input end of the first inverter and the power supply end of the second inverter, and is grounded through the capacitor C1; The output end of the first inverter is used to output the high voltage detection signal, and the output end of the second inverter is used to output the low voltage detection signal.

2. The clock control circuit with high noise immunity according to claim 1, characterized in that: The number of TFF flip-flops connected in series is four.

3. The clock control circuit with high noise immunity according to claim 1, characterized in that: The first inverter comprises a MOS transistor P1 and a MOS transistor N1, the source of the MOS transistor P1 is the power supply terminal of the first inverter, the drain of the MOS transistor P1 is electrically connected to the drain of the MOS transistor N1 and is the output terminal of the first inverter, the gate of the MOS transistor P1 is electrically connected to the gate of the MOS transistor N1 and is the input terminal of the first inverter, and the source of the MOS transistor N1 is grounded; The second inverter includes a MOS transistor P2 and a MOS transistor N2. The source of the MOS transistor P2 is the power supply terminal of the second inverter. The drain of the MOS transistor P2 is electrically connected to the drain of the MOS transistor N2 and is the output terminal of the second inverter. The gate of the MOS transistor P2 is electrically connected to the gate of the MOS transistor N2 and is the input terminal of the second inverter. The source of the MOS transistor N2 is grounded.

4. The clock control circuit with high noise immunity according to claim 3, characterized in that: The size of the MOS transistor P1 is the same as that of the MOS transistor P2, and the size of the MOS transistor N1 is the same as that of the MOS transistor N2.

5. The clock control circuit with high noise immunity according to claim 4, characterized in that: The width-to-length ratio of the MOS transistor P1 is greater than the width-to-length ratio of the MOS transistor N1.

6. The clock control circuit with high noise immunity according to claim 5, characterized in that: The sizes of the resistor R1 , the capacitor C1 , the MOS transistor P1 , the MOS transistor N1 , the MOS transistor P2 , and the MOS transistor N2 are adjustable to match different detection sensitivities.

7. A power supply control circuit, characterized in that it comprises the high-interference-immunity clock control circuit according to any one of claims 1 to 6, and further comprises a transmission gate, a resistor R2 and a capacitor C2, wherein one end of the resistor R2 and the input end of the transmission gate are respectively used to input the power supply voltage, the other end of the resistor R2 is respectively electrically connected to the output end of the transmission gate and one end of the capacitor C2, and the other end of the capacitor C2 is grounded; One control terminal of the transmission gate inputs the latch control signal CLK_LAT, and the other control terminal inputs the transmission control signal CLK_LAT_N, wherein the latch control signal CLK_LAT and the transmission control signal CLK_LAT_N are two opposite signals; The transmission gate is turned on when the latch control signal CLK_LAT is at a high level, and is turned off when the latch control signal CLK_LAT is at a low level.

8. A power control circuit according to claim 7, characterized in that: The transmission gate includes a MOS transistor P3 and a MOS transistor N3. The source of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N3, which is the input end of the transmission gate. The drain of the MOS transistor P3 is electrically connected to the source of the MOS transistor N3, which is the output end of the transmission gate. The gate of the MOS transistor N3 is used to input the latch control signal CLK_LAT, and the gate of the MOS transistor P3 is used to input the transmission control signal CLK_LAT_N.

9. An integrated circuit, characterized in that: The power control circuit comprises the power control circuit as claimed in claim 7 or 8, and further comprises a digital circuit, wherein the output end of the transmission gate is electrically connected to the digital circuit to provide an operating voltage for the digital circuit, and the Q output end of the latch LAT is electrically connected to the digital circuit to provide an output clock CLKOUT for the digital circuit.

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