Driving signal acquisition module and vehicle

Abstract

The invention provides a driving signal acquisition module and a vehicle, and belongs to the technical field of electronics, and the driving signal acquisition module outputs a driving signal to a load through a driving circuit according to a first PWM signal; the pulse width modulation (PWM) circuit outputs a first PWM signal, and the signal delay circuit is used for performing delay processing on the input first PWM signal to generate a second PWM signal; and finally, the signal acquisition assembly acquires the driving signal under the condition that the second PWM signal is input.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and in particular, relates to a driving signal acquisition module and a vehicle. Background Art

[0002] At present, current detection is widely used in automotive electronic systems, such as at least one of a triode current detection circuit, a high-sensitivity current detection circuit, and a current feedback circuit. In the prior art, pulse width modulation (PWM) is generally used to excite the drive bridge drive circuit to control the load operation, and the signal acquisition component set in the chip collects the current signal of the drive bridge drive circuit. In the related art, in order to ensure the accuracy of current acquisition, one or more PWM signals are generally added as the trigger source collected by the trigger signal acquisition component. In this way, for each additional motor, at least one additional PWM signal is required. When the number of motors increases and the application scenarios are complex, a large number of PWM signals need to be used additionally, and the limited PWM resources inside the chip cannot provide a sufficient number of PWM signals as a trigger source on the basis of providing a PWM signal with more data for driving the load, and thus cannot meet the current acquisition of multiple motors. Summary of the invention

[0003] The embodiments of the present application provide a drive signal acquisition module and a vehicle, which are intended to solve the technical problem that the limited PWM resources inside the chip cannot meet the current acquisition needs of multiple motors.

[0004] A first aspect of an embodiment of the present application provides a drive signal acquisition module, comprising: a drive circuit, the drive circuit is used to output a drive signal to a load according to a first PWM signal; a control component, the control component includes a pulse width modulation PWM circuit, the PWM circuit is electrically connected to the drive circuit, and the PWM circuit is used to output the first PWM signal; a signal delay circuit, the first end of the signal delay circuit is electrically connected between the drive circuit and the PWM circuit, the signal delay circuit is used to delay the input first PWM signal to generate a second PWM signal; a signal acquisition component, the signal acquisition component is electrically connected to the drive circuit and the second end of the signal delay circuit, and the signal acquisition component is used to acquire the drive signal when the second PWM signal is input.

[0005] In one embodiment, the signal delay circuit includes a signal conversion element for performing delay processing on an input first PWM signal and then selecting a trigger request or an interrupt request to output a second PWM signal.

[0006] In one embodiment, the signal conversion element includes: a selection circuit, the selection circuit serving as the input end of the signal conversion element, for selecting an input first PWM signal; a logic circuit electrically connected to the selection circuit, for performing a logic operation on the first PWM signal; and a control circuit electrically connected to the logic circuit, for receiving the first PWM signal after the logic operation, and then selecting a trigger request or an interrupt request to output a second PWM signal.

[0007] In one embodiment, the signal conversion element further includes a connection matrix, which is electrically connected to the logic control circuit and the control circuit and is used to set a priority for the first PWM signal after the logic operation and then input it into the control circuit.

[0008] In one embodiment, the signal delay circuit includes an RC delay circuit; the delay time of the RC delay circuit is determined according to the following expression: T = RC,

[0009] Among them, T represents the delay time of the RC delay circuit, R represents the resistance in the RC delay circuit, and C represents the capacitance in the RC delay circuit.

[0010] In one embodiment, the driving signal acquisition module also includes a filtering module, a first end of the filtering module is electrically connected to the driving circuit; a second end of the filtering module is electrically connected to the signal acquisition module; and when the signal acquisition module acquires the driving circuit current signal, the filtering module first filters the current signal to be collected, and then outputs the filtered current signal to the signal acquisition module.

[0011] In one embodiment, the control component further includes: a timer; the timer is electrically connected to the first end of the PWM circuit, and is used to set the pulse signal generation time, triggering the PWM circuit to generate a first PWM signal to the delay circuit.

[0012] A second aspect of an embodiment of the present application provides a vehicle, the vehicle comprising a drive motor, the drive motor being driven according to a first PWM signal output by a drive circuit according to claim 1 .

[0013] A third aspect of an embodiment of the present application provides a trigger acquisition device, comprising the drive signal acquisition module of any one of claims 1 to 7.

[0014] A fourth aspect of an embodiment of the present application provides a storage medium storing a computer program for controlling the operation of the control component of claim 1.

[0015] The technical solution provided by the embodiment of the present application brings at least the following beneficial effects: the driving circuit outputs the driving signal to the load according to the first PWM signal; then the pulse width modulation PWM circuit outputs the first PWM signal, and the signal delay circuit is used to delay the input first PWM signal to generate a second PWM signal; finally, the signal acquisition component acquires the driving signal when the second PWM signal is input; the embodiment of the present application can convert the first PWM signal driving the load into the second PWM signal through the signal delay circuit, and the second PWM signal is used as the trigger source collected by the trigger signal acquisition component. On the one hand, through the delay of the signal delay circuit, a phase difference can be made between the first PWM signal and the second PWM signal, that is, the second PWM signal is later than the first PWM signal, so that when the second PWM signal triggers the trigger signal acquisition component to collect the driving signal, the load has been working stably, and thus a stable and accurate driving signal can be collected; on the other hand, the first PWM signal driving the load is converted into the second PWM signal through the signal delay circuit, and the second PWM signal is used as the trigger source collected by the trigger signal acquisition component, which is equivalent to reusing the delayed first PWM signal as the trigger source collected by the trigger signal acquisition component, so that there is no need to add one or more PWM signals as the trigger source collected by the trigger signal acquisition component, saving PWM resources. Therefore, compared with the prior art, when the number of motors increases and the application scenarios are complex, since the present application multiplexes the first PWM signal after delay (i.e., the second PWM signal) as the trigger source collected by the trigger signal acquisition component, or in other words, the first PWM signal is used to control the drive circuit to drive the load to work, and is also used as the trigger source collected by the trigger signal acquisition component after the delay, the number of PWM signals used in the present application can be reduced. Therefore, the limited PWM resources inside the chip can meet the driving needs of multiple motors and the current collection needs of multiple motors. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 It is a structural schematic diagram of a driving signal acquisition module provided in an embodiment of the present application;

[0018] Figure 2 This is a circuit principle diagram of a signal delay circuit provided by an embodiment of the present application;

[0019] Figure 3This is a structural schematic diagram of a signal conversion component provided by an embodiment of the present application;

[0020] Figure 4 is another principle schematic diagram of a signal conversion element provided in one embodiment of the present application;

[0021] Figure 5 This is a schematic diagram of a circuit principle of a driving circuit provided by an embodiment of the present application;

[0022] Figure 6 This is another circuit principle schematic diagram of a driving signal acquisition module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0024] See also Figure 1 , Figure 1 It is a structural schematic diagram of a driving signal acquisition module provided in one embodiment of the present application.

[0025] The first aspect of the embodiment of the present application provides a driving signal acquisition module, including: a driving circuit 11, the driving circuit 11 is used to output a driving signal to a load according to a first pulse width modulation (PWM) signal. A control component 21, the control component 21 includes a pulse width modulation PWM circuit, the PWM circuit is electrically connected to the driving circuit 11, and the PWM circuit is used to output a first PWM signal. A signal delay circuit 31, the first end of the signal delay circuit 31 is electrically connected between the driving circuit 11 and the PWM circuit, and the signal delay circuit 31 is used to delay the input first PWM signal to generate a second PWM signal. A signal acquisition component 41, the signal acquisition component 41 is electrically connected to the driving circuit 11 and the second end of the signal delay circuit 31, and the signal acquisition component 41 is used to collect the driving signal when the second PWM signal is input.

[0026] The technical solution provided by the embodiment of the present application brings at least the following beneficial effects: the driving circuit 11 outputs a driving signal to the load according to the first PWM signal. Then the pulse width modulation PWM circuit outputs the first PWM signal, and the signal delay circuit 31 is used to delay the input first PWM signal to generate a second PWM signal; finally, the signal acquisition component 41 acquires the driving signal when the second PWM signal is input. In the embodiment of the present application, a first PWM signal driving a load can be converted into a second PWM signal through a signal delay circuit, and the second PWM signal is used as a trigger source for collection by a trigger signal collection component. On the one hand, a phase difference can be made between the first PWM signal and the second PWM signal through the delay of the signal delay circuit, that is, the second PWM signal is later than the first PWM signal. In this way, when the second PWM signal triggers the trigger signal collection component to collect the driving signal, the load has been working stably, thereby ensuring that a stable and accurate driving signal is collected; on the other hand, the first PWM signal driving the load is converted into a second PWM signal through a signal delay circuit, and the second PWM signal is used as a trigger source for collection by the trigger signal collection component, which is equivalent to reusing the delayed first PWM signal as the trigger source for collection by the trigger signal collection component. In this way, there is no need to add one or more additional PWM signals as trigger sources for collection by the trigger signal collection component, thereby saving PWM resources. Therefore, compared with the prior art, when the number of motors increases and the application scenarios are complex, since the present application multiplexes the first PWM signal after delay (i.e., the second PWM signal) as the trigger source collected by the trigger signal acquisition component, or in other words, the first PWM signal is used to control the drive circuit to drive the load to work, and is also used as the trigger source collected by the trigger signal acquisition component after the delay, the number of PWM signals used in the present application can be reduced. Therefore, the limited PWM resources inside the chip can meet the driving needs of multiple motors and the current collection needs of multiple motors.

[0027] In this embodiment, the drive circuit 11 may be an H-bridge drive circuit 11, and the H-bridge drive circuit 11 includes an H-bridge drive circuit 11 composed of multiple groups of switch components. The specific H-bridge drive circuit 11 combines the switch components according to the load usage. For example, when the load uses a three-phase motor 12, the H-bridge drive circuit 11 can be provided with three groups of switch components, and each group of switch components includes any one or two of the three types of switch components, two IGBTs, triodes, and field effect transistors, which are connected in series.

[0028] In this embodiment, the switch element is any one or more of IGBT, triode, and field effect transistor, and the switch element can be connected in parallel with a unidirectional diode to prevent breakdown voltage. When the specific switch element is IGBT, each switch element is connected in parallel with a unidirectional diode, and each group of switch elements is connected to the power supply in series, and the specific connection method is not repeated.

[0029] Furthermore, when the H-bridge driving circuit 11 is provided with three groups of switch elements, the three groups of switch elements output driving signals to the load after receiving the first PWM signal according to the H-bridge control principle, and the driving signals control the operation or interruption of the load; wherein the first PWM signal is a pulse signal, which is used to provide electrical energy to the driving circuit 11.

[0030] In this embodiment, the control component 21 may be a specific chip control terminal or a control device, and the specific chip control terminal may be an MCU chip control terminal or a PCB board control terminal, etc. The control component 21 includes a pulse width modulation PWM circuit, and the PWM circuit is first connected to a generic timer (Generic Timer Module, GTM). When the pulse time set by the timer GTM triggers the PWM circuit to generate a pulse, the PWM circuit is used to output a first PWM signal to the drive circuit 11.

[0031] In this embodiment, the signal delay circuit 31 is used to ensure that the signal acquisition component 41 and the drive circuit 11 meet a certain phase relationship, and an RC delay circuit is added. Among them, the first end of the signal delay circuit 31 is electrically connected between the drive circuit 11 and the PWM, and the signal delay circuit 31 is used to delay the input first PWM signal to generate a second PWM signal. It should be noted that after the signal delay circuit 31 is used to delay the input first PWM signal, the signal conversion component selects a trigger request or an interrupt request to output the second PWM signal.

[0032] See also Figure 2 , Figure 2 It is a circuit principle diagram of a signal delay circuit 31 provided in an embodiment of the present application. Furthermore, when the signal delay circuit 31 adds an RC delay circuit, since the capacitor is an element for storing charge, the voltage across the capacitor is U=Q / C, and the voltage rises with the accumulation of charge. The 3.3V signal charges C1 through R1, and the time t for the voltage at point A to rise from 0 to the effective voltage required by the subsequent circuit is the delay time of the RC circuit. When precise calculation is not required, the delay time generated by the delay circuit can be directly calculated using T=RC, with units: T for seconds (s), R for ohms (Ω), and C for farads (F). Among them, T represents the delay time of the RC delay circuit, R represents the resistance size in the RC delay circuit, and C represents the capacitance size in the RC delay circuit.

[0033] Specifically, when the PWM driving frequency of motor 12 is 100Hz (cycle 10ms), ADC acquisition is triggered when the PWM high level is close to the middle position, and the delay circuit charging time required is about 2.5ms, that is, 2.5*0.001(s)=R(Ω)*C(F), and R=2.5MΩ, C=1uF can be selected.

[0034] Preferably, the resistance value selection of the delay circuit is 2MΩ, 2.2MΩ, 2.4MΩ for the resistor R, and 1uF for the capacitor C, which can meet the usage scenario. Other selections can be selected according to experimental needs, without specific restrictions.

[0035] In this embodiment, the signal acquisition component 41 can be a current acquisition module configured by the MCU chip; or a dedicated analog-to-digital converter (ADC) is set on the chip to collect current, and can be an external current detection module. Specifically, when the above-mentioned signal acquisition component 41 uses a dedicated analog-to-digital converter (ADC), the acquisition component is electrically connected to the second end of the drive circuit 11 and the signal delay circuit 31, and the signal acquisition component 41 collects the drive signal when the second PWM signal is input.

[0036] See also Figure 3 , Figure 3 It is a structural schematic diagram of a signal conversion component provided by an embodiment of the present application. In one embodiment, the signal delay circuit 31 includes a signal conversion component, which is connected to the control component 21 and the signal acquisition component 41, and is used to delay the input first PWM signal and then select a trigger request or an interrupt request to output a second PWM signal.

[0037] In this embodiment, ERU (External Event Request Unit) is a multifunctional event and mode detection unit inside the MCU, and its main function is to generate interrupts based on optional trigger events. For example, the software configures the input pin rising edge to trigger the interrupt, and when the input pin rising edge trigger event occurs, a corresponding interrupt request is generated. Other modules can use the events detected by the ERU module to trigger or start specific operations. For example, the ADC module sequence conversion.

[0038] In this embodiment, the signal conversion element may be an ERU module; or other devices for converting signals. Preferably, when the signal conversion element is an ERU module, the ERU module is arranged on the MCU chip. Specifically, the ERU module includes an external request selection unit (Enterprises Run System, ERS), an external trigger logic unit (Extract-Transform-Load, ETL), an output gating selection unit (output gating selection, OGU) and a connecting matrix 24 (Connecting Matrix, CM).

[0039] Combination Figure 3 , see Figure 4 , Figure 4It is another principle schematic diagram of a signal converter provided by an embodiment of the present application. The signal converter includes: a selection circuit 22, the selection circuit 22 is electrically connected to the control component 21 as the input end of the signal converter; and is used to select the input first PWM signal. The logic circuit 23 is electrically connected to the selection circuit 22, and is used to perform a logic operation on the first PWM signal. The control circuit 25 is electrically connected to the logic circuit 23 and the signal acquisition component 41, receives the first PWM signal after the logic operation, and then selects a trigger request or an interrupt request to output a second PWM signal. Specifically, when the selection circuit 22 and the logic circuit 23 set input channel0, input channel1, input channel2, input channel3, input channel4, input channel5, input channel6, and input channel7, the channel signals are converged through the connection matrix 24, and then output to the output channel0, output channel1, output channel2, output channel3, output channel4, output channel5, output channel6, and output channel7 of the control circuit 25, and then output.

[0040] In this embodiment, the selection circuit 22 may be a plurality of pulse signal channels, and the pulse signal channels preset corresponding pulse values, allowing pulses in the first PWM signal that meet the preset pulse values ​​to pass. The logic circuit 23 may be a plurality of channels corresponding to the selection circuit 22, and the pulses that meet the preset pulse values ​​that are allowed to pass are subjected to logical operations, and a plurality of AND gates, NOT gates or NAND gates are specifically set to output pulses that meet the logic to the connection matrix 24. The control circuit 25 may be a plurality of control gates, which control the output of the second PWM signal.

[0041] Preferably, the selection circuit 22 can be an ERS, which is used to select a pulse signal channel from multiple pulse signal channels as an input channel. The logic circuit 23 is an ETL, and each ETL can be based on a jump edge detection block, in which the detection of the rising edge and the falling edge can be independently enabled. If there are two enable bits, the two jump edges generate a trigger event (for example, processing a flip input). The control circuit 25 is an OGU, and each OGU unit can combine the available trigger events and status flags from the input channel to dispatch the results. Specifically, the control circuit 25 can be set as an OGU with a reset gate and an update gate. The reset gate combines the new input signal with the previous incoming signal, and the update gate saves the previous incoming signal to the current time, calculates the signal amount, and outputs the signal amount that meets the preset, that is, outputs the second PWM signal.

[0042] In one embodiment, the signal conversion element further includes a connection matrix 24, which is electrically connected to the logic control circuit 25 and the control circuit 25, and is used to set a priority for the first PWM signal after the logic operation and then input it into the control circuit 25.

[0043] In this embodiment, when the connection matrix 24 is CM, the first end of the connection matrix 24 is connected to the logic control circuit 25; the second end of the connection matrix 24 is electrically connected to the control circuit 25, and CM mainly concentrates the signals of the logic circuit 23 and inputs them to the control circuit 25.

[0044] See also Figure 5 , FIG. 1 is a schematic diagram of a circuit principle of a driving circuit 11 provided in an embodiment of the present application. The driving circuit 11 includes: a power supply; a load; at least one set of switch components, at least one set of switch components is electrically connected to the power supply and receives power from the power supply; at least one set of switch components is used to control the load drive after receiving power from the power supply.

[0045] In this embodiment, when the drive circuit 11 is an H-bridge drive circuit 11, it can be any one of a half-bridge drive circuit 11, a full-bridge drive circuit 11, or a three-phase bridge circuit set according to the load. Specifically, when the drive circuit 11 is a half-bridge drive circuit 11, the switch element is a group of switch elements, that is, a group of switch elements is two switches connected in series to the power supply; or when the drive circuit 11 is a full-bridge drive circuit 11, the switch element is two groups of switch elements, and the specific connection method is not repeated.

[0046] In this embodiment, when the load is a three-phase load, the bridge drive circuit 11 is composed of three groups of switch elements, such as Figure 5 The switch components are Q1, Q2, Q3, Q4, Q5, and Q6. The bridge drive circuit drives the motor through A, B, and C. At the same time, Figure 5The timing waveform diagram when the bridge drive circuit 11 drives the motor is shown in the figure, which are the PWM timing waveforms collected by the ADC module at A, B, and C respectively.

[0047] In one embodiment, the driving signal acquisition module also includes a filtering module, a first end of the filtering module is electrically connected to the driving circuit 11; a second end of the filtering module is electrically connected to the signal acquisition module; and when the signal acquisition module acquires the current signal of the driving circuit 11, the current signal to be collected is first filtered, and then the filtered current signal is output to the signal acquisition module.

[0048] In this embodiment, the filter module may be the bridge current recovery circuit 51, or other devices or equipment with a filtering function. There is no specific restriction on the selection of the filter module.

[0049] In one embodiment, the control component 21 further includes: a timer 26; the timer 26 is electrically connected to the first end of the PWM circuit, and is used to set the pulse signal generation time, triggering the PWM circuit to generate a first PWM signal to the delay circuit.

[0050] In this embodiment, the timer 26 can be a generic timer module (GTM), or other devices or modules with a pulse timing function. Specifically, when the timer 26 is a GTM, it includes a clock management unit, a common time base unit, a timer input module, a timer output module, and a dead time module. The timer 26 triggers the control component 21 to generate a PWM signal through the above modules and units.

[0051] Combination Figure 6 Further explanation of the drive signal acquisition module: Figure 6 This is another circuit principle schematic diagram of a driving signal acquisition module provided in an embodiment of the present application.

[0052] In this design, the GTM timer module inside the chip MCU is assigned to the PWM circuit for PWM signal generation, and the PWM signal drives the motor 12 through the drive circuit. The motor 12 drive current is filtered by the sampling circuit and collected by the ADC module. The motor 12 drive PWM signal is processed by the external delay circuit and then triggered to collect the ADC, ensuring the accuracy of the ADC acquisition of the bridge drive current. The external delay circuit mainly uses the RC delay circuit, and the specific delay time is determined according to the design scenario.

[0053] Furthermore, the ERU module inside the MCU collects the delayed PWM edge signal to generate an interrupt request, and redirects the interrupt signal by configuring the internal register of the MCU as a trigger source for ADC collection.

[0054] In one embodiment, the driving circuit 11 is an H-bridge driving circuit 11 .

[0055] In this embodiment, when the driving circuit 11 is an H-bridge driving circuit 11, different switch groups are selected according to different loads required by the experiment, and the details are not repeated here.

[0056] A second aspect of an embodiment of the present application provides a vehicle, the vehicle comprising the driving signal acquisition module of any one of the above embodiments.

[0057] In one embodiment, the vehicle further includes a driving motor 12 , the driving motor 12 is electrically connected to the driving circuit 11 in the driving signal acquisition module, and the first PWM signal driving circuit is used to drive the driving motor 12 .

[0058] Since the specific structure of the drive signal acquisition module has been described in detail in the above embodiments, and other structures of the above drive signal acquisition module are known in the art, they are not described here. The above embodiments are only used to illustrate the technical solution of the present application, rather than to limit it; although the present application is described in detail with reference to the above embodiments, ordinary technicians in the field should understand that: it is still possible to modify the technical solutions recorded in the above embodiments, or to replace some of the technical features therein by equivalent; and these modifications or replacements should be included in the protection scope of the present application so as not to make the essence of the corresponding technical solution deviate from the spirit of the technical solution of each embodiment of the present application.

Claims

1. A driving signal acquisition module, characterized in that: include: A driving circuit, wherein the driving circuit is used to output a driving signal to a load according to the first PWM signal; A control component, the control component comprising a pulse width modulation (PWM) circuit, the PWM circuit is electrically connected to the driving circuit, and the PWM circuit is used to output the first PWM signal; a signal delay circuit, wherein a first end of the signal delay circuit is electrically connected between the drive circuit and the PWM circuit, and the signal delay circuit is used to perform delay processing on an input first PWM signal to generate a second PWM signal; A signal acquisition component is electrically connected to the drive circuit and the second end of the signal delay circuit, and is used to acquire the drive signal when the second PWM signal is input.

2. The driving signal acquisition module according to claim 1, characterized in that: The signal delay circuit includes a signal conversion component, which is connected to the control component and the signal acquisition component, and is used to delay the input first PWM signal and then select a trigger request or an interrupt request to output a second PWM signal.

3. The driving signal acquisition module according to claim 2, characterized in that: The signal conversion element comprises: A selection circuit, the selection circuit being electrically connected to the control component as an input end of the signal conversion element; and being used for selecting the first input PWM signal; a logic circuit, electrically connected to the selection circuit, and configured to perform a logic operation on the first PWM signal; The control circuit is electrically connected to the logic circuit and the signal acquisition component, receives the first PWM signal after the logic operation, selects a trigger request or an interrupt request, and outputs a second PWM signal.

4. The driving signal acquisition module according to claim 2, characterized in that: The signal conversion component also includes a connection matrix, which is electrically connected to the logic control circuit and the control circuit and is used to set a priority for the first PWM signal after the logic operation and then input it into the control circuit.

5. The driving signal acquisition module according to claim 1, characterized in that: The signal delay circuit includes an RC delay circuit; The delay time of the RC delay circuit is determined according to the following expression: T = RC, Wherein, T represents the delay time of the RC delay circuit, R represents the resistance in the RC delay circuit, and C represents the capacitance in the RC delay circuit.

6. The driving signal acquisition module according to claim 1, characterized in that: The drive signal acquisition module also includes a filtering module, a first end of which is electrically connected to the drive circuit; a second end of the filtering module is electrically connected to the signal acquisition module; and when the signal acquisition module acquires the current signal of the drive circuit, the filtering module first filters the current signal to be collected and then outputs the filtered current signal to the signal acquisition module.

7. The driving signal acquisition module according to claim 1, characterized in that: The control component also includes: Timer; the timer is electrically connected to the first end of the PWM circuit, and is used to set the pulse signal generation time, triggering the PWM circuit to generate the first PWM signal to the delay circuit.

8. The driving signal acquisition module according to claim 1, characterized in that: The driving circuit is an H-bridge driving circuit.

9. A vehicle, characterized in that: The vehicle comprises a driving signal acquisition module as claimed in any one of claims 1 to 8.

10. The vehicle further includes a drive motor, which is electrically connected to a drive circuit in the drive signal acquisition module, and the first PWM signal drive is used to drive the drive motor.

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