Circuit for suppressing crosstalk signal, signal transmission system and chip

Abstract

A circuit for suppressing crosstalk signals, a signal transmission system and a chip, the circuit is applied to the chip, the chip is provided with a victim network, a first signal line in the victim network and the ground form ground capacitance, and a first crosstalk signal exists between an attack network located at one side of the victim network and the victim network; the circuit comprises a compensation network located on the other side of the victim network, a second crosstalk signal exists between the compensation network and the victim network, and the first crosstalk signal and the second crosstalk signal are mutually offset after signal superposition.

Description

Technical Field

[0001] The present invention relates to chip design technology, and in particular to a circuit, a signal transmission system and a chip for suppressing crosstalk signals. Background Art

[0002] Noise refers to undesirable or unintentional phenomena that affect the normal operation of a chip. In nanotechnology, noise can affect the timing of functions or devices. In deep submicron processes, the impact of noise becomes more prominent for the following reasons:

[0003] (1) Increase in the number of metal layers: For example, a 0.25um or 0.3um process has four or five metal layers, while the number increases to ten or more metal layers in 65nm and 45nm processes.

[0004] (2) Vertically dominated metal aspect ratio: This means that the traces are thin and tall, unlike the relatively wide geometry in earlier processes. Therefore, a larger proportion of the capacitance is composed of sidewall coupling capacitance, which is the inter-trace capacitance between adjacent signal lines.

[0005] (3) Higher wiring density: With finer geometry, more metal wires can be physically close together.

[0006] (4) A large number of interactive devices and interconnects: More standard cells and signal lines are packaged in the same silicon chip area, resulting in more interactions.

[0007] (5) Faster waveform switching due to higher frequency: Faster edge rates result in more current spikes and greater coupling effects on adjacent traces and cells.

[0008] (6) Lower power supply voltage: The reduction in power supply voltage results in a smaller noise margin.

[0009] Among the above noises, there is a kind of crosstalk noise, where crosstalk noise refers to the unintentional coupling between two or more signals. Crosstalk noise is caused by capacitive coupling between adjacent signals on the chip, which causes the high and low levels of one network to switch, thus having an unexpected effect on the coupled signal. The affected signal is called the victim, and the signal that causes the effect is called the aggressor. Crosstalk noise affects the function and timing of the device.

[0010] In the prior art, in order to reduce the negative impact of crosstalk noise on the chip, the size of the crosstalk noise can be reduced by reducing the size of the coupling capacitor. Since the design process of reducing the size of the coupling capacitor is relatively complicated, the process complexity of the chip design is increased. Summary of the invention

[0011] Embodiments of the present application provide a circuit, a signal transmission system, and a chip for suppressing crosstalk signals.

[0012] A circuit for suppressing crosstalk signals is applied to a chip, wherein the chip is provided with a victim network, wherein a first signal line in the victim network forms a ground capacitance with a ground, and a first crosstalk signal exists between an attack network located on one side of the victim network and the victim network; wherein the circuit comprises:

[0013] The compensation network is located at the other side of the victim network, wherein a second crosstalk signal exists between the compensation network and the victim network, and the first crosstalk signal and the second crosstalk signal cancel each other out after signal superposition.

[0014] A signal transmission system is applied to a chip, wherein the system comprises a victim network, an attack network and the circuit described above.

[0015] A chip is provided with the circuit or system described above.

[0016] In the embodiment of the present application, a compensation network is added near the victim network, wherein the compensation network and the attack network are respectively deployed on both sides of the victim network, so that a first crosstalk signal exists on one side of the victim network and a second crosstalk signal exists on the other side. Since the first crosstalk signal and the second crosstalk signal cancel each other after signal superposition, the crosstalk noise of the victim network is significantly reduced, thereby improving the signal transmission quality of the victim network. In addition, the design process is relatively simple, reducing the process complexity of chip design.

[0017] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0019] Figure 1 is a schematic diagram of a signal transmission system in the related art;

[0020] Figure 2 This is a schematic diagram of an application of a signal transmission system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0022] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0023] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0024] Figure 1 FIG. 1 is a schematic diagram of a signal transmission system in the related art. Figure 1 As shown, the signal transmission system includes a victim network and an attack network, wherein the input end of the victim signal line in the victim network is connected to the driving unit, that is, Figure 1In the AND gate U_AND0, a capacitance Cground is formed between the victim signal line and the ground, wherein the attack signal line in the attack network is adjacent to the victim signal line and the parallel running line is relatively long, wherein the victim signal transmitted by the victim signal line and the attack signal transmitted by the attack signal line have signal jumps within the same timing window. For example, within the same timing window, the attack signal switches from a low level of 0v to a high level of 0.8v; the victim signal switches from a high level of 0.8v to 0v, and within the time window, a coupling capacitance is formed between the attack signal metal line and the victim signal metal line, wherein the coupling capacitance refers to the parasitic capacitance between two adjacent metal lines of the same layer.

[0025] by Figure 1 Taking the signal transition scenario shown as an example, when the signals of the attack network and the victim network switch levels in opposite directions, the charge required by the coupling capacitor Cc between the two will be greater. The attack network switching levels in opposite directions increases the required charge amount from the driver unit of the victim network. The two signals will interfere with each other through this coupling capacitor, and increase the delay of the signal line between the driver unit U_AND0 and the victim network, resulting in a timing violation of the circuit, which makes the function disordered, causing the jump time of the signal of the victim network to lag, the conversion time of the signal becomes longer, the drive will become weaker, the delay of the metal line and the delay of the next-level unit will become longer, resulting in a larger overall delay of this path, so violations are likely to occur when establishing the time check.

[0026] By the same token, if the attack signal and the victim signal have the same jump direction, the victim signal's jump time will be advanced, the signal conversion time will be shortened, the drive will be stronger, the metal line delay and the next-level unit delay will be shortened, resulting in a shorter overall delay for this path. In this case, violations are likely to occur during the hold time check.

[0027] In summary, whether the jump direction of the attack signal is consistent with that of the victim signal, it will have an adverse effect on the timing and may cause a timing violation.

[0028] Based on the above problems, the embodiments of the present application propose the following solutions, including:

[0029] The present application provides a signal transmission system, which is applied to a chip, wherein the system includes a victim network, an attack network, and a circuit for suppressing crosstalk signals.

[0030] The first signal line in the victim network forms a capacitance to ground with the ground;

[0031] There is a first crosstalk signal between the attack network located at one side of the victim network and the victim network;

[0032] The circuit is provided with a compensation network located at the other side of the victim network, wherein a second crosstalk signal exists between the compensation network and the victim network, and wherein the first crosstalk signal and the second crosstalk signal cancel each other out after signal superposition.

[0033] The structure provided by this application is combined with Figure 1 By comparing the structures shown, it can be seen that the structure provided by the present application is additionally provided with a compensation network, wherein a second crosstalk signal exists between the compensation network and the victim network.

[0034] The first crosstalk signal and the second crosstalk signal cancel each other out after being superimposed, wherein the mutual cancellation of signals means that when two or more signals are superimposed, their amplitudes are reduced or completely eliminated due to their phase relationship. This phenomenon usually occurs when the two signals have a specific phase relationship, such as a 180-degree phase difference, in which case the two signals are completely inverted, resulting in full phase cancellation after superposition, and therefore the output signal is silent.

[0035] Different from the method of reducing the size of the coupling capacitor to reduce the crosstalk signal in the related art, the signal transmission system provided in the embodiment of the present application is additionally provided with a compensation network, wherein the compensation network and the attack network are respectively deployed on both sides of the victim network, so that there is a first crosstalk signal on one side of the victim network and a second crosstalk signal on the other side. Since the first crosstalk signal and the second crosstalk signal cancel each other after signal superposition, the crosstalk noise of the victim network is significantly reduced, thereby improving the signal transmission quality of the victim network. In addition, the design process is relatively simple, reducing the process complexity of the chip design.

[0036] Optionally, the system further includes:

[0037] a first driving unit, connected to the victim network, and configured to output a signal transmitted by the first signal line;

[0038] The second driving unit is connected to the attack network and is used to output the signal transmitted by the second signal line.

[0039] The first drive unit and the second drive unit may be functional modules or standard units (eg, Figure 1 AND gate U_AND0 in the circuit).

[0040] The circuit for suppressing crosstalk signals provided in the embodiment of the present application is described below:

[0041] Crosstalk refers to the coupling between two signal lines, the mutual inductance and mutual capacitance between the signal lines causing noise on the line. Capacitive coupling causes coupling current, while inductive coupling causes coupling voltage.

[0042] During signal line transmission, electromagnetic coupling generates unwanted voltage or current noise interference on adjacent transmission lines. Therefore, the edge field effect of the signal line is the root cause of crosstalk. Capacitive coupling is caused by the voltage change on the interference source causing induced current on the interfered object, while inductive coupling is caused by the magnetic field generated by the current change on the interference source causing induced voltage on the interfered object.

[0043] In the embodiment of the present application, a coupling capacitor is formed between the attack network and the victim network to generate a first crosstalk signal; correspondingly, a coupling capacitor is formed between the compensation network and the victim network to generate a second crosstalk signal.

[0044] The same mechanism is used to generate a second crosstalk signal to offset the first crosstalk signal, thereby reducing the difficulty of chip design.

[0045] Furthermore, the attack network is provided with a second signal line for transmitting the signal of the attack network; the compensation network is provided with a third signal line for transmitting the signal of the compensation network;

[0046] The first signal line, the second signal line and the third signal line are arranged in parallel on the same metal layer of the chip to ensure that the coupling capacitance formed between the third signal line and the first signal line is infinitely close to the coupling capacitance formed between the second signal line and the first signal line.

[0047] Furthermore, the second signal line and the third signal line are distributed on both sides of the first signal line, wherein the routing width between the second signal line and the first signal line is equal to the routing width between the second signal line and the first signal line, and the routing distances between the second signal line and the third signal line are the same.

[0048] Based on the above wiring layout, the wiring layouts of the attack network and the compensation network are the same, so that the equivalent sizes of the coupling capacitors formed based on the same adjacent signal line (ie, the first signal line) are equal.

[0049] Furthermore, within the same time window, the signal transmitted by the victim network and the signal transmitted by the attack network both undergo jumps, generating the first crosstalk signal;

[0050] In the same time window, the signal transmitted by the victim network and the signal transmitted by the compensation network both jump, generating the second crosstalk signal;

[0051] The jump directions of the signals in the attack network and the compensation network are opposite.

[0052] When the jump direction of the signal in the compensation network is opposite to that of the signal in the victim signal, a first crosstalk signal is generated between the attack network and the victim network, wherein the first crosstalk signal causes the jump of the signal in the victim network to lag; since the jump direction of the attack network and the signal in the compensation network is opposite, when the jump direction of the signal in the compensation network is opposite to that of the signal in the victim signal, the jump direction of the signal in the compensation network is the same as that of the signal in the victim network, and a second crosstalk signal is generated between the compensation network and the victim network, wherein the second crosstalk signal causes the jump of the signal in the victim network to occur in advance. Therefore, at the transmission end of the first signal line, under the joint action of the first crosstalk signal and the second crosstalk signal, the jump state of the signal in the victim network basically maintains a normal state, which greatly offsets the crosstalk caused by the attack network.

[0053] Similarly, when the jump direction of the signal in the compensation network is the same as that of the signal in the victim signal, a first crosstalk signal is generated between the attack network and the victim network, wherein the first crosstalk signal causes the jump of the signal in the victim network to occur in advance; since the jump directions of the attack network and the signal in the compensation network are opposite, when the jump directions of the signal in the compensation network and the signal in the victim signal are the same, the jump directions of the signal in the compensation network and the signal in the victim network are opposite, and a second crosstalk signal is generated between the compensation network and the victim network, wherein the second crosstalk signal causes the jump of the signal in the victim network to occur later. Therefore, at the transmission end of the first signal line, under the joint action of the first crosstalk signal and the second crosstalk signal, the jump state of the signal in the victim network basically maintains a normal state, which greatly offsets the crosstalk caused by the attack network.

[0054] Based on the above description, it can be known that since the signals in the victim network, the attack network and the compensation network jump within the same time window, the first crosstalk signal and the second crosstalk signal exist simultaneously in the same time window. In addition, since the jumping directions of the signals in the attack network and the compensation network are opposite, the first crosstalk signal and the second crosstalk signal have opposite effects on the delay of the jumping of the signal in the victim network. Under the joint action of the first crosstalk signal and the second crosstalk signal, the jumping state of the signal in the victim network basically maintains a normal state, which greatly offsets the crosstalk caused by the attack network.

[0055] Furthermore, the numerical value corresponding to the high level in the attack network is equal to the numerical value corresponding to the high level in the compensation network, which can effectively achieve signal cancellation and effectively cancel out the crosstalk caused by the attack network.

[0056] Since the signal transmitted by the third metal wire in the compensation network needs to meet many conditions, if a signal generator is specially set as the signal source of the compensation network, it will not only increase the hardware cost but also increase the complexity of the operation. To solve the above technical problems, the embodiment of the present application proposes the following solutions, including:

[0057] A connection point is provided on the second signal line, wherein the connection point divides the signal received by the attack network into two paths, one path continues to be the signal transmitted by the second signal line, and the other path is used as the input signal of the compensation network after being processed.

[0058] Specifically, the circuit further includes:

[0059] An inverter, wherein the input end of the inverter is connected to the input end of the attack network through the connection point, and the output end is connected to the input end of the compensation network, and is used to invert the signal transmitted by the second signal line and use it as the signal transmitted by the third signal line.

[0060] Among them, the inverter is a circuit that can reverse the phase of the input signal by 180 degrees. Specifically, when the input signal is high, the inverter will output a low level; and when the input signal is low, the inverter will output a high level.

[0061] Based on the working characteristics of the inverter, the jump directions of the signals in the attack network and the compensation network are opposite, the circuit structure is simple, and the hardware cost is low.

[0062] Furthermore, the signal of the third signal line obtained by the inverter has a certain lag relative to the signal transmitted by the second signal line, and it is possible that the signal of the third signal line and the signal transmitted by the second signal line are not in the same time window. To solve the above technical problems, the embodiment of the present application proposes the following solutions, including:

[0063] In an embodiment of the present application, the circuit also includes a buffer, wherein the buffer is connected to the input end of the attack network through the connection point, and is used to control the signal transmitted by the second signal line and the signal transmitted by the third signal line to be within the same time window.

[0064] In the above method, the buffer reserves time for the inverter to process the signal by delaying the received signal. After determining the inverter output signal, the buffer outputs the received signal so that the signal transmitted by the second signal line and the signal transmitted by the third signal line are within the same time window.

[0065] Figure 2 This is a schematic diagram of an application of a signal transmission system provided in an embodiment of the present application. Figure 2 As shown, the signal transmission system and Figure 1 The structure is similar to that shown in Figure 2 In the structure shown, the signal of the first signal line in the victim network comes from the driver unit U_AND0, and the signal of the second signal line in the attack network comes from the driver unit U_BUF0.

[0066] Figure 2 The structure shown is Figure 1 The difference between the structures shown is that a circuit for suppressing crosstalk signals is added. The specific differences are as follows:

[0067] A compensation network is added, wherein the compensation network is distributed on the other side of the victim signal network and is consistent with the attack network in terms of metal layer and trace length, forming a coupling capacitor network opposite to the coupling capacitor network between the attack network and the victim network;

[0068] An inverter U_INV1 is added to the output end of the driving unit U_BUF0, wherein the inverter U_INV1 serves as a driving unit of the compensation network;

[0069] In addition, a buffer U_BUF1 is added at the output end of the driving unit U_BUF0, wherein the driving unit U_BUF1 drives the signal in the attack network to continue to be transmitted on the second signal line, ensuring that the signal jumps of the second signal line and the third signal line are within the same time window.

[0070] by Figure 2 Taking the application scenario shown as an example, within the same time window, the signal in the second signal line switches from a low level of 0v to a high level of 0.8v; the signal in the first signal line switches from a high level of 0.8v to 0v. Since the signals of the attacking network and the victim network are switched in level in opposite directions, the charge required for the coupling capacitor between the two will be greater. The attacking network switching in level in opposite directions increases the required charge amount from the driving unit of the victim network. The two signals will interfere with each other through the coupling capacitor and increase the delay of the signal line between the driving unit U_AND0 and the victim network, causing the jump time lag of the signal of the victim network (as shown in signal S1).

[0071] Since the jump directions of the signals in the attack network and the compensation network are opposite, when the jump directions of the signal in the compensation network and the signal in the victim network are opposite, the jump directions of the signal in the compensation network and the signal in the victim network are the same, that is, the signal in the third signal line switches from a high level of 0.8v to 0v, causing the signal jump in the victim network to occur in advance (as shown by signal S2), and the final signal jump state of the victim network is the superposition state of signal S1 and signal S2, so that the signal jump transmitted by the first signal line in the victim network basically maintains the original state (as shown by signal S3), which greatly offsets the crosstalk caused by the original attack network.

[0072] When checking the signal establishment time in the victim network, the signal will jump earlier than before due to the influence of the crosstalk signal. Figure 2 The scheme shown can effectively offset the crosstalk caused by the attack network, ensure that the signal jump maintains the original state, and is conducive to the establishment time check; similarly, if the victim signal is checked for hold time, the signal will lag behind the jump compared to the previous one under the influence of the crosstalk signal. Figure 2 The scheme shown can effectively offset the crosstalk caused by the attack network, can ensure that the signal jump maintains the original state, and is conducive to the inspection of the maintenance time. Therefore, the scheme provided by the embodiment of the present application maintains the jump state of the signal in the victim network, which is conducive to the convergence of the timing.

[0073] In addition, an embodiment of the present application also provides a chip, which is provided with the circuit described above or the system described above.

[0074] Based on the above description, it can be seen that the solution provided in the embodiment of the present application has the following advantages, including:

[0075] The design idea of ​​shielding crosstalk signals is not adopted, so there is no need to insert metal shielding wires, which reduces the difficulty of chip design;

[0076] There is no need to change the routing of the signal lines of the attack network and the victim network, which reduces the difficulty of routing layout design;

[0077] The purpose of suppressing crosstalk signals is achieved by using two-way crosstalk signals for signal cancellation, and the anti-interference accuracy is higher.

[0078] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A circuit for suppressing crosstalk signals, applied to a chip, wherein the chip is provided with a victim network, wherein a first signal line in the victim network forms a capacitance to ground with a ground, and a first crosstalk signal exists between an attack network located on one side of the victim network and the victim network; wherein the circuit comprises: The compensation network is located at the other side of the victim network, wherein a second crosstalk signal exists between the compensation network and the victim network, and the first crosstalk signal and the second crosstalk signal cancel each other out after signal superposition.

2. The circuit according to claim 1, characterized in that: A coupling capacitor is formed between the attack network and the victim network to generate a first crosstalk signal; A coupling capacitor is formed between the compensation network and the victim network to generate a second crosstalk signal.

3. The circuit according to claim 2, characterized in that: The first signal line, the second signal line of the attack network and the third signal line of the compensation network are arranged in parallel on the same metal layer of the chip.

4. The circuit according to claim 3, characterized in that: A routing width between the second signal line and the first signal line is equal to a routing width between the second signal line and the first signal line, and routing distances between the second signal line and the third signal line are the same.

5. The circuit according to claim 4, characterized in that: In the same time window, the signal transmitted by the victim network and the signal transmitted by the attack network both undergo jumps, generating the first crosstalk signal; In the same time window, the signal transmitted by the victim network and the signal transmitted by the compensation network both jump, generating the second crosstalk signal; The jump directions of the signals in the attack network and the compensation network are opposite.

6. The circuit according to claim 5, characterized in that: The numerical value corresponding to the high level in the attack network is equal to the numerical value corresponding to the high level in the compensation network.

7. The circuit according to claim 6, characterized in that: The second signal line is provided with a connection point; Wherein, the circuit further includes: An inverter, wherein the input end of the inverter is connected to the input end of the attack network through the connection point, and the output end is connected to the input end of the compensation network, and is used to invert the signal transmitted by the second signal line and use it as the signal transmitted by the third signal line.

8. The circuit according to claim 7, characterized in that The circuit further comprises: A buffer is connected to the input end of the attack network through the connection point, and is used to control the signal transmitted by the second signal line and the signal transmitted by the third signal line to be within the same time window.

9. A signal transmission system applied to a chip, wherein the system comprises a victim network, an attack network and the circuit according to any one of claims 1 to 8.

10. A chip provided with the circuit according to any one of claims 1 to 8 or the system according to claim 9.

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