Low-power-consumption digital-analog mixed sampling time-sharing circuit with self-checking function and control method

Abstract

According to the low-power-consumption digital-analog mixed acquisition time-sharing circuit with the self-checking function and the control method, time-sharing control and acquisition can be carried out on different digital quantity and different analog quantity signals only by adjusting a software program, timing acquisition and time-sharing acquisition of the signals can be achieved without changing a hardware circuit, and the time-sharing control and acquisition efficiency is improved. Therefore, random switching between digital quantity acquisition and analog quantity acquisition is realized, low-power-consumption sampling operation is realized, and the purpose of saving energy is realized. The circuit self-checking function is achieved, and the quality of the circuit can be judged in real time.

Description

Technical Field

[0001] The present invention relates to the technical field of digital processing, and in particular to a low-power digital-analog mixed sampling time-sharing circuit with self-checking function and a control method thereof. Background Art

[0002] The existing solutions generally use different hardware circuits and different software to collect digital and analog quantities. If you want to adjust the collection range, you need to change the hardware circuit, and dynamic adjustment cannot be achieved. At the same time, the necessary self-test and low-power modes are missing, and the circuit has poor versatility.

[0003] Digital and analog quantities are collected using different hardware circuits and different software. If you want to adjust the collection range, you need to change the hardware circuit, which cannot be adjusted dynamically. The adaptability and economy are very poor. At the same time, the necessary self-test and low-power modes are missing, and the circuit has poor versatility. Summary of the invention

[0004] According to the technical problems mentioned in the above background technology, a low-power digital-analog mixed sampling time-sharing circuit and control method with self-checking are provided. The present invention provides a low-power digital-analog mixed sampling time-sharing circuit and control method with self-checking. Time-sharing control and acquisition can be performed for different digital quantities and different analog signals only by adjusting the software program. There is no need to change the hardware circuit to realize the timing acquisition and time-sharing acquisition of signals, and realize the arbitrary switching between digital quantity acquisition and analog quantity acquisition. At the same time, low-power sampling operation is realized to achieve the purpose of energy saving. It has a circuit self-checking function, which can judge the quality of the circuit in real time.

[0005] The technical means adopted by the present invention are as follows:

[0006] A low-power digital-analog mixed sampling time-sharing circuit with self-checking, comprising:

[0007] The negative input electrode is connected to the protection circuit I through the switch A1, and then connected to the follower circuit I and then to the operation circuit; the switch A1 is connected in parallel with the switch A2 and then connected to GND;

[0008] The positive input electrode is connected to the protection circuit II through the switch B1, and then connected to the follower circuit II, and then connected to the potentiometer I and then to the operation circuit; the switch B1 is connected in parallel with the switch B2 and then connected to DC 5V;

[0009] The operation circuit is connected to the processor; the processor feeds back the processed information to the switch A1 and the switch A2; the processor feeds back the processed information to the switch B1 and the switch B2;

[0010] Potentiometers I and II realize information exchange with the processor via II2C communication bus; the potentiometer II is connected to the negative input electrode;

[0011] The processor controls the switch B1 to be disconnected, and then the switch A1 is closed. After the switch A1 is closed, the input negative electrode is grounded to GND, and then the switch A2 and the switch B2 are closed. The processor adjusts the resistance values ​​of the potentiometers I and II to be equal.

[0012] Furthermore, the switch A1 and the switch A2 are MOS tubes, and the closing and breaking of the MOS tubes are respectively controlled by the IO pins of the processor.

[0013] Furthermore, the switch B1 and the switch B2 are optocouplers, and the closing and opening of the optocouplers are respectively controlled by IO pins of the processor.

[0014] Furthermore, the protection circuit I and the protection circuit II realize input protection.

[0015] The present invention also includes a low-power digital-analog mixed sampling time-sharing method with self-checking, comprising the following steps:

[0016] Step 1: Dynamically adjust the analog acquisition voltage range;

[0017] Step 2: Dynamically adjust the digital quantity acquisition voltage range

[0018] Step 3: arbitrary switching and collection of analog and digital quantities;

[0019] Step 4: Make a real-time judgment on the state of the circuit; control the switch B1 to be disconnected through the processor, and then close the switch A1. After the switch A1 is closed, the negative pole of the input is grounded with GND, and then the switch A2 and the switch B2 are closed. The resistance values ​​of the potentiometers I and II are adjusted to be equal through the processor;

[0020] Step 5: The processor controls switch A1 and switch B1 to be closed or opened to achieve time-sharing acquisition.

[0021] Furthermore, the step 1 comprises the following steps:

[0022] Step 11: Set the switch state through the processor software to ensure that the circuit works in the analog quantity acquisition state; set switch A1 to the closed state and switch A2 to the disconnected state to ensure that the potentials of point X and point Y are consistent with the input negative electrode potential; switch B1 is in the closed state and switch B2 is in the disconnected state to ensure that the potential of point N is consistent with the input positive electrode potential, and the potential of point M is dynamically set through the resistance values ​​of potentiometers I and II;

[0023] Step 12: Calculate the resistance values ​​of potentiometer I and potentiometer II based on the actual requirements of the collected analog voltage.

[0024] Furthermore, the step 2 comprises the following steps:

[0025] Step 21: Set the switch state to ensure that the circuit works in the analog quantity acquisition state; set switch A1 to the closed state and switch A2 to the disconnected state to ensure that the potentials of point X and point Y are consistent with the input negative electrode potential; switch B1 is in the closed state and switch B2 is in the disconnected state to ensure that the potential of point N is consistent with the input positive electrode potential, and the potential of point M is dynamically set through the resistance values ​​of potentiometers I and II;

[0026] Step 22: Calculate the resistance values ​​of potentiometer I and potentiometer II according to the actual requirements of the collected digital voltage.

[0027] Furthermore, in step 3, if digital quantity acquisition is to be performed, the processor controls switch A2 and switch B2 to be disconnected, and then switch A1 and switch B1 are closed, and then the resistance values ​​of potentiometers I and II are adjusted according to the voltage value of the digital quantity to be acquired, and the potentiometer value is controlled by the processor through the IIC bus;

[0028] If analog quantity acquisition is to be performed, the processor controls switch A2 and switch B2 to be disconnected, and then switch A1 and switch B1 are closed. Then, the resistance values ​​of potentiometers I and II can be adjusted according to the analog quantity voltage value to be acquired. The potentiometer values ​​are controlled by the processor through the IIC bus.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] According to actual needs, the present invention can dynamically adjust the analog quantity acquisition voltage range and perform effective acquisition in combination with the software control method; the present invention can dynamically adjust the digital quantity acquisition voltage range and perform effective acquisition in combination with the software control method; the present invention realizes arbitrary switching and acquisition of analog quantity and digital quantity through the software control method.

[0031] The circuit of the present invention has a self-checking function and can judge the quality of the circuit in real time. By combining the circuit with a software control method, time-sharing acquisition can be realized, thereby achieving the purpose of reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 The present invention is a schematic diagram of a low-power digital-analog mixed sampling time-sharing circuit with self-checking function.

[0034] In the figure: 1. Input negative pole; 2. Input positive pole; 3. Switch A1; 4. Switch B1; 5. Switch A2; 6. GND; 7. Switch B2; 8. DC 5V; 9. Protection circuit I; 10. Protection circuit II; 11. Follower circuit I; 12. Follower circuit II; 13. Potentiometer II; 14 is operation circuit; 15 is potentiometer II; 16. Processor; 17. II2C communication bus. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] like Figure 1 As shown, the present invention provides a low-power digital-analog mixed sampling time-sharing circuit with self-checking, comprising:

[0038] The input negative electrode 1 is connected to the protection circuit I9 through the switch A13, and then connected to the follower circuit I11 and then connected to the operation circuit 14; the switch A13 is connected in parallel with the switch A25 and then connected to GND6;

[0039] The input positive electrode 2 is connected to the protection circuit II10 through the switch B14, and then connected to the follower circuit II12, and then connected to the potentiometer I13 and then connected to the operation circuit 14; the switch B14 is connected in parallel with the switch B27 and then connected to DC 5V8;

[0040] The operation circuit 14 is connected to the processor 16; the processor 16 feeds back the processed information to the switch A13 and the switch A25; the processor 16 feeds back the processed information to the switch B14 and the switch B27;

[0041] Potentiometers I13 and II15 implement information exchange with the processor 16 via the II2C communication bus 17; the potentiometer II15 is connected to the input cathode 1;

[0042] The processor 16 controls the disconnection of the switch B14, and then closes the switch A13. After the switch A13 is closed, the input cathode 1 and GND6 are grounded together, and then the switch A25 and the switch B27 are closed. The processor 16 adjusts the resistance values ​​of the potentiometers I13 and II15 to be equal.

[0043] As a preferred implementation, in the present application, the switch A13 and the switch A25 are MOS tubes (model: IRF640NS), and the closing and breaking of the MOS tubes are respectively controlled by the IO pins of the processor.

[0044] Preferably, in the present application, the switch B1 4 and the switch B2 7 are optocouplers (model: TLP173), and the closing and opening of the optocouplers are respectively controlled by the IO pins of the processor.

[0045] As a preferred implementation, in the present application, the protection circuit I9 and the protection circuit II10 implement input protection.

[0046] In the present application, both potentiometer I13 and potentiometer II15 are adjustable potentiometers (model: MCP4561, resistance setting range 0-10k) with IIC communication function, and the processor can set the resistance of the potentiometer in real time through the IIC bus.

[0047] Preferably, the present invention further comprises a low-power digital-analog mixed sampling time-sharing method with self-checking, comprising the following steps:

[0048] Step 1: Dynamically adjust the analog quantity acquisition voltage range; Step 1 includes the following steps:

[0049] Step 11: Set the switch state through the processor software to ensure that the circuit works in the analog quantity acquisition state; set switch A1 to the closed state and switch A2 to the disconnected state to ensure that the potentials of point X and point Y are consistent with the input negative electrode potential; switch B1 is in the closed state and switch B2 is in the disconnected state to ensure that the potential of point N is consistent with the input positive electrode potential, and the potential of point M is dynamically set through the resistance values ​​of potentiometers I and II;

[0050] Step 12: Calculate the resistance of potentiometer I and potentiometer II according to the actual demand of the collected analog voltage. For example, it is necessary to collect an input voltage of 0-DC20V. The AD pin of the processor collects a voltage of 0-DC2.5V, and the operation circuit is reduced by 4 times, so the input voltage range of the front end of the operation circuit is 0-DC10V. The input collection voltage is divided by digital potentiometer 1 and potentiometer 2 to ensure that the input voltage range of the front end of the operation circuit should be 0-DC10V, so the potential of point M should be 10V, and the resistance of digital potentiometer 1 and potentiometer 2 should satisfy R1 / R2=, both set to 10k, through processor software programming, and then through the IIC bus, the resistance of digital potentiometer 1 and potentiometer 2 can be set, so when the input voltage is 20V, the potential of point M is 10V, and the potential of point Y is 0V, so the analog quantity can be effectively collected through the processor, that is, input 0-DC20V to processor 0-DC2.5V.

[0051] Step 2: Dynamically adjust the digital quantity acquisition voltage range; Step 2 includes the following steps:

[0052] Step 21: Set the switch state to ensure that the circuit works in the analog quantity acquisition state; set switch A1 to the closed state and switch A2 to the disconnected state to ensure that the potentials of point X and point Y are consistent with the input negative electrode potential; switch B1 is in the closed state and switch B2 is in the disconnected state to ensure that the potential of point N is consistent with the input positive electrode potential, and the potential of point M is dynamically set through the resistance values ​​of potentiometers I and II;

[0053] Step 22: Calculate the resistance of potentiometer I and potentiometer II according to the actual demand for the collected digital voltage. For example, a DC100V input voltage needs to be collected. The AD pin of the processor collects a voltage of 0-DC2.5V, and the operation circuit is reduced by 4 times, so the input voltage range of the front end of the operation circuit is 0-DC10V. The input collection voltage is divided by digital potentiometer 1 and potentiometer 2 to ensure that the input voltage range of the front end of the operation circuit should be 0-DC10V, so the resistance of digital potentiometer 1 and potentiometer 2 should be the same, both set to 10k, through the processor software programming, and then through the IIC bus, the resistance of digital potentiometer 1 and potentiometer 2 can be set, so when the input voltage is 20V, the potential of point M is 10V, and the potential of point Y is 0V, the analog quantity can be effectively collected through the processor, that is, the input 0-DC20V is 0-DC2.5V for the processor.

[0054] Step 3: arbitrary switching and collection of analog quantity and digital quantity; in the step 3, if digital quantity collection is to be performed, the processor controls switch A2 and switch B2 to be disconnected, and then switch A1 and switch B1 are closed, and then the resistance values ​​of potentiometers I and II are adjusted according to the voltage value of the digital quantity to be collected. The potentiometer value is controlled by the processor through the IIC bus;

[0055] If analog quantity acquisition is to be performed, the processor controls switch A2 and switch B2 to be disconnected, and then switch A1 and switch B1 are closed. Then, the resistance values ​​of potentiometers I and II can be adjusted according to the analog quantity voltage value to be acquired. The potentiometer values ​​are controlled by the processor through the IIC bus.

[0056] Step 4: Make a real-time judgment on the state of the circuit; control the switch B1 to be disconnected through the processor, and then close the switch A1. After the switch A1 is closed, the negative pole of the input is grounded with GND, and then the switch A2 and the switch B2 are closed. The resistance values ​​of the potentiometers I and II are adjusted to be equal through the processor;

[0057] Step 5: Control the switch A1 and switch B1 to be closed or disconnected by the processor to achieve time-sharing acquisition. From the perspective of energy saving and power consumption reduction, for the acquisition of some non-critical digital or analog signals, the processor can be used to control the switch A1 and switch B1 to be closed or disconnected to achieve the purpose of time-sharing sampling, thereby achieving the purpose of energy saving. For example, a certain digital or analog sampling signal only needs to be collected once every 60 minutes, and does not need to be collected at other times. The processor can control the switch A1 to be closed and the switch B1 to be closed in the 0th to 1st minute, and the switches A2 and B2 to be disconnected, and the sampling channel is turned on, and then the signal sampling is completed; after the sampling is completed, the processor controls the switch A2 and B2 to be disconnected in the 2nd to 60th minute, and the sampling channel is disconnected, and there is no current consumption, so that only 1 minute of energy is consumed every 60 minutes, achieving the purpose of energy saving. In addition, according to actual needs, timed acquisition can also be performed: for example, it can be set to perform signal acquisition at the hour within 24 hours, and the switches A1 and B1 are closed during the acquisition, and the switches A2 and B2 are disconnected. When the acquisition is completed, the switches A1 and B1 are disconnected.

[0058] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments. In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-power digital-analog mixed sampling time-sharing circuit with self-checking, characterized in that: include: The input negative electrode (1) is connected to the protection circuit I (9) through the switch A1 (3), and then connected to the follower circuit I (11) and then connected to the operation circuit (14); the switch A1 (3) is connected in parallel with the switch A2 (5) and then connected to GND (6); The input positive electrode (2) is connected to the protection circuit II (10) through the switch B1 (4), and then connected to the follower circuit II (12), and then connected to the potentiometer I (13) and then connected to the operation circuit (14); the switch B1 (4) is connected in parallel with the switch B2 (7) and then connected to the DC 5V (8); The operation circuit (14) is connected to a processor (16); the processor (16) feeds back processed information to the switch A1 (3) and the switch A2 (5); the processor (16) feeds back processed information to the switch B1 (4) and the switch B2 (7); Potentiometer I (13) and potentiometer II (15) realize information exchange with the processor (16) via a II2C communication bus (17); the potentiometer II (15) is connected to the input negative electrode (1); The processor (16) controls the switch B1 (4) to be opened, and then the switch A1 (3) is closed. After the switch A1 (3) is closed, the input negative electrode (1) and the GND (6) are grounded. Then, the switch A2 (5) and the switch B2 (7) are closed, and the resistance values ​​of the potentiometers I (13) and II (15) are adjusted to be equal through the processor (16).

2. A low-power digital-analog mixed sampling time-sharing circuit with self-checking according to claim 1, characterized in that: The switch A1 (3) and the switch A2 (5) are MOS tubes, and the closing and opening of the MOS tubes are controlled by the IO pins of the processor.

3. A low-power digital-analog mixed sampling time-sharing circuit with self-checking according to claim 1, characterized in that: The switch B1 (4) and the switch B2 (7) are optocouplers, and the closing and opening of the optocouplers are controlled by the IO pins of the processor.

4. A low-power digital-analog mixed sampling time-sharing circuit with self-checking according to claim 1, characterized in that: The protection circuit I (9) and the protection circuit II (10) realize input protection.

5. A low-power digital-analog mixed sampling time-sharing method with self-checking, using the circuit described in any one of claims 1 to 4, characterized in that: The following steps are involved: Step 1: Dynamically adjust the analog acquisition voltage range; Step 2: Dynamically adjust the digital quantity acquisition voltage range Step 3: arbitrary switching and collection of analog and digital quantities; Step 4: Make a real-time judgment on the state of the circuit; control the switch B1 to be disconnected through the processor, and then close the switch A1. After the switch A1 is closed, the negative pole of the input is grounded with GND, and then the switch A2 and the switch B2 are closed. The resistance values ​​of the potentiometers I and II are adjusted to be equal through the processor; Step 5: The processor controls switch A1 and switch B1 to be closed or opened to achieve time-sharing acquisition.

6. A low-power digital-analog mixed sampling time-sharing method with self-checking according to claim 5, characterized in that: The step 1 comprises the following steps: Step 11: Set the switch state through the processor software to ensure that the circuit works in the analog quantity acquisition state; set switch A1 to the closed state and switch A2 to the disconnected state to ensure that the potentials of point X and point Y are consistent with the input negative electrode potential; switch B1 is in the closed state and switch B2 is in the disconnected state to ensure that the potential of point N is consistent with the input positive electrode potential, and the potential of point M is dynamically set through the resistance values ​​of potentiometers I and II; Step 12: Calculate the resistance values ​​of potentiometer I and potentiometer II based on the actual requirements of the collected analog voltage.

7. A low-power digital-analog mixed sampling time-sharing method with self-checking according to claim 5, characterized in that: The step 2 comprises the following steps: Step 21: Set the switch state to ensure that the circuit works in the analog quantity acquisition state; set switch A1 to the closed state and switch A2 to the disconnected state to ensure that the potentials of point X and point Y are consistent with the input negative electrode potential; switch B1 is in the closed state and switch B2 is in the disconnected state to ensure that the potential of point N is consistent with the input positive electrode potential, and the potential of point M is dynamically set through the resistance values ​​of potentiometers I and II; Step 22: Calculate the resistance values ​​of potentiometer I and potentiometer II according to the actual requirements of the collected digital voltage.

8. A low-power digital-analog mixed sampling time-sharing method with self-checking according to claim 5, characterized in that: In step 3, if digital quantity acquisition is to be performed, the processor controls switch A2 and switch B2 to be disconnected, and then switch A1 and switch B1 are closed, and then the resistance values ​​of potentiometers I and II are adjusted according to the voltage value of the digital quantity to be acquired. The potentiometer value is controlled by the processor through the IIC bus; If analog quantity acquisition is to be performed, the processor controls switch A2 and switch B2 to be disconnected, and then switch A1 and switch B1 are closed. Then, the resistance values ​​of potentiometers I and II can be adjusted according to the analog quantity voltage value to be acquired. The potentiometer values ​​are controlled by the processor through the IIC bus.

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