Transceiver for data or signal transmission and memory system including transceiver
By designing transceivers for low-power environments in memory devices, using technologies such as inverter chains and reset circuits, the reliability and accuracy of signal transmission and reception in high-speed data input/output are solved, and the power is reduced Consumption improves the performance of the storage system.
Patent Information
- Application Number
- CN202311653571.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-27
- Filing Date
- 2023-12-05
- Publication Date
- 2024-12-27
AI Technical Summary
When performing high-speed data input/output operations in low-power environments, there are reliability and accuracy problems in the transmission and reception of data or signals in existing memory devices, and the power consumption is high in standby state, making errors prone to occur.
A transceiver is designed, including a first inverter chain and a second inverter chain, and controls the operation of the inverter through an enable signal and an inverting enable signal, combining a reset circuit, a sense amplifier and a three-state inverter. Inverter, reduces power consumption and improves signal accuracy and reliability.
In a low-power environment, it improves the reliability and accuracy of data or signals transmission and reception, reduces power consumption in standby state, and reduces the possibility of errors.
Smart Images
Figure CN119210493A_ABST