Clock synchronization method and device and storage medium
By establishing multiple clock links in the 1588v2 clock synchronization system and selecting the target link for clock synchronization, the clock synchronization failure problem caused by device or link abnormality in complex network environments is solved, and the clock synchronization is improved Accuracy and stability.
Patent Information
- Application Number
- CN202310715370.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2024-12-27
AI Technical Summary
When the clock synchronization server device is abnormal or the link is abnormal in complex network environments, the clock synchronization failure occurs, affecting the accuracy and stability of timing synchronization.
By obtaining clock configuration information, generating and broadcasting clock request configuration messages, establishing multiple clock links, selecting the target clock link for clock synchronization, ensuring that the clock link reaches a preset number and no abnormalities, and achieving clock synchronization.
Improve the accuracy and stability of clock synchronization, ensure the establishment of multiple clock links between the first clock source device and the multiple second clock source devices, realize clock synchronization based on the target clock link, and enhance the system's abnormal resistance ability.
Smart Images
Figure CN119210636A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to a clock synchronization method, device and storage medium. Background Art
[0002] With the development of wireless communication technology and the increasing application of wireless access equipment, each device must rely on high-precision time synchronization to reliably meet user needs. In this context, 1588v2 clock was born. 1588v2 clock is a high-precision clock that uses the IEEE1588 protocol (precision clock synchronization protocol standard for network measurement and control systems). 1588v2 clock is a general specification to enhance the timing synchronization capability of network systems, enabling distributed communication networks to have strict timing synchronization and be applied to industrial automation systems. The basic concept is to synchronize the internal clock of the network device (client) with the main clock of the master control machine through hardware and software, providing a synchronization establishment time of less than 10μs. Compared with the Ethernet delay time of 1000μs that does not implement the IEEE1588 protocol, the timing synchronization index of the entire network has been significantly improved.
[0003] 1588v2 clock is a master-slave synchronization system. The clock synchronization of slave devices must rely on the normal operation of the master clock synchronization server device and a reliable transmission link. In a complex network environment, the requirements for clock synchronization server devices and links are relatively high. Abnormalities in the clock synchronization server device, link abnormalities, and communication transmission jitter will cause the 1588v2 clock source to be unavailable, which will lead to clock synchronization failure. Summary of the invention
[0004] The embodiments of the present invention provide a clock synchronization method, a device and a storage medium, aiming to improve the accuracy of clock synchronization.
[0005] In a first aspect, an embodiment of the present invention provides a clock synchronization method, which is applied to a first clock source device, and the method includes:
[0006] Obtaining slave clock configuration information, and generating and broadcasting a clock request configuration message according to the slave clock configuration information;
[0007] Establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links;
[0008] A target clock link is selected from the multiple clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link through the target clock link.
[0009] In a second aspect, an embodiment of the present invention further provides another clock synchronization method, which is applied to a second clock source device, and the method includes:
[0010] Obtain a clock request configuration message, and if a preset master clock configuration condition is met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information;
[0011] Establishing a clock link with a first clock source device that broadcasts the clock request configuration message according to the master clock configuration information;
[0012] Clock synchronization is performed with the first clock source device via the clock link.
[0013] In a third aspect, an embodiment of the present invention further provides a device, comprising a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for implementing a connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of any clock synchronization method provided in the specification of the present invention are implemented.
[0014] In a fourth aspect, an embodiment of the present invention further provides a storage medium for computer-readable storage, characterized in that the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of any clock synchronization method provided in the specification of the present invention.
[0015] The embodiment of the present invention provides a clock synchronization method, device and storage medium. The embodiment of the present invention obtains slave clock configuration information, and generates and broadcasts a clock request configuration message according to the slave clock configuration information; then establishes a clock link with multiple second clock source devices that perform master clock configuration according to the clock request configuration message, until the clock link of the first clock source device reaches a preset number and there are no abnormal clock links, and multiple clock links are obtained; selects a target clock link from the multiple clock links, and performs clock synchronization with the second clock source device corresponding to the target clock link through the target clock link. This solution can accurately establish multiple clock links for the first clock source device and multiple second clock source devices, and perform clock synchronization based on the target clock link in the multiple clock links, which greatly improves the accuracy and stability of the clock synchronization of the first clock source device. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of a flow chart of a clock synchronization method provided by an embodiment of the present invention;
[0017] Figure 2 A schematic diagram of a process for configuring a first clock source device provided by an embodiment of the present invention;
[0018] Figure 3 for Figure 1 A schematic diagram of the sub-step flow chart of the clock synchronization method in FIG.
[0019] Figure 4 A schematic diagram of a process for configuring a second clock source device provided by an embodiment of the present invention;
[0020] Figure 5 A schematic diagram of a scenario for establishing a clock link provided by an embodiment of the present invention;
[0021] Figure 6 A schematic diagram of another scenario of establishing a clock link provided by an embodiment of the present invention;
[0022] Figure 7 A schematic diagram of a process for establishing a clock link provided by an embodiment of the present invention;
[0023] Figure 8 A schematic diagram of another scenario of establishing a clock link provided by an embodiment of the present invention;
[0024] Fig. 9 A schematic diagram of a flow chart of another clock synchronization method provided by an embodiment of the present invention;
[0025] Fig.10 A schematic block diagram of the structure of a device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0027] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.
[0028] It should be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.
[0029] The embodiment of the present invention provides a clock synchronization method, device and storage medium. The clock synchronization method can be applied to a device, which can be an electronic device such as a mobile phone, a base station, a router, a server, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant and a wearable device. For example, the first clock source device is a mobile phone, the mobile phone obtains the slave clock configuration information, and generates and broadcasts a clock request configuration message according to the slave clock configuration information; establishes a clock link with multiple second clock source devices that perform master clock configuration according to the clock request configuration message, until the clock link of the first clock source device reaches a preset number and there is no abnormal clock link, and multiple clock links are obtained; selects a target clock link from the multiple clock links, and performs clock synchronization with the second clock source device corresponding to the target clock link through the target clock link.
[0030] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0031] Please refer to Figure 1 , Figure 1 A flowchart of a clock synchronization method provided by an embodiment of the present invention.
[0032] like Figure 1 As shown, the clock synchronization method includes steps S101 to S103.
[0033] Step S101: Obtain slave clock configuration information, and generate and broadcast a clock request configuration message according to the slave clock configuration information.
[0034] The slave clock configuration information is characteristic information for configuring the master and slave clocks, and includes a domain number, a user profile Profile type of an IP clock, and an Internet Protocol Address (IP address) of a first clock source device.
[0035] In one embodiment, the user management engine in the first clock source device configures the configuration function enable item of the 1588v2 clock to enable the first clock source device to enter the clock link configuration mode. The user management engine is a configuration function set in the first clock source device. The specific working mode of the user management engine can be set according to actual conditions. The embodiment of the present invention does not specifically limit this. The user management engine can accurately enable the first clock source device to enter the clock link configuration mode, greatly improving the efficiency of the clock link configuration.
[0036] It should be noted that the user management engine can also be set in other terminal devices, for example, the terminal device can be a mobile phone, and the mobile phone is configured with a user management engine. The user management engine in the mobile phone configures the configuration function enable item instruction of the 1588v2 clock, and sends the configuration function enable item instruction of the 1588v2 clock to the first clock source device. The first clock source device configures the configuration function enable item of the 1588v2 clock according to the configuration function enable item instruction of the 1588v2 clock. By controlling the configuration function enable item instruction of the 1588v2 clock configured by other terminal devices, the first clock source device configures the configuration function enable item of the 1588v2 clock, which can improve the flexibility of establishing a clock link.
[0037] In one embodiment, the slave clock configuration information is obtained to determine whether the first clock source device meets the condition that the clock source state is abnormal and is not used as the master clock device; when the first clock source device meets the condition that the clock source state is abnormal and is not used as the master clock device, a clock request configuration message is generated and broadcast according to the slave clock configuration information; when the first clock source device does not meet at least one of the conditions that the clock source state is abnormal and is not used as the master clock device, only a preset clock request configuration message is broadcast to establish a clock link according to the broadcast preset clock request configuration message. The preset clock request configuration message is. The preset clock request configuration message is pre-set in the first clock source device, and the preset clock request configuration message may be generated when the clock link is established last time. By determining whether the first clock source device meets the condition that the clock source state is abnormal and is not used as the master clock device, the efficiency and accuracy of establishing the clock link can be improved.
[0038] For example, Figure 2 As shown, step S201 detects whether the clock source state of the first clock source device is abnormal; when the clock source state of the first clock source device is not abnormal, execute step S202 to ensure that the first clock source device maintains the current configuration; when the clock source state of the first clock source device is abnormal, execute step S203 to determine whether the first clock source device serves as a 1588v2 master clock; when the first clock source device serves as a 1588v2 master clock, execute step S202 to ensure that the first clock source device maintains the current configuration; when the first clock source device does not serve as a 1588v2 master clock, execute step S204 to configure the first clock source device with a 1588v2 slave clock according to the slave clock configuration information; step S205 generates and broadcasts a clock request configuration message according to the slave clock configuration information.
[0039] In one embodiment, according to the slave clock configuration information, the method of generating and broadcasting the clock request configuration message can be: adding the clock request configuration flag, domain number, user profile type of the IP clock and device IP address in the message to generate the clock request configuration message, and broadcasting the clock request configuration message. By adding the clock request configuration flag, domain number, user profile type of the IP clock and device IP address in the message, the clock request configuration message can be accurately obtained, which greatly improves the efficiency and accuracy of establishing the clock link.
[0040] In one embodiment, after the clock request configuration message is generated, the clock request configuration message is broadcasted so that each second clock source device can receive the clock request configuration message. It should be noted that the scope of broadcasting the clock request configuration message can be determined according to actual conditions, and the embodiment of the present invention does not make specific limitations on this. For example, the broadcast scope is within a preset local area network, and the preset local area network can be set according to actual conditions. The embodiment of the present invention does not make specific limitations on this. For example, the preset local area network is a local area network composed of multiple base stations.
[0041] Step S102, establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message, until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links.
[0042] Among them, the clock link is a communication link used for clock synchronization.
[0043] In one embodiment, if Figure 3 As shown, step S102 includes sub-steps S1021 and S1022.
[0044] Sub-step S1021: When the clock link of the first clock source device does not reach the preset number, establish clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock link of the first clock source device reaches the preset number, thereby obtaining multiple clock links.
[0045] The preset number may be set according to actual conditions, and the embodiment of the present invention does not specifically limit this. For example, the preset number may be set to 5.
[0046] In one embodiment, when the clock link of the first clock source device does not reach the preset number, the second clock source device obtains the clock request configuration message, and when the preset master clock configuration condition is met, performs master clock configuration according to the clock request configuration message, generates master clock configuration information; and establishes a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information. The preset master clock configuration condition includes that the clock source state of the second clock source device is normal and it is not the master clock source or slave clock source of the first clock source device that broadcasts the clock request configuration message. The second clock source device performs master clock configuration according to the clock request configuration message, can accurately generate master clock configuration information, and establishes a clock link with the first clock source device according to the master clock configuration information.
[0047] In one embodiment, the master clock is configured according to the clock request configuration message, and the master clock configuration information is generated by: parsing the clock request configuration message, generating the domain number, the Profile type of the IP clock and the device IP address, and synchronously sending the domain number, the Profile type of the IP clock and the device IP address to the 1588v2 master clock to complete the configuration of the master clock.
[0048] In one embodiment, the method of establishing a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information may be: establishing a communication connection with the first clock source device according to the master clock configuration information, and establishing the clock link after interacting with the first clock source device through the clock message. The clock link can be accurately established after the first clock source device interacts with the second clock source device through the clock message.
[0049] For example, Figure 4 As shown, step S301, the second clock source device obtains a clock request configuration message; step S302 determines whether the clock source state of the second clock source device is abnormal; when the clock source state of the second clock source device is abnormal, execute step S303 to maintain the current configuration and end the establishment of the clock link; when the clock source state of the second clock source device is normal, step S304 determines whether the second clock source device serves as the master clock source or slave clock source of the first clock source device; when the second clock source device serves as the master clock source or slave clock source of the first clock source device, execute step S303 to maintain the current configuration and end the establishment of the clock link; when the second clock source device does not serve as the master clock source or slave clock source of the first clock source device, step S305 performs master clock configuration according to the clock request configuration message to generate master clock configuration information.
[0050] In one embodiment, when the clock link of the first clock source device does not reach the preset number, clock links are established with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock link of the first clock source device reaches the preset number, thereby obtaining multiple clock links. By establishing clock links with each second clock source device, multiple clock links can be accurately obtained, greatly improving the stability of clock synchronization.
[0051] In one embodiment, when the clock link of the first clock source device does not reach the preset number, and when there is a newly added second clock source device in the local area network where the first clock source device is located, a clock request configuration message is broadcasted; and a clock link is established with the newly added second clock source device that performs the master clock configuration according to the clock request configuration message. By establishing a clock link with the newly added second clock source device in the local area network, the number of clock links can be increased, and the stability of clock synchronization is improved.
[0052] For example, Figure 5 As shown, in the case where the clock link of the first clock source device 11 does not reach the preset number, where the preset number is 3, a clock request configuration message is generated and broadcast according to the slave clock configuration information, the second clock source device a21 receives the clock request configuration message, performs master clock configuration according to the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 11 according to the master clock configuration information; the second clock source device b22 receives the clock request configuration message, performs master clock configuration according to the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 11 according to the master clock configuration information; the second clock source device d24 receives the clock request configuration message, performs master clock configuration according to the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 11 according to the master clock configuration information. If the clock link of the first clock source device 11 has reached the preset number of 3, the first clock source device 11 does not establish a clock link with the second clock source device c23.
[0053] For example, Figure 6 As shown, the first clock source device 31 establishes clock links with the second clock source device e41, the second clock source device f42 and the second clock source device g43 respectively, and when there is a newly added second clock source device h44 in the local area network where the first clock source device 31 is located, a clock request configuration message is broadcast; the second clock source device h44 receives the clock request configuration message, performs master clock configuration according to the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 31 according to the master clock configuration information.
[0054] Sub-step S1022: When the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, rebuild each abnormal clock link until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining multiple reconstructed clock links.
[0055] In one embodiment, when the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, an abnormal clock link is deleted, and a clock link is re-established with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to a clock request configuration message; when it is determined that there are still abnormal clock links, the steps of deleting an abnormal clock link and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to a clock request configuration message are performed until there are no abnormal clock links, and multiple clock links are obtained. By deleting the abnormal clock link and re-establishing the clock link, the stability of clock synchronization is improved while maximizing the reuse of the resources of the second clock source device is achieved.
[0056] For example, Figure 7 As shown, step S401 determines whether the clock link of the first clock source device reaches the preset number; when the clock link of the first clock source device reaches the preset number, execute step S402 to determine whether there is an abnormal clock link; when there is no abnormal clock link, execute step S403 to determine that the clock link of the first clock source device has been established; when there is an abnormal clock link, execute step S404 to delete an abnormal clock link; step S405 broadcasts a clock request configuration message; when the clock link of the first clock source device does not reach the preset number, execute step S405 to broadcast a clock request configuration message; step S406 the second clock source device establishes a clock link with the first clock source device according to the clock request configuration message.
[0057] For example, Figure 8 As shown, the first clock source device 51 has established clock links with the second clock source device i61, the second clock source device j62 and the second clock source device k63 respectively, wherein there is an abnormality in the clock link between the first clock source device 51 and the second clock source device k63, the clock link between the first clock source device 51 and the second clock source device k63 is deleted, the first clock source device 51 broadcasts a clock request configuration message, the second clock source device m64 receives the clock request configuration message, and performs master clock configuration according to the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 51 according to the master clock configuration information.
[0058] Step S103: Select a target clock link from the multiple clock links, and perform clock synchronization with a second clock source device corresponding to the target clock link through the target clock link.
[0059] In one embodiment, a target clock link is selected from a plurality of clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link through the target clock link, so that the first clock source device and the second clock source device complete clock synchronization. The clock synchronization of the first clock source device and the second clock source device can be accurately and stably achieved through the target clock link.
[0060] It should be noted that the method of selecting the target clock link can be set according to actual conditions, and the embodiment of the present invention does not specifically limit this. For example, a clock link is randomly selected from multiple clock links as the target clock link.
[0061] In one embodiment, when the clock synchronization between the first clock source device and the second clock source device fails, the clock link with the second clock source device is disconnected, and a target clock link is selected from multiple clock links that have not failed, and clock synchronization is performed with the second clock source device corresponding to the target clock link through the target clock link. When the clock synchronization of the first clock source device fails, it can be switched to the clock link that has not failed in time to complete the clock synchronization, which greatly improves the accuracy and stability of the clock synchronization.
[0062] The clock synchronization method in the above embodiment obtains the slave clock configuration information, and generates and broadcasts the clock request configuration message according to the slave clock configuration information; then establishes clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message, until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, and multiple clock links are obtained; selects a target clock link from the multiple clock links, and performs clock synchronization with the second clock source device corresponding to the target clock link through the target clock link. This solution can accurately establish multiple clock links for the first clock source device and multiple second clock source devices, and perform clock synchronization based on the target clock link in the multiple clock links, which greatly improves the accuracy and stability of the clock synchronization of the first clock source device.
[0063] Please refer to Fig. 9 , Fig. 9 A schematic flow chart of another clock synchronization method provided by an embodiment of the present invention.
[0064] like Fig. 9 As shown, the clock synchronization method includes steps S501 to S503.
[0065] Step S501: Obtain a clock request configuration message, and if a preset master clock configuration condition is met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information.
[0066] In one embodiment, the user management engine in the first clock source device configures the configuration function enable item of the 1588v2 clock to enable the first clock source device to enter the clock link configuration mode. The user management engine is a configuration function set in the first clock source device. The user management engine can be set according to actual conditions. The embodiment of the present invention does not specifically limit this. The user management engine can accurately enable the first clock source device to enter the clock link configuration mode, greatly improving the efficiency of the clock link configuration.
[0067] In one embodiment, the slave clock configuration information is obtained to determine whether the first clock source device meets the condition that the clock source state is abnormal and is not used as the master clock device; when the first clock source device meets the condition that the clock source state is abnormal and is not used as the master clock device, a clock request configuration message is generated and broadcast according to the slave clock configuration information; when the first clock source device does not meet at least one of the conditions that the clock source state is abnormal and is not used as the master clock device, only a preset clock request configuration message is broadcast to establish a clock link according to the broadcast preset clock request configuration message. The preset clock request configuration message is. The preset clock request configuration message is pre-set in the first clock source device, and the preset clock request configuration message may be generated when the clock link is established last time. By determining whether the first clock source device meets the condition that the clock source state is abnormal and is not used as the master clock device, the efficiency and accuracy of establishing the clock link can be improved.
[0068] In one embodiment, when the clock link of the first clock source device does not reach the preset number, the second clock source device obtains the clock request configuration message, and when the preset master clock configuration condition is met, performs master clock configuration according to the clock request configuration message, generates master clock configuration information; and establishes a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information. The preset master clock configuration condition includes that the clock source state of the second clock source device is normal and it is not the master clock source or slave clock source of the first clock source device that broadcasts the clock request configuration message. The second clock source device performs master clock configuration according to the clock request configuration message, can accurately generate master clock configuration information, and establishes a clock link with the first clock source device according to the master clock configuration information.
[0069] Step S502: Establish a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information.
[0070] In one embodiment, the clock request configuration message is parsed to generate the domain number, the Profile type of the IP clock and the device IP address, and the domain number, the Profile type of the IP clock and the device IP address are synchronously sent to the 1588v2 master clock to complete the configuration of the master clock. A communication connection is established with the first clock source device according to the master clock configuration information, and a clock link is established after interacting with the first clock source device through the clock message. The clock link can be accurately established after the first clock source device interacts with the second clock source device through the clock message.
[0071] Step S503: Perform clock synchronization with the first clock source device through the clock link.
[0072] In one embodiment, after the clock link is established, clock synchronization is performed with the first clock source device according to the clock link. The clock link can accurately perform clock synchronization with the first clock source device, greatly improving the accuracy and stability of clock synchronization.
[0073] The clock synchronization method in the above embodiment obtains a clock request configuration message, and when the preset master clock configuration conditions are met, performs master clock configuration according to the clock request configuration message to generate master clock configuration information; establishes a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information; and performs clock synchronization with the first clock source device through the clock link, thereby greatly improving the accuracy and stability of clock synchronization.
[0074] See also Fig.10 , Fig.10 A schematic block diagram of the structure of a device provided in an embodiment of the present invention.
[0075] like Fig.10 As shown, the device 600 includes a processor 601 and a memory 602, and the processor 601 and the memory 602 are connected via a bus 603, such as an I2C (Inter-integrated Circuit) bus.
[0076] Specifically, the processor 601 is used to provide computing and control capabilities to support the operation of the entire device. The processor 601 can be a central processing unit (CPU), and the processor 601 can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
[0077] Specifically, the memory 602 may be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a mobile hard disk.
[0078] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present invention, and does not constitute a limitation on the device to which the scheme of the present invention is applied. The specific device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0079] The processor is used to run a computer program stored in a memory, and implement any one of the clock synchronization methods provided by the embodiments of the present invention when executing the computer program.
[0080] In one embodiment, the processor 601 is used to run a computer program stored in a memory, and implements the following steps when executing the computer program:
[0081] Obtaining slave clock configuration information, and generating and broadcasting a clock request configuration message according to the slave clock configuration information;
[0082] Establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links;
[0083] A target clock link is selected from the multiple clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link through the target clock link.
[0084] In one embodiment, after implementing the acquisition of slave clock configuration information, the processor 601 is further configured to implement:
[0085] Determine whether the first clock source device meets the condition that the clock source state is abnormal and does not serve as a master clock device;
[0086] When the first clock source device does not meet at least one of the conditions of abnormal clock source state and not serving as a master clock device, only a preset clock request configuration message is broadcasted to establish a clock link according to the broadcasted preset clock request configuration message.
[0087] In one embodiment, the clock request configuration message includes a clock request configuration flag, a domain number, a user configuration file Profile type of the IP clock, and a device IP address.
[0088] In one embodiment, the processor 601 is used to implement the establishment of clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, and multiple clock links are obtained, and is used to implement:
[0089] When the clock link of the first clock source device does not reach a preset number, establish clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock link of the first clock source device reaches a preset number, thereby obtaining multiple clock links;
[0090] When the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, each abnormal clock link is rebuilt until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining multiple rebuilt clock links.
[0091] In one embodiment, when the processor 601 realizes that the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, each abnormal clock link is rebuilt until there are no abnormal clock links in the clock links of the first clock source device, and a plurality of rebuilt clock links are obtained, the processor 601 is used to realize:
[0092] Deleting an abnormal clock link, and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to the clock request configuration message;
[0093] When it is determined that abnormal clock links still exist, the steps of deleting an abnormal clock link and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs are performed, until no abnormal clock links exist, and multiple clock links are obtained.
[0094] In one embodiment, the processor 601, when implementing the clock link of the first clock source device does not reach a preset number, establishes a clock link with a plurality of second clock source devices that perform master clock configuration according to the clock request configuration message, and is further configured to implement:
[0095] In the case where a newly added second clock source device exists in the local area network where the first clock source device is located, broadcasting the clock request configuration message;
[0096] A clock link is established with the newly added second clock source device that performs master clock configuration according to the clock request configuration message.
[0097] In one embodiment, after implementing the clock synchronization with the second clock source device corresponding to the target clock link through the target clock link, the processor 601 is further configured to implement:
[0098] When it is determined that the clock synchronization between the first clock source device and the second clock source device corresponding to the target clock link is abnormal, selecting a backup target clock link from the multiple clock links;
[0099] Clock synchronization is performed with a second clock source device corresponding to the target clock link through the backup target clock link.
[0100] In one embodiment, the processor 601 is further configured to implement:
[0101] Obtain a clock request configuration message, and if a preset master clock configuration condition is met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information;
[0102] Establish a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information; perform clock synchronization with the first clock source device through the clock link
[0103] In one embodiment, the preset master clock configuration condition includes that the clock source status of the second clock source device is normal and the second clock source device is not used as the master clock source or slave clock source of the first clock source device that broadcasts the clock request configuration message.
[0104] In one embodiment, the processor 601, when implementing the establishment of a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information, is configured to implement:
[0105] A communication connection is established with the first clock source device according to the master clock configuration information, and a clock link is established after interacting with the first clock source device through clock messages.
[0106] It should be noted that those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned clock synchronization method embodiment, and will not be repeated here.
[0107] An embodiment of the present invention also provides a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of any clock synchronization method provided in the specification of the present invention.
[0108] The storage medium may be an internal storage unit of the device described in the foregoing embodiment, such as a hard disk or memory of the device. The storage medium may also be an external storage device of the device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc., equipped on the device.
[0109] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
[0110] It should be understood that the term "and / or" used in the present specification refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations. It should be noted that, in this article, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a..." does not exclude the presence of other identical elements in the process, method, article or system including the element.
[0111] The serial numbers of the embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments. The above description is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be covered within the protection scope of the present invention.
Claims
1. A clock synchronization method, characterized in that: Applied to a first clock source device, the method comprises: Obtaining slave clock configuration information, and generating and broadcasting a clock request configuration message according to the slave clock configuration information; Establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links; A target clock link is selected from the multiple clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link through the target clock link.
2. The clock synchronization method according to claim 1, characterized in that: After acquiring the slave clock configuration information, the method further includes: Determine whether the first clock source device meets the condition that the clock source state is abnormal and does not serve as a master clock device; When the first clock source device does not meet at least one of the conditions of abnormal clock source state and not serving as a master clock device, only a preset clock request configuration message is broadcasted to establish a clock link according to the broadcasted preset clock request configuration message.
3. The clock synchronization method according to claim 2, characterized in that: The clock request configuration message includes a clock request configuration flag, a domain number, a user configuration file Profile type of the IP clock, and a device IP address.
4. The clock synchronization method according to claim 1, characterized in that: The step of establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links, includes: When the clock link of the first clock source device does not reach a preset number, establish clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock link of the first clock source device reaches a preset number, thereby obtaining multiple clock links; When the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, each abnormal clock link is rebuilt until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining multiple rebuilt clock links.
5. The clock synchronization method according to claim 4, characterized in that: When the clock links of the first clock source device reach a preset number and there are abnormal clock links, reconstructing each abnormal clock link until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining a plurality of reconstructed clock links, including: Deleting an abnormal clock link, and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to the clock request configuration message; When it is determined that abnormal clock links still exist, the steps of deleting an abnormal clock link and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs are performed, until no abnormal clock links exist, and multiple clock links are obtained.
6. The clock synchronization method according to claim 4, characterized in that: The step of establishing clock links with a plurality of second clock source devices that perform master clock configuration according to the clock request configuration message when the clock links of the first clock source device do not reach a preset number further includes: In the case where a newly added second clock source device exists in the local area network where the first clock source device is located, broadcasting the clock request configuration message; A clock link is established with the newly added second clock source device that performs master clock configuration according to the clock request configuration message.
7. The clock synchronization method according to claim 1, characterized in that: After performing clock synchronization with a second clock source device corresponding to the target clock link through the target clock link, the method further includes: When it is determined that the clock synchronization between the first clock source device and the second clock source device corresponding to the target clock link is abnormal, selecting a backup target clock link from the multiple clock links; Clock synchronization is performed with a second clock source device corresponding to the target clock link through the backup target clock link.
8. A clock synchronization method, characterized in that: Applied to a second clock source device, the method comprises: Obtain a clock request configuration message, and if a preset master clock configuration condition is met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information; Establishing a clock link with a first clock source device that broadcasts the clock request configuration message according to the master clock configuration information; Clock synchronization is performed with the first clock source device via the clock link.
9. The clock synchronization method according to claim 8, characterized in that: The preset master clock configuration condition includes that the clock source status of the second clock source device is normal and the second clock source device is not used as the master clock source or slave clock source of the first clock source device that broadcasts the clock request configuration message.
10. The clock synchronization method according to claim 8, characterized in that: The step of establishing a clock link with a first clock source device that broadcasts the clock request configuration message according to the master clock configuration information includes: A communication connection is established with the first clock source device according to the master clock configuration information, and a clock link is established after interacting with the first clock source device through clock messages.
11. A device, characterized in that: The device includes a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of the clock synchronization method as described in any one of claims 1 to 10 are realized.
12. A storage medium for computer-readable storage, characterized in that: The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the clock synchronization method according to any one of claims 1 to 10.