Variable-length data frame receiving method and device, storage medium and electronic equipment
Determine the sending time through SPI interrupts and timers, and use DMA to receive unfixed data frames, solving the problem of data accumulation and analysis processing of DMA mode when processing unfixed data in SPI communication increases application burden, realizing more efficient data reception .
Patent Information
- Application Number
- CN202411123551.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-15
- Publication Date
- 2024-12-27
AI Technical Summary
When the SPI communication protocol processes uncertain data, the DMA method has the problem of data accumulation and parsing processing increasing the application burden, which limits the ability of the SPI slave to receive uncertain data using DMA alone.
Through the SPI interrupt and timer, the transmission time of the longest byte data frame in the unfixed data frame is determined to the slave side to send the slave side the transmission time, and the timing time of the timer is updated to trigger the timing of the slave side based on each transmission time. , receive indefinitely long data frames through DMA data reception.
It reduces data accumulation in DMA registers, improves the integrity and accuracy of data reception, reduces application burden, and enhances the ability of SPI slaves to receive uncertain data.
Smart Images
Figure CN119211395A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of communication technology, and in particular to a method for receiving a data frame of indefinite length, a device for receiving a data frame of indefinite length, a storage medium, and an electronic device. Background Art
[0002] SPI (Serial Peripheral Interface) is a synchronous serial data communication protocol, usually used to transfer data between microcontrollers or embedded systems. DMA (Direct Memory Access) is a data transmission method in computer systems, which allows peripherals (such as hard disks, network interfaces, audio devices, etc.) to directly access system memory without the intervention of the central processing unit (CPU). However, DMA has certain disadvantages when processing variable-length data, that is, the length of the transmission byte needs to be set before each transmission, and because the idle state of the SPI bus cannot be obtained, multiple frames of data are stacked in the DMA buffer, and the application needs to perform additional data parsing and processing, which increases the application burden. Therefore, the SPI slave uses DMA alone to receive variable-length data, which has obvious limitations. Summary of the invention
[0003] In view of this, the embodiments of the present disclosure are intended to provide a method for receiving a data frame of indefinite length, a device for receiving a data frame of indefinite length, a storage medium, and an electronic device.
[0004] The technical solution of the present disclosure is achieved as follows:
[0005] In a first aspect, the present disclosure provides a method for receiving a data frame of indefinite length, which is applied to a slave side based on SPI communication.
[0006] The method for receiving a variable-length data frame provided by an embodiment of the present disclosure includes:
[0007] Based on the SPI interrupt and timer, determine the sending time of the longest byte data frame in the indefinite length data frame sent by the host side to the slave side;
[0008] Updating the timing duration of the timer to the sending duration;
[0009] Based on the SPI interrupt and the timer with the sending duration, the slave side is triggered to receive the variable-length data frame sent by the host side through a DMA data receiving mode based on the timing of each sending duration.
[0010] In some embodiments, the method of triggering the slave side to receive the variable-length data frame sent by the host side through a DMA data receiving mode based on the timing of each sending duration based on the SPI interrupt and the timer having the sending duration includes:
[0011] When the slave side starts to receive the indefinite length data frame sent by the host side, it enters the SPI receive non-empty interrupt and executes the timing interrupt function;
[0012] By executing the timing interrupt function, the timer is turned on, timing is started, and data reception is started through DMA mode;
[0013] When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the indefinite-length data frame is received and completed in DMA mode.
[0014] In some embodiments, the receiving of the variable-length data frame in a DMA manner includes:
[0015] Determine the number of bytes remaining in the DMA register after the DMA mode data reception is completed;
[0016] Based on the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received, the byte length of the variable-length data frame sent by the host side this time is determined.
[0017] In some embodiments, determining the sending duration used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side based on the SPI interrupt and the timer includes:
[0018] Initialize the timer duration and set the maximum number of bytes that DMA can receive;
[0019] The slave side starts polling to detect the level state of the SPI CS chip select pin. When it is detected that the host side pulls down the SPI CS chip select pin and starts to send the first byte of the longest byte data frame, the slave enters the receive non-empty interrupt and records the current time T1;
[0020] When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data and records the current time T2;
[0021] The time difference between the current time T2 and the current time T1 is determined as the sending duration used by the host side to send the longest byte data frame in the indefinite-length data frame to the slave side.
[0022] In a second aspect, the present disclosure provides a variable-length data frame receiving device, which is applied to a slave side based on SPI communication, comprising:
[0023] A sending duration determination module is used to determine the sending duration used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side based on the SPI interrupt and the timer;
[0024] A timing duration updating module, used for updating the timing duration of the timer to the sending duration;
[0025] The data receiving module is used to trigger the timing of each transmission duration on the slave side based on the SPI interrupt and the timer with the transmission duration, and receive the variable-length data frame sent by the host side through the DMA data receiving mode.
[0026] In some embodiments, the data receiving module is used to
[0027] When the slave side starts to receive the indefinite length data frame sent by the host side, it enters the SPI receive non-empty interrupt and executes the timing interrupt function;
[0028] By executing the timing interrupt function, the timer is turned on, timing is started, and data reception is started through DMA mode;
[0029] When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the indefinite-length data frame is received and completed in DMA mode.
[0030] In some embodiments, the data receiving module is used to
[0031] Determine the number of bytes remaining in the DMA register after the DMA mode data reception is completed;
[0032] Based on the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received, the byte length of the variable-length data frame sent by the host side this time is determined.
[0033] In some embodiments, the sending duration determination module is used to
[0034] Initialize the timer duration and set the maximum number of bytes that DMA can receive;
[0035] The slave side starts polling to detect the level state of the SPI CS chip select pin. When it is detected that the host side pulls down the SPI CS chip select pin and starts to send the first byte of the longest byte data frame, the slave enters the receive non-empty interrupt and records the current time T1;
[0036] When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data and records the current time T2;
[0037] The time difference between the current time T2 and the current time T1 is determined as the sending duration used by the host side to send the longest byte data frame in the indefinite-length data frame to the slave side.
[0038] In a third aspect, the present disclosure provides a computer-readable storage medium having a variable-length data frame receiving program stored thereon. When the variable-length data frame receiving program is executed by a processor, the variable-length data frame receiving method described in the first aspect is implemented.
[0039] In a fourth aspect, the present disclosure provides an electronic device comprising a memory, a processor, and a variable-length data frame receiving program stored in the memory and executable on the processor, wherein when the processor executes the variable-length data frame receiving program, the variable-length data frame receiving method described in the first aspect is implemented.
[0040] The variable-length data frame receiving method provided by the embodiment of the present disclosure includes: based on the SPI interrupt and the timer, determining the sending duration used by the host side to send the longest byte data frame in the variable-length data frame to the slave side; updating the timing duration of the timer to the sending duration; based on the SPI interrupt and the timer with the sending duration, triggering the slave side to receive the variable-length data frame sent by the host side based on the timing of each sending duration. In the present application, the timer timing duration is set to the sending duration used by the host side to send the longest byte data frame in the variable-length data frame to the slave side, so that the slave can complete the complete reception of each frame of the variable-length data frame through the DMA method, which is conducive to reducing the data accumulation in the DMA register.
[0041] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 is a flow chart of a method for receiving a data frame of indefinite length according to an exemplary embodiment;
[0043] Figure 2 is a schematic diagram of hardware connection according to an exemplary embodiment;
[0044] Figure 3 is a flow chart of a process for receiving a data frame of indefinite length according to an exemplary embodiment;
[0045] Figure 4 It is a schematic diagram of the structure of a device for receiving data frames of variable length according to an exemplary embodiment. DETAILED DESCRIPTION
[0046] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.
[0047] SPI (Serial Peripheral Interface) is a synchronous serial data communication protocol, usually used to transfer data between microcontrollers or embedded systems. DMA (Direct Memory Access) is a data transmission method in computer systems, which allows peripherals (such as hard disks, network interfaces, audio devices, etc.) to directly access system memory without the intervention of the central processing unit (CPU). However, DMA has certain disadvantages when processing variable-length data, that is, the length of the transmission byte needs to be set before each transmission, and because the idle state of the SPI bus cannot be obtained, multiple frames of data are stacked in the DMA buffer, and the application needs to perform additional data parsing and processing, which increases the application burden. Therefore, the SPI slave uses DMA alone to receive variable-length data, which has obvious limitations.
[0048] In view of the above situation, the present disclosure provides a method for receiving a data frame of indefinite length, which is applied to a slave side based on SPI communication. Figure 1 FIG. 1 is a flow chart of a method for receiving a data frame of variable length according to an exemplary embodiment. Figure 1 As shown, the variable-length data frame receiving method includes:
[0049] Step 10: Based on the SPI interrupt and the timer, determine the sending time length used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side;
[0050] Step 11, updating the timing duration of the timer to the sending duration;
[0051] Step 12: Based on the SPI interrupt and the timer with the transmission duration, trigger the slave side to receive the variable-length data frame sent by the host side through a DMA data receiving mode based on the timing of each transmission duration.
[0052] In this exemplary embodiment, when the slave side receives the variable-length data frame sent by the host side through the DMA data receiving mode, since the DMA register itself does not know the idle state of the SPI bus, the DMA register itself does not know when the data transmission of the host side ends, causing the slave to be unable to sort out different data frames when reading data, which easily causes confusion in data reception. In this regard, an interrupt plus timer method is adopted to set the data reception duration, and the timing duration of the timer is determined to be the transmission duration used by the host side to send the longest byte data frame in the variable-length data frame to the slave side. In this way, the slave side can fully receive after the host side sends a frame of data, receive a complete frame of variable-length data frame, and then the host sends the next frame of variable-length data frame, and the slave receives data again. In this way, the situation of data reception confusion on the slave side can be reduced.
[0053] In some embodiments, the method of triggering the slave side to receive the variable-length data frame sent by the host side through a DMA data receiving mode based on the timing of each sending duration based on the SPI interrupt and the timer having the sending duration includes:
[0054] When the slave side starts to receive the indefinite length data frame sent by the host side, it enters the SPI receive non-empty interrupt and executes the timing interrupt function;
[0055] By executing the timing interrupt function, the timer is turned on, timing is started, and data reception is started through DMA mode;
[0056] When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the indefinite-length data frame is received and completed in DMA mode.
[0057] In this exemplary embodiment, when receiving variable-length data frames in DMA mode, it is necessary to start a timer for timing when the slave side starts to receive the variable-length data frames sent by the host side, and complete the reception of the variable-length data frames within the timing time. This can be achieved by starting an SPI interrupt, for example, entering the SPI receive non-empty interrupt and executing the timing interrupt function. Then, by executing the timing interrupt function, the timer is turned on and the timing is started. After the timer starts timing, the slave side starts to receive data in DMA mode. When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the variable-length data frame is received in DMA mode. That is, the reception of the variable-length data frame is completed in DMA mode.
[0058] In some embodiments, the receiving of the variable-length data frame in a DMA manner includes:
[0059] Determine the number of bytes remaining in the DMA register after the DMA mode data reception is completed;
[0060] Based on the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received, the byte length of the variable-length data frame sent by the host side this time is determined.
[0061] In this exemplary embodiment, since the received data frame is of indefinite length, after the indefinite length data frame is received, the byte length of the received indefinite length data frame needs to be determined. To this end, the byte length of the indefinite length data frame sent by the host side this time can be determined by the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received. For example, if the maximum number of bytes that can be received by the DMA register is 2M and the remaining number of bytes that can be received is 0.5M, then the byte length of the indefinite length data frame sent by the host side this time is 1.5M.
[0062] In this exemplary embodiment, Figure 2 FIG. 1 is a schematic diagram of hardware connection according to an exemplary embodiment. Figure 2 As shown, the SPI master and the SPI slave are connected through four lines: SCLK (clock line), MOSI (master output, slave input, unidirectional transmission), MISO (master input, slave output, unidirectional transmission), and CS (chip select signal, used by the master to select the slave).
[0063] In this exemplary embodiment, when the host side and the slave side start the normal transmission of the protocol frame, the SPI slave starts to receive the indefinite length data frame of the SPI host. The slave side enters the SPI receive non-empty interrupt, starts the timer in its interrupt function, and sets the timer timeout to T. When the timeout is reached, the timing interrupt function is entered, and the timer is turned off in the timing interrupt function. Then the DMA register is read to obtain the number of bytes remaining unread in the DMA, and finally the maximum number of bytes that can be received by setting the DMA to subtract the remaining number of bytes that can be received will be obtained to obtain the number of bytes received in this transmission (maximum number of bytes that can be received-remaining number of bytes that can be received=number of bytes received). After waiting for the number of bytes received this time, it is processed, and finally the DMA is reset to the idle state, and the second SPI DMA reception is prepared at the same time.
[0064] In some embodiments, determining the sending duration used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side based on the SPI interrupt and the timer includes:
[0065] Initialize the timer duration and set the maximum number of bytes that DMA can receive;
[0066] The slave side starts polling to detect the level state of the SPI CS chip select pin. When it is detected that the host side pulls down the SPI CS chip select pin and starts to send the first byte of the longest byte data frame, the slave enters the receive non-empty interrupt and records the current time T1;
[0067] When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data and records the current time T2;
[0068] The time difference between the current time T2 and the current time T1 is determined as the sending duration used by the host side to send the longest byte data frame in the indefinite-length data frame to the slave side.
[0069] In this exemplary embodiment, Figure 3 FIG. 1 is a flow chart of a process for receiving a data frame of variable length according to an exemplary embodiment. Figure 3 As shown in FIG. 1 , the receiving process of the variable-length data frame includes:
[0070] Step 30, start;
[0071] Step 31, the slave SPI, timer and DMA controller are initialized, the slave multiplexes the SPI CS chip select pin as GPIO, the slave SPI interrupt mode is configured as RXNE (receive not empty interrupt), and the slave is enabled to set the timer timeout time T0 and the DMA transfer byte number to the maximum receivable byte number;
[0072] Step 32, the slave enables timer and DMA;
[0073] Step 33, the slave polls and detects the CS chip select pin;
[0074] Step 34, the host pulls down the SPI CS chip select pin to select the slave, the host is ready to send data, and the slave starts to receive the longest frame of indefinite length data frames. When the slave receives the first byte sent by the host, the slave enters the receive non-empty interrupt, and the current time T1 is recorded at this time;
[0075] Step 35, the slave receives the remaining bytes, enters the slave receiving non-empty interrupt, records and updates the current time T2;
[0076] Step 36, the host pulls up the chip select pin, releases the slave, and determines that the host has completed sending data;
[0077] Step 37, the slave polling detects that the CS pin changes from low level to high level, checks the time T2, and determines that the slave has completed receiving data;
[0078] Step 38, the slave timer is reinitialized and the timeout period is set to T=T2-T1;
[0079] Step 39, the slave SPI starts receiving data;
[0080] Step 40, the slave receives a non-empty interrupt and starts the timer;
[0081] Step 41, slave timer interrupt;
[0082] Step 42, turn off the slave timer and read the DMA register to obtain the number of remaining receivable bytes;
[0083] Step 43, determine the number of bytes received by the slave = the maximum number of bytes that can be received - the remaining number of bytes that can be received;
[0084] Step 44 : The slave DMA is reset to idle to execute step 39 .
[0085] like Figure 3It is a schematic diagram of the software control flow in the present invention. First, the slave peripherals are initialized (including the initialization of the slave SPI, timer and DMA controller), the slave SPI CS chip select pin is multiplexed as GPIO, and the slave SPI interrupt mode is configured as RXNE (receive non-empty interrupt) (an interrupt is entered each time data is received). Here, the timer timeout time can be set to be long enough for the first time, and the value is T0 (such as 1 hour, etc.), and the maximum number of bytes that can be received by DMA is set to be large enough. Then the slave starts polling to detect the level state of the SPI CS chip select pin. When the host sends a fixed-length frame (here, the longest frame in the variable-length data frame), the host pulls down the SPI CS chip select pin, selects the slave, and the slave starts to prepare to receive data. When the slave receives the first byte sent by the host, the slave enters the receive non-empty interrupt, and the current time T1 is recorded at this time. When the next byte is received again, the current time T2 is recorded and updated in the receive non-empty interrupt. When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data. At this time, check the time T2 and determine that the slave has finished receiving data at time T2. If T2 is no longer accumulated, the reception is completed. (T2-T1 is the transmission time of the longest data frame transmitted this time, which is determined as the transmission time used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side). At this time, reinitialize the timer, reset the timer timeout to T (T=T2-T1), and start normal data communication with the host.
[0086] The present disclosure provides a variable-length data frame receiving device, which is applied to a slave side based on SPI communication. Figure 4 FIG. 1 is a schematic diagram of a structure of a device for receiving a data frame of indefinite length according to an exemplary embodiment. Figure 4 As shown, the variable-length data frame receiving device includes:
[0087] The sending duration determination module 40 is used to determine the sending duration used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side based on the SPI interrupt and the timer;
[0088] A timing duration updating module 41, used for updating the timing duration of the timer to the sending duration;
[0089] The data receiving module 42 is used to trigger the timing of each transmission duration on the slave side based on the SPI interrupt and the timer with the transmission duration, and receive the variable-length data frame sent by the host side through the DMA data receiving mode.
[0090] In this exemplary embodiment, when the slave side receives the variable-length data frame sent by the host side through the DMA data receiving mode, since the DMA register itself does not know the idle state of the SPI bus, the DMA register itself does not know when the data transmission of the host side ends, causing the slave to be unable to sort out different data frames when reading data, which easily causes confusion in data reception. In this regard, an interrupt plus timer method is adopted to set the data reception duration, and the timing duration of the timer is determined to be the transmission duration used by the host side to send the longest byte data frame in the variable-length data frame to the slave side. In this way, the slave side can fully receive after the host side sends a frame of data, receive a complete frame of variable-length data frame, and then the host sends the next frame of variable-length data frame, and the slave receives data again. In this way, the situation of data reception confusion on the slave side can be reduced.
[0091] In some embodiments, the data receiving module is used to
[0092] When the slave side starts to receive the indefinite length data frame sent by the host side, it enters the SPI receive non-empty interrupt and executes the timing interrupt function;
[0093] By executing the timing interrupt function, the timer is turned on, timing is started, and data reception is started through DMA mode;
[0094] When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the indefinite-length data frame is received and completed in DMA mode.
[0095] In this exemplary embodiment, when receiving variable-length data frames in DMA mode, it is necessary to start a timer for timing when the slave side starts to receive the variable-length data frames sent by the host side, and complete the reception of the variable-length data frames within the timing time. This can be achieved by starting an SPI interrupt, for example, entering the SPI receive non-empty interrupt and executing the timing interrupt function. Then, by executing the timing interrupt function, the timer is turned on and the timing is started. After the timer starts timing, the slave side starts to receive data in DMA mode. When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the variable-length data frame is received in DMA mode. That is, the reception of the variable-length data frame is completed in DMA mode.
[0096] In some embodiments, the data receiving module is used to
[0097] Determine the number of bytes remaining in the DMA register after the DMA mode data reception is completed;
[0098] Based on the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received, the byte length of the variable-length data frame sent by the host side this time is determined.
[0099] In this exemplary embodiment, since the received data frame is of indefinite length, after the indefinite length data frame is received, the byte length of the received indefinite length data frame needs to be determined. To this end, the byte length of the indefinite length data frame sent by the host side this time can be determined by the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received. For example, if the maximum number of bytes that can be received by the DMA register is 2M and the remaining number of bytes that can be received is 0.5M, then the byte length of the indefinite length data frame sent by the host side this time is 1.5M.
[0100] In this exemplary embodiment, when the host side and the slave side start the normal transmission of the protocol frame, the SPI slave starts to receive the indefinite length data frame of the SPI host. The slave side enters the SPI receive non-empty interrupt, starts the timer in its interrupt function, and sets the timer timeout to T. When the timeout is reached, the timing interrupt function is entered, and the timer is turned off in the timing interrupt function. Then the DMA register is read to obtain the number of bytes remaining unread in the DMA, and finally the maximum number of bytes that can be received by setting the DMA to subtract the remaining number of bytes that can be received will be obtained to obtain the number of bytes received in this transmission (maximum number of bytes that can be received-remaining number of bytes that can be received=number of bytes received). After waiting for the number of bytes received this time, it is processed, and finally the DMA is reset to the idle state, and the second SPI DMA reception is prepared at the same time.
[0101] In some embodiments, the sending duration determination module is used to
[0102] Initialize the timer duration and set the maximum number of bytes that DMA can receive;
[0103] The slave side starts polling to detect the level state of the SPI CS chip select pin. When it is detected that the host side pulls down the SPI CS chip select pin and starts to send the first byte of the longest byte data frame, the slave enters the receive non-empty interrupt and records the current time T1;
[0104] When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data and records the current time T2;
[0105] The time difference between the current time T2 and the current time T1 is determined as the sending duration used by the host side to send the longest byte data frame in the indefinite-length data frame to the slave side.
[0106] In this exemplary embodiment, the slave peripherals are first initialized (including the initialization of the slave SPI, timer, and DMA controller), the slave SPI CS chip select pin is multiplexed as GPIO, and the slave SPI interrupt mode is configured as RXNE (receive non-empty interrupt) (an interrupt is entered each time data is received), and the timer timeout time can be set to be long enough for the first time, taking the value T0 (such as 1 hour, etc.), and the maximum number of bytes that can be received by DMA is set to be large enough. Then the slave starts polling to detect the level state of the SPI CS chip select pin. When the host sends a fixed-length frame (here, the longest frame in the variable-length data frame), the host pulls down the SPI CS chip select pin, selects the slave, and the slave starts to prepare to receive data. When the slave receives the first byte sent by the host, the slave enters the receive non-empty interrupt, and the current time T1 is recorded at this time. When the next byte is received again, the current time T2 is recorded and updated in the receive non-empty interrupt. When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data. At this time, check the time T2 and determine that the slave has finished receiving data at time T2. If T2 is no longer accumulated, the reception is completed. (T2-T1 is the transmission time of the longest data frame transmitted this time, which is determined as the transmission time used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side). At this time, reinitialize the timer, reset the timer timeout to T (T=T2-T1), and start normal data communication with the host.
[0107] The present disclosure provides a computer-readable storage medium on which a variable-length data frame receiving program is stored. When the variable-length data frame receiving program is executed by a processor, the variable-length data frame receiving method described in the above embodiments is implemented.
[0108] The present disclosure provides an electronic device, including a memory, a processor, and a variable-length data frame receiving program stored in the memory and executable on the processor. When the processor executes the variable-length data frame receiving program, the variable-length data frame receiving method described in the above embodiments is implemented.
[0109] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can determine instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.
[0110] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.
[0111] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0112] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.
[0113] In addition, the terms "first", "second", etc. used in the embodiments of the present disclosure are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the embodiments. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present disclosure may explicitly or implicitly indicate that at least one of the features is included in the embodiment. In the description of the present disclosure, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.
[0114] In the present disclosure, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. appearing in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific implementation situation.
[0115] In the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0116] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.
Claims
1. A method for receiving a data frame of indefinite length, characterized in that: Applied to the slave side based on SPI communication, including: Based on the SPI interrupt and timer, determine the sending time of the longest byte data frame in the indefinite length data frame sent by the host side to the slave side; Updating the timing duration of the timer to the sending duration; Based on the SPI interrupt and the timer with the sending duration, the slave side is triggered to receive the variable-length data frame sent by the host side through a DMA data receiving mode based on the timing of each sending duration.
2. The method for receiving variable-length data frames according to claim 1, wherein: The method of triggering the slave side to receive the variable-length data frame sent by the host side through a DMA data receiving mode based on the timing of each sending duration based on the SPI interrupt and the timer having the sending duration includes: When the slave side starts to receive the indefinite length data frame sent by the host side, it enters the SPI receive non-empty interrupt and executes the timing interrupt function; By executing the timing interrupt function, the timer is turned on, timing is started, and data reception is started through DMA mode; When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the indefinite-length data frame is received and completed in DMA mode.
3. The method for receiving variable-length data frames according to claim 2, wherein: The receiving and completing the variable-length data frame in a DMA manner includes: Determine the number of bytes remaining in the DMA register after the DMA mode data reception is completed; Based on the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received, the byte length of the variable-length data frame sent by the host side this time is determined.
4. The method for receiving variable-length data frames according to claim 1, wherein: The method of determining the sending duration of the longest byte data frame in the indefinite-length data frame sent from the host side to the slave side based on the SPI interrupt and the timer includes: Initialize the timer duration and set the maximum number of bytes that DMA can receive; The slave side starts polling to detect the level state of the SPI CS chip select pin. When it is detected that the host side pulls down the SPI CS chip select pin and starts to send the first byte of the longest byte data frame, the slave enters the receive non-empty interrupt and records the current time T1; When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data and records the current time T2; The time difference between the current time T2 and the current time T1 is determined as the sending duration used by the host side to send the longest byte data frame in the indefinite-length data frame to the slave side.
5. A device for receiving data frames of indefinite length, characterized in that: Applied to the slave side based on SPI communication, including: A sending duration determination module is used to determine the sending duration used by the host side to send the longest byte data frame in the indefinite length data frame to the slave side based on the SPI interrupt and the timer; A timing duration updating module, used for updating the timing duration of the timer to the sending duration; The data receiving module is used to trigger the timing of each transmission duration on the slave side based on the SPI interrupt and the timer with the transmission duration, and receive the variable-length data frame sent by the host side through the DMA data receiving mode.
6. The variable-length data frame receiving device according to claim 5, characterized in that: The data receiving module is used to When the slave side starts to receive the indefinite length data frame sent by the host side, it enters the SPI receive non-empty interrupt and executes the timing interrupt function; By executing the timing interrupt function, the timer is turned on, timing is started, and data reception is started through DMA mode; When the timing reaches the sending duration, the timer is turned off by executing the timing interrupt function, and the data reception in DMA mode is ended, thereby completing the reception of the indefinite-length data frame sent by the host side this time.
7. The variable-length data frame receiving device according to claim 6, characterized in that: The data receiving module is used to Determine the number of bytes remaining in the DMA register after the DMA mode data reception is completed; Based on the maximum number of bytes that can be received by the DMA register and the remaining number of bytes that can be received, the byte length of the variable-length data frame sent by the host side this time is determined.
8. The variable-length data frame receiving device according to claim 5, characterized in that: The sending duration determination module is used to Initialize the timer duration and set the maximum number of bytes that DMA can receive; The slave side starts polling to detect the level state of the SPI CS chip select pin. When it is detected that the host side pulls down the SPI CS chip select pin and starts to send the first byte of the longest byte data frame, the slave enters the receive non-empty interrupt and records the current time T1; When the slave detects that the chip select pin changes from low level to high level, it determines that the host has finished sending data and records the current time T2; The time difference between the current time T2 and the current time T1 is determined as the sending duration used by the host side to send the longest byte data frame in the indefinite-length data frame to the slave side.
9. A computer-readable storage medium, characterized in that: A variable-length data frame receiving program is stored thereon, and when the variable-length data frame receiving program is executed by a processor, the variable-length data frame receiving method described in any one of claims 1-4 is implemented.
10. An electronic device, characterized in that: It includes a memory, a processor, and a variable-length data frame receiving program stored in the memory and executable on the processor. When the processor executes the variable-length data frame receiving program, it implements the variable-length data frame receiving method described in any one of claims 1 to 4.