Memory array and method for forming memory array including strings of memory cells

Abstract

The invention relates to a memory array and a method for forming a memory array including strings of memory cells. A method for forming a memory array includes forming a stack including vertically alternating first and second layers. A first insulator material is over the stack. The first insulator material includes at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. A string of channel material is in the uppermost material directly above the stack and protrudes upward from the uppermost material. Conductive material directly abuts against respective lateral inner sides of the upwardly protruding channel material strings and upwardly protrudes from the individual upwardly protruding channel material strings. Circular rings each including an insulating material circumferentially around the upwardly protruding conductive material are formed. A second insulator material is formed over the first insulator material, the annulus, and the upwardly protruding conductive material.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of an invention patent application with an application date of October 20, 2020, application number 202011122699.0, and invention name “Memory array and method for forming a memory array including a memory cell string”. Technical Field

[0003] Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays including strings of memory cells. Background Art

[0004] A memory is an integrated circuit and is used in computer systems to store data. The memory may be fabricated in one or more arrays of individual memory cells. The memory cells may be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines may interconnect the memory cells in a conductive manner along the columns of the array, and the access lines may interconnect the memory cells in a conductive manner along the rows of the array. Each memory cell may be uniquely addressable by a combination of the sense lines and the access lines.

[0005] Memory cells can be volatile, semi-volatile or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is usually specified as a memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of several milliseconds or less. In any case, the memory cell is configured to retain or store storage content in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some of the individual memory cells can be configured to store information of more than two bits or states.

[0006] Field effect transistors are electronic components that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0007] Flash memory is a type of memory that is used extensively in modern computers and devices. For example, a modern personal computer may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of solid-state drives in place of conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0008] NAND can be the basic architecture of integrated flash memory. A NAND cell component includes at least one selection device coupled in series to a series combination of memory cells (wherein the series combination is generally referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement, including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include transistors.

[0009] The memory array may be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, such as shown and described in any of U.S. Patent Application Publications No. 2015 / 0228659, No. 2016 / 0267984, and No. 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, on which vertically extending conductive vias contact to provide electrical access to the word lines. Summary of the invention

[0010] In one aspect, the present application provides a method for forming a memory array, comprising: forming a stack including vertically alternating first and second layers, with a first insulator material above the stack; the first insulator material including at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; a channel material string is in the uppermost material directly above the stack and protrudes upward from the uppermost material, and a conductive material directly abuts against the respective lateral inner side of the upwardly protruding channel material string and protrudes upward from the individual upwardly protruding channel material string; forming an annular ring including an insulating material each circumferentially surrounding the upwardly protruding conductive material; forming a second insulator material above the first insulator material, the annular ring and the upwardly protruding conductive material; the first insulator material and the second insulator material include different compositions relative to each other; and forming conductive vias in the second insulator material, each of the conductive vias being directly electrically coupled to the individual channel material string through the upwardly protruding conductive material.

[0011] In another aspect, the present application provides a method for forming a memory array, comprising: forming a stack comprising a first layer and a second layer alternating vertically; forming a first insulator material above the stack, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; forming a string of channel materials in the uppermost material directly above the stack and protruding upward from the uppermost material, with memory cell materials along each of the channel materials, and conductive materials directly against the lateral inner side of each of the upwardly protruding channel material strings; making the channel The channel material of the material string is vertically recessed and the memory cell material is vertically recessed to form the conductive material that protrudes upward from the individual upwardly protruding channel material string; an annular ring is formed that circumferentially surrounds the upwardly protruding conductive material and directly abuts the upwardly protruding conductive material and includes an insulating material; a second insulator material is formed over the first insulator material, the annular ring and the upwardly protruding conductive material; the first insulator material and the second insulator material include different compositions relative to each other; and conductive vias are formed in the second insulator material, each of which is directly electrically coupled to the individual channel material string through the upwardly protruding conductive material.

[0012] In another aspect, the present application provides a memory array comprising: a vertical stack comprising alternating insulating layers and conductive layers, a channel material string of a memory cell being in the stack, the channel material string protruding upward above the stack, conductive material being directly against each lateral inner side of the upwardly protruding channel material string and protruding upward from the individual upwardly protruding channel material string; a first insulator material being above the stack and next to the lateral outer side of the channel material string, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; an annulus, each circumferentially surrounding the upwardly protruding conductive material comprising an insulating material; a second insulator material being above the first insulator material, the annulus and the upwardly protruding conductive material; the first insulator material and the second insulator material comprising different compositions relative to each other; and conductive vias being in the second insulator material, each of the conductive vias being directly electrically coupled to the individual channel material string through the upwardly protruding conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It passes through Figure 2 A diagrammatic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention, taken along line 1 - 1 in FIG.

[0014] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0015] Figure 3 , 3A , 3B, 4, 4A, 4B, 5, 5A, 6, 7, 7A-9A, 10, 11, 11A, 12, 13, 13A, 14-17A, 18, 19, 19A, 20, 21 and 21A are examples of processes according to some embodiments of the present invention. Figure 1 and 2 Diagrammatical representations of the structure or parts thereof in sequential cross-sectional and / or enlarged views.

[0016] Fig. 22 , 22A , 23 and 23A illustrate alternative example method and / or structural embodiments of the present invention. DETAILED DESCRIPTION

[0017] Embodiments of the present invention encompass methods for forming a memory array, such as an array of NAND or other memory cells with peripheral control circuitry beneath the array (e.g., CMOS-under-array). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, whether existing or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass a memory array (e.g., a NAND architecture) that is independent of the method of manufacture. Reference may be made to what may be considered a "gate-last" or "replacement-gate" process. Figure 1-21A Example method embodiments are described.

[0018] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive / conductive / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrically herein) materials. Various materials are formed vertically over base substrate 11. The materials may be Figure 1 and 2 1. The base substrate 11 may be provided with a plurality of subarrays or arrays of memory cells. For example, other partially fabricated or fully fabricated components of the integrated circuit may be provided somewhere above, around, or within the base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within an array of vertically extending memory cell strings (e.g., array 12) may also be fabricated, and may or may not be completely or partially within an array or subarray. In addition, multiple subarrays may also be fabricated and operated independently, sequentially, or otherwise relative to one another. As used herein, a "subarray" may also be considered an array.

[0019] A conductor layer 16 including conductive material 17 is formed above substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 is formed above conductor layer 16. An example thickness for each of layers 20 and 22 is 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown, with stack 18 more likely to include tens, a hundred, or more (etc.) layers 20 and 22. Other circuitry that may or may not be part of peripheral and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below a lowermost conductive layer 22 and / or above an uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and lowermost conductive layer 22, and one or more select gate layers may be above uppermost conductive layer 22. Regardless, conductive layer 22 (alternatively referred to as a first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as a second layer) may not include insulating material or may be insulating when processed in conjunction with the "gate last" or "replacement gate" example method embodiments initially described herein. Example conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. Example insulating layer 20 includes a second material 24 (e.g., silicon dioxide) that has a composition different from that of first material 26 and that may be fully or partially sacrificial. Uppermost insulating layer 20 and stack 18 may be considered to have a top 21.

[0020] A first insulator material 39 is formed over the top 21 of the stack 18 and an insulator material 19 (e.g., silicon dioxide) is formed over the first insulator material 39. The first insulator material 39 includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. In one embodiment, the first insulator material 39 includes (a). In one such embodiment, the first insulator material 39 includes one and only one of carbon, oxygen, boron, or phosphorus. In another such embodiment, the first insulator material 39 includes at least two of carbon, oxygen, boron, and phosphorus. In one embodiment, one or more of carbon, oxygen, boron, and phosphorus in the first insulator material 39 has a total concentration of at least about 2 atomic %, and in one such embodiment, such total concentration is no greater than about 20 atomic %. In one embodiment, such total concentration is at least about 4 atomic %, and in one embodiment, is at least about 10 atomic %. In one embodiment, such total concentration is from about 6 atomic % to about 11 atomic %. In one embodiment, the first insulator material 39 includes (b). In one embodiment, first insulator material 39 includes both (a) and (b), and another embodiment includes only one of (a) and (b). In one embodiment, insulating layer 20 includes an insulating material (e.g., 24) having a different composition than first insulator material 39. Regardless, the first insulator material may be deposited to any suitable thickness, an example being 100 to 600 angstroms.

[0021] A channel opening 25 is formed (e.g., by etching) through the insulator material 19, the first insulator material 39, the insulating layer 20, and the conductive layer 22 to the conductor layer 16. The channel opening 25 may taper radially inward (not shown), moving deeper into the stack 18. In some embodiments, the channel opening 25 may partially enter the conductive material 17 of the conductor layer 16 as shown, or may stop at the top (not shown). Alternatively, as an example, the channel opening 25 may stop atop or inside the lowermost insulating layer 20. The reason for extending the channel opening 25 to at least the conductive material 17 of the conductor layer 16 is to ensure that the subsequently formed channel material (not shown) is directly electrically coupled to the conductor layer 16 when such connection is desired without using alternative processes and structures to achieve this. An etch stop material (not shown) may be within or atop the conductive material 17 of the conductor layer 16 to help stop etching of the channel opening 25 relative to the conductor layer 16 when such a connection is desired. Such an etch stop material may be sacrificial or non-sacrificial. By way of example and for simplicity only, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory block regions 58, which in a finished circuit system configuration will include laterally spaced memory blocks 58. In this document, a "block" generally includes a "sub-block". Memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and oriented, for example, along direction 55. It is possible that memory block regions 58 are not discernible at this processing point. Any alternative existing or future developed arrangements and configurations may be used.

[0022] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thus including individual channel material strings that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure that is laterally located between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cell is vertically along the individual charge blocking region. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulator oxides (e.g., silicon dioxide) is laterally located between the channel material and the storage material.

[0023] Figure 3 , 3A, 3B, 4, 4A, and 4B show an embodiment in which charge blocking material 30, storage material 32, and charge transfer material 34 are formed vertically in individual channel openings 25 along insulating layer 20 and conductive layer 22. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing respective thin layers of the transistor materials over stack 18 and within individual channel openings 25 and subsequently planarizing such transistor materials back to at least the top surface of stack 18. In one embodiment, at least some of memory cell materials 30, 32, and / or 34 include silicon dioxide, and additional example memory cell materials are described in more detail below.

[0024] Also formed in the channel opening 25 is a channel material 36 vertically along the insulating layer 20 and the conductive layer 22, the channel material 36 thus comprising individual operational channel material strings 53, along which in one embodiment there are memory cell materials (e.g., 30, 32, and 34) and second layer materials (e.g., 24) horizontally between immediately adjacent channel material strings 53. Due to the proportions, the materials 30, 32, 34, and 36 are arranged in a substantially parallel relationship. Figure 3 and 4 37. Example channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more of silicon, germanium, and so-called Group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. As shown, a stamp etch may be performed to remove materials 30, 32, and 34 from the base of the channel opening 25 to expose the conductor layer 16 so that the channel material 36 is directly against the conductive material 17 of the conductor layer 16. Such a stamp etch may occur individually with respect to each of the materials 30, 32, and 34 (as shown), or may occur collectively with respect to all materials after deposition of material 34 (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and the channel material 36 may be directly electrically coupled to the conductive material 17 of the conductor layer 16 through a separate conductive interconnect (not shown). Channel opening 25 is shown as including a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, a radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown). Regardless, conductive material 31 (e.g., a conductive plug, such as conductively doped polysilicon) directly abuts lateral inner portion 44 in an upper portion of individual channel material strings 53. One or more of materials 30, 32, 34, and 36 may not extend to the top of conductive material 31 (not shown).

[0025] refer to Figure 5 and 5A, the insulator material 19 (not shown) is removed (e.g., by etching) back to the first insulator material 39. This produces a string of channel materials 53 that protrudes upward from the uppermost material directly above the stack 18. In such examples, such uppermost material is at least the first insulator material 39. Alternatively and by way of example only, if less than all of the insulator material 19 is removed (not shown), then such remaining insulator material 19 is at least such uppermost material. In addition, the memory cell materials 30, 32 and 34 and the channel material 36 are vertically recessed (e.g., by etching) so that the conductive material 31 now protrudes upward from the individual upwardly protruding string of channel materials 53. As an example, consider an embodiment in which the memory cell materials 30, 32 and 34 are each one or more of a silicon dioxide and a silicon nitride layer. In such example embodiments, the depicted construction can be produced by selectively etching the silicon dioxide and silicon nitride sequentially relative to each other using modified or different chemistries. As an example, a solution of 100:1 (by volume) water to HF selectively etches silicon dioxide relative to silicon nitride, while a solution of 1000:1 (by volume) water to HF solution selectively etches silicon nitride relative to silicon dioxide. Thus, in such examples, such etching chemistries may be used in an alternating manner to sequentially remove memory cell materials 30, 32, and 34 laterally / radially outward from channel material 36. Channel material 36 may then be removed, for example, by etching. As an example, and by way of example only, conductively doped polysilicon serving as channel material 36 may be wet etched using a solution of HNO3 / H2O / HF (50:20:1 by volume) or dry etched using SF6 plasma. Practitioners may be able to select other chemistries to etch other different materials. One or more of materials 30, 32, and 34 may be etched so that their tops are below the top of first insulator material 39 (not shown).

[0026] The embodiments described and shown above are merely examples of ways to form channel material strings 53 protruding upward from the uppermost material directly above first insulator material 39, and to form conductive material 31 protruding upward from the individual upwardly protruding channel material strings 53. Any other existing or future developed technology may be used.

[0027] Forming respective rings of insulating material circumferentially surrounding the upwardly protruding conductive material. Figure 6-9A Describes an example method for forming such a ring. Figure 6 , 7and 7A, blanket depositing a layer of insulating material 70. In one embodiment, insulating material 70 and first insulator material 39 comprise different compositions relative to each other. In one embodiment, insulating material 70 comprises at least one of (a) and (b). In such embodiments, insulating material 70 may have any of the properties described above with respect to first insulator material 39. Further, and in one such embodiment, insulating material 70 and first insulator material 39 comprise the same composition relative to each other, and in another such embodiment, comprise different compositions relative to each other.

[0028] refer to Figure 8 , 9 9A, anisotropically etching the insulating material 70 to form annular rings 75 each circumferentially surrounding the upwardly protruding conductive material 31 including the insulating material 70. This is only one example of forming the annular rings 75, and any other existing or future developed methods may be used. In one embodiment and as shown, the annular rings 75 are directly against the upwardly protruding conductive material 31. The annular rings 75 can be considered to have a top surface 62 and a side surface 59.

[0029] In one embodiment and as shown, the annular ring 75 is not formed directly against the first insulator material 39 . Fig. 22 and 22A An alternative embodiment configuration 10a is shown in which a circular ring 75a is formed directly against the first insulator material 39. The same reference numerals of the embodiments described above are used where appropriate, with certain construction differences indicated by the suffix "a" or by different reference numerals. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0030] refer to Fig.10 , 11 11A, horizontally elongated trenches 40 are formed (e.g., by anisotropic etching) through first insulator material 39 and into stack 18 to form laterally spaced memory blocks 58. Horizontally elongated trenches 40 may have respective bottoms directly against (atop or within) conductive material 17 of conductive layer 16 (as shown) or may have respective bottoms above conductive material 17 of conductive layer 16 (not shown).

[0031] The above process shows that the channel opening 25 is formed and filled before the trench 40 is formed. This process can be reversed. Alternatively, the trench 40 can be formed between forming and filling the channel opening 25 (not ideal).

[0032] refer to Fig.12 , 13, 13A, 14 and 15, and in one embodiment, the material 26 (not shown) of the conductive layer 22 is removed, for example, by isotropically etching away, ideally selectively relative to other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, where the material 26 is silicon nitride, the insulating material 70 includes (a) and / or (b), and the other materials include one or more oxides or polysilicon). In an example embodiment, the material 26 (not shown) in the conductive layer 22 is sacrificial and is replaced by the conductive material 48 and thereafter removed from the trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56. .

[0033] A thin insulating liner (such as Al2O3 and not shown) may be formed prior to forming the conductive material 48. The approximate location of the transistor and / or memory cell 56 is Fig.15 Indicated by brackets in Fig.12 , 13 13A, where the transistor and / or memory cell 56 is substantially annular or ring-shaped in the depicted example. Alternatively, the transistor and / or memory cell 56 may not completely surround the individual channel openings 25, so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surround the individual channel openings in the individual conductive layers, where there may be multiple word lines per channel opening in the individual conductive layers, and not shown). The conductive material 48 may be viewed as having ends 50 ( Fig.15 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally located between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an example "gate last" process, conductive material 48 of conductive layer 22 is formed after forming channel opening 25 and / or trench 40. Alternatively, for example with respect to a "gate first" process, conductive material of the conductive layer may be formed before forming channel opening 25 and / or trench 40 (not shown).

[0034] A charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and each control gate region 52. The charge blocking member may have the following functions in a memory cell: in a programming mode, the charge blocking member may prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in an erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of each memory cell. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32) where such storage material is insulating (e.g., in the absence of any material of different composition between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any single-composition insulator material 30. Furthermore, the interface of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may together act as a charge blocking region and alternatively or additionally may act as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0035] refer to Fig.16 , 17 , 17A and 18 and in one embodiment, an intervening material 57 is formed in the trench 40 between the laterally adjacent memory block regions 58. The intervening material 57 can provide lateral electrical isolation (insulation) between the laterally adjacent memory block regions 58 and the final memory block 58. This can include one or more of insulating, semiconducting and conductive materials, and in any case, can facilitate shorting of the conductive layers 22 relative to each other in the finished circuit system structure. Example insulating materials are one or more of SiO2, Si3N4, Al2O3 and undoped polysilicon. In one embodiment, the intervening material 57 includes a laterally outermost insulating material (e.g., silicon dioxide and / or silicon nitride and not shown) and a laterally inner material (e.g., undoped polysilicon and not shown) having a different composition than the laterally outermost insulating material. In one such embodiment, the laterally inner material is insulating. In one embodiment, the intervening material 57 is insulating everywhere between the laterally adjacent memory blocks.

[0036] refer to Fig.19 and 19A, a second insulator material 41 is formed over the first insulator material 39, the intermediate material 57, the annulus 75, and the upwardly protruding conductive material 31. The first insulator material 39 and the second insulator material 41 include different compositions relative to each other, and one example second insulator material 41 is silicon dioxide. Regardless, the second insulator material 41 may include the same composition as at least some of the memory cell materials 30, 32, and / or 34. In one embodiment, the second insulator material 41 is formed beside the annulus 75 and in one such embodiment, is formed directly against the side surface 59 of the annulus 75 as shown.

[0037] refer to Fig. 20 , 21 and 21A, forming (e.g., by etching) contact openings 61 through the second insulator material 41 and thereafter forming conductive vias 43 therein that are each electrically coupled directly to individual string of channel materials 53 by upwardly protruding conductive material 31. In one embodiment and as shown, the conductive vias 43 are formed beside the ring 75 and in one such embodiment are formed directly against the side surface 59 of the ring 75. In one embodiment and as shown, the conductive vias 43 are formed atop the ring 75 and in one such embodiment are formed directly against the top surface 62 of the ring 75. In one embodiment and as shown, the conductive vias 43 are formed to extend into the first insulator material 39 in part due to mask misalignment as depicted in the example. Alternatively, the trenches 40 and / or the intervening fill material 57 therein may be formed sometime after the second insulator material 41 is formed, including sometime after the contact openings 61 and / or conductive vias 43 are formed therein.

[0038] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used with respect to the above-described embodiments.

[0039] Fig.23 and 23A An example final configuration is shown with respect to configuration 10a.Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0040] The present invention is intended to address the following processing challenges, but is not limited thereto. Consider a scenario where the second insulator material 41 and some of the memory cell materials 30, 32, and / or 34 comprise the same material (e.g., silicon dioxide). In the absence of the ring 75, the etching chemistry used to etch the contact opening 61 may also etch such memory cell materials in the event of a slight mask misalignment, which may cause the contact opening to extend to the conductive material 48 of the conductive line 29 (not shown), thereby creating a fatal short circuit when the conductive via 43 is formed. The ring 75 may prevent or at least reduce such risk.

[0041] Alternative embodiment configurations may result from the method embodiments described above or in other ways. Regardless, embodiments of the present invention encompass memory arrays that are independent of the method of manufacture. However, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0042] Embodiments of the present invention include a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56). The memory array includes a vertical stack (e.g., 18) including alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). Strings (e.g., 53) of channel materials of the memory cells are in the stack and protrude upwardly above the stack. Conductive material (e.g., 31) is directly against and protrudes upwardly from respective lateral inner portions (e.g., 44) of the upwardly protruding strings of channel materials. A first insulator material (e.g., 39) is disposed above the stack beside the lateral outer portions of the strings of channel materials (e.g., at Fig.21A , but in one embodiment and as shown not directly against). The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. Rings (e.g., 75, 75a) comprising insulating material (e.g., 70) each circumferentially surround the upwardly protruding conductive material. A second insulator material (e.g., 41) is above the first insulator material, the ring and the upwardly protruding conductive material. The first insulator material and the second insulator material include different compositions relative to each other. Conductive vias (e.g., 43) are in the second insulator material and are each directly electrically coupled to individual strings of channel material through the upwardly protruding conductive material. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0043] The above-described processing or construction may be considered to be associated with an array of components formed as a single stack or single stack of such components above or as part of an underlying base substrate or within the single stack or single stack (although the single stack / stack may have multiple layers). Control and / or other peripheral circuits for operating or accessing such components within the array may also be formed at any location as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / stacks may be provided or manufactured above and / or below the stacks / stacks shown in the en route or described above. In addition, the arrays of components may be the same or different in different stacks / stacks relative to each other, and different stacks / stacks may have the same thickness or different thicknesses relative to each other. Intermediate structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuits and / or dielectric layers). Also, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be manufactured substantially simultaneously.

[0044] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0045] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "below...", "under...", "upward" and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the substrate processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" refers to the direction along the surface of the main substrate (i.e., not forming a degree with the surface) and can be referenced to the substrate during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction that deviates from the just horizontal by at least 45°. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc., relative to a field effect transistor, are references to the orientation of the channel length of the transistor, and the current flows along the said orientation between the source / drain regions in operation. For bipolar junction transistors, "extending vertically", "extending vertically", "extending horizontally", "extending horizontally", etc. are reference to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature and / or region extending vertically extends vertically or within 10° of vertical.

[0046] In addition, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Moreover, the use of "above" without a preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components).

[0047] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0048] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not uniform. If the two stated materials or regions are not directly against each other, then in the case of such materials or regions being not uniform, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical contact relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical touching contact of the stated materials, regions, or structures relative to one another.

[0049] As used herein, regions / materials / components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region / material / component to another, and flows primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0050] "Rows" and "columns" are used in this document for the convenience of distinguishing features of one series or orientation from features of another series or orientation, and components have been or may be formed along said "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns can be the same. In addition, rows and columns can intersect at 90° or at one or more other angles (i.e., other than straight angles) relative to each other.

[0051] The composition of any one of the conductive / conductor / conductive materials herein can be a metallic material and / or a conductively doped semiconductive / semiconductive / semiconductive material. "Metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0052] As used herein, any use of "selective" with respect to etching, removing, depositing, forming, and / or shaping is such action performed on one stated material relative to another stated material being acted upon in a volume ratio of at least 2:1. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or forming of one material relative to another stated material or materials for at least the first 75 angstroms in a volume ratio of at least 2:1.

[0053] Unless otherwise indicated, the use of "or" herein includes either and both.

[0054] in conclusion

[0055] In some embodiments, a method for forming a memory array includes forming a stack including vertically alternating first and second layers. A first insulator material is above the stack. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. A channel material string is in the uppermost material directly above the stack and protrudes upward from the uppermost material. A conductive material directly abuts against the lateral inner side of each of the upwardly protruding channel material strings and protrudes upward from the individual upwardly protruding channel material strings. An annulus is formed that includes an insulating material that circumferentially surrounds the upwardly protruding conductive material. A second insulator material is formed above the first insulator material, the annulus and the upwardly protruding conductive material. The first insulator material and the second insulator material include different compositions relative to each other. Conductive vias are formed in the second insulator material, each of which is directly electrically coupled to the individual channel material string through the upwardly protruding conductive material.

[0056] In some embodiments, a method for forming a memory array includes forming a stack including vertically alternating first and second layers. A first insulator material is formed above the stack. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. A channel material string is formed in the uppermost material directly above the stack and protrudes upward from the uppermost material. Memory cell material is provided along individual channel materials. Conductive material is directly against the lateral inner side of each of the upwardly protruding channel material strings. The channel material of the channel material string is vertically recessed and the memory cell material is vertically recessed to form the conductive material protruding upward from the individual upwardly protruding channel material string. An annulus is formed that includes an insulating material that circumferentially surrounds the upwardly protruding conductive material and directly against the upwardly protruding conductive material. A second insulator material is formed above the first insulator material, the annulus, and the upwardly protruding conductive material. The first insulator material and the second insulator material include different compositions relative to each other. Conductive vias are formed in the second insulator material, each of the conductive vias being electrically coupled directly to the individual strings of channel material through the upwardly protruding conductive material.

[0057] In some embodiments, a memory array includes a vertical stack including alternating insulating layers and conductive layers. A channel material string of a memory cell is in the stack. The channel material string protrudes upward above the stack. Conductive material is directly against each lateral inner side of the upwardly protruding channel material string and protrudes upward from the individual upwardly protruding channel material string. A first insulator material is above the stack beside the lateral outer side of the channel material string. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. Rings including insulating material each circumferentially surround the upwardly protruding conductive material. A second insulator material is above the first insulator material, the ring and the upwardly protruding conductive material. The first insulator material and the second insulator material include different compositions relative to each other. Conductive vias in the second insulator material are each directly electrically coupled to the individual channel material string through the upwardly protruding conductive material.

[0058] As specified, the subject matter disclosed herein has been described in language more or less specific in terms of structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A memory array comprising: a vertical stack comprising alternating insulating and conductive layers, wherein strings of channel materials of memory cells are in the stack, wherein the strings of channel materials protrude upwardly above the stack, and wherein conductive material directly abuts respective lateral inner portions of the upwardly protruding strings of channel materials and protrudes upwardly from individual strings of the upwardly protruding strings of channel materials; a first insulator material over the stack and adjacent to laterally outer portions of the string of channel material, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; comprising annular rings of insulating material each circumferentially surrounding said upwardly projecting conductive material; a second insulator material overlying the first insulator material, the annular ring, and the upwardly protruding conductive material; the first insulator material and the second insulator material comprising different compositions relative to each other; and Conductive vias are provided in the second insulator material, each of the conductive vias being electrically coupled directly to a respective string of channel materials through the upwardly protruding conductive material.

2. The memory array of claim 1 wherein the second insulator material is beside the ring.

3. The memory array of claim 2, wherein the second insulator material is directly against a side surface of the annular ring.

4. The memory array of claim 1 wherein the annular ring directly abuts the upwardly protruding conductive material. The memory array of claim 1 , wherein the conductive via is beside the ring. The memory array of claim 5 , wherein the conductive vias are directly against a side surface of the ring.

7. The memory array of claim 1 wherein the conductive via is on top of the ring.

8. The memory array of claim 7 wherein the conductive vias are directly against a top surface of the annular ring.

9. The memory array of claim 8, wherein the conductive vias are directly against a side surface of the ring.

10. The memory array of claim 1 wherein the annular ring is directly against the first insulator material.

11. The memory array of claim 1 wherein the conductive vias extend vertically into the first insulator material.

12. The memory array of claim 1 wherein the insulating material and the first insulator material comprise different compositions relative to each other.

13. The memory array of claim 1, wherein the at least one comprises the (a).

14. The memory array of claim 13 wherein the one or more of carbon, oxygen, boron, and phosphorus in the first insulator material has a total concentration of at least 2 atomic %.

15. The memory array of claim 14 wherein the total concentration is no greater than 20 atomic %.

16. The memory array of claim 14 wherein the one or more of carbon, oxygen, boron, and phosphorus in the first insulator material has a total concentration of at least 4 atomic %.

17. The memory array of claim 16 wherein the total concentration is at least 10 atomic %.

18. The memory array of claim 1, wherein the at least one comprises the (b).

19. The memory array of claim 1, wherein the at least one comprises both of (a) and (b).

20. The memory array of claim 1, wherein the insulating material comprises at least one of (a) and (b).

21. The memory array of claim 20 wherein the insulating material and the first insulator material comprise different compositions relative to each other.

22. The memory array of claim 20 wherein the insulating material and the first insulator material comprise a same composition relative to one another.

23. The memory array of claim 1 wherein the insulating material comprises the (a).

24. The memory array of claim 1 wherein said insulating material comprises said (b).

25. The memory array of claim 1 wherein the insulating material comprises both (a) and (b).

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