Sonos memory device and method of making the same

Abstract

The application provides a SONOS memory device and a preparation method thereof, which comprises the following steps: providing a substrate, forming a charge storage layer, a polysilicon gate material layer and a hard mask layer on the substrate; forming two separate oxide layers in the hard mask layer through a self-aligned etching process; removing the polysilicon gate material layer exposed by the two oxide layers through a self-aligned etching process to form two separate polysilicon gates; forming a side wall to isolate the gap between the two polysilicon gates; covering the side wall of each polysilicon gate away from the side wall with the ion implantation; and performing source-drain heavy doping ion implantation into the substrate away from the side wall. The application increases the storage density, saves the source end shared by two storage tubes and the side wall near the source end of each storage tube, and directly uses the side wall to isolate the two storage tubes, so that the area of the storage unit can be effectively reduced. The two storage tubes are formed through a self-aligned process, have high consistency and improve the uniformity of the storage unit.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a SONOS memory device and a manufacturing method thereof. Background Art

[0002] With the development of technology, the demand for data storage and processing for big data analysis is increasing, and therefore the demand for non-volatile memory is also increasing. As an essential storage device in computers, non-volatile memory plays a vital role in storing the information being processed. Among non-volatile memories, SONOS memory has advantages such as small cell size, good memory retention, low operating voltage, and compatibility with complementary metal oxide semiconductor (CMOS) manufacturing processes, and is widely used in electronic products.

[0003] like Figure 1 As shown in the figure, a two-transistor, two-bit SONOS memory is currently available. A memory cell consists of two memory transistors (memory transistor 1 and memory transistor 2). In this two-transistor, two-bit SONOS memory, the two memory transistors share a source terminal S, which does not require a contact hole (CT). At smaller process nodes, the spacers of the two memory transistors near the source terminal S and the source terminal S, which does not require a contact hole, occupy a large area. Summary of the Invention

[0004] The present invention aims to provide a SONOS memory device and its fabrication method, which increase storage density and enable each memory cell to store two bits of data. This eliminates the need for a shared source terminal between two memory cells and the heavily doped source terminal fabrication process. It also eliminates the need for sidewalls on each side of the two memory cells near the source terminals. Instead, isolation sidewalls are used to separate the two memory cells and fill the gap between them, effectively reducing the memory cell area. The two memory cells are formed using a self-aligned process, resulting in greater consistency than existing processes, improving the uniformity of the memory cells and facilitating control of operational interference.

[0005] The present invention provides a method for preparing a SONOS memory device, comprising:

[0006] Providing a substrate, and sequentially forming a charge storage layer, a polysilicon gate material layer, and a hard mask layer on the surface of the substrate;

[0007] Etching the hard mask layer to form an opening to define the total channel length of the two storage tubes;

[0008] forming two separate oxide layers in the opening using a self-aligned etching process;

[0009] Etching and removing the hard mask layer; self-aligning etching and removing the polysilicon gate material layer exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer;

[0010] forming sidewalls, the sidewalls comprising an isolation sidewall and a side sidewall; the isolation sidewall fills the gap between the two polysilicon gates; the side sidewall covers the sidewalls of the two polysilicon gates away from the isolation sidewall;

[0011] Source and drain heavy doping ions are implanted into the substrate at a side of each of the side sidewalls away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

[0012] Furthermore, forming the two oxide layers by using a self-aligned etching process specifically includes:

[0013] growing an oxide material layer, wherein the oxide material layer covers the surface of the hard mask layer and the surface of the polysilicon gate material layer exposed by the opening, and the oxide material layer forms a recess in a middle region of the opening;

[0014] The oxide material layer is self-alignedly etched to remove the oxide material layer above the upper surface of the hard mask layer and the oxide material layer below the recess to expose the polysilicon gate material layer of a preset width. The oxide material layer after the self-aligned etching is defined as the oxide layer.

[0015] Furthermore, after removing the oxide layer and before forming the sidewall spacer, the preparation method further includes:

[0016] Light doping is performed into the substrate to form a first lightly doped region and a second lightly doped region; the first lightly doped region is located in the substrate below the gap between the two polysilicon gates; the second lightly doped region is located in a storage well in the substrate on one side of each of the two polysilicon gates away from the gap.

[0017] Furthermore, after providing the substrate and before forming the charge storage layer, the preparation method further includes:

[0018] forming a pad oxide layer on the surface of the substrate, and performing ion implantation on the substrate to form a storage well;

[0019] The pad oxide layer formed on the entire surface of the substrate is removed by an etching process.

[0020] Furthermore, forming the sidewall specifically includes:

[0021] Growing a spacer material layer, wherein the spacer material layer fills the gap between the two polysilicon gates and also covers the upper surfaces and side surfaces of the two polysilicon gates and the surface of the charge storage layer;

[0022] The spacer material layer is etched in a self-aligned manner, and the remaining spacer material layer is defined as the spacer.

[0023] The present invention further provides a SONOS memory device, comprising a plurality of memory cells, each of which comprises:

[0024] A substrate, on which a first storage tube and a second storage tube are formed; the first storage tube includes a first charge storage layer and a first polysilicon gate from bottom to top on the substrate; the second storage tube includes a second charge storage layer and a second polysilicon gate from bottom to top on the substrate;

[0025] Sidewalls, the sidewalls comprising an isolation sidewall and a side sidewall; the side sidewalls comprising a first sidewall and a second sidewall; the isolation sidewall filling a gap between the first polysilicon gate and the second polysilicon gate; the first sidewall covering the sidewall of the first polysilicon gate away from the isolation sidewall; the second sidewall covering the sidewall of the second polysilicon gate away from the isolation sidewall;

[0026] A first heavily doped region and a second heavily doped region, wherein the first heavily doped region is located in the substrate on a side of the sidewall 1 away from the isolation sidewall, and the second heavily doped region is located in the substrate on a side of the sidewall 2 away from the isolation sidewall.

[0027] Furthermore, the storage unit further includes:

[0028] a first lightly doped region, the first lightly doped region being located in the substrate below a gap between the first polysilicon gate and the second polysilicon gate;

[0029] A second lightly doped region is located in a storage well in the substrate on one side of the polysilicon gate 1 and the polysilicon gate 2, respectively, away from the isolation sidewall.

[0030] Furthermore, the first heavily doped region serves as the source region of the first storage transistor, and the first lightly doped region serves as the drain region of the first storage transistor; moreover, the first lightly doped region also serves as the source region of the second storage transistor, and the second heavily doped region serves as the drain region of the second storage transistor.

[0031] Furthermore, one of the storage units is composed of two storage tubes, namely the first storage tube and the second storage tube; wherein, when one storage tube is read, the other storage tube is forcibly turned on or off to act as a selection tube.

[0032] Furthermore, the memory cell further includes: an interlayer dielectric layer, the interlayer dielectric layer covering the substrate, the sidewalls, the first polysilicon gate, and the second polysilicon gate; a plurality of contact holes formed in the interlayer dielectric layer, the contact holes being filled with metal to lead out electrical signals corresponding to each electrode;

[0033] A first contact hole penetrates the interlayer dielectric layer to expose the first heavily doped region; in the first storage tube, a second contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 1; in the second storage tube, a third contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 2; and a fourth contact hole penetrates the interlayer dielectric layer to expose the second heavily doped region.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The present invention provides a SONOS memory device and a preparation method thereof. The preparation method comprises: providing a substrate, sequentially forming a charge storage layer, a polysilicon gate material layer, and a hard mask layer on the surface of the substrate; etching the hard mask layer to form an opening to define the total channel length of two storage tubes; forming two separate oxide layers in the opening using a self-aligned etching process; etching and removing the hard mask layer; self-aligned etching and removing the polysilicon gate material layers exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer; forming sidewalls, the sidewalls comprising an isolation sidewall and a side sidewall; the isolation sidewall filling a gap between the two polysilicon gates; the side sidewall covering the sidewalls of the two polysilicon gates on a side away from the isolation sidewall; and implanting source and drain heavily doped ions into the substrate on a side of the side sidewall away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

[0036] The present invention provides a novel two-transistor, two-bit SONOS memory device and its fabrication method, which increases storage density, enabling each memory cell to store two bits of data. This eliminates the need for a shared source terminal between the two memory cells and the heavily doped source terminal fabrication process. It also eliminates the need for sidewalls on each side of the two memory cells near the source terminals. Instead, isolation sidewalls are used to separate the two memory cells and fill the gap between them, effectively reducing the memory cell area. The two memory cells are formed using a self-aligned process, resulting in greater consistency than existing processes, improving the uniformity of the memory cells and facilitating control of operational interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a SONOS storage device.

[0038] Figure 2 The figure is a flow chart of a method for manufacturing a SONOS memory device according to an embodiment of the present invention.

[0039] Figure 3 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming a liner oxide layer.

[0040] Figure 4 Schematic diagram of the method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming a charge storage layer, a polysilicon gate material layer, and a hard mask layer.

[0041] Figure 5 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after an opening is formed in the hard mask layer.

[0042] Figure 6 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming an oxide material layer.

[0043] Figure 7 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after an oxide layer is formed.

[0044] Figure 8 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after removing the hard mask layer.

[0045] Figure 9 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming two separate polysilicon gates.

[0046] Figure 10 Schematic diagram of a SONOS memory device after light doping implantation in a method for manufacturing the device according to an embodiment of the present invention.

[0047] Figure 11 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming a spacer material layer.

[0048] Figure 12 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming a spacer. FIG.

[0049] Figure 13 Schematic diagram of the source and drain after heavy doping in the method for preparing a SONOS memory device according to an embodiment of the present invention.

[0050] Figure 14 FIG. 1 is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming contact holes.

[0051] The accompanying drawings are numerals as follows:

[0052] 01-substrate; 02-storage well; 03-pad oxide layer; 04-charge storage layer; 41-charge storage layer one; 42-charge storage layer two; 05-polysilicon gate material layer; 05'-polysilicon gate; 51-polysilicon gate one; 52-polysilicon gate two; 06-hard mask layer; 07-oxide material layer; 07'-oxide layer; 08-sidewall material layer; 08'-sidewall; 80-isolation sidewall; 81-sidewall one; 82-sidewall two; a-first lightly doped region; LDD-second lightly doped region; P1-first heavily doped region; P2-second heavily doped region; 10-first contact hole; 11-second contact hole; 12-third contact hole; 13-fourth contact hole. DETAILED DESCRIPTION

[0053] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a highly simplified form and are not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention. In the drawings, the dimensions of layers, regions, and components, as well as their relative dimensions, may be exaggerated for clarity. Identical reference numerals throughout represent identical elements.

[0054] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] The embodiment of the present invention provides a method for preparing a SONOS memory device, such as Figure 2 Shown, including:

[0058] Step S1, providing a substrate, and sequentially forming a charge storage layer, a polysilicon gate material layer, and a hard mask layer on the surface of the substrate;

[0059] Step S2: etching the hard mask layer to form an opening to define the total channel length of the two storage tubes;

[0060] Step S3, forming two separate oxide layers in the opening using a self-aligned etching process;

[0061] Step S4, etching and removing the hard mask layer; self-aligned etching and removing the polysilicon gate material layer exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer;

[0062] Step S5, forming sidewalls, the sidewalls including an isolation sidewall and a side sidewall; the isolation sidewall fills the gap between the two polysilicon gates; the side sidewall covers the sidewalls of the two polysilicon gates away from the isolation sidewall;

[0063] Step S6: implanting source and drain heavily doped ions into the substrate on a side of each of the side sidewalls away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

[0064] The following will describe in detail the SONOS memory device and its manufacturing method provided in the embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that, to simplify the drawing, the following embodiments of the present invention and the accompanying drawings are described using a single memory cell forming a SONOS memory device as an example. However, in actual practice, multiple memory cells including two memory transistors provided in the memory area of ​​the embodiments of the present invention may be included, but the present invention is not limited thereto.

[0065] The following will describe in detail the method for manufacturing any memory cell in a SONOS memory device by combining it with the structural schematic diagram corresponding to each manufacturing step of the method for manufacturing any memory cell in a SONOS memory device provided in an embodiment of the present invention.

[0066] See also Figure 3 , Figure 3 Schematic diagram of the structure after providing a substrate 01 and forming a liner oxide layer 03 and a storage well 02 in the storage area in an embodiment of the present invention. Figure 3 As shown, step S01 is performed to provide a substrate 01, which provides a platform for the subsequent formation of various components included in a memory cell of a SONOS memory device. The substrate 01 can be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or can also be a double-sided polished silicon wafer, or a ceramic substrate such as alumina, a quartz or glass substrate, etc. For example, in this embodiment, the substrate 01 is, for example, a silicon wafer, and it is a doped silicon wafer, and its doping type can be determined according to the type of storage tube actually formed. In this embodiment, it is exemplarily set to a P-type doped substrate.

[0067] Next, a plurality of grooves are formed in the substrate 01 using an etching process, such as a dry etching process or a wet etching process, and an insulating material, such as silicon dioxide, is filled in each groove using a deposition process, such as at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process, to form a plurality of device isolation structures, such as a shallow trench isolation (STI) structure, for isolating and defining active areas.

[0068] Afterwards, a deposition process, such as at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process, is used to form a liner oxide layer 03 on the entire surface of the substrate 01. Ions are then implanted into the substrate 01 region in the storage area to form a storage well 02 in the region. Whether to form an N-well or a P-well depends on the type of storage transistors in the SONOS memory device. In the embodiment of the present invention, a P-well is exemplarily formed in the region to prepare for the subsequent formation of an N-channel storage transistor in the region.

[0069] Then, if Figure 3 and Figure 4 As shown, the pad oxide layer 03 formed on the entire surface of the substrate 01 can be removed by an etching process. Then, a charge storage layer 04, a polysilicon gate material layer 05, and a hard mask layer 06 are sequentially stacked on the exposed surface of the substrate 01 by a deposition process. The charge storage layer 04 can be a multilayer film structure, such as, but not limited to, an ONO stack structure. The hard mask layer 06 can be, for example, a silicon nitride layer. The charge storage layer 04 can have a thickness of, for example, 80 to 150 angstroms, the polysilicon gate material layer 05 can have a thickness of, for example, 800 to 2000 angstroms, and the hard mask layer 06 can have a thickness of, for example, 800 to 2000 angstroms.

[0070] Then, if Figure 5 As shown, the hard mask layer 06 is etched to form an opening to define the total channel length of the two storage tubes, and the hard mask layer 06 is etched using a photomask to expose the polysilicon gate material layer 05.

[0071] Then, if Figure 6 As shown, an oxide material layer 07 is grown. The oxide material layer 07 covers the surface of the hard mask layer 06 and the surface of the polysilicon gate material layer 05 exposed by the opening. The oxide material layer 07 forms a recess in the middle area of ​​the opening. The thickness of the oxide material layer 07 defines the channel length of the SONOS transistor. The thickness of the oxide material layer 07 is, for example, 50 angstroms to 100 angstroms.

[0072] Then, if Figure 7 As shown, the oxide material layer 07 is self-aligned etched to remove the oxide material layer 07 above the upper surface of the hard mask layer 06 and the oxide material layer 07 below the recess to expose the polysilicon gate material layer 05 of a preset width. The oxide material layer 07 after self-aligned etching is defined as oxide layer 07'.

[0073] Then, if Figure 8 As shown, the hard mask layer 06 is removed by etching to expose the polysilicon gate material layer 05 .

[0074] Then, if Figure 9 As shown, the polysilicon gate material layer 05 is self-aligned and etched using a dry or wet etching process to remove the portion of the polysilicon gate material layer 05 not covered by the oxide layer 07', exposing the charge storage layer 04. The remaining polysilicon gate material layer 05 is etched to form two separate polysilicon gates 05'. The two storage transistors are formed using a self-aligned process, resulting in higher consistency than existing processes, which helps improve the uniformity of the storage cells and facilitates control of operational interference.

[0075] Then, if Figure 10 As shown, the oxide layer 07' is removed; a light doping injection is performed into the substrate 01, specifically between the two storage tubes, to form a first lightly doped region a in the substrate 01; and a light doping injection is performed into the storage well 02 outside the two polysilicon gates 05' (each on a side away from the first lightly doped region a) to form a second lightly doped region LDD.

[0076] Then, if Figure 11 As shown, a spacer material layer 08 is grown. The spacer material layer 08 fills the gap between the two storage tubes (i.e., the two polysilicon gates 05') above the first lightly doped region a. The spacer material layer 08 also covers the upper and side surfaces of the two polysilicon gates 05' and the surface of the charge storage layer 04. The spacer material layer 08 can be a silicon oxide-silicon nitride-silicon oxide composite layer or a silicon oxide layer. The spacer material layer 08 can be grown using a deposition process such as at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0077] Then, if Figure 12As shown, the spacer material layer 08 is self-alignedly etched, and the remaining spacer material layer 08 is defined as a spacer 08'. The spacer 08' includes an isolation spacer 80 and a side spacer. The side spacer includes a first sidewall 81 and a second sidewall 82. The isolation spacer 80 fills the gap between the two storage tubes (i.e., the two polysilicon gates 05') above the first lightly doped region a. The side spacers cover the outer side surfaces of the two polysilicon gates 05' (each away from the isolation spacer 80). The side spacers also cover a portion of the width of the charge storage layer 04 surface on the side of each polysilicon gate 05' away from the isolation spacer 80. The charge storage layer 04 on the side of each of the two side spacers away from the isolation spacer 80 is removed by etching, exposing the surface of the substrate 01. The two polysilicon gates 05' are polysilicon gate 1 51 and polysilicon gate 2 52. The two storage tubes are formed using a self-aligned process, which has higher consistency than existing processes, is beneficial to improving the uniformity of the storage unit and facilitates the control of operational interference.

[0078] Then, if Figure 13 As shown, heavily doped ions are implanted into the substrate 01 on the side of the two side sidewalls away from the middle isolation sidewall 80 to form a first heavily doped region P1 and a second heavily doped region P2.

[0079] Then, if Figure 13 and Figure 14 As shown, an interlayer dielectric layer (not shown) is formed, covering the substrate 01, the sidewalls, and the two polysilicon gates. Contact holes are formed in the interlayer dielectric layer and filled with metal (plugs) to lead out the electrical signals of each electrode. For example, a SONOS memory is composed of multiple memory cells, which include a first memory transistor and a second memory transistor. The first heavily doped region P1 serves as the source region of the first memory transistor, and the first lightly doped region a serves as the drain region of the first memory transistor; furthermore, the first lightly doped region a also serves as the source region of the second memory transistor, and the second heavily doped region P2 serves as the drain region of the second memory transistor. The first contact hole 10 penetrates the interlayer dielectric layer, exposing the first heavily doped region P1 and leading the first heavily doped region P1 out through the metal in the contact hole. In the first memory transistor, the second contact hole 11 penetrates the interlayer dielectric layer, exposing the polysilicon gate 151 and leading the polysilicon gate 151 out through the metal in the contact hole. In the second storage transistor, the third contact hole 12 penetrates the interlayer dielectric layer to expose the second polysilicon gate 52 and leads the second polysilicon gate 52 out through the metal in the contact hole. The fourth contact hole 13 penetrates the interlayer dielectric layer to expose the second heavily doped region P2 and leads the second heavily doped region P2 out through the metal in the contact hole.

[0080] The present invention provides a novel method for fabricating a two-transistor, two-bit SONOS memory device. Each memory cell can store two bits of data, thereby increasing storage density. This method eliminates the need for a shared source terminal between the two memory cells and the manufacturing process for heavily doping the source terminal. It also eliminates the sidewalls on each side of the two memory cells near the source terminals. Instead, a single isolation sidewall 80 is used to isolate the two memory cells, effectively reducing the area of ​​the memory cells. The two memory cells are formed using a self-aligned process, resulting in greater consistency than existing processes. This improves the uniformity of the memory cells and facilitates control of operational interference.

[0081] The present invention also provides a SONOS storage device, such as Figure 14 As shown, the SONOS memory device includes a plurality of memory cells, each of which includes:

[0082] A substrate 01 is provided, on which a first storage tube and a second storage tube are formed. The first storage tube includes a charge storage layer 1 41 and a polysilicon gate 1 51 extending from bottom to top on the substrate 01. The second storage tube includes a charge storage layer 2 42 and a polysilicon gate 2 52 extending from bottom to top on the substrate 01. The charge storage layer 1 41 and the charge storage layer 2 42 are connected to form a charge storage layer 04.

[0083] The sidewalls include an isolation sidewall 80 and a side sidewall; the side sidewalls include a first sidewall 81 and a second sidewall 82; the sidewalls are located on the charge storage layer 04, and the isolation sidewall 80 fills the gap between the polysilicon gate 1 51 and the polysilicon gate 2 52; the first sidewall 81 covers the sidewall of the polysilicon gate 1 51 away from the isolation sidewall 80; the second sidewall 82 covers the sidewall of the polysilicon gate 2 52 away from the isolation sidewall 80; the first sidewall 81 also covers a portion of the width of the charge storage layer 04 surface on the side of the polysilicon gate 1 51 away from the isolation sidewall 80; the second sidewall 82 also covers a portion of the width of the charge storage layer 04 surface on the side of the polysilicon gate 2 52 away from the isolation sidewall 80;

[0084] The first heavily doped region P1 and the second heavily doped region P2 are located in the substrate 01 on the side of the first sidewall 81 away from the isolation sidewall 80 , and the second heavily doped region P2 is located in the substrate 01 on the side of the second sidewall 82 away from the isolation sidewall 80 .

[0085] Specifically, the memory cell may further include a first lightly doped region a and a second lightly doped region LDD. The first lightly doped region a is located in the substrate 01 below the gap between the first polysilicon gate 51 and the second polysilicon gate 52. The second lightly doped region LDD is located in the memory well 02 on the side of the first polysilicon gate 51 and the second polysilicon gate 52 away from the isolation spacer 80.

[0086] The first heavily doped region P1 serves as the source region of the first storage tube, and the first lightly doped region a serves as the drain region of the first storage tube. Furthermore, the first lightly doped region a also serves as the source region of the second storage tube, and the second heavily doped region P2 serves as the drain region of the second storage tube. In the present invention, a storage cell comprises two storage tubes (a first storage tube and a second storage tube). When one storage tube is read, the other storage tube is forced on or off to act as a selector. The present invention provides a novel two-tube, two-bit SONOS storage cell structure, in which each storage cell stores two bits of data, thereby increasing storage density. This eliminates the need for a shared source terminal between the two storage tubes and the manufacturing process for heavily doping the source terminal. It also eliminates the need for sidewalls on each side of the two storage tubes near the source terminal. Instead, isolation sidewalls are used to isolate the two storage tubes, effectively reducing the area of ​​the storage cell. The two storage tubes are formed using a self-aligned process, resulting in higher consistency than existing processes. This improves the uniformity of the storage cells and facilitates control of operational interference.

[0087] In this embodiment, the substrate 01 is, for example, a silicon wafer, and it is a doped silicon wafer. The charge storage layer 04 can be a multi-layer film structure, such as an ONO (first oxide layer, silicon nitride layer, and second oxide layer from bottom to top) stacked structure. A storage unit is composed of two storage tubes (a first storage tube and a second storage tube). The storage tube device uses a gate stack structure of silicon substrate-tunneling oxide layer-silicon nitride layer-blocking oxide layer-polysilicon (Silicon-Oxide-Nitride-Oxide-Silicon), which is a charge trap type memory. Specifically, the silicon substrate corresponds to Figure 14 The substrate 01 in the storage pipe area, the tunneling oxide layer corresponds to the first oxide layer in the charge storage layer 04, and the silicon nitride layer corresponds to Figure 14 The silicon nitride layer in the charge storage layer 04 and the blocking oxide layer correspond to Figure 14 The second oxide layer is located in the charge storage layer 04. When storing data, the quantum tunneling effect or hot carrier injection effect is used to inject charges (electrons or holes) into the silicon nitride layer through the tunneling oxide layer. The charges entering the silicon nitride layer are blocked by the blocking oxide layer and captured by the charge traps in the silicon nitride layer, thereby storing data information in the SONOS memory. When erasing data, the charges are moved from the silicon nitride layer to the silicon substrate through the tunneling oxide layer, thereby erasing the data information in the SONOS memory.

[0088] The memory cell also includes an interlayer dielectric layer (not shown), which covers the substrate 01, the sidewalls, and the two polysilicon gates. Contact holes are formed in the interlayer dielectric layer and filled with metal (plugs) to lead out the electrical signals of each electrode. The first contact hole 10 penetrates the interlayer dielectric layer to expose the first heavily doped region P1 and leads the first heavily doped region P1 out through the metal in the contact hole. In the first memory tube, the second contact hole 11 penetrates the interlayer dielectric layer to expose the polysilicon gate 1 51 and leads the polysilicon gate 1 51 out through the metal in the contact hole. In the second memory tube, the third contact hole 12 penetrates the interlayer dielectric layer to expose the polysilicon gate 2 52 and leads the polysilicon gate 2 52 out through the metal in the contact hole. The fourth contact hole 13 penetrates the interlayer dielectric layer to expose the second heavily doped region P2 and leads the second heavily doped region P2 out through the metal in the contact hole.

[0089] In summary, the present invention provides a SONOS memory device and a preparation method thereof, the preparation method comprising: providing a substrate, sequentially forming a charge storage layer, a polysilicon gate material layer, and a hard mask layer on the surface of the substrate; etching the hard mask layer to form an opening to define the total channel length of two storage tubes; forming two separate oxide layers in the opening using a self-aligned etching process; etching and removing the hard mask layer; self-aligned etching and removing the polysilicon gate material layers exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer; forming sidewalls, the sidewalls comprising an isolation sidewall and a side sidewall; the isolation sidewall filling a gap between the two polysilicon gates; the side sidewall covering the sidewalls of the two polysilicon gates on a side away from the isolation sidewall; and performing source and drain heavily doped ion implantation into the substrate on a side of the side sidewall away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

[0090] The present invention provides a novel two-transistor, two-bit SONOS memory device and its fabrication method, which increases storage density, enabling each memory cell to store two bits of data. This eliminates the need for a shared source terminal between the two memory cells and the heavily doped source terminal fabrication process. It also eliminates the need for sidewalls on each side of the two memory cells near the source terminals. Instead, isolation sidewalls are used to separate the two memory cells and fill the gap between them, effectively reducing the memory cell area. The two memory cells are formed using a self-aligned process, resulting in greater consistency than existing processes, improving the uniformity of the memory cells and facilitating control of operational interference.

[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The methods disclosed in the embodiments are described briefly because they correspond to the devices disclosed in the embodiments. For relevant details, refer to the method description.

[0092] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a SONOS memory device, characterized in that: include: Providing a substrate, and sequentially forming a charge storage layer, a polysilicon gate material layer, and a hard mask layer on the surface of the substrate; Etching the hard mask layer to form an opening to define the total channel length of the two storage tubes; forming two separate oxide layers in the opening using a self-aligned etching process; etching and removing the hard mask layer; Self-aligned etching is performed to remove the polysilicon gate material layer exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer; forming sidewalls, the sidewalls comprising an isolation sidewall and a side sidewall; the isolation sidewall fills the gap between the two polysilicon gates; the side sidewall covers the sidewalls of the two polysilicon gates away from the isolation sidewall; Source and drain heavy doping ions are implanted into the substrate at a side of each of the side sidewalls away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

2. The method for preparing a SONOS memory device according to claim 1, wherein: The two oxide layers are formed by a self-aligned etching process, specifically comprising: growing an oxide material layer, wherein the oxide material layer covers the surface of the hard mask layer and the surface of the polysilicon gate material layer exposed by the opening, and the oxide material layer forms a recess in a middle region of the opening; The oxide material layer is self-alignedly etched to remove the oxide material layer above the upper surface of the hard mask layer and the oxide material layer below the recess to expose the polysilicon gate material layer of a preset width. The oxide material layer after the self-aligned etching is defined as the oxide layer.

3. The method for preparing a SONOS memory device according to claim 1, wherein: After removing the oxide layer and before forming the sidewall spacer, the preparation method further includes: Light doping is performed into the substrate to form a first lightly doped region and a second lightly doped region; the first lightly doped region is located in the substrate below the gap between the two polysilicon gates; the second lightly doped region is located in a storage well in the substrate on one side of each of the two polysilicon gates away from the gap.

4. The method for preparing a SONOS memory device according to claim 1, wherein: After providing the substrate and before forming the charge storage layer, the preparation method further includes: forming a pad oxide layer on the surface of the substrate, and performing ion implantation on the substrate to form a storage well; The pad oxide layer formed on the entire surface of the substrate is removed by an etching process.

5. The method for preparing a SONOS memory device according to claim 1, wherein: Forming the sidewall specifically includes: Growing a spacer material layer, wherein the spacer material layer fills the gap between the two polysilicon gates and also covers the upper surfaces and side surfaces of the two polysilicon gates and the surface of the charge storage layer; The spacer material layer is etched in a self-aligned manner, and the remaining spacer material layer is defined as the spacer.

6. A SONOS memory device comprising a plurality of memory cells, characterized in that: The storage unit includes: A substrate, on which a first storage tube and a second storage tube are formed; the first storage tube includes a first charge storage layer and a first polysilicon gate from bottom to top on the substrate; the second storage tube includes a second charge storage layer and a second polysilicon gate from bottom to top on the substrate; Sidewalls, the sidewalls comprising an isolation sidewall and a side sidewall; the side sidewalls comprising a first sidewall and a second sidewall; the isolation sidewall filling a gap between the first polysilicon gate and the second polysilicon gate; the first sidewall covering the sidewall of the first polysilicon gate away from the isolation sidewall; the second sidewall covering the sidewall of the second polysilicon gate away from the isolation sidewall; A first heavily doped region and a second heavily doped region, wherein the first heavily doped region is located in the substrate on a side of the sidewall 1 away from the isolation sidewall, and the second heavily doped region is located in the substrate on a side of the sidewall 2 away from the isolation sidewall.

7. The SONOS memory device according to claim 6, wherein: The storage unit further includes: a first lightly doped region, the first lightly doped region being located in the substrate below a gap between the first polysilicon gate and the second polysilicon gate; A second lightly doped region is located in a storage well in the substrate on one side of the polysilicon gate 1 and the polysilicon gate 2, respectively, away from the isolation sidewall.

8. The SONOS memory device according to claim 7, wherein: The first heavily doped region serves as the source region of the first storage transistor, and the first lightly doped region serves as the drain region of the first storage transistor; moreover, the first lightly doped region also serves as the source region of the second storage transistor, and the second heavily doped region serves as the drain region of the second storage transistor.

9. The SONOS memory device according to claim 6, wherein: One of the storage units is composed of two storage tubes, namely the first storage tube and the second storage tube; when one storage tube is read, the other storage tube is forcibly turned on or off to act as a selection tube.

10. The SONOS memory device according to claim 6, wherein: The memory cell further includes an interlayer dielectric layer, the interlayer dielectric layer covering the substrate, the sidewalls, the first polysilicon gate, and the second polysilicon gate; a plurality of contact holes formed in the interlayer dielectric layer, the contact holes being filled with metal to lead out electrical signals corresponding to each electrode; A first contact hole penetrates the interlayer dielectric layer to expose the first heavily doped region; in the first storage tube, a second contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 1; in the second storage tube, a third contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 2; and a fourth contact hole penetrates the interlayer dielectric layer to expose the second heavily doped region.

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