PMOS transistor and manufacturing method thereof
By employing a polysilicon gate structure that is wide at the top and narrow at the bottom, along with a protective layer design in the PMOS transistor, the problem of increased contact resistance of the polysilicon gate is solved, resulting in lower contact resistance and higher performance consistency, while simplifying the manufacturing process.
Patent Information
- Application Number
- CN202411085912.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-08
- Publication Date
- 2026-02-13
AI Technical Summary
During the shrinking of feature size in MOS transistors, the metal silicide of polysilicon gates is difficult to convert from a high-resistivity phase to a low-resistivity phase, resulting in increased contact resistance, which affects threshold voltage and high-frequency characteristics. At the same time, existing processes are unable to effectively protect the gate from epitaxial growth defects.
A top-wide, bottom-narrow structure is formed on the polysilicon gate, and a protective layer is used to cover the gate in the epitaxial process. Combined with the use of anisotropic etching and conformal material layers, the etching load effect is avoided, forming a Σ-shaped trench for epitaxial growth.
It effectively reduces the contact resistance of polysilicon gates, protects the gates from epitaxial growth defects, improves the performance consistency and electrical performance of PMOS transistors, simplifies the process flow, and reduces costs.
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Figure CN121531735A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor technology, and in particular to a PMOS transistor and a manufacturing method of the PMOS transistor. BACKGROUND
[0002] The polysilicon gate surface in a MOS transistor is usually formed with a metal silicide to reduce the contact resistance, and a metal contact hole formed above the polysilicon gate is electrically connected to the polysilicon gate through the metal silicide. However, as the feature size of the MOS transistor is reduced, the size of the polysilicon gate is reduced, and the metal silicide (such as cobalt silicide (CoSi)) on the surface of the polysilicon gate is difficult to be converted from a high-resistance phase to a low-resistance phase due to the line width effect, resulting in an increase in the resistance of the metal silicide, and ultimately leading to an increase in the contact resistance of the polysilicon gate, which can cause the threshold voltage of the MOS transistor to rise and also affect the high-frequency characteristics of the MOS transistor.
[0003] If the polysilicon gate is formed in an inverted trapezoidal structure, the upper surface area of the polysilicon gate can be increased while the feature size of the MOS transistor is reduced, which is beneficial to the conversion of the metal silicide from a high-resistance phase to a low-resistance phase, thereby avoiding an increase in the contact resistance of the polysilicon gate. However, in a conventional process for manufacturing a PMOS transistor, a polysilicon material layer is usually first formed and covered with a hard mask layer, and the polysilicon material layer and the hard mask layer are patterned, the polysilicon gate is formed from the polysilicon material layer, the hard mask layer covers the upper surface of the polysilicon gate, and a source / drain is formed using a trench epitaxy process. During the epitaxy process, the hard mask layer can protect the upper surface of the polysilicon gate to avoid the formation of "mushroom-shaped" gate defects due to selective epitaxial growth at the top end of the polysilicon gate, thereby avoiding the influence of such defects on the work function of the device and even causing the device to fail. However, the longitudinal cross-section of the PMOS transistor formed using this process is rectangular, which is not conducive to reducing the contact resistance of the gate surface. At present, there is a lack of a PMOS transistor manufacturing method that can effectively reduce the contact resistance of the gate surface while effectively protecting the gate during the epitaxy process for forming the source / drain to improve the performance of the PMOS transistor. SUMMARY
[0004] The present application provides a manufacturing method of a PMOS transistor, which can effectively reduce the contact resistance of the gate surface while effectively protecting the gate during the epitaxy process for forming the source / drain to improve the performance of the PMOS transistor. The present application further provides a PMOS transistor.
[0005] In one aspect, the present application provides a manufacturing method of a PMOS transistor, the manufacturing method comprising:
[0006] forming a first dielectric layer on a substrate and forming a first trench penetrating through the first dielectric layer;
[0007] forming a side wall covering the sidewall of the first trench and a gate dielectric layer connecting the side wall and covering the bottom wall of the first trench;
[0008] filling the first trench with a polysilicon gate, the upper surface of the polysilicon gate being flush with the upper surface of the first dielectric layer;
[0009] etching back the first dielectric layer to expose part of the outer side of the side wall;
[0010] sequentially covering the substrate with a first conformal material layer and a second conformal material layer, the upper surface of the second conformal material layer being higher than the top surface of the first dielectric layer;
[0011] performing a planarization process to expose the top surface of the first conformal material layer, to make the top surface of the first conformal material layer flush with the upper surface of the second conformal material layer, and to etch the exposed first conformal material layer to expose the upper surface of the polysilicon gate, forming a second trench with the polysilicon gate as the bottom wall;
[0012] filling the second trench with a protective layer, the protective layer covering the upper surface of the polysilicon gate, and removing the first dielectric layer, the first conformal material layer and the second conformal material layer; and
[0013] forming a Σ-shaped trench on both sides of the polysilicon gate and growing a source / drain epitaxial layer in the Σ-shaped trench by an epitaxial process, wherein the side surface of the polysilicon gate is covered with the side wall and the upper surface is covered with the protective layer when the epitaxial process is performed.
[0014] Optionally, the manufacturing method further comprises:
[0015] removing the protective layer covering the upper surface of the polysilicon gate; and
[0016] forming a metal silicide on the upper surface of the polysilicon gate and the source / drain epitaxial layer.
[0017] Optionally, before forming the side wall, the first trench exposes the substrate.
[0018] Optionally, forming a side wall covering the sidewall of the first trench and a gate dielectric layer connecting the side wall and covering the bottom wall of the first trench comprises:
[0019] forming a second dielectric layer along the surface of the first dielectric layer and the inner wall of the first trench;
[0020] etching the second dielectric layer by a non-isotropic etching process to expose the upper surface of the first dielectric layer and the substrate in the first trench, the remaining second dielectric layer covering the sidewall of the first trench and being upper-narrow and lower-wide; and
[0021] forming a third dielectric layer along the first dielectric layer, the second dielectric layer and the surface of the substrate, the stack of the second dielectric layer and the third dielectric layer covering the first trench sidewall forms the sidewall, and the third dielectric layer covering part of the substrate forms the gate dielectric layer.
[0022] Optionally, after forming the first dielectric layer and the first trench, the first trench bottom wall has a pad oxide layer covering the substrate.
[0023] Optionally, forming a sidewall covering the first trench sidewall and forming a gate dielectric layer connecting the sidewall and covering the first trench bottom wall comprises:
[0024] forming a second dielectric layer along the first dielectric layer surface and the first trench inner wall;
[0025] etching the second dielectric layer by a non-isotropic etching process to expose the first dielectric layer upper surface and the substrate inside the first trench, and the remaining second dielectric layer covers the first trench sidewall and is narrow on top and wide on bottom; and
[0026] forming a third dielectric layer along the first dielectric layer, the second dielectric layer and the surface of the substrate, the stack of the third dielectric layer and the second dielectric layer covering the first trench sidewall and the pad oxide layer covered thereon forms the sidewall, and the stack of the third dielectric layer and the pad oxide layer inside the first trench between the opposite sidewalls forms the gate dielectric layer.
[0027] Optionally, filling a protective layer in the second trench comprises:
[0028] forming a fourth dielectric layer along the upper surface of the second conformal material layer and the inner wall of the second trench; and
[0029] performing a planarization process to make the upper surface of the remaining fourth dielectric layer flush with the upper surface of the first conformal material layer, and the remaining fourth dielectric layer covers the upper surface of the polysilicon gate and forms the protective layer.
[0030] Optionally, the fourth dielectric layer comprises at least one of silicon nitride, silicon oxide and silicon oxynitride, and the fourth dielectric layer is formed by an ALD process or an SCVD process.
[0031] Optionally, filling a protective layer in the second trench comprises:
[0032] forming a metal layer along the upper surface of the second conformal material layer and the inner wall of the second trench; and
[0033] The metal layer is subjected to thermal annealing to form a metal silicide layer by silicidation reaction between the metal layer and the polysilicon gate, and the metal silicide layer is used as the protective layer.
[0034] In another aspect, the application provides a PMOS transistor formed by the above manufacturing method, comprising:
[0035] a substrate;
[0036] a gate dielectric layer, a polysilicon gate and a sidewall formed on the substrate, the sidewall covering side surfaces of the gate dielectric layer and the polysilicon gate, wherein the polysilicon gate has a structure of being wide at the top and narrow at the bottom; and
[0037] a source / drain epitaxial layer formed in the Σ-shaped groove on both sides of the polysilicon gate.
[0038] Optionally, the PMOS transistor further comprises a protective layer located above the sidewall and covering a top surface of the polysilicon gate.
[0039] The manufacturing method of the PMOS transistor and the PMOS transistor provided by the application have at least the following advantages:
[0040] Firstly, the polysilicon gate in the PMOS transistor has a structure of being wide at the top and narrow at the bottom, which can increase the top surface area of the polysilicon gate while meeting the requirement of small transistor feature size, and is conducive to the conversion of the metal silicide formed on the top surface of the polysilicon gate from high resistance phase to low resistance phase, thereby helping to reduce the contact resistance of the polysilicon gate and improve the device performance.
[0041] Secondly, the protective layer on the top surface of the polysilicon gate and the sidewall can protect the polysilicon gate in the epitaxial process of forming the source / drain epitaxial layer, so as to avoid the epitaxial growth of the polysilicon gate and form gate defects, and help to improve the device performance.
[0042] Thirdly, by using the manufacturing method, the formation of the polysilicon gate and the protective layer does not need to use photolithography process, and the process is simple and the manufacturing cost is low. In addition, when filling the protective layer in the second groove with the top surface of the polysilicon gate as the bottom wall, the polysilicon gate does not need to be etched to reduce its top surface, which can avoid the uneven thickness of the polysilicon gate due to etching load effect, thereby reducing the risk of device performance deterioration caused by uneven thickness of the polysilicon gate. In addition, by the cooperation of the first conformal material layer and the second conformal material layer, the depth of the second groove can be accurately controlled, and the top of the polysilicon gate of any size has the same thickness of the second groove, which is also conducive to the same influence on the polysilicon gate of any size in the subsequent ion implantation and other steps, and is conducive to the consistency of all device performances. BRIEF DESCRIPTION OF DRAWINGS
[0043] Figure 1 is a flow chart of a manufacturing method of a PMOS transistor according to an embodiment of the present application.
[0044] Figures 2A-2N is a cross-sectional view of a manufacturing method of a PMOS transistor according to an embodiment of the present application.
[0045] Figures 3A-3D is a cross-sectional view of a manufacturing method of a PMOS transistor according to another embodiment of the present application. DETAILED DESCRIPTION
[0046] The PMOS transistor and the manufacturing method thereof according to the present application will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the terms "first", "second", etc. are used in the description for the purpose of differentiating between similar elements, and do not necessarily describe a particular order or time sequence. It should be understood that these terms can be replaced under appropriate circumstances. It should be understood that the drawings of the specification are greatly simplified and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the purpose of the embodiments of the present application. In addition, the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the devices described in the figures. For example, if the structure in the figure is inverted or otherwise positioned differently (such as rotated), the exemplary term "on" can also include "under" and other orientation relationships.
[0047] The manufacturing method of a PMOS transistor according to an embodiment of the present application will be described below with reference to the accompanying drawings.
[0048] Referring to Figure 1 , Figure 2A and Figure 3A , the manufacturing method of a PMOS transistor according to an embodiment of the present application includes, at step S1, forming a first dielectric layer 110 on a substrate 100, and forming a first trench 10 penetrating through the first dielectric layer 110.
[0049] The substrate 100 can be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), or can be other substrates well known to those skilled in the art for carrying semiconductor devices. In the following description, the substrate 100 is, for example, a silicon substrate. The substrate 100 can include configurations depending on the design requirements of the semiconductor device, such as certain doping ions can be implanted to adjust the electrical parameters according to the design requirements, and isolation structures can be formed in the substrate 100.
[0050] The first dielectric layer 110 may include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and NDC (nitrogen-doped silicon carbide). The first dielectric layer 110 may be one or a combination of borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin-coated glass (SOG), tetraethyl orthosilicate (TEOS), or high-density plasma CVD (HDP-CVD) oxide. In the following description, the first dielectric layer 110 is, for example, silicon oxide formed from tetraethyl orthosilicate (TEOS).
[0051] like Figure 2A As shown, in one embodiment, no other material is formed on the surface of the substrate 100 before the formation of the first dielectric layer 110. However, the invention is not limited to this; for example, in another embodiment, an oxide layer or other materials may be formed on the surface of the substrate 100 before the formation of the first dielectric layer 110.
[0052] The first trench 10, penetrating the first dielectric layer 110, can be formed using photolithography and etching processes. For example... Figure 2B As shown, in one embodiment, the first trench 10 exposes the substrate 100, meaning the substrate 100 forms the bottom wall of the first trench 10. The invention is not limited thereto; for example, in another embodiment, see... Figure 3A After etching the first dielectric layer 110 to form the first trench 10, a pad oxide layer 101 (e.g., silicon oxide) can be formed on the exposed substrate 100 surface by a process such as thermal oxidation.
[0053] Reference Figure 1 In step S2, a sidewall that is narrower at the top and wider at the bottom is formed, covering the sidewall of the first trench 10, and a grid dielectric layer is formed connecting the sidewall and covering the bottom wall of the first trench 10. The width direction of the sidewall is parallel to the length direction of the trench.
[0054] As an example, in one embodiment, in Figure 2A Based on the structure shown, step S2 may include the following process:
[0055] First, refer to Figure 2B A second dielectric layer 120 is formed along the surface of the first dielectric layer 110 and the inner wall of the first trench 10. The second dielectric layer 120 conformally covers the surface of the first dielectric layer 110 and the inner wall of the first trench 10, for example, using silicon nitride.
[0056] Then, refer to Figure 2CThe second dielectric layer 120 is etched by a non-isotropic etching process to expose the upper surface of the first dielectric layer 110 and the substrate 100 in the first trench 10, and the remaining second dielectric layer 120 covers the sidewall of the first trench 10 and is narrow on top and wide on bottom. For example, the first dielectric layer 110 and the substrate 100 can be used as etching stop layers of the non-isotropic etching process by using the etching selectivity of the second dielectric layer 120 to the first dielectric layer 110 and the substrate 100.
[0057] Then, referring to Figure 2D , a third dielectric layer 130 is formed on the surface of the first dielectric layer 110, the second dielectric layer 120 and the substrate 100, for example, conformally covering the surface of the first dielectric layer 110, the second dielectric layer 120 and the substrate 100 in the first trench 10, and the third dielectric layer 130 is, for example, silicon oxide. In this embodiment, the stack of the third dielectric layer 130 covering the sidewall of the first trench 10 and the second dielectric layer 120 forms a sidewall SP1, and the part of the third dielectric layer 130 covering the surface of the substrate 100 in the first trench 10 forms a gate dielectric layer GOX.
[0058] For example, in another embodiment, based on the structure shown in Figure 3A , the step S2 can include the following processes:
[0059] First, referring to Figure 3B , the second dielectric layer 120 is formed on the surface of the first dielectric layer 110 and the inner wall of the first trench 10, for example, conformally covering the surface of the first dielectric layer 110 and the inner wall of the first trench 10, and the second dielectric layer 120 is, for example, silicon nitride.
[0060] Then, referring to Figure 3C , the second dielectric layer 120 is etched by a non-isotropic etching process to expose the upper surface of the first dielectric layer 110 and the pad oxide layer 101 in the first trench 10, and the remaining second dielectric layer 120 covers the sidewall of the first trench 10 and is narrow on top and wide on bottom. For example, the first dielectric layer 110 and the pad oxide layer 101 can be used as etching stop layers of the non-isotropic etching process by using the etching selectivity of the second dielectric layer 120 to the first dielectric layer 110 and the pad oxide layer 101.
[0061] Then, referring to Figure 3DA third dielectric layer 130 is formed on the surface of the first dielectric layer 110, the second dielectric layer 120 and the pad oxide layer 101 in the first trench 10, for example, conformally covering the surface of the first dielectric layer 110, the second dielectric layer 120 and the pad oxide layer 101 in the first trench 10, and the third dielectric layer 130 is, for example, silicon oxide. In this embodiment, the stack of the third dielectric layer 130 covering the sidewall of the first trench 10 and the second dielectric layer 120 and the pad oxide layer 101 covered thereby constitutes a side wall SP1', and the stack of the third dielectric layer 130 and the pad oxide layer 101 between the opposite side walls SP1' in the first trench 10 constitutes a gate dielectric layer GOX'. The side wall SP1' and the gate dielectric layer GOX' are different from the side wall SP1 and the gate dielectric layer GOX in the above embodiment.
[0062] As can be seen from the above description, according to the embodiment of the present application, the gate dielectric layer (such as the gate dielectric layer GOX shown in Figure 2D or the gate dielectric layer GOX' shown in Figure 3D ) is formed after the formation of the first trench 10, which can avoid the damage of the gate dielectric layer caused by the etching process for forming the first trench 10, compared with the formation of the first trench after the formation of the gate dielectric layer. Moreover, by setting the thickness of the second dielectric layer 120 and / or the third dielectric layer 130 and the parameters of the above-mentioned anisotropic etching process, the side wall (such as the side wall SP shown in Figure 2D or the side wall SP1' shown in Figure 3D ) can have a structure of being narrow at the top and wide at the bottom, and the thickness of the second dielectric layer 120 and / or the third dielectric layer 130 and the parameters of the anisotropic etching process can be adjusted as needed. For example, the anisotropic dry etching is performed by using a dry etching device, wherein the process gas includes, for example, CH2F2 and O2, and the morphology of the second dielectric layer 120 after the completion of the anisotropic etching process can be adjusted by adjusting the parameters such as the flow rate of the process gas, the pressure, the ion acceleration voltage, the RF source power and the etching time.
[0063] In the following embodiments, the structure shown in Figure 2D is taken as an example to describe the subsequent steps of the manufacturing method of the PMOS transistor shown in Figure 1 . It can be understood that the subsequent steps can also be performed based on the structure shown in Figure 3D .
[0064] Referring to Figure 1 , Figure 2E and Figure 2F , in step S3, a polysilicon gate PG is filled in the first trench 10, and the upper surface of the polysilicon gate PG is flush with the upper surface of the first dielectric layer 110.
[0065] As an example, referring to Figure 2E , first, a chemical vapor deposition process can be used to deposit a polysilicon material on the substrate 100 to form a polysilicon material layer 140, the polysilicon material layer 140 fills the first trench 10 and covers on the third dielectric layer 130 outside the first trench 10, and the upper surface of the polysilicon material layer 140 is higher than the third dielectric layer 130; then, referring to Figure 2F , a planarization process (such as CMP (chemical mechanical polishing)) is performed to expose the upper surface of the first dielectric layer 110 outside the first trench 10, and the remaining polysilicon material layer 140 fills in the first trench 10 to form a polysilicon gate PG, and the upper surface of the polysilicon gate PG is flush with the upper surface of the first dielectric layer 110. Optionally, ion implantation can be performed on the polysilicon gate PG to adjust its electrical properties.
[0066] After the above process, the gate dielectric layer GOX (or the gate dielectric layer GOX' as shown in Figure 3D ) and the polysilicon gate PG are formed in the first trench 10 on the substrate 100, and since the sidewall of the first trench 10 forms the upper-narrow-and-lower-wide sidewall SP1 (or the sidewall SP1' as shown in Figure 3D ), after the polysilicon gate PG is filled in the first trench 10, the polysilicon gate PG has an upper-wide-and-lower-narrow structure, which can increase the upper surface area of the polysilicon gate PG while meeting the requirement of small channel size, and is beneficial to the phase conversion of the metal silicide formed on the upper surface of the polysilicon gate PG from high resistance to low resistance, thereby helping to reduce the contact resistance of the polysilicon gate PG; by controlling the morphology of the sidewall, the morphology of the polysilicon gate PG is adjusted, and compared with the method of directly forming an upper-wide-and-lower-narrow polysilicon gate and then forming a sidewall on the side of the polysilicon gate, the process of the embodiment of the present application is more convenient to control the side morphology of the polysilicon gate PG. In addition, it is found that if the upper-wide-and-lower-narrow polysilicon gate is formed first and then the sidewall is formed on the side, it is difficult for the sidewall material to adhere to the bottom of the narrow polysilicon gate, and voids are easily formed, which affects the performance of the PMOS transistor. The embodiment of the present application first forms an upper-narrow-and-lower-wide sidewall in the first trench 10, and the remaining space in the first trench 10 is upper-wide-and-lower-narrow, and it is difficult for the polysilicon material to fill in the space, and voids are not easily formed.
[0067] The embodiment of the present application uses a trench epitaxy process to form source / drain epitaxial layers on both sides of the polysilicon gate PG to facilitate the formation of the source / drain of the PMOS transistor, and in order to avoid the formation of "mushroom-shaped" gate defects due to selective epitaxial growth on the upper surface of the polysilicon gate PG in the trench epitaxy process, a protective layer is formed on the upper surface of the polysilicon gate PG before the trench epitaxy process is performed. The following will be described in detail.
[0068] Referring toFigure 1 and Figure 2G In step S4, the first dielectric layer 110 is etched back to expose part of the outer side surface of the side wall SP.
[0069] For example, a non-isotropic dry etching process can be used to etch the first dielectric layer 110 without a mask, using the etching selectivity of the first dielectric layer 110 to the polysilicon gate PG and the side wall SP. Through this etching back, the upper surface of the first dielectric layer 110 is lower than the upper surface of the polysilicon gate PG.
[0070] Referring to Figure 1 and Figure 2H In step S5, a first conformal material layer 150 and a second conformal material layer 160 are sequentially deposited on the substrate 100, and the upper surface of the second conformal material layer 160 is higher than the top surface of the first conformal material layer 150.
[0071] The first conformal material layer 150 and the second conformal material layer 160 can be formed by a CVD process, and sequentially conformally cover the substrate 100. By adjusting the thickness of the first conformal material layer 150 and the second conformal material layer 160, the upper surface of the second conformal material layer 160 can be higher than the top surface of the first conformal material layer 150, facilitating subsequent planarization process to make the top surface of the first conformal material layer 150 and the upper surface of the second conformal material layer 160 flush. As an example, the first conformal material layer 150 is silicon oxide, and the second conformal material layer 160 is silicon nitride.
[0072] Referring to Figure 1 , Figure 2I and Figure 2J In step S6, a planarization process is performed to expose the top surface of the first conformal material layer 150, make the top surface of the first conformal material layer 150 flush with the upper surface of the second conformal material layer 160, and etch the exposed first conformal material layer to expose the upper surface of the polysilicon gate PG, forming a second trench 20 with the polysilicon gate PG as the bottom wall.
[0073] As an example, in step S6, a planarization process is first performed, which can be CMP. When performing CMP, the first conformal material layer 150 can be used as a polishing stop layer, and after CMP, the top surface of the exposed first conformal material layer 150 is flush with the upper surface of the remaining second conformal material layer 160, as shown in Figure 2I Then, for example, a non-isotropic dry etching process is used to etch the exposed first conformal material layer 150, which can use the polysilicon gate PG as an etching stop layer, as shown in Figure 2JBecause the second conformal material layer 160 has etching selectivity with the first conformal material layer 150, the second conformal material layer 160 and the first conformal material layer 150 covered thereby on both sides of the polysilicon gate PG are substantially not etched, and after the etching is completed, the upper surface of the polysilicon gate PG is exposed, and the upper surface of the polysilicon gate PG is lower than the upper surface of the second conformal material layer 160, thereby forming the second trench 20 with the polysilicon gate PG as the bottom wall, and the sidewall of the second trench 20 is formed by the second conformal material layer 160 and the first conformal material layer 150 on both sides of the polysilicon gate PG.
[0074] By using the cooperation of the first conformal material layer 150 and the second conformal material layer 160 (after mechanical chemical planarization, etching is performed), the second trench 20 is formed, and the thickness of the second trench 20 is directly related to the thickness of the first conformal material layer 150, so when this process is used to form the protective layer on the top of the polysilicon gate PG, the second trench 20 with consistent depth can be formed corresponding to the large size of the polysilicon gate PG (large channel width) or the small size of the polysilicon gate PG (small channel width). For reference Figure 1 、 Figure 2K and Figure 2L In step S7, the protective layer BL is filled in the second trench 20, so that the protective layer BL covers the upper surface of the polysilicon gate PG, and the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 are removed.
[0075] Because the depth of the second trench 20 is relatively consistent throughout the wafer, that is, the thickness of the protective layer BL is relatively consistent regardless of the size of the polysilicon gate PG (i.e. the channel size) (the thickness of the second conformal material layer 150 determines the depth of the second trench 20, and the thickness of the second conformal material layer 150 on the top of each polysilicon gate PG is the same), so when subsequent processes such as pre-amorphization to form metal silicide or ion implantation of source and drain are performed, the polysilicon gate PG is affected consistently, which well guarantees the device performance consistency of the germanium-silicon epitaxial source and drain device formed by the method of forming the upper wide and lower narrow polysilicon gate PG structure adopted by the present application.
[0076] The protective layer BL can be formed of a material suitable for protecting the polysilicon gate PG in an epitaxial process to avoid selective epitaxial growth of the polysilicon gate PG. As an example, at least one of silicon nitride, silicon oxide and silicon oxynitride can be used to form the protective layer BL, or a metal material can also be used to form the protective layer BL.
[0077] As an example, in an embodiment, the process of forming the protective layer BL includes the following process: first, referring to Figure 2K, a fourth dielectric layer 170 is formed along the upper surface of the second conformal material layer 160 and the inner wall of the second trench 20; then, referring to Figure 2L , a planarization process (such as CMP) is performed to make the upper surface of the remaining fourth dielectric layer 170 flush with the upper surface of the second conformal material layer 160, and the remaining fourth dielectric layer 170 covers the upper surface of the polysilicon gate PG and forms a protective layer BL. In order to avoid the protective layer BL being removed when the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 on both sides of the polysilicon gate PG are removed later, the fourth dielectric layer 170 can be formed by ALD (atomic layer deposition) or SCVD (sulfur chemical vapor deposition) process, so that the film layer of the fourth dielectric layer 170 is more compact than that formed by conventional CVD process. Before the planarization process is performed, the fourth dielectric layer 170 can be filled or not filled in the second trench 20. In this embodiment, the fourth dielectric layer 170 can include at least one of silicon nitride, silicon oxide and silicon oxynitride.
[0078] In another embodiment, the protective layer BL is formed by using a metal material. Specifically, the following process (not shown in the figure) can be included: first, a fourth dielectric layer 170 is formed along the upper surface of the second conformal material layer 160 and the inner wall of the second trench 20 to form a metal layer, which can include Ti, Ni or Co and the like; then, heat annealing is performed to make the metal layer react with the polysilicon gate PG to form a metal silicide layer, and the metal silicide layer is used as the protective layer BL; then, the remaining metal layer which does not react can be removed by etching or CMP, and then the protective layer BL which is the same as that shown in the figure but is made of metal silicide can also be obtained. Figure 2L
[0079] After the protective layer BL is formed, dry etching or wet etching can be used to remove the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 on both sides of the polysilicon gate PG. Referring to Figure 2M In an embodiment, the protective layer BL is, for example, a silicon nitride film formed by ALD process, and because the film layer is compact, when the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 are removed, the protective layer BL can be more compact than the silicon nitride formed by conventional CVD process on both sides of the polysilicon gate PG, so that the protective layer BL and the silicon nitride on both sides of the polysilicon gate PG have etching selectivity. After the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 are removed by etching, the upper surface of the polysilicon gate PG is still covered by the protective layer BL.
[0080] In another embodiment, the protective layer BL is a silicon oxide film formed by an ALD or SCVD process. Since the film layer is dense, when the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 are removed, the protective layer BL is more dense than the silicon oxide formed by a conventional CVD process on both sides of the polysilicon gate PG. Therefore, the protective layer BL has etching selectivity with the silicon oxide on both sides of the polysilicon gate PG. After the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 are removed, the upper surface of the polysilicon gate PG is still covered by the protective layer BL.
[0081] In yet another embodiment, the protective layer BL is a metal silicide layer formed on the upper surface of the polysilicon gate PG by depositing a metal material and performing thermal annealing. When the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 on both sides of the polysilicon gate PG are removed, the metal silicide layer has etching selectivity with the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160. Therefore, after the first dielectric layer 110, the first conformal material layer 150 and the second conformal material layer 160 are removed, the upper surface of the polysilicon gate PG is still covered by the protective layer BL.
[0082] Optionally, before the subsequent steps are performed, p-type ion implantation can be performed on the substrate 100 on both sides of the polysilicon gate PG to form a PLDD region (not shown in the figure) on both sides of the polysilicon gate PG.
[0083] Referring to Figure 1 and Figure 2N In step S8, a Σ-shaped trench is formed on the surface of the substrate 100 on both sides of the polysilicon gate PG, and a source / drain epitaxial layer 180 is formed in the Σ-shaped trench by an epitaxial process. When the epitaxial process is performed, the side surface of the polysilicon gate PG is covered by the side wall SP1 and the upper surface is covered by the protective layer BL.
[0084] The source / drain epitaxial layer 180 formed in the Σ-shaped trench on both sides of the polysilicon gate PG serves as the source / drain of the PMOS transistor. The protective layer BL and the side wall SP1 can protect the polysilicon gate PG from epitaxial growth in the epitaxial process of forming the source / drain epitaxial layer 180, which helps to improve the quality of the PMOS transistor.
[0085] As an example, step S8 can include:
[0086] First, a recess is formed in the region of the substrate 100 on both sides of the polysilicon gate PG to be the source / drain, for example, by anisotropic dry etching;
[0087] Afterwards, the above-mentioned groove is etched by using a suitable alkaline etchant such as tetramethylammonium-hydroxide (TMAH) to form a concave angle on the sidewall of the groove, so that the longitudinal section of the groove parallel to the channel length direction is in the shape of ∑ (see Fig. 2B), thereby forming a ∑-shaped trench. By forming the ∑-shaped trench, it is beneficial for the source / drain epitaxial layer 180 formed in the ∑-shaped trench later to generate compressive stress on the substrate 100 of the channel region, thereby improving the hole mobility. Figure 2N ) to form a ∑-shaped trench. By forming the ∑-shaped trench, it is beneficial for the source / drain epitaxial layer 180 formed in the ∑-shaped trench later to generate compressive stress on the substrate 100 of the channel region, thereby improving the hole mobility.
[0088] Afterwards, an epitaxial process (for example, selective epitaxy) is performed in the ∑-shaped trench to form the source / drain epitaxial layer 180. As an example, a germanium-silicon seed layer can be first formed on the inner wall of the ∑-shaped trench, and then a germanium-silicon layer is grown on the seed layer by epitaxial growth to fill the ∑-shaped trench, and a cap layer of monocrystalline silicon is formed on the top of the ∑-shaped trench. The seed layer, the germanium-silicon layer and the cap layer form the source / drain epitaxial layer 180. During the epitaxial growth, a dopant gas such as borane (B2H6) can be doped to introduce p-type dopant ions as needed.
[0089] After the epitaxial process is completed, the manufacturing method can further include the steps of covering another sidewall (not shown in the figure) on the surface of the sidewall SP1 away from the polysilicon gate PG and performing source / drain ion implantation (not shown in the figure) on the source / drain epitaxial layer 180. The other sidewall can be formed by a sidewall process known in the art, which can include at least one of silicon nitride, silicon oxide or silicon oxynitride. The source / drain ion implantation is, for example, a p-type heavy doping implantation.
[0090] The manufacturing method of the PMOS transistor of the embodiment of the present application can further include the following process: forming a metal silicide on the surface of the polysilicon gate PG and the source / drain epitaxial layer 180. The metal silicide can include at least one of titanium silicide, cobalt silicide, nickel silicide and tantalum silicide. Referring to the above-mentioned process of forming the protective layer BL, when the protective layer BL is formed by using a dielectric material such as silicon nitride or silicon oxide, the protective layer BL can be removed first. When the protective layer BL is formed as a metal silicide layer, the protective layer BL can not be removed. Further, an interlayer dielectric layer (ILD) can be formed on the substrate 100 and a metal plug can be formed through the interlayer dielectric layer. The metal plug connects the corresponding polysilicon gate PG or source / drain epitaxial layer 180 through the metal silicide. Compared with the case where the metal silicide is not formed, the metal silicide can reduce the contact resistance of the polysilicon gate PG. In addition, since the polysilicon gate PG has a structure of being wide at the top and narrow at the bottom, the upper surface area of the polysilicon gate PG can be increased while satisfying a smaller transistor feature size, so that the metal silicide is more likely to be converted from a high resistance phase to a low resistance phase, thereby effectively reducing the resistance between the metal contact hole and the polysilicon gate PG, which helps to improve the performance of the PMOS transistor.
[0091] Using the PMOS transistor manufacturing method described in the above embodiments, a polysilicon gate PG, which is wider at the top and narrower at the bottom, can be formed on the substrate 100. Furthermore, the upper surface of the polysilicon gate PG is covered by a protective layer BL, and the sides are covered by sidewalls SP1 (or as shown in the previous embodiments). Figure 3D The sidewall SP1' shown is covered by an epitaxial layer. The process of forming the source / drain epitaxial layer 180 using an epitaxial process does not cause selective epitaxial growth on the upper surface of the polysilicon gate PG, which helps to improve the performance of the PMOS transistor. Moreover, using this manufacturing method, the formation of the polysilicon gate PG and the protective layer BL does not require photolithography, which simplifies the process and reduces manufacturing costs. Furthermore, when forming the second trench 20 with the upper surface of the polysilicon gate PG as the bottom wall, it is not necessary to etch the polysilicon gate PG to reduce its upper surface, which can avoid uneven thickness of the polysilicon gate PG due to the etching load effect, thereby reducing the risk of device performance degradation due to uneven thickness of the polysilicon gate PG.
[0092] This invention also relates to a PMOS transistor, which can be formed using the manufacturing method of the PMOS transistor described in the above embodiments. (Refer to...) Figures 2A-2N as well as Figures 3A-3D The PMOS transistor includes a substrate 100 and a gate dielectric layer GOX (or as shown) formed on the substrate 100. Figure 3D The gate dielectric layer (GOX'), polysilicon gate (PG), and sidewall (SP) shown are also described. Figure 3D The sidewall SP1' shown also includes source / drain epitaxial layers 180 embedded in the substrate 100 on both sides of the polysilicon gate PG, and the sidewall SP (or as shown) Figure 3D The sidewall SP1' shown is covered with a grid dielectric layer GOX (or as shown) Figure 3D The side of the gate dielectric layer (GOX') and the polysilicon gate PG shown is shown. The polysilicon gate PG has a structure that is wider at the top and narrower at the bottom.
[0093] like Figure 2NAs shown, Σ-shaped trenches can be formed in the substrate 100 on both sides of the polysilicon gate PG. The source / drain epitaxial layer 180 fills the Σ-shaped trenches. The Σ-shaped trenches help the source / drain epitaxial layer 180 generate compressive stress on the substrate 100 in the channel region, thereby improving the hole mobility. Optionally, the PMOS transistor may also include a protective layer BL, which covers the upper surface of the polysilicon gate PG. During the formation of the source / drain epitaxial layer 180, the protective layer BL can protect the upper surface of the polysilicon gate PG to avoid selective epitaxial growth on the upper surface of the polysilicon gate PG, which could lead to gate defects and affect device performance. The present invention is not limited thereto. In another embodiment of the PMOS transistor, the protective layer BL on the upper surface of the polysilicon gate PG is removed after the epitaxial process is completed. Metal silicide is formed on the surface of the source / drain epitaxial layer 180 and the polysilicon gate PG. Furthermore, the PMOS transistor may also include an interlayer dielectric layer covering the polysilicon gate PG and the source / drain epitaxial layer 180, and a metal plug penetrating the interlayer dielectric layer. The metal plug is connected to the corresponding polysilicon gate PG or the source / drain epitaxial layer 180 through the metal silicide.
[0094] A second dielectric layer 120 and a third dielectric layer 130 may be formed on the substrate 100. The second dielectric layer 120 is located on both sides of the polysilicon gate PG, and is narrower at the top and wider at the bottom (i.e., in a longitudinal section along the channel length, the width of the top of the second dielectric layer 120 is smaller than the width of the bottom). The third dielectric layer 130 is located between the polysilicon gate PG and the second dielectric layer 120, and between the polysilicon gate 130 and the substrate 100. The sidewall SP includes the second dielectric layer 120 and the third dielectric layer 130 located on the side of the polysilicon gate PG. The gate dielectric layer (e.g., Figure 2N The gate dielectric layer shown is GOX or as shown Figure 3D The gate dielectric layer (GOX') shown includes a third dielectric layer 130 located between the polysilicon gate PG and the substrate 100. Optionally, refer to Figure 3D In one embodiment, a pad oxide layer 101 may also be formed on the substrate 100 below the third dielectric layer 130, wherein the gate dielectric layer (e.g. Figure 3D The gate dielectric layer (GOX') shown may also include a pad oxide layer 101 located between the polysilicon gate PG and the substrate 100.
[0095] The PMOS transistor has a polysilicon gate PG with a structure of narrow top and wide bottom (i.e., from the longitudinal section in the channel length direction, the width of the top of the polysilicon gate PG is smaller than the width of the bottom), which can increase the upper surface area of the polysilicon gate PG when the transistor feature size is small, and can avoid the upper surface area of the polysilicon gate PG being too small when the transistor feature size is reduced, which is beneficial to the metal silicide formed on the upper surface of the polysilicon gate PG being converted from a high-resistance phase to a low-resistance phase, and helps to avoid the contact resistance of the upper surface of the polysilicon gate PG being increased, thereby helping to improve the performance of the PMOS transistor. The PMOS transistor can be formed by using the manufacturing method described above, wherein, in the epitaxial process of forming the source / drain epitaxial layer 180, the protective layer BL covering the upper surface of the polysilicon gate PG and the side wall SP (or the side wall SP1' as shown in Figure 3D The protective layer BL and the side wall SP (or the side wall SP1' as shown in
[0096] It should be noted that the embodiments in the present specification are described in a progressive manner, and each part focuses on the differences from the previous part, and the related parts can be understood by reference.
[0097] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not deviate from the technical solutions of the present application, shall fall within the protection scope of the present application.
Claims
1. A method for manufacturing a PMOS transistor, characterized in that, include: A first dielectric layer is formed on the substrate, and a first trench is formed through the first dielectric layer; A sidewall that is narrow at the top and wide at the bottom is formed to cover the sidewall of the first trench, and a grid dielectric layer is formed to connect the sidewall and cover the bottom wall of the first trench. A polysilicon gate is filled in the first trench, and the upper surface of the polysilicon gate is flush with the upper surface of the first dielectric layer. The first dielectric layer is etched back to expose a portion of the outer surface of the sidewall; A first conformal material layer and a second conformal material layer are sequentially deposited on the substrate, wherein the upper surface of the second conformal material layer is higher than the top surface of the first dielectric layer; A planarization process is performed to expose the top surface of the first conformal material layer, making the top surface of the first conformal material layer flush with the upper surface of the second conformal material layer, and the exposed first conformal material layer is etched to expose the upper surface of the polysilicon gate, forming a second trench with the polysilicon gate as the bottom wall. A protective layer is filled into the second trench to cover the upper surface of the polysilicon gate, and the first dielectric layer, the first conformal material layer, and the second conformal material layer are removed. as well as A Σ-shaped trench is formed on both sides of the polysilicon gate, and a source / drain epitaxial layer is grown in the Σ-shaped trench using an epitaxial process. During the epitaxial process, the sidewalls of the polysilicon gate are covered and the protective layer is covered on the upper surface.
2. The manufacturing method as described in claim 1, characterized in that, After completing the epitaxial process, the process further includes: Remove the protective layer covering the upper surface of the polysilicon gate; and Metal silicides are formed on the upper surfaces of the polysilicon gate and the source / drain epitaxial layers.
3. The manufacturing method as described in claim 1, characterized in that, The first trench exposes the substrate before the sidewalls are formed.
4. The manufacturing method as described in claim 3, characterized in that, Forming a sidewall covering the sidewall of the first trench, and forming a grid dielectric layer connecting the sidewall and covering the bottom wall of the first trench, includes: A second dielectric layer is formed along the surface of the first dielectric layer and the inner wall of the first trench; The second dielectric layer is etched using an anisotropic etching process, exposing the upper surface of the first dielectric layer and the substrate within the first trench. The remaining second dielectric layer covers the sidewalls of the first trench and is narrower at the top and wider at the bottom. A third dielectric layer is formed along the first dielectric layer, the second dielectric layer, and the surface of the substrate. The stack of the second dielectric layer and the third dielectric layer covering the sidewall of the first trench constitutes the sidewall. The portion of the third dielectric layer covering the substrate constitutes the gate dielectric layer.
5. The manufacturing method as described in claim 1, characterized in that, After the first dielectric layer and the first trench are formed, the bottom wall of the first trench has a pad oxide layer covering the substrate.
6. The manufacturing method as described in claim 5, characterized in that, Forming a sidewall covering the sidewall of the first trench, and forming a grid dielectric layer connecting the sidewall and covering the bottom wall of the first trench, includes: A second dielectric layer is formed along the surface of the first dielectric layer and the inner wall of the first trench; The second dielectric layer is etched using an anisotropic etching process, exposing the substrate on the upper surface of the first dielectric layer and within the first trench. The remaining second dielectric layer covers the sidewalls of the first trench and is narrower at the top and wider at the bottom. A third dielectric layer is formed along the first dielectric layer, the second dielectric layer and the substrate surface. The stack of the third dielectric layer and the second dielectric layer covering the sidewall of the first trench and the covered pad oxide layer constitute the sidewall. The stack of the third dielectric layer and the pad oxide layer located between the opposite sidewalls in the first trench constitutes the gate dielectric layer.
7. The manufacturing method according to any one of claims 1 to 6, characterized in that, The protective layer filling the second trench includes: A fourth dielectric layer is formed along the upper surface of the second conformal material layer and the inner wall of the second trench; and A planarization process is performed to make the upper surface of the remaining fourth dielectric layer flush with the upper surface of the first conformal material layer, and the remaining fourth dielectric layer covers the upper surface of the polysilicon gate and forms the protective layer.
8. The manufacturing method as described in claim 7, characterized in that, The fourth dielectric layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride; the fourth dielectric layer is formed using an ALD process or a SCVD process.
9. The manufacturing method according to any one of claims 1 to 6, characterized in that, The protective layer filling the second trench includes: A metal layer is formed along the upper surface of the second conformal material layer and the inner wall of the second trench; and Thermal annealing is performed to cause the metal layer and the polysilicon gate to undergo a silicide reaction to form a metal silicide layer, which serves as the protective layer.
10. A PMOS transistor, characterized in that, The PMOS transistor, formed using the manufacturing method according to any one of claims 1 to 9, comprises: Substrate; A gate dielectric layer, a polysilicon gate, and sidewalls are formed on the substrate, the sidewalls covering the sides of the gate dielectric layer and the polysilicon gate, wherein the polysilicon gate has a top-wide and bottom-narrow structure; and Source / drain epitaxial layers formed in Σ-shaped grooves on both sides of the polysilicon gate.
11. The PMOS transistor as claimed in claim 10, characterized in that, It also includes a protective layer located above the sidewall and covering the upper surface of the polysilicon gate.