Bias current receiver with selective coupling circuit

Abstract

An integrated circuit (IC) includes a current mirror including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, where the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, where the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 831,306, filed on June 2, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to bias current receivers, and particularly to bias current receivers having selective coupling circuits. Background Art

[0004] Integrated circuits (ICs) typically include multiple functional cores that perform various operations. In some cases, the functional cores may each include a bias current receiver that receives a reference current and generates a set of one or more bias currents from the reference current for implementing various operations of the functional core. The reference current may be generated by a process voltage temperature (PVT) stable (e.g., bandgap) current generator. During the manufacture of the IC, a metal trace may be formed to couple the reference current generator to a current mirror that is part of the bias current receiver. If the metal trace is directly coupled to the gate of a current mirror field effect transistor (FET), the FET may be damaged due to the gate antenna effect. That is, the charge accumulated on the metal trace during IC processing may be discharged through the gate oxide / insulator of the FET, which may cause the FET to fail. Summary of the invention

[0005] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is subsequently presented.

[0006] One aspect of the present disclosure relates to an integrated circuit (IC). The IC includes a current mirror, the current mirror including: a first field effect transistor (FET), the first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET, the second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET and the second source is coupled to the first voltage rail; and a selective coupling circuit, the selective coupling circuit being configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET.

[0007] Another aspect of the present disclosure relates to a method that includes selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of a second FET to implement a current mirror operation of the first FET and the second FET in response to a voltage at the first drain of the first FET.

[0008] Another aspect of the present disclosure relates to an apparatus. The apparatus includes: a first field effect transistor (FET); a second FET; and means for selectively coupling a first drain of the first FET to a first gate of the first FET and a second gate of the second FET to implement a current mirror operation of the first FET and the second FET in response to a voltage at the first drain of the first FET.

[0009] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: a reference current generator; a bias current receiver coupled to the reference current generator, wherein the bias current receiver includes a current mirror, the current mirror including: a first field effect transistor (FET), the first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET, the second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET; and one or more signal processing cores coupled to the bias current receiver.

[0010] To achieve the foregoing and related purposes, one or more specific implementations include the features fully described below and specifically pointed out in the claims. The following description and the accompanying illustrations set forth in detail certain illustrative aspects of the one or more specific implementations. However, these aspects are merely indicative of several of the various ways in which the principles of each specific implementation can be employed, and the specification specific implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of an example integrated circuit (IC) including an example bias current receiver according to an aspect of the present disclosure is illustrated.

[0012] Figure 2 A schematic diagram of another example integrated circuit (IC) including another example bias current receiver according to another aspect of the disclosure is illustrated.

[0013] Figure 3 A schematic diagram of another example integrated circuit (IC) including another example bias current receiver according to another aspect of the disclosure is illustrated.

[0014] Figure 4 A schematic diagram of another example integrated circuit (IC) including another example bias current receiver according to another aspect of the disclosure is illustrated.

[0015] Figure 5 A schematic diagram of another example integrated circuit (IC) including another example bias current receiver according to another aspect of the disclosure is illustrated.

[0016] Figure 6 A schematic diagram illustrating another example bias current receiver according to another aspect of the present disclosure is illustrated.

[0017] Figure 7 A schematic diagram of another example integrated circuit (IC) including another example bias current receiver according to another aspect of the disclosure is illustrated.

[0018] Figure 8 A schematic diagram illustrating another example bias current receiver according to another aspect of the present disclosure is illustrated.

[0019] Fig. 9 Another aspect of the present disclosure is illustrated. Figure 8 Schematic diagram of an example voltage rail collapse control circuit for a bias current receiver and an example send gate.

[0020] Fig.10 Another aspect of the present disclosure is illustrated. Figure 8 Schematic diagram of an example voltage rail collapse control circuit for a bias current receiver and an example inverter.

[0021] Fig.11 Another aspect of the present disclosure is illustrated. Figure 8 Schematic diagram of an example voltage level shifter for an example voltage rail collapse control circuit of a bias current receiver.

[0022] Fig.12 A schematic diagram illustrating another example selective coupling circuit according to another aspect of the present disclosure is illustrated.

[0023] FIG. 13A to FIG. 13B A side view of an example integrated circuit (IC) that eliminates gate antenna effects associated with coupling of metal traces to the body of a field effect transistor (FET) according to another aspect of the disclosure is illustrated.

[0024] Fig.14 A flow chart illustrating an example method of generating a bias current according to another aspect of the present disclosure.

[0025] Fig.15 A block diagram of an example wireless communication device according to another aspect of the disclosure is illustrated. DETAILED DESCRIPTION

[0026] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0027] An integrated circuit (IC) typically includes multiple functional cores or circuits that perform various operations. As some examples, the IC may include a display serial interface (DSI), a serial data bus interface, a double data rate (DDR) memory interface, a physical controller messaging interface, and / or others. In some cases, these functional cores may incorporate a bias current receiver that receives a reference current and generates a set of one or more bias currents from the reference current for implementing various operations of the functional core or circuit. The reference current may be generated by a process voltage temperature (PVT) stable (e.g., bandgap) current generator.

[0028] Figure 1 A schematic diagram of an example integrated circuit (IC) 100 is illustrated in accordance with an aspect of the present disclosure.

[0029] IC 100 includes a reference current generator 110 and a bias current receiver 120. Reference Current Generator

[0030] 110 is configured to generate a reference current I REF The bias current receiver 120 is configured to generate a bias current related to or based on a reference current I REF A set of one or more bias currents I B1 to I BN The bias current receiver 120 may be a device that uses one or more bias currents I B1 to I BN to perform its operations or be co-located with one or more functional cores or circuits.

[0031] Specifically, the reference current generator 110 includes a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) M11 coupled in series with a current source 112 (e.g., a PVT stable or bandgap current source) between a first upper voltage rail VDD1 and a lower voltage rail VSS (e.g., ground). That is, the PMOS FET M11 includes a source coupled to the first upper voltage rail VDD1 and a gate and a drain coupled together. The current source 112 is coupled between the gate and the drain of the PMOS FET M11 and the lower voltage rail VSS. The current source 112 is configured to generate a PVT stable or bandgap current I BG .

[0032] The reference current generator 110 further includes a second PMOS FET M12 including a source coupled to the first upper voltage rail VDD1, a gate coupled to the gate and drain of the first PMOS FET M11 to form a current mirror, and a drain serving as a current output terminal of the reference current generator 110. Therefore, the reference current generator 110 is configured to generate a reference current I through the PMOS FET M12. REF , where the reference current I REF Related to or based on the current I generated by the current source 112 BG (For example, based on the current gain of the current mirror (I REF / I BG )). Current gain I REF / I BG The reference current I may be based on the ratio of the channel width-to-length ratio (W / L2) of the second PMOS FET M12 to the channel width-to-length ratio (W / L1) of the first PMOS FET M11. REF The bias current is provided to the bias current receiver 120 via a metal trace shown as resistor R.

[0033] The bias current receiver 120 in turn includes a first n-channel metal oxide semiconductor field effect transistor (NMOS FET) M13 coupled between a current input terminal (Vin) of the bias current receiver 120 and a lower voltage rail VSS. As used herein, the term (Vin) in brackets refers to the current input terminal, while the term Vin without brackets refers to the voltage at the current input terminal. As depicted, a metal trace R is coupled between the output terminal of the reference current generator 110 and the current input terminal (Vin) of the bias current receiver 120. The first NMOS FET M13 includes a drain coupled to or used as the current input terminal (Vin) of the bias current receiver 120, a gate coupled to its drain, and a source coupled to the lower voltage rail VSS.

[0034] The bias current generator 120 also includes a PMOS FET M15 coupled in series with the second NMOS FET M14 between the second upper voltage rail VDD2 and the lower voltage rail VSS. That is, the PMOS FET M15 includes a source coupled to the second upper voltage rail VDD2 and a gate and a drain coupled together. The second NMOS FET M14 includes a drain coupled to the gate and drain of the PMOS FET M15, a gate coupled to the gate and drain of the first NMOS FET M13, and a source coupled to the lower voltage rail VSS. In such a configuration, the first NMOS FET M13 and the second NMOS FET M14 form a current mirror to generate a mirror current I flowing through the PMOS FET M15 and the second NMOS FET M14. MMR , the mirror current is related to or based on the reference current I REF Reference current (e.g., based on the current gain of a current mirror (I MRR / I REF )). That is, the received reference current I REF A voltage V is generated at the gates of the NMOS FETs M13 and M14. MRR , which generates a mirror current I flowing through NMOS FET M14 MMR Current gain I MRR / I REF It may be based on a ratio of a channel width-to-length ratio (W / L4 ) of the second NMOS FET M14 to a channel width-to-length ratio (W / L3 ) of the first NMOS FET M13 .

[0035] The bias current receiver 120 may further include a group of one or more PMOS FETs MB1 to MBN, which are configured to generate a bias current related to or based on the mirror current I MMR A set of one or more bias currents I B1 to I BN(where N may be a positive integer of one (1) or greater). That is, the group of one or more PMOS FETs MB1 to MBN includes a source coupled to the second upper voltage rail VDD2, a gate coupled to the gate / drain of the PMOS FET M15, and a gate coupled to the gate / drain of the PMOS FET M15. B1 to I BN to implement the drain of one or more functional cores or circuits for its operation.

[0036] In such a configuration, the PMOS FET M15 and the PMOS FETs MB1 to MBN form a current mirror to generate the group of one or more bias currents I flowing through the group of one or more PMOS FETs MB1 to MBN, respectively. B1 to I BN , these bias currents are related to or based on the mirror current I MRR Related to or based on the mirror current I (e.g., based on a set of one or more current gains (I B1 / I MRR to I BN / I MRR )). The group of one or more current gains I B1 / I MRR to I BN / I MRR The channel width-to-length ratio W / L of the group of one or more second PMOS FETs MB1 to MBN may be respectively determined based on the channel width-to-length ratio W / L of the group of one or more second PMOS FETs MB1 to MBN. B1 To W / L BN A set of one or more ratios of the channel width-to-length ratio (W / L5) of the PMOS FET M15. The set of one or more current gains can be used to effectively multiply and / or spread the reference current I REF To generate one or more bias currents I B1 to I BN .

[0037] In IC 100, the metal trace R coupling the reference current generator 110 to the bias current receiver 120 is directly coupled to the gates of the NMOS FETs M13 and M14. Therefore, the NMOS FETs M13 and M14 may be susceptible to the gate antenna effect. That is, during the manufacture of the IC 100, and specifically during the plasma etching for forming the metal trace R, a large amount of charge may accumulate on the metal trace R, especially if the metal trace R is long (e.g., 10 to 15 millimeters (mm)). Since the gate oxide or insulator of the NMOS FETs M13 and M14 may be thin, the charge on the metal trace R may be discharged to the lower voltage rail VSS via the gate oxide or insulator of the NMOSFETs M13 and M14. This discharge may cause damage or failure of the NMOS FETs M13 and M14, thereby causing the manufacture of the IC 100 to have a reduced yield.

[0038] Figure 2 A schematic diagram of another example integrated circuit (IC) 200 including another example bias current receiver 220 according to another aspect of the present disclosure is illustrated. IC 200 is similar to IC 100 and includes a reference current generator 210 coupled to bias current receiver 220 via metal traces R.

[0039] Similarly, the reference current generator 210 includes a first PMOS FET M21 and a second PMOS FET M22 and a PVT stabilization or bandgap current source 212, which have the same configuration as the first PMOS FET M11 and the second PMOS FET M12 and the PVT stabilization or bandgap current source 112 of the reference current generator 110. In addition, in a similar manner, the bias current receiver 220 includes a first NMOS FET M23 and a second NMOS FET M24 and a PMOS FET M25, which have the same configuration as the first NMOS FET M13 and the second NMOS FET M14 and the PMOS FET M15 of the bias current receiver 120. Although not explicitly shown, the bias current receiver 220 may include a group of one or more PMOS FETs MB1 to MBN coupled to the PMOS FET M25 in a current mirror configuration for generating a group of bias currents I respectively. B1 to I BN .

[0040] To address the potential gate antenna effect, the bias current receiver 220 also includes a reverse bias diode D1, which includes a cathode coupled to the gates of the NMOS FETs M23 and M24 and an anode coupled to the lower voltage rail VSS. The reverse bias diode D1 provides a path for the charge that has accumulated on the metal trace R to discharge to the lower voltage rail VSS. In this way, the charge is not discharged through the thin gate oxide / insulator of the NMOS FETs M23 and M24, thereby eliminating or reducing the possibility of damaging the NMOS FETs M23 and M24. During normal operation of the IC 100, the reverse bias diode D1 is not turned on and does not affect the operation of the IC 100. The disadvantage of such an approach is that the reverse bias diode D1 occupies a considerable IC area, which is generally disadvantageous.

[0041] Figure 3 A schematic diagram of another example integrated circuit (IC) 300 including another example bias current receiver 320 according to another aspect of the present disclosure is illustrated. IC 300 is similar to IC 100 and includes a reference current generator 310 coupled to bias current receiver 320 via metal traces R.

[0042] Similarly, the reference current generator 310 includes a first PMOS FET M31 and a second PMOS FET M32 and a PVT stabilization or bandgap current source 312, having the same configuration as the first PMOS FET M11 and the second PMOS FET M12 and the PVT stabilization or bandgap current source 112 of the reference current generator 110. Likewise, similarly, the bias current receiver 320 includes a first NMOS FET M33 and a second NMOS FET M34 and a PMOS FET M35, having a similar configuration as the first NMOS FET M13 and the second NMOS FET M14 and the PMOS FET M15 of the bias current receiver 120, except that the drain of the NMOS FET M33 is not directly coupled to its gate, as further discussed herein. Although not explicitly shown, the bias current receiver 320 may include a set of one or more PMOS FETs MB1 to MBN coupled to the PMOS FET M35 in a current mirror configuration for generating a set of one or more bias currents I B1 to I BN .

[0043] To address potential gate antenna effects, the bias current receiver 320 also includes a selective coupling circuit 322 that includes an input coupled to a metal trace R (current input (Vin) of the bias current receiver 320) and an output coupled to the gates of the NMOS FETs M33 and M34. In such a configuration, the gates of the NMOS FETs M33 and M34 are not directly coupled to the metal trace R, thus protecting the NMOS FETs M33 and M34 from the gate antenna effect from the metal trace R. Furthermore, in this example, there is no other gate antenna effect with respect to the metal trace R because it does not terminate at the gate of any device.

[0044] In this example, the selective coupling circuit 322 includes an NMOS FET M36 coupled between the current input terminal (Vin) of the bias current receiver 320 (for example, one end of the metal trace R is coupled thereto) and the gates of the NMOS FETs M33 and M34. That is, the NMOS FET M36 includes a drain coupled to the current input terminal (Vin) of the bias current receiver 320, a source coupled to the gates of the NMOS FETs M33 and M34, and a gate configured to receive a non-complementary enable signal (en). The selective coupling circuit 322 also includes an NMOS FET M37 coupled between the gates of the NMOS FETs M33 and M34 and the lower voltage rail VSS. That is, the NMOS FET M37 includes a drain coupled to the gates of the NMOS FETs M33 and M34, a source coupled to the lower voltage rail VSS, and a gate configured to receive a complementary enable signal (enb). The enable signals en and enb may be associated with enabling / disabling the bias current receiver 320 including a functional core or circuit to which the bias current receiver 320 is coupled and / or associated.

[0045] In operation, when the enable signal is asserted (e.g., en=high (H) (e.g., at substantially VDD2 potential) and enb=low (L) (e.g., at substantially VSS potential)), the NMOS FET M36 is turned on and the NMOS FET M37 is turned off. Therefore, the turned-on NMOS FET M36 electrically couples the drain of the NMOS FET M33 to the gates of the NMOS FETs M33 and M34, thereby enabling the current mirror operation of the NMOS FETs M33 and M34 to achieve the reference current I REF The mirror image of the current I MMR The turned-off NMOS FET M37 electrically isolates the gates of the NMOS FETs M33 and M34 from the lower voltage rail VSS.

[0046] When the enable signal is not asserted (de-asserted) (e.g., en=L, enb=H), NMOS FET M36 is turned off and NMOS FET M37 is turned on. Therefore, the turned-off NMOS FET M36 electrically isolates the drain of NMOS FET M33 from the gates of NMOS FETs M33 and M34, and the turned-on NMOS FET M37 electrically couples the gates of NMOS FETs M33 and M34 to the lower voltage rail VSS. This disables the current mirror operation of NMOS FETs M33 and M34.

[0047] The disadvantage of the bias current receiver 320 is that when it is enabled (en=H, enb=L), the turned-on NMOS FET M36 may not be able to fully transfer the voltage Vin at the current input terminal of the bias current receiver 320 to generate the voltage V at the gates of the NMOS FETs M33 and M34. MRR In order to accurately implement the current mirror operation. Generally speaking, the voltage drop across the NMOS FET M36 is substantially the threshold voltage V T Therefore, the voltage V at the gate of NMOS FETs M33 and M34 is MRR Instead of being at Vin to perform accurate current mirroring, it is at Vin-V T , which results in a reference current I REF The inaccurate mirror image of the current I MRR If the mirrored current I is multiplied by using a current mirror coupled to the PMOS FET M35 MRR To generate one or more bias currents I B1 to I BN , the error in the current mirror increases by a multiplication factor.

[0048] Figure 4 A schematic diagram of another example integrated circuit (IC) 400 including another example bias current receiver 420 according to another aspect of the present disclosure is illustrated. IC 400 is similar to IC 100 and includes a reference current generator 410 coupled to bias current receiver 420 via metal traces R.

[0049] Similarly, the reference current generator 410 includes a first PMOS FET M41 and a second PMOS FET M42 and a PVT stabilization or bandgap current source 412, having the same configuration as the first PMOS FET M11 and the second PMOS FET M12 and the PVT stabilization or bandgap current source 112 of the reference current generator 110. Likewise, similarly, the bias current receiver 420 includes a first NMOS FET M43 and a second NMOS FET M44 and a PMOS FET M45, having a similar configuration as the first NMOS FET M13 and the second NMOS FET M14 and the PMOS FET M15 of the bias current receiver 120, except that the drain of the NMOS FET M43 is not directly coupled to its gate, as further discussed herein. Although not explicitly shown, the bias current receiver 420 may include a set of one or more PMOS FETs MB1 to MBN coupled to the PMOS FET M45 in a current mirror configuration for generating a set of one or more bias currents I B1 to I BN .

[0050] To address potential gate antenna effects, the bias current receiver 420 also includes a selective coupling circuit 422 that includes an input coupled to a metal trace R (current input (Vin) of the bias current receiver 420) and an output coupled to the gates of the NMOS FETs M43 and M44. In such a configuration, the gates of the NMOS FETs M43 and M44 are not directly coupled to the metal trace R, thus protecting the NMOS FETs M43 and M44 from the gate antenna effect from the metal trace R. Furthermore, in this example, there is no other gate antenna effect with respect to the metal trace R because it does not terminate at the gate of any device.

[0051] In this example, the selective coupling circuit 422 includes a transmission gate 424 (including an NMOS FET M46 and a PMOS FET M47 coupled in parallel) coupled between a current input terminal (Vin) of the bias current receiver 420 (e.g., one end of the metal trace R is coupled thereto) and the gates of the NMOS FETs M43 and M44. That is, the NMOS FET M46 of the transmission gate 424 includes a drain coupled to the current input terminal (Vin) of the bias current receiver 420, a source coupled to the gates of the NMOS FETs M43 and M44, and a gate configured to receive a non-complementary enable signal (en). The PMOS FET M47 of the transmission gate 424 includes a source coupled to the current input terminal (Vin) of the bias current receiver 420, a drain coupled to the gates of the NMOS FETs M43 and M44, and a gate configured to receive a complementary enable signal (enb).

[0052] The selective coupling circuit 422 also includes an NMOS FET M48 coupled between the gates of the NMOS FETs M43 and M44 and the lower voltage rail VSS. That is, the NMOS FET M48 includes a drain coupled to the gates of the NMOS FETs M43 and M44, a source coupled to the lower voltage rail VSS, and a gate configured to receive a complementary enable signal (enb). The enable signals en and enb may be associated with enabling / disabling the bias current receiver 420, which includes a functional core or circuit to which the bias current receiver 420 is coupled and / or associated.

[0053] In operation, when the enable signal is asserted (e.g., en=H, enb=L), the transmission gate 424 is turned on and the NMOSFET M48 is turned off. Therefore, the turned-on transmission gate 424 electrically couples the drain of the NMOS FET M43 to the gates of the NMOS FETs M43 and M44; thereby enabling the current mirror operation of the NMOS FETs M43 and M44 to achieve the reference current I REF The mirror image of the current I MMR The turned-off NMOS FET M48 electrically isolates the gates of the NMOS FETs M43 and M44 from the lower voltage rail VSS.

[0054] When the enable signals en and enb are deasserted (e.g., en=L, enb=H), the transmission gate 424 is turned off and the NMOSFET M48 is turned on. Therefore, the turned-off transmission gate 424 electrically isolates the drain of the NMOS FET M43 from the gates of the NMOS FETs M43 and M44, and the turned-on NMOS FET M48 electrically couples the gates of the NMOS FETs M43 and M44 to the lower voltage rail VSS. This disables the current mirror operation of the NMOS FETs M43 and M44.

[0055] The disadvantage of the bias current receiver 420 is that the PMOS FET M47 of the transmission gate 424 may not be completely turned off due to the difference in the operating voltage domains (VDD1 and VDD2) of the reference current generator 410 and the bias current receiver 420, so when the bias current receiver 420 is disabled (e.g., en=L, enb=H), a leakage current may be generated. For example, the supply voltage at the upper voltage rail VDD1 of the reference current generator 410 may be at 1.2 volts (V), while the supply voltage at the upper voltage rail VDD2 of the bias current receiver 420 may be at 0.8V. Therefore, the high voltage of the complementary enable signal enb applied to the gate of the PMOS FET M47 is at 0.8V. If the transmission gate 424 is turned off, the reference current I REF is smaller, so the voltage Vin at the current input terminal of the bias current receiver 420 is about 1.2 V. With the voltage Vin applied to the source of the PMOS FET M47, the PMOS FET M47 may experience a source-to-gate voltage (Vsg) of about 0.4 V. This Vsg may not be small enough to completely turn off the PMOS FET M47, thus generating a leakage current flowing through the transmission gate 424.

[0056] Figure 5A schematic diagram of another example integrated circuit (IC) 500 including an example bias current receiver 520 according to another aspect of the present disclosure is illustrated. In this implementation, the bias current receiver 520 includes a selective coupling circuit 522 that includes a control input coupled to a current input of the bias current receiver 520 to selectively couple the current input to a gate of a current mirror NMOS FET in response to a voltage at the current input and an enable signal. More specifically, when the bias current receiver 520 is disabled, the control input receives a voltage Vin at the current input of the bias current receiver 520, and the selective coupling circuit decouples the current input of the bias current receiver 520 from the gate of the current mirror NMOS FET using the voltage Vin. As further discussed herein with reference to example implementations, the selective coupling circuit may include a PMOS FET having a source coupled to the current input of the bias current receiver 520 and a gate selectively driven by Vin. In this way, such a PMOS FET can be completely turned off because, in this case, Vsg is substantially zero (0) V, thereby preventing leakage current from flowing through the PMOS FET.

[0057] Specifically, IC 500 includes a reference current generator 510 coupled to a bias current receiver 520 via a metal trace R. Reference current generator 510 includes first and second PMOS FETs M51, M52 and a PVT stabilization or bandgap current source 512, having the same configuration as first and second PMOS FETs M11, M12 and PVT stabilization or bandgap current source 112 of reference current generator 110. Bias current receiver 520 includes first and second NMOS FETs M53, M54 and a PMOS FET M55, having a similar configuration as first and second NMOS FETs M13, M14 and PMOS FET M15 of bias current receiver 120, except that the drain of NMOS FET M53 is not directly coupled to its gate, as further discussed herein. Although not explicitly shown, the bias current receiver 520 may include a set of one or more PMOS FETs MB1 to MBN coupled to the PMOS FET M55 in a current mirror configuration for generating a set of one or more bias currents I B1 to I BN .

[0058] To address potential gate antenna effects, the bias current receiver 520 also includes a selective coupling circuit 522 that includes an input coupled to a metal trace R (current input (Vin) of the bias current receiver 520) and an output coupled to the gates of the NMOS FETs M53 and M54. In such a configuration, the gates of the NMOS FETs M53 and M54 are not directly coupled to the metal trace R, thus protecting the NMOS FETs M53 and M54 from the gate antenna effect from the metal trace R. Furthermore, in this example, there is no other gate antenna effect with respect to the metal trace R because it does not terminate at the gate of any device.

[0059] In this specific implementation, the selective coupling circuit 522 includes a first control input coupled to the current input terminal (Vin) of the bias current receiver 520 to receive the input voltage Vin therefrom. The selective coupling circuit 522 also includes a second control input configured to receive at least one of a non-complementary enable signal (en) and / or a complementary enable signal (enb). For example, via the second control input, the selective coupling circuit 522 may receive the non-complementary enable signal en and generate the complementary enable signal enb internally using an inverter; or receive the complementary enable signal enb and generate the non-complementary enable signal en internally using an inverter; or receive both the non-complementary signal en and the complementary enable signal enb. In addition, as depicted, the selective coupling circuit 522 may include a third control input coupled to the lower voltage rail VSS.

[0060] As further discussed herein with respect to an example implementation of the selective coupling circuit 522, the selective coupling circuit 522 decouples the current input terminal (Vin) of the bias current receiver 520 from the gates of the NMOS FETs M53 and M54 based on the input voltage Vin and the deasserted enable signal en / enb (e.g., en=L, enb=H). The decoupling of the current input terminal (Vin) of the bias current receiver 520 from the gates of the NMOS FETs M53 and M54 is in a manner that substantially eliminates leakage current. In addition, the selective coupling circuit 522 couples the current input terminal (Vin) of the bias current receiver 520 to the gates of the NMOS FETs M53 and M54 based on the voltage potential (e.g., 0V) at the lower voltage rail VSS and the asserted enable signal en / enb (e.g., en=H, enb=L).

[0061] Figure 6Schematic diagram of another example bias current receiver 600 according to another aspect of the present disclosure is illustrated. The bias current receiver 600 may be an example implementation of the bias current receiver 520 of the IC 500. Similarly, the bias current receiver 600 includes a first NMOS FET M61 and a second NMOS FET M62 and a PMOS FET M63, having a similar configuration as the first NMOS FET M13 and the second NMOS FET M14 and the PMOS FET M15 of the bias current receiver 120, except that the drain of the NMOS FET M61 is not directly coupled to its gate, as further discussed herein. Although not explicitly shown, the bias current receiver 600 may include a set of one or more PMOS FETs MB1 to MBN coupled to the PMOS FET M63 in a current mirror configuration for generating a set of one or more bias currents I B1 to I BN .

[0062] The bias current receiver 600 also includes a selective coupling circuit 622, which includes an input terminal coupled to or also used as a current input terminal (Vin) of the bias current receiver 600 and an output terminal coupled to the gates of the NMOS FETs M61 and M62. The selective coupling circuit 622 includes a first PMOS FET M67, a second PMOS FET M65, an NMOS FET M64, and an NMOS FET M66. In addition, the selective coupling circuit 622 includes an inverter 626, which includes a PMOS FET M68, an NMOS FET M69, and an NMOS FET M70 coupled in series between the current input terminal (Vin) of the bias current receiver 600 and the lower voltage rail VSS.

[0063] More specifically, PMOS FET M67 includes a source coupled to the current input terminal (Vin) of bias current receiver 600, a drain coupled to the source of PMOS FET M65, and a gate coupled to the output terminal of inverter 626. NMOS FET M64 includes a drain coupled to the current input terminal (Vin), a source coupled to the drain of PMOS FET M65, and a gate configured to receive a non-complementary enable signal (en). PMOS FET M65 includes a gate configured to receive a complementary enable signal (enb). NMOS FET M66 includes a drain coupled to the source / drain of NMOS FET M64 / PMOS FET M65 (and the gates of NMOS FET M61 and M62), a source coupled to the lower voltage rail VSS, and a gate configured to receive a complementary enable signal enb.

[0064] The PMOS FET M68 of the inverter 626 includes a source coupled to the current input (Vin) of the bias current receiver 600. The NMOS FET M69 of the inverter 626 includes a drain coupled to the drain of the PMOS FET M68. The gates of the PMOS FET M68 and the NMOS FET M69 are coupled together and coupled to the source / drain of the NMOS FET M64 / PMOS FET M65 (as well as the drain of the NMOS FET M66 and the gates of the NMOS FETs M61 and M62). The gates of the PMOS FET M68 and the NMOS FET M69 serve as the input of the inverter 626, and the drains of the PMOS FET M68 and the NMOS FET M69 serve as the output of the inverter 626, which is coupled to the gate of the PMOS FET M67 as discussed. NMOS FET M70 of inverter 626 includes a drain coupled to the source of NMOS FET M69 , a source coupled to the lower voltage rail VSS, and a gate configured to receive a non-complementary enable signal en.

[0065] In operation, when the bias current receiver 600 is enabled by the asserted enable signal (en=H, enb=L), the NMOS FET M64 and the PMOS FET M65 are turned on, the NMOS FET M66 is turned off, and the NMOS FET M70 of the inverter 626 is turned on. Thus, there will be a certain reference current I flowing into the selective coupling circuit 622. REF , which may result in a voltage Vin at the current input terminal (Vin) of the bias current receiver 600 being approximately 0.8 V (eg, approximately VDD1-I REF *R). Initially, there is a certain voltage drop across NMOS FET M64, which causes the voltage V at the input of inverter 626 (and the gates of current mirror NMOS FETs M61 and M62) to be MRR is about 0.6V (e.g., Vin-V T , where V T is the threshold voltage of NMOS FET M64). In response to this voltage V MRR , PMOS FET M68 is turned off and NMOS FET M69 is turned on. Therefore, the output of inverter 626 is at a voltage substantially at VSS potential (e.g., 0V), which is provided to the gate of PMOS FET M67. This fully turns on PMOS FET M67, resulting in a voltage V at the gates of current mirror NMOS FETs M61 and M62. MRR Raised to substantially Vin for accurate current mirror operation.

[0066] When the bias current receiver 600 is disabled by the enable signal (en=L, enb=H) being deasserted, the NMOSFET M64 and the PMOS FET M65 are turned off, the NMOS FET M66 is turned on, and the NMOS FET M70 of the inverter 626 is turned off. REF The voltage Vin at the current input terminal (Vin) of the bias current receiver 600 is about 1.2V (e.g., about VDD1) due to the NMOS FET M64 / PMOS FET M65 being turned off and is smaller. The voltage V at the input terminal of the inverter 626 (and the gates of the current mirror NMOS FETs M61 and M62) is about 1.2V (e.g., about VDD1). MRR Since the NMOS FET M66 is turned on, it is at substantially VSS potential (eg, 0V). In response to the voltage V MRR , PMOS FET M68 is turned on and NMOS FET M69 is turned off. Therefore, the output of inverter 626 is at a voltage substantially at Vin potential (e.g., 1.2V), which is provided to the gate of PMOS FET M67. This completely turns off PMOS FET M67 because its Vsg is at substantially 0V, thereby preventing any leakage current from flowing therethrough.

[0067] Another problem occurs when the supply voltage VDD2 collapses to the VSS potential or 0 V. In this regard, the enable signals en and enb also collapse to the VSS potential or 0 V. Therefore, referring again to Figure 6 , PMOS FET M65 will be turned on, and if the output terminal of inverter 626 is at VSS potential or 0V, PMOS FET M67 will also be turned on. Since the supply voltage VDD1 exists in the reference current generator, the reference current I REF Flows into the selective coupling circuit 622. As a result, a large amount of current will be latched into the gates of the current mirror NMOS FETs M61 and M62. As further discussed herein, circuits are provided in the following example implementations of the selective coupling circuit to prevent or reduce the latching of current into the current mirror NMOS FETs in response to the collapse of VDD2.

[0068] Figure 7 A schematic diagram of another example integrated circuit (IC) 700 including an example reference current generator 710 and an example bias current receiver 720 according to another aspect of the present disclosure is illustrated. In this implementation, the bias current receiver 720 includes circuitry that responds to a collapse of a supply voltage VDD2 of the bias current receiver 720 when a supply voltage VDD1 of the reference current generator 710 is present.

[0069] More specifically, the IC 700 includes a reference current generator 710 coupled to a bias current receiver 720 via a metal trace R. The reference current generator 710 includes a first PMOS FET M71 and a second PMOS FET M72 and a PVT stabilization or bandgap current source 712, having the same configuration as the first PMOS FET M11 and the second PMOS FET M12 and the PVT stabilization or bandgap current source 112 of the reference current generator 110. The bias current receiver 720 includes a first NMOS FET M73 and a second NMOS FET M74 and a PMOS FET M75, having a similar configuration as the first NMOS FET M13 and the second NMOS FET M14 and the PMOS FET M15 of the bias current receiver 120, except that the drain of the NMOS FET M73 is not directly coupled to its gate, as further discussed herein. Although not explicitly shown, the bias current receiver 720 may include a set of one or more PMOS FETs MB1 to MBN coupled to the PMOS FET M75 in a current mirror configuration for generating a set of one or more bias currents I B1 to I BN .

[0070] To address potential gate antenna effects, the bias current receiver 720 also includes a selective coupling circuit 722 that includes an input coupled to a metal trace R (current input (Vin) of the bias current receiver 720) and an output coupled to the gates of the NMOS FETs M73 and M74. In such a configuration, the gates of the NMOS FETs M73 and M74 are not directly coupled to the metal trace R, thus protecting the NMOS FETs M73 and M74 from the gate antenna effect from the metal trace R. Furthermore, in this example, there is no other gate antenna effect with respect to the metal trace R because it does not terminate at the gate of any device.

[0071] In this specific implementation, the selective coupling circuit 722 includes a first control input coupled to the current input terminal (Vin) of the bias current receiver 720 to receive an input voltage Vin therefrom. The selective coupling circuit 722 also includes a second control input configured to receive at least one of a non-complementary enable signal (en) and / or a complementary enable signal (enb). Similarly, via the second control input, the selective coupling circuit 722 may receive the non-complementary enable signal en and generate a complementary enable signal enb internally using an inverter; or receive the complementary enable signal enb and generate a non-complementary enable signal en internally using an inverter; or receive both the non-complementary signal en and the complementary enable signal enb. The selective coupling circuit 722 also includes a third control input configured to receive a supply voltage VDD2. In addition, as depicted, the selective coupling circuit 722 may also be coupled to the lower voltage rail VSS.

[0072] As further discussed herein with respect to an example implementation of the selective coupling circuit 722, the selective coupling circuit 722 decouples the current input terminal (Vin) of the bias current receiver 720 from the gates of the NMOS FETs M73 and M74 based on the input voltage Vin and in response to the supply voltage VDD2 including the collapsed enable signals en / enb (e.g., all at the VSS potential or 0V). The decoupling of the current input terminal (Vin) of the bias current receiver 720 from the gates of the NMOS FETs M73 and M74 is in a manner that substantially eliminates leakage or latching current. In addition, when VDD2 has not collapsed, the selective coupling circuit 722 couples the current input terminal (Vin) of the bias current receiver 720 to the gates of the NMOS FETs M73 and M74 based on the voltage potential at the lower voltage rail VSS (e.g., 0V) and the asserted enable signals en / enb (e.g., en=H, enb=L).

[0073] Figure 8Schematic diagram of another example bias current receiver 800 according to another aspect of the present disclosure is illustrated. The bias current receiver 800 may be an example implementation of the bias current receiver 720 of the IC 700. Similarly, the bias current receiver 800 includes a first NMOS FET M81 and a second NMOS FET M82 and a PMOS FET M83, having a similar configuration as the first NMOS FET M13 and the second NMOS FET M14 and the PMOS FET M15 of the bias current receiver 120, except that the drain of the NMOS FET M81 is not directly coupled to its gate, as further discussed herein. Although not explicitly shown, the bias current receiver 800 may include a set of one or more PMOS FETs MB1 to MBN coupled to the PMOS FET M83 in a current mirror configuration for generating a set of one or more bias currents I B1 to I BN .

[0074] The bias current receiver 800 also includes a selective coupling circuit 822, which includes an input terminal coupled to or used as a current input terminal (Vin) of the bias current receiver 800 and an output terminal coupled to the gates of the NMOS FETs M81 and M82. The selective coupling circuit 822 includes a first PMOS FET M92, a second PMOS FET M88, a third PMOSFET M85, a first NMOS FET M84, a second NMOS FET M86, and a third NMOS FET M87. In addition, the selective coupling circuit 822 includes an inverter 826, which includes a PMOS FET M89, an NMOS FET M90, and an NMOS FET M91 coupled in series between the current input terminal (Vin) of the bias current receiver 800 and the lower voltage rail VSS. In addition, the selective coupling circuit 822 includes a supply voltage (VDD2) collapse control circuit 830.

[0075] More specifically, the first PMOS FET M92 includes a source coupled to the current input terminal (Vin) of the bias current receiver 800, a drain coupled to the source of the second PMOS FET M88, and a first control output terminal coupled to the VDD2 collapse control circuit 830 to receive the first control voltage V CPThe second PMOS FET M88 includes a drain coupled to the source of the third PMOS FET M85 and a gate coupled to the output terminal of the inverter 826. The third PMOS FET M85 includes a gate configured to receive a complementary enable signal (enb). The first NMOS FET M84 includes a drain coupled to the current input terminal (Vin) of the bias current receiver 800, a source coupled to the drain of the third PMOS FET M85, and a gate configured to receive a non-complementary enable signal (en).

[0076] The second NMOS FET M86 includes a drain coupled to the source / drain of the NMOS FET M84 / PMOS FET M85 (and the gates of the NMOS FETs M81 and M82), a source coupled to the lower voltage rail VSS, and a gate configured to receive the complementary enable signal enb. The third NMOS FET M87 also includes a drain coupled to the source / drain of the NMOS FET M84 / PMOS FET M85 (and the gates of the NMOS FETs M81 and M82), a source coupled to the lower voltage rail VSS, and a second control output terminal of the VDD2 collapse control circuit 830 to receive the second control voltage V CN of the gate.

[0077] The PMOS FET M89 of the inverter 826 includes a source coupled to the current input terminal (Vin) of the bias current receiver 800. The NMOS FET M90 of the inverter 826 includes a drain coupled to the drain of the PMOS FET M89. The gates of the PMOS FET M89 and the NMOS FET M90 are coupled together and coupled to the source / drain of the NMOS FET M84 / PMOS FET M85 (as well as the drains of the second NMOS FET M86 and the third NMOS FET M87 and the gates of the current mirror NMOS FETs M81 and M82). The gates of the PMOS FET M89 and the NMOS FET M90 serve as the input terminals of the inverter 826, and the drains of the PMOS FET M89 and the NMOS FET M90 serve as the output terminals of the inverter 826, which are coupled to the gate of the second PMOS FET M88 as discussed. The NMOS FET M91 of the inverter 826 includes a drain coupled to the source of the NMOS FET M90, a source coupled to the lower voltage rail VSS, and a gate configured to receive a non-complementary enable signal en.

[0078] The VDD2 collapse control circuit 830 includes a first control input coupled to the current input terminal (Vin) of the bias current receiver 800 to receive the voltage Vin therefrom. The VDD2 collapse control circuit 830 includes a second control input coupled to the upper voltage rail VDD2 of the bias current receiver 800 to receive the supply voltage VDD2 therefrom. Additionally, as depicted, the VDD2 collapse control circuit 830 may include a third control input coupled to the lower voltage rail VSS; because the VSS potential is used to generate the control voltage V CP and V CN , so it is called the control input terminal.

[0079] In operation, when the supply voltage VDD2 has not collapsed, the selective coupling circuit 822 operates similarly to the selective coupling circuit 622 discussed previously. That is, when VDD2 has not collapsed, the VDD2 collapse control circuit 830 generates V when it is at the VSS potential (e.g., 0V). CP To maintain the first PMOS FET M92 turned on, and also generate V when it is at VSS potential (eg, 0V). CN To maintain the third NMOS FET M87 off. As mentioned, the VDD2 collapse control circuit 830 uses its third control input to generate a control voltage V at the VSS potential. CP and V CN .

[0080] Therefore, when the bias current receiver 800 is enabled by the asserted enable signal (en=H, enb=L), the first NMOS FET M84 and the third PMOS FET M85 are turned on, the second NMOS FET M86 is turned off, and the NMOSFET M91 of the inverter 826 is turned on. In this way, there will be a certain reference current I flowing into the selective coupling circuit 822. REF , which may result in a voltage Vin at the current input terminal (Vin) of the bias current receiver 800 being approximately 0.8 V (eg, approximately VDD1-I REF *R). Initially, there is a certain voltage drop across the first NMOS FET M84, resulting in a voltage V at the input of the inverter 826 (and the gates of the current mirror NMOS FETs M81 and M82) of MRR is about 0.6V (e.g., Vin-V T In response to the voltage V MRR, PMOS FET M89 is turned off and NMOS FET M90 is turned on. Therefore, the output of inverter 826 is at a voltage substantially at VSS potential (e.g., 0V), which is provided to the gate of the second PMOS FET M88. This fully turns on PMOS FET M88, resulting in a voltage V at the gates of current mirror NMOS FETs M81 and M82. MRR Raised to substantially Vin for accurate current mirror operation.

[0081] When the bias current receiver 800 is disabled by the deasserted enable signal (en=L, enb=H), the first NMOS FET M84 and the third PMOS FET M85 are turned off, the second NMOS FET M86 is turned on, and the NMOSFET M91 of the inverter 826 is turned off. REF The voltage Vin at the current input terminal (Vin) of the bias current receiver 800 is about 1.2V (e.g., about VDD1) due to the NMOS FET M84 / PMOS FET M85 being turned off and is smaller. The voltage V at the input terminal of the inverter 826 (and the gates of the current mirror NMOS FETs M81 and M82) is about 1.2V (e.g., about VDD1). MRR Due to the turned-on second NMOS FET M86, the voltage V is substantially at VSS potential (eg, 0V). MRR , PMOS FET M89 is turned on and NMOS FET M90 is turned off. Therefore, the output of inverter 826 is at a voltage substantially at Vin potential (e.g., 1.2V), which is provided to the gate of the second PMOS FET M88. This completely turns off PMOS FET M88 because its Vsg is at substantially 0V, thereby preventing any leakage or latching current from entering the gates of the current mirror NMOS FETs M81 and M82.

[0082] When the VDD2 collapse control circuit 830 senses that the supply voltage VDD2 has collapsed, the VDD2 collapse control circuit 830 generates a first control voltage V at substantially Vin. CP To turn off the first PMOS FET M92, and at substantially Vin-V T The second control voltage V CN The VDD2 collapse control circuit 830 uses its coupling to the current input terminal (Vin) of the bias current receiver 800 to turn on the third NMOS FET M87, as discussed in further detail herein with reference to an example implementation of the VDD2 collapse control circuit 830. The VDD2 collapse control circuit 830 uses its coupling to the current input terminal (Vin) of the bias current receiver 800 to respectively T The control signal V is generated at CP and VCN The turned-off first PMOS FET M92 and the turned-on third NMOS FET M87 prevent current from leaking or latching into the gates of the current mirror NMOS FETs M81 and M82.

[0083] Fig. 9 A schematic diagram of an example transmission gate 900 according to another aspect of the present disclosure is illustrated. The transmission gate 900 may be an example implementation of a second control input circuit of the VDD2 collapse control circuit 830. As discussed further herein, the transmission gate 900 is coupled between the second upper voltage rail VDD2 and the input terminal (gate) of the inverter discussed further herein. Since there may be a long metal trace between the VDD2 voltage rail and the gate of the inverter, the transmission gate 900 isolates the gate from the metal trace to eliminate or reduce the possibility of the gate antenna effect damaging the FET of the inverter.

[0084] More specifically, the transmission gate 900 includes a parallel-coupled NMOSFET M95 and a PMOS FET M96, each including a drain and a source coupled together, which are used as a second control input terminal of the VDD2 collapse control circuit 830. The NMOS FET M95 and the PMOS FET M96 include a source and a drain coupled together, respectively, which are configured to generate a voltage VDD2' related to (e.g., substantially the same as) the supply voltage VDD2. The NMOS FET M95 includes a gate configured to receive a voltage Vin', which may be substantially equal to the voltage Vin at the current input terminal of the bias current receiver 800 minus the threshold voltage V of the NMOS FET. T , as discussed further herein. PMOS FET M96 includes a gate coupled to a lower voltage rail VSS.

[0085] In operation, when the supply voltage VDD2 has not collapsed (e.g., VDD2=0.8V), the PMOSFET M96 of the transmission gate 900 is used to substantially pass the supply voltage VDD2 to generate the voltage VDD2'. When the supply voltage VDD2 has collapsed (e.g., VDD2=0V), the NMOS FET M95 of the transmission gate 900 is used to substantially pass the supply voltage VDD2 to generate the voltage VDD2'.

[0086] Fig.10 1 illustrates a schematic diagram of an example inverter 1000 according to another aspect of the present disclosure. The inverter 1000 is used to generate a second control voltage VDD2 for the gate of the third NMOS FET M87 of the selective coupling circuit 822 in response to the voltage VDD2′ generated by the transmission gate 900. CN An example of a circuit.

[0087] Specifically, the inverter 1000 includes a PMOS FET M101, a diode-connected NMOS FET M102, a PMOS FET M103, and an NMOS FET 104 that are serially coupled between a current input terminal (Vin) of the bias current receiver 800 and a lower voltage rail VSS. More specifically, the PMOS FET M101 includes a source coupled to the current input terminal (Vin) of the bias current receiver 800, a gate coupled to the lower voltage rail VSS, and a drain coupled to the drain and gate of the diode-connected NMOS FET M102. The diode-connected NMOS FET M102 includes a source coupled to the source of the PMOS FET M103. The NMOS FET M104 includes a gate coupled to the gate of the PMOS FET M103, a drain coupled to the drain of the PMOS FET M103, and a source coupled to the lower voltage rail VSS.

[0088] The gates of the PMOS FET M103 and the NMOS FET M104 are coupled to the output terminal of the transmission gate 900 to receive the voltage VDD2′ therefrom. The sources of the diode-connected NMOS FET M102 and the PMOS FET M103 are coupled to the gate of the NMOS FET M95 of the transmission gate 900 to provide the voltage Vin′ thereto. The second control voltage V CN Generated at the drains of the PMOS FET M103 and the NMOS FET M104.

[0089] In operation, the diode-connected NMOS FET M102 reduces the voltage Vin by the threshold voltage V T This is done to prevent the inverter 1000 from generating a logic low control voltage V CN For example, when the voltage VDD2′ is logic high (eg, when the supply voltage VDD2 has not collapsed), the inverter 1000 generates a logic low control voltage V CNWhen not collapsed, the voltage VDD2' may be about 0.8V. If Vin (e.g., at 1.2V) is directly applied to the source of the PMOS FET M103, the PMOS FET M103 will have a Vsg of about 0.4V, which may not be sufficient to turn off the PMOS FET M103; and a leakage current will be generated that flows through the PMOS FET M103. Therefore, the diode-connected NMOS FET M102 reduces the voltage Vin' at the source of the PMOS FET M103 to reduce the Vsg of the PMOS FET M103, thereby reducing or preventing the leakage current flowing therethrough.

[0090] Therefore, when the supply voltage VDD2 has not collapsed, the voltage VDD2′ is logic high (eg, at 0.8V), which causes the inverter 1000 to generate a control voltage VDD2′ at logic low at the VSS potential. CN The control voltage V is at VSS potential. CN The third NMOS FET M87 of the selective coupling circuit 822 is turned off, thereby allowing the gates of the current mirror NMOS FETs M81 and M82 to respond to the reference current I REF Generate gate voltage V MRR When the supply voltage VDD2 has collapsed, the voltage VDD2' is logic low (eg, at 0V), which causes the inverter 1000 to generate a current mirror at Vin-V T The logic high control voltage V CN . At Vin-V T The control voltage V CN The third NMOS FET M87 of the selective coupling circuit 822 is turned on, thereby grounding the gates of the current mirror NMOS FETs M81 and M82 to disable the current mirror operation.

[0091] Fig.11 1 is a schematic diagram illustrating an exemplary voltage level shifter 1100 according to another aspect of the present disclosure. The voltage level shifter 1100 is configured to respond to a voltage VDD2′ generated by a transmission gate 900 and a second control voltage VDD2′ generated by an inverter 1000. CN To generate a first control voltage V for the gate of the first PMOS FET M92 of the selective coupling circuit 822 CP Circuit 1100 is referred to as a voltage level shifter because the input voltage VDD2′ and V CN Basically, the first control voltage V CP Basically varies according to the VDD1 voltage domain (eg, between 0 and 1.2V).

[0092] Specifically, the voltage level shifter 1100 includes a first PMOS FET M111, a second PMOS FET M112, and a first NMOS FET M113 that are coupled in series between a current input terminal (Vin) of the bias current receiver 800 and a lower voltage rail VSS. That is, the first PMOS FET M111 includes a source coupled to the current input terminal (Vin) of the bias current receiver 800 and a drain coupled to the source of the second PMOS FET M112. The second PMOS FET M112 includes a gate and a drain coupled together and coupled to the drain of the first NMOS FET M113. The first NMOS FET M113 includes a source coupled to the lower voltage rail VSS and a gate coupled to the output terminal of the transmission gate 900 to receive the voltage VDD2'.

[0093] The voltage level shifter 1100 includes a third PMOS FET M114, a fourth PMOS FET M115, and a second NMOS FET M116 that are serially coupled between the current input terminal (Vin) of the bias current receiver 800 and the lower voltage rail VSS. That is, the third PMOS FET M114 includes a source coupled to the current input terminal (Vin) of the bias current receiver 800, a gate coupled to the gate and drain of the second PMOS FET M112, and a drain coupled to the source of the fourth PMOS FET M115. The fourth PMOS FET M115 includes a gate and a drain that are coupled together and coupled to the gate of the first PMOS FET M111 and the drain of the second NMOS FET M116. The second NMOS FET M116 includes a source coupled to the lower voltage rail VSS and coupled to the output terminal of the inverter 1000 to receive the second control voltage V CN of the gate.

[0094] In addition, the voltage level shifter 1100 includes a fifth PMOS FET M117 and a third NMOS FET M118 coupled in series between the current input terminal (Vin) of the bias current receiver 800 and the lower voltage rail VSS. That is, the fifth PMOS FET M117 includes a source coupled to the current input terminal (Vin) of the bias current receiver 800, a gate coupled to the drain of the third PMOS FET M114 and the source of the fourth PMOS FET M115, and a drain coupled to the drain of the third NMOS FET M118. The NMOS FET M118 includes a gate coupled to the gate / drain of the fourth PMOS FET M115 (as well as the gate of the first PMOS FET M111 and the drain of the second NMOS FET M116). The NMOS FET M118 includes a source coupled to the lower voltage rail VSS. The first control voltage V CP Generated at the drains of the PMOS FET M117 and the NMOS FET M118.

[0095] In operation, when the supply voltage VDD2 has not collapsed, the voltage VDD2′ is logic high, and the second control voltage V CN 117 is turned off. The turned-on third PMOS FET M114 also applies Vin to the source of the diode-connected fourth PMOS FET M115. Therefore, the voltage at the gate / drain of the diode-connected fourth PMOS FET M115 is Vin-V T , which is applied to the gate of the third NMOS FET M118, causing the NMOS FET M118 to turn on. This causes the first control voltage V CP The potential is reduced to the VSS potential to turn on the PMOS FET M92 of the selective coupling circuit 822 .

[0096] When the supply voltage VDD2 has collapsed, the voltage VDD2′ is logic low, and the second control voltage V CN Logic high voltage V CNThe second NMOS FET M116 is turned on. Therefore, the gate of the first PMOS FET M111 is driven to the VSS potential (e.g., 0V), causing the first PMOS FET M111 to be turned on. The turned-on first PMOS FET M111 applies Vin to the source of the diode-connected second PMOS FET M112. Therefore, the voltage at the gate / drain of the diode-connected second PMOS FET M112 is greater than Vin-V T , which voltage is applied to the gate of the third PMOS FET M114, thereby turning off the PMOS FET M114. The gate of the third NMOS FET M118 is driven to the VSS potential, thereby turning off the NMOS FET M118. In addition, the gate of the fourth PMOS FET M115 is driven to the VSS potential (e.g., 0V), thereby turning on the fourth PMOS FET M115. The turned-on fourth PMOS FET M115 causes V T The potential is applied to the gate of the fifth PMOS FET M117 to turn on the PMOS FET M117. The turned-on PMOS FET M117 causes the first control voltage V CP The PMOS FET M92 of the selective coupling circuit 822 is at Vin to turn off.

[0097] Fig.12 1 is a schematic diagram illustrating another example selective coupling circuit 1200 according to another aspect of the present disclosure. The selective coupling circuit 1200 may be an example more detailed implementation of the selective coupling circuit 822 of the bias current receiver 800 discussed previously. Although not shown, the selective coupling circuit 1200 may include a VDD2 collapse control circuit 830.

[0098] The selective coupling circuit 1200 includes a first PMOS FET M121, a second PMOS FET M122, and a third PMOS FET M124, a first NMOS FET M123, a second NMOS FET M125, and a third NMOS FET M126, and an inverter 1220 including a PMOS FET M127 and NMOS FETs M128 and M129. These devices correspond to the first PMOS FET M92, the second PMOS FET M88, and the third PMOS FET M85, the first NMOSFET M84, the second NMOS FET M86, and the third NMOS FET M87, and the inverter 826 including a PMOS FET M89 and NMOS FETs M90 and M91 of the selective coupling circuit 822 discussed in detail previously, respectively.

[0099] In the selective coupling circuit 1200, the body (n-well) of each of the PMOS FETs M121, M122, M124, and M127 is coupled to the current input terminal (Vin) of the associated bias current receiver to prevent leakage current from flowing through the corresponding source / n-well junction when the body (n-well) is biased with the supply voltage VDD2 of the bias current receiver. For example, a voltage Vin (e.g., 1.2V) may be applied to the source of the PMOS FETs M121, M122, M124, and M127, and if a supply voltage VDD2 (e.g., 0.8V) is applied to the body (n-well) of these FETs, the p-doped source and the n-well form a pn junction that will be forward biased based on such voltage. Therefore, leakage current occurs through the source / n-well junction of the PMOS FETs M121, M122, M124, and M127. Therefore, in the selective coupling circuit 1200, the body (n-well) of each of the PMOS FETs M121, M122, M124, and M127 is coupled to the current input terminal (Vin) to prevent such leakage current.

[0100] Fig.13A A side view of an example integrated circuit (IC) 1300 that eliminates gate antenna effects associated with coupling of metal traces to the body of a field effect transistor (FET) according to another aspect of the present disclosure is illustrated. As previously mentioned with respect to IC 100, metal trace R may have a length (e.g., 10 mm to 15 mm) that may cause a gate antenna effect if it terminates at the gate of the FET. In addition, as previously discussed, metal traces R of ICs 100, 200, 300, 400, 500, and 700 terminate at current input terminals (Vin) of corresponding bias current receivers 120, 220, 320, 420, 520, and 720, respectively.

[0101] Thus, with respect to the selective coupling circuit 1200, such metal traces R may terminate at the body (n-well) of each of the PMOS FETs M121, M122, M124, and M127. Because the body (n-well) is directly coupled to the gate oxide or insulator of the corresponding PMOS FET, the gate oxide or insulator may experience gate antenna effect damage due to the direct coupling of the metal traces R to the body (n-well) of the corresponding PMOS FET. The IC 1300 includes a layout method to eliminate the gate antenna effect caused by the coupling of the metal traces R to the body (n-well) of the PMOSFET.

[0102] Specifically, IC 1300 includes a first n-well 1310 that can be associated with a reference current generator. IC 1300 includes a second n-well 1330 that can be associated with a bias current receiver, such as a bias current receiver that includes selective coupling circuit 1200. For example, second n-well 1330 can be the body (n-well) of any of PMOS FETs M121, M122, M124, and M127 of selective coupling circuit 1200. IC 1300 also includes a metal trace 1320 that electrically couples first n-well 1310 to second n-well 1330.

[0103] More specifically, one end (left end, as shown) of the metal trace 1320 may be coupled to the first n-well 1310 via an upper metallization via 1318, a lower metal layer 1316, and a lower metallization via 1314. Similarly, the other end (right end, as shown) of the metal trace 1320 may be coupled to the second n-well 1330 via an upper metallization via 1338, a lower metal layer 1336, and a lower metallization via 1334. In such a configuration, the metal trace 1320 is coupled to a pin of a cell including the n-wells 1310 and 1330. Therefore, if the metal trace 1320 is located at a metal layer or a higher metal layer including an end coupled to both the n-wells 1310 and 1330 when formed, the gate antenna effect may not be a problem because the charge accumulated on the metal trace 1320 is discharged via multiple paths and a relatively large area to prevent a high concentration of charge from being discharged via a gate oxide or an insulator, which may otherwise damage the corresponding FET.

[0104] Fig. 13B A side view of another example integrated circuit (IC) 1350 that eliminates gate antenna effects associated with coupling of metal traces to the body of a field effect transistor (FET) according to another aspect of the disclosure is illustrated.

[0105] IC 1350 includes a first n-well 1360 that can be associated with a reference current generator. IC 1350 includes a second n-well 1380 that can be associated with a bias current receiver, such as a bias current receiver including the selective coupling circuit 1200. Similarly, the second n-well 1380 can be the body (n-well) of any one of the PMOS FETs M121, M122, M124, and M127 of the selective coupling circuit 1200. IC 1350 also includes a metal trace 1374 that electrically couples the first n-well 1360 to the second n-well 1380. Unlike the metal trace 1320, the metal trace 1374 is located below the metal layer that is directly coupled to the pins of the unit incorporating the n-wells 1360 and 1380, respectively. In this case, the manufacturing sequence of IC 1350 should be considered to prevent the influence of the gate antenna on the device associated with the n-well 1380.

[0106] For example, metal trace 1374 may be formed on the same metal layer as metal contacts 1366 and 1386, which are coupled to n-wells 1360 and 1380 through metallized vias 1364 and 1384, respectively. Next, jumpers 1370 and 1390 may be formed to couple to metal trace 1374 through metallized vias 1372 and 1392, respectively. Jumpers 1370 and 1390 may also be coupled to metal contacts 1366 and 1386 through metallized vias 1368 and 1388, respectively. Thus, during fabrication, metal trace 1374 is electrically coupled to n-wells 1360 and 1380 via jumpers 1370 and 1390 at the same time, thereby allowing charges accumulated on metal trace 1374 to be discharged through multiple paths and a relatively large area, to prevent high concentrations of charges from being discharged through gate oxides or insulators, which may otherwise damage the corresponding FETs.

[0107] Fig.14 A flow chart illustrating an example method 1400 of generating a bias current according to another aspect of the present disclosure is illustrated. The method 1400 includes selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of a second FET to achieve a current mirror operation of the first FET and the second FET in response to a voltage at the first drain of the first FET (block 1410). Examples of means for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET in response to a voltage at the first drain of the first field effect transistor (FET) to achieve a current mirror operation of the first FET and the second FET include selective coupling circuits 522, 622, 722, 822, including sub-circuits 900, 1000, and 1100 described herein.

[0108] With respect to selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, the method 1400 may further include selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, in response to an enable signal. Examples of means for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, in response to the enable signal include any of the selective coupling circuits described herein.

[0109] In addition, the method 1400 may include generating a current through the second FET based on the supply voltage, wherein the first drain of the first FET is selectively coupled to the first gate of the first FET and the second gate of the second FET, respectively, and further includes decoupling the first drain of the first FET from the first gate of the first FET and the second gate of the second FET in response to the supply voltage collapse. Examples of means for generating a current through the second FET based on the supply voltage include PMOS FETs M15, M25, M35, M45, M55, M63, M75, and M83 coupled in series with NMOS FETs M14, M24, M34, M44, M54, M62, M74, and M82, respectively, between the upper voltage rail VDD2 and the lower voltage rail VSS. Examples of means for decoupling the first drain of the first FET from the first gate of the first FET and the second gate of the second FET in response to the supply voltage collapse include selective coupling circuits 722 and 822, including sub-circuits 900, 1000, and 1100 described herein.

[0110] Fig.15 A block diagram of an example wireless communication device 1500 according to another aspect of the present disclosure is illustrated. The wireless communication device 1500 may be a smartphone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0111] Specifically, the wireless communication device 1500 includes an integrated circuit (IC) that can be implemented as a system on chip (SOC) 1510. The SOC 1510 includes a reference current generator 1520, a bias current receiver 1530, and one or more signal processing cores 1540. For example, the reference current generator 1520 is coupled to the bias current receiver 1530 to provide a reference current I REF The bias current receiver 1530 is coupled to one or more signal processing cores 1540 to bias the current based on the reference current I REF Provide one or more bias currents I B1 and I BN The one or more signal processing cores 1540 may use the set of one or more bias currents I B1 and I BN To generate the transmit baseband (BB) signal and process the receive baseband (BB) signal.

[0112] The wireless communication device 1500 may also include a transceiver 1550 and at least one antenna 1560 (e.g., an antenna array). The transceiver 1550 is coupled to one or more signal processing cores 1540 to receive a transmit BB signal therefrom and provide a receive BB signal thereto. The transceiver 1550 is configured to convert the transmit BB signal into a transmit radio frequency (RF) signal and convert the receive RF signal into a receive BB signal. The transceiver 1550 is coupled to at least one antenna 1560 to provide it with a transmit RF signal for electromagnetic radiation into a wireless medium for wireless transmission, and to receive a receive RF signal electromagnetically picked up from the wireless medium by at least one antenna 1560.

[0113] The following provides an overview of various aspects of the disclosure:

[0114] Aspect 1: An integrated circuit (IC), comprising: a current mirror, the current mirror comprising: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET, the second FET comprising a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET and the second source is coupled to the first voltage rail; and a selective coupling circuit, the selective coupling circuit being configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET.

[0115] Aspect 2: An IC according to Aspect 1, wherein the selective coupling circuit includes: a third FET, the third FET including a third source, a third gate and a third drain, wherein the third source is coupled to the first drain of the first FET; and an inverter, the inverter is coupled between the first drain of the first FET and the first voltage rail, wherein the inverter includes an input terminal coupled to the third drain of the third FET and an output terminal coupled to the third gate of the third FET.

[0116] Aspect 3: An IC according to Aspect 2, wherein the inverter includes: a fourth FET, the fourth FET including a fourth source, a fourth gate and a fourth drain, wherein the fourth source is coupled to the first drain of the first FET; and a fifth FET, the fifth FET including a fifth drain, a fifth gate and a fifth source, wherein the fifth drain is coupled to the fourth drain of the fourth FET, wherein the fifth gate is coupled to the fourth gate of the fourth FET, and wherein the fifth source is coupled to the first voltage rail.

[0117] Aspect 4: An IC according to Aspect 3, wherein the first FET, the second FET and the fifth FET each include an n-channel metal oxide semiconductor field effect transistor (NMOS FET), and wherein the third FET and the fourth FET each include a p-channel metal oxide semiconductor field effect transistor (PMOS FET).

[0118] Aspect 5: The IC of aspect 4, wherein the third FET and the fourth FET each include an n-well coupled to the first drain of the first FET.

[0119] Aspect 6: The IC of aspect 5, wherein the n-well is coupled to a metal trace via a jumper.

[0120] Aspect 7: The IC of any one of aspects 1 to 6, wherein the selective coupling circuit is further configured to couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a first enable signal.

[0121] Aspect 8: An IC according to Aspect 7, wherein the selective coupling circuit includes: a first NMOS FET, the first NMOS FET including a third drain, a third gate, and a third source, wherein the third drain is coupled to the first drain of the first FET, wherein the third gate is configured to receive the first enable signal, and wherein the third source is coupled to the first gate of the first FET and the second gate of the second FET; and a first PMOSFET, the first PMOS FET including a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the third drain of the first NMOS FET, wherein the fourth gate is configured to receive a second enable signal complementary to the first enable signal, and wherein the fourth drain is coupled to the third source of the first NMOS FET.

[0122] Aspect 9: An IC according to Aspect 8, wherein the selective coupling circuit further includes a second NMOS FET, the second NMOS FET including a fifth drain, a fifth gate, and a fifth source, wherein the fifth drain is coupled to the first gate of the first FET and the second gate of the second FET, wherein the fifth gate is configured to receive the second enable signal, and wherein the fifth source is coupled to the first voltage rail.

[0123] Aspect 10: An IC according to Aspect 9, wherein the selective coupling circuit further includes: a second PMOS FET, the second PMOS FET including a sixth source, a sixth gate and a sixth drain, wherein the sixth source is coupled to the first drain of the first FET, and wherein the sixth drain is coupled to the fourth source of the first PMOS FET; and an inverter, the inverter is coupled between the first drain of the first FET and the first voltage rail, wherein the inverter includes an input terminal coupled to the first gate of the first FET and the second gate of the second FET and an output terminal coupled to the sixth gate of the second PMOS FET.

[0124] Aspect 11: The IC of aspect 10, wherein the first PMOS FET and the second PMOS FET each include an n-well coupled to the first drain of the first FET.

[0125] Aspect 12: The IC of any one of aspects 1 to 11, further comprising a third FET coupled in series with the second FET between a second voltage rail and the first voltage rail.

[0126] Aspect 13: The IC of aspect 12, wherein the selective coupling circuit is further configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a supply voltage at the second voltage rail.

[0127] Aspect 14: An IC according to Aspect 13, wherein the selective coupling circuit includes: a control circuit, the control circuit including a first control input terminal coupled to the first drain of the first FET, a second control input terminal coupled to the second voltage rail, and a third control input terminal coupled to the first voltage rail; a first control output terminal and a second control output terminal; a PMOS FET, the PMOS FET including a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the first drain of the first FET, wherein the fourth gate is coupled to the first control output terminal of the control circuit, and wherein the fourth drain is coupled to the first gate of the first FET and the second gate of the second FET; and an NMOS FET, the NMOS FET including a fifth drain, a fifth gate, and a fifth source, wherein the fifth drain is coupled to the first gate of the first FET and the second gate of the second FET, wherein the fifth gate is coupled to the second control output terminal of the control circuit, and wherein the fifth source is coupled to the first voltage rail.

[0128] Aspect 15: An IC according to Aspect 14, wherein the control circuit sets the first control signal at the first control output terminal to turn on the PMOS FET and sets the second control signal at the second control output terminal to turn off the NMOS FET based on the power supply voltage not collapsing; and sets the first control signal at the first control output terminal to turn off the PMOS FET and sets the second control signal at the second control output terminal to turn on the NMOS FET based on the power supply voltage having collapsed.

[0129] Aspect 16: The IC of aspect 15, wherein the control circuit further comprises an inverter configured to generate the second control signal in response to the supply voltage.

[0130] Aspect 17: The IC of aspect 16, wherein the control circuit comprises a transmission gate including an input coupled to or used as the second control input and an output coupled to an input of the inverter.

[0131] Aspect 18: The IC according to any one of aspects 15 to 17, wherein the control circuit further comprises a voltage level shifter configured to generate the first control signal in response to the supply voltage and the second control signal.

[0132] Aspect 19: A method comprising selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of a second FET to implement a current mirror operation of the first FET and the second FET in response to a voltage at the first drain of the first FET.

[0133] Aspect 20: The method according to Aspect 19, wherein selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, further comprises: selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, in response to an enable signal.

[0134] Aspect 21: The method according to Aspect 19 or 20 further includes generating a current flowing through the second FET based on a power supply voltage, wherein selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, further includes: decoupling the first drain of the first FET from the first gate of the first FET and the second gate of the second FET in response to a collapse of the power supply voltage.

[0135] Aspect 22: A device comprising: a first field effect transistor (FET); a second FET; and a component for selectively coupling a first drain of the first FET to a first gate of the first FET and a second gate of the second FET to implement a current mirror operation of the first FET and the second FET in response to a voltage at the first drain of the first FET.

[0136] Aspect 23: An apparatus according to Aspect 22, wherein the component for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, includes: a component for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, in response to an enable signal.

[0137] Aspect 24: An apparatus according to Aspect 22 or 23, the apparatus further comprising a component for generating a current flowing through the second FET based on a supply voltage, wherein the component for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, comprises: a component for decoupling the first drain of the first FET from the first gate of the first FET and the second gate of the second FET in response to a collapse of the supply voltage.

[0138] Aspect 25: A wireless communication device, the wireless communication device comprising: a reference current generator; a bias current receiver, the bias current receiver coupled to the reference current generator, wherein the bias current receiver comprises: a current mirror, the current mirror comprising: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET, the second FET comprising a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET and the second source is coupled to the first voltage rail; and a selective coupling circuit, the selective coupling circuit being configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET; and one or more signal processing cores, the one or more signal processing cores being coupled to the bias current receiver.

[0139] Aspect 26: A wireless communication device according to Aspect 25, wherein the selective coupling circuit includes: a third FET, the third FET including a third source, a third gate and a third drain, wherein the third source is coupled to the first drain of the first FET; and an inverter, the inverter is coupled between an input terminal and the first voltage rail, wherein the inverter includes an input terminal coupled to an output terminal and the third drain of the third FET and an output terminal coupled to the third gate of the third FET.

[0140] Aspect 27: A wireless communication device according to Aspect 25 or 26, wherein the selective coupling circuit includes: a second control input terminal, the second control input terminal is configured to receive an enable signal; and a transmission gate, the transmission gate is coupled between the first drain of the first FET and the first gate and the second gate, wherein the transmission gate is coupled to the second control input terminal.

[0141] Aspect 28: A wireless communication device according to any one of Aspects 25 to 27, wherein the bias current receiver also includes a third FET coupled in series with the second FET between a second voltage rail and the first voltage rail, and wherein the selective coupling circuit also includes: a control circuit, the control circuit including a first control input terminal coupled to the first drain of the first FET, a second control input terminal coupled to the second voltage rail, and a third control input terminal coupled to the first voltage rail; a first control output terminal and a second control output terminal; a fourth FET, the fourth FET including a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the first drain of the first FET, wherein the fourth gate is coupled to the first control output terminal of the control circuit, and wherein the fourth drain is coupled to the first gate and the second gate; and a fifth FET, the fifth FET including a fifth drain, a fifth gate, and a fifth source, wherein the fifth drain is coupled to the first gate and the second gate, wherein the fifth gate is coupled to the second control output terminal of the control circuit, and wherein the fifth source is coupled to the first voltage rail.

[0142] Aspect 29: An integrated circuit (IC), comprising: a bias current receiver, the bias current receiver comprising: a current mirror, the current mirror comprising: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail and the first drain is coupled to a current input terminal of the bias current receiver; and a second FET, the second FET comprising a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET and the second source is coupled to the first voltage rail; and a selective coupling circuit, the selective coupling circuit being configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET.

[0143] Aspect 30: An IC according to Aspect 1, wherein the selective coupling circuit is further configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a first enable signal received at a second control input of the selective coupling circuit, wherein the voltage at the first drain of the first FET is received via the first control input of the selective coupling circuit coupled to the current input of the bias current receiver.

[0144] Aspect 31: A method comprising selectively coupling a first drain of a first field effect transistor (FET) to a first gate of a first FET and a second gate of a second FET of a bias current receiver to mirror a first current received at an input terminal of the bias current receiver, thereby generating a mirror current flowing through the second FET based on a voltage generated at the input terminal of the bias current receiver in response to the first current.

[0145] Aspect 32: A device comprising: a bias current receiver, the bias current receiver comprising: a first field effect transistor (FET); a second FET; and a component for: selectively coupling a first drain of the first FET to a first gate of the first FET and a second gate of the second FET to mirror a first current received at an input terminal of the bias current receiver, thereby generating a mirror current flowing through the second FET based on a voltage generated at the input terminal of the bias current receiver in response to the first current.

[0146] Aspect 33: A wireless communication device, the wireless communication device comprising: a reference current generator; a bias current receiver, the bias current receiver coupled to the reference current generator via a metal trace, wherein the bias current receiver comprises: a current mirror, the current mirror comprising: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail and the first drain is coupled to a current input terminal of the bias current receiver; and a second FET, the second FET comprising a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET and the second source is coupled to the first voltage rail; and a selective coupling circuit, the selective coupling circuit having an input terminal coupled to the current input terminal of the bias current receiver and an output terminal coupled to the gates of the first FET and the second FET, wherein the selective coupling circuit is configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET; and one or more signal processing cores, the one or more signal processing cores coupled to the bias current receiver.

[0147] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC), comprising: A current mirror, the current mirror comprising: a first field effect transistor (FET) comprising a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and A selective coupling circuit is configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET.

2. The IC of claim 1 , wherein the selective coupling circuit comprises: a third FET comprising a third source, a third gate, and a third drain, wherein the third source is coupled to the first drain of the first FET; as well as An inverter is coupled between the first drain of the first FET and the first voltage rail, wherein the inverter includes an input coupled to the third drain of the third FET and an output coupled to the third gate of the third FET.

3. The IC of claim 2, wherein the inverter comprises: a fourth FET comprising a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the first drain of the first FET; as well as a fifth FET comprising a fifth drain, a fifth gate, and a fifth source, wherein the fifth drain is coupled to the fourth drain of the fourth FET, wherein the fifth gate is coupled to the fourth gate of the fourth FET, and wherein the fifth source is coupled to the first voltage rail.

4. The IC of claim 3 , wherein the first FET, the second FET, and the fifth FET each comprise an n-channel metal oxide semiconductor field effect transistor (NMOS FET), and wherein the third FET and the fourth FET each comprise a p-channel metal oxide semiconductor field effect transistor (PMOS FET).

5. The IC of claim 4, wherein the third FET and the fourth FET each include an n-well coupled to the first drain of the first FET.

6. The IC of claim 5, wherein the n-well is coupled to a metal trace via a jumper. 7 . The IC of claim 1 , wherein the selective coupling circuit is further configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a first enable signal.

8. The IC of claim 7, wherein the selective coupling circuit comprises: a first NMOS FET comprising a third drain, a third gate, and a third source, wherein the third drain is coupled to the first drain of the first FET, wherein the third gate is configured to receive the first enable signal, and wherein the third source is coupled to the first gate of the first FET and the second gate of the second FET; as well as a first PMOS FET comprising a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the third drain of the first NMOS FET, wherein the fourth gate is configured to receive a second enable signal complementary to the first enable signal, and wherein the fourth drain is coupled to the third source of the first NMOS FET.

9. The IC of claim 8, wherein the selective coupling circuit further comprises a second NMOS FET, the second NMOS FET comprising a fifth drain, a fifth gate, and a fifth source, wherein the fifth drain is coupled to the first gate of the first FET and the second gate of the second FET, wherein the fifth gate is configured to receive the second enable signal, and wherein the fifth source is coupled to the first voltage rail.

10. The IC of claim 9, wherein the selective coupling circuit further comprises: a second PMOS FET comprising a sixth source, a sixth gate, and a sixth drain, wherein the sixth source is coupled to the first drain of the first FET, and wherein the sixth drain is coupled to the fourth source of the first PMOSFET; as well as an inverter coupled between the first drain of the first FET and the first voltage rail, wherein the inverter includes an input coupled to the first gate of the first FET and the second gate of the second FET and an output coupled to the sixth gate of the second PMOS FET.

11. The IC of claim 10, wherein the first PMOS FET and the second PMOS FET each include an n-well coupled to the first drain of the first FET.

12. The IC of claim 1, further comprising a third FET coupled in series with the second FET between a second voltage rail and the first voltage rail.

13. The IC of claim 12, wherein the selective coupling circuit is further configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a supply voltage at the second voltage rail.

14. The IC of claim 13, wherein the selective coupling circuit comprises: a control circuit comprising a first control input coupled to the first drain of the first FET, a second control input coupled to the second voltage rail, and a third control input coupled to the first voltage rail; a first control output and a second control output; a PMOS FET comprising a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the first drain of the first FET, wherein the fourth gate is coupled to the first control output of the control circuit, and wherein the fourth drain is coupled to the first gate of the first FET and the second gate of the second FET; as well as an NMOS FET comprising a fifth drain, a fifth gate, and a fifth source, wherein the fifth drain is coupled to the first gate of the first FET and the second gate of the second FET, wherein the fifth gate is coupled to the second control output of the control circuit, and wherein the fifth source is coupled to the first voltage rail.

15. The IC of claim 14, wherein the control circuit is configured to: Based on the supply voltage not collapsing, setting a first control signal at the first control output to turn on the PMOS FET and setting a second control signal at the second control output to turn off the NMOS FET; and Based on the supply voltage having collapsed, the first control signal at the first control output is set to turn off the PMOS FET and the second control signal at the second control output is set to turn on the NMOSFET. 16 . The IC of claim 15 , wherein the control circuit further comprises an inverter configured to generate the second control signal in response to the supply voltage.

17. The IC of claim 16, wherein the control circuit comprises a transmission gate including an input coupled to or used as the second control input and an output coupled to an input of the inverter. 18 . The IC of claim 15 , wherein the control circuit further comprises a voltage level shifter configured to generate the first control signal in response to the supply voltage and the second control signal.

19. A method comprising selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of a second FET to achieve a current mirror operation of the first FET and the second FET in response to a voltage at the first drain of the first FET.

20. The method of claim 19, wherein selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, further comprises: In response to an enable signal, the first drain of the first FET is selectively coupled to the first gate of the first FET and the second gate of the second FET, respectively.

21. The method of claim 19, further comprising generating a current flowing through the second FET based on a supply voltage, wherein selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, further comprises: In response to the supply voltage collapsing, the first drain of the first FET is decoupled from the first gate of the first FET and the second gate of the second FET.

22. A device, comprising: a first field effect transistor (FET); Second FET; as well as means for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET to achieve a current mirror operation of the first FET and the second FET in response to a voltage at the first drain of the first FET.

23. The apparatus of claim 22, wherein the means for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, comprises: Means for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, in response to an enable signal.

24. The apparatus of claim 22, further comprising means for generating a current flowing through the second FET based on a supply voltage, wherein the means for selectively coupling the first drain of the first FET to the first gate of the first FET and the second gate of the second FET, respectively, comprises: Means for decoupling the first drain of the first FET from the first gate of the first FET and the second gate of the second FET in response to the supply voltage collapsing.

25. A wireless communication device, comprising: reference current generator; a bias current receiver coupled to the reference current generator, wherein the bias current receiver comprises: A current mirror, the current mirror comprising: a first field effect transistor (FET) comprising a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET comprising a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first gate of the first FET and the second gate of the second FET based on a voltage at the first drain of the first FET; and One or more signal processing cores are coupled to the bias current receiver.

26. The wireless communication device of claim 25, wherein the selective coupling circuit comprises: a third FET comprising a third source, a third gate, and a third drain, wherein the third source is coupled to the first drain of the first FET; as well as An inverter is coupled between the first drain of the first FET and the first voltage rail, wherein the inverter includes an input coupled to an output terminal and the third drain of the third FET and an output terminal coupled to the third gate of the third FET.

27. The wireless communication device of claim 25, wherein the selective coupling circuit comprises: a second control input terminal, the second control input terminal being configured to receive an enable signal; as well as A transmission gate is coupled between the first drain of the first FET and the first gate and the second gate, wherein the transmission gate is coupled to the second control input.

28. The wireless communication device of claim 25, wherein the bias current receiver further comprises a third FET coupled in series with the second FET between a second voltage rail and the first voltage rail, and wherein the selective coupling circuit further comprises: a control circuit comprising a first control input coupled to the first drain of the first FET, a second control input coupled to the second voltage rail, and a third control input coupled to the first voltage rail; a first control output and a second control output; a fourth FET comprising a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the first drain of the first FET, wherein the fourth gate is coupled to the first control output of the control circuit, and wherein the fourth drain is coupled to the first gate and the second gate; as well as a fifth FET comprising a fifth drain, a fifth gate, and a fifth source, wherein the fifth drain is coupled to the first gate and the second gate, wherein the fifth gate is coupled to the second control output of the control circuit, and wherein the fifth source is coupled to the first voltage rail.

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