Selectively updating branch predictor for loops executed from loop buffer in processor

Abstract

Selectively updating a branch predictor for loops performed from a loop buffer is disclosed herein. In some aspects, a branch predictor update circuit of a processor is configured to detect a loop comprising a plurality of loop instructions in an instruction stream, and determine that the loop is stored within a loop buffer circuit of the processor. The branch predictor update circuitry is further configured to determine a count of potential history register updates to the history register for the plurality of loop instructions, and to determine whether the count of potential history register updates exceeds a size of the history register. The branch predictor update circuit is also configured to update a branch predictor of the branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential historical register updates does not exceed the size of the historical register.

Description

Technical Field

[0001] The techniques of this disclosure relate to the processing of instructions for execution in a microprocessor ("processor"), and in particular to branch prediction of branch instructions in a processor. Background Art

[0002] Microprocessors, also referred to herein as "processors," perform computing tasks for a wide variety of applications. Conventional processors include a central processing unit (CPU), which includes one or more processor cores or "CPU cores." The CPU executes computer program instructions ("instructions" or "software instructions") to perform data-based operations and generate results. The results may then be stored in a memory, provided as output to an input / output ("I / O") device, or made available (i.e., communicated) as an input value to another instruction executed by the CPU, as non-limiting examples.

[0003] The processor can adopt a processing technique known as instruction pipelining, so that the throughput of the computer instructions being executed can be increased by dividing the processing of each instruction into a series of steps, which are then executed in an execution pipeline consisting of multiple stages. If all stages in the execution pipeline can process instructions simultaneously and in the order in which the instructions are sorted in the execution pipeline, optimal processor performance can be achieved. However, a situation known as structural hazard may occur, so that the next instruction cannot be executed without causing incorrect calculation results. For example, a control hazard may occur as a result of the execution of a branch instruction, which can redirect the path of instruction execution based on the result evaluated when executing the branch instruction. When encountering a branch instruction, the processor may need to suspend the extraction of additional instructions until the branch instruction has been executed, which may cause processor performance to decrease and power consumption to increase.

[0004] A method for maximizing processor performance involves using a branch predictor circuit to speculatively predict the path to be taken by a branch instruction (based on, for example, the results of a previously executed branch instruction), and basing the fetching of subsequent instructions on the branch prediction. When a branch instruction reaches the execution stage of an instruction pipeline and is executed, the resulting target address of the branch instruction is verified by comparing the resulting target address of the branch instruction with the target address previously predicted when the branch instruction was fetched. If the predicted target address matches the actual target address (i.e., the branch prediction is correct), instruction execution can proceed without delay because subsequent instructions at the target address have already been fetched and will be presented in the instruction pipeline. In order to correlate branch predictions with previously observed program behavior, the branch predictor circuit can use a limited-size history register to track data related to, for example, global branch history, path history, etc.

[0005] Many conventional processors can achieve further pipeline optimization and power savings by providing special processing of loops. As used herein, a "loop" refers to any sequence of instructions in an instruction pipeline whose processing is sequentially repeated in back-to-back operations. For example, a loop can be obtained from a software loop construct that is compiled into an instruction group that is repeatedly and sequentially processed. Figure 1 An example of an instruction stream 100 including instructions including an exemplary loop 102 is shown. Figure 1 The loop 102 in the example of is a "while" loop that begins with a while instruction 104, which when processed determines whether a specified conditional evaluation is true or false. If the conditional evaluation of the while instruction 104 is determined to be true, instructions 106 to 112 in the loop 102 are executed, and as long as the conditional evaluation of the while instruction 104 is true, the execution of instructions 106 to 112 in the loop 102 will continue to be executed as a loop. If the conditional evaluation of the while instruction 104 is determined to be false, the while instruction 104 is considered to be an exit branch instruction, and the loop 102 exits to the next instruction 114 at the exit target address.

[0006] If a loop can be detected within the instruction pipeline (such as Figure 1 In the example of loop 102 in FIG. 1 , the instructions constituting the loop can be captured and replayed for the number of iterations processed by the loop before exiting, without the instruction pipeline having to re-fetch and re-decode the instructions. This is because each subsequent iteration of the loop after the first iteration necessarily involves the same sequence of instructions that have been fetched and decoded for the first iteration of the loop. In this regard, many conventional processors provide loop buffer circuits to detect, capture, and replay loop instructions. Power savings can be achieved by deactivating or otherwise pausing the fetch and decode stages of the instruction pipeline when replaying loop instructions from the loop buffer.

[0007] However, the use of a loop buffer circuit may raise issues with respect to updates to the branch predictor (i.e., history registers and / or branch predictor table entries) used by the branch predictor circuit. In particular, issues may arise regarding whether the branch predictor should be updated for branch instructions within a loop that is replayed from the loop buffer circuit. For example, with respect to the history register, a conventional approach may update the history register with new data for each branch instruction encountered, which causes older data recorded in the history register to be shifted. If the history register contains 64 bits and each branch instruction encountered inserts one (1) bit into the history register, then a loop with two (2) branches per iteration will update the history register twice during each loop iteration. After 32 loop iterations, all data stored in the history register from instructions prior to the loop will be shifted by updates performed during the loop, and therefore the branch predictor will not be able to correlate with any history prior to the loop. Furthermore, because each update per loop iteration will be the same (except perhaps for the last iteration), there is no way to distinguish different loops beyond 32 iterations (i.e., the branch predictor will not be able to distinguish between two loops where one loop iterates 40 times and the other loop iterates 100 times). Repeatedly updating the branch predictor table entries for every branch instruction encountered during a loop may result in excessive power consumption without corresponding benefit in terms of the branch predictor table entries. Summary of the invention

[0008] Aspects disclosed herein include selectively updating a branch predictor for a loop executed from a loop buffer in a processor. The processor provides a branch predictor update circuit configured to detect a loop including a plurality of loop instructions and configured to determine a count of potential history register updates to a history register for the plurality of loop instructions, the plurality of loop instructions being stored in a loop buffer circuit of the processor. In some aspects, the count of potential history register updates may be determined as a product of a predicted count of loop iterations, a count of one or more branch instructions within the plurality of loop instructions, and a count of bits of the history register updated for each of the one or more branch instructions. If the count of potential history register updates does not exceed the size of the history register, the branch predictor update circuit is configured to update a branch predictor (i.e., a history register and / or a branch predictor table entry of a branch predictor table of a branch predictor circuit of the processor) based on the plurality of loop instructions. In aspects where the branch predictor to be updated is a history register, the branch predictor update circuit may "fast forward" updates to the history register by performing all updates to the history register before initiating execution of the loop from the loop buffer circuit. If the branch predictor update circuitry determines that the count of potential history register updates exceeds the size of the history register, then in some aspects the branch predictor update circuitry may initiate execution of the loop from the loop buffer circuitry without updating the branch predictor for the loop.

[0009] In aspects where the branch predictor circuitry provides multiple branch predictor tables associated with corresponding history registers of different sizes, it may be desirable to update only the branch predictor for the branch predictor table associated with the larger history register, while leaving the branch predictor for the branch predictor table associated with the smaller history register unchanged. In this regard, such aspects may provide that the branch predictor circuitry is further configured to determine whether the size of the history register exceeds a history register size threshold, and to update the branch predictor only if the size of the history register exceeds the history register size threshold.

[0010] Some aspects may provide that the branch predictor update circuitry performs updates to the branch predictor only for a subset of potential historical register updates that are performed during a loop iteration (e.g., in the case of a long running loop). In such aspects, the branch predictor update circuitry may be configured to determine whether a count of potential historical register updates exceeds an update count threshold. If so, the branch predictor update circuitry is configured to update the branch predictor of the branch predictor circuitry only for a subset of potential historical register updates. In some such aspects, the subset of potential historical register updates may be determined by the equation x+log 10 n-log 10x is determined, where x is a non-zero integer representing an update count threshold, and n is a non-zero integer representing a count of potential history register updates. Thus, for example, if the branch predictor to be updated is a 100-bit history register, the update count threshold is 80, 1 bit is updated into the history register per loop iteration, and the count of potential history register updates is between 100 and 999, then the branch predictor will be updated 81 times.

[0011] In this regard, in one exemplary aspect, a processor for selectively updating a branch predictor for a loop executed from a loop buffer is disclosed. The processor includes: an instruction processing circuit configured to process an instruction stream including a plurality of instructions in an instruction pipeline; a branch predictor circuit including a history register; and a branch predictor update circuit. The branch predictor update circuit is configured to detect a loop including a plurality of loop instructions among the plurality of instructions in the instruction stream. The branch predictor update circuit is also configured to determine a count of potential history register updates to the history register for a plurality of loop instructions. The branch predictor update circuit is additionally configured to determine whether the count of potential history register updates exceeds the size of the history register. The branch predictor update circuit is also configured to update a branch predictor of the branch predictor circuit based on a plurality of loop instructions in response to determining that the count of potential history register updates does not exceed the size of the history register.

[0012] In another exemplary aspect, a method for selectively updating a branch predictor for a loop executed from a loop buffer is disclosed. The method includes detecting a loop including a plurality of loop instructions among a plurality of instructions in an instruction stream. The method also includes determining that the loop is stored in a loop buffer circuit. The method also includes determining a count of potential history register updates to a history register for the plurality of loop instructions. The method additionally includes determining whether the count of potential history register updates exceeds a size of the history register. The method also includes updating a branch predictor of a branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential history register updates does not exceed a size of the history register.

[0013] In another exemplary aspect, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium stores computer-executable instructions that, when executed, cause a processor to selectively update a branch predictor for a loop executed from a loop buffer by causing the processor to detect a loop including a plurality of loop instructions among a plurality of instructions in an instruction stream. The computer-executable instructions also cause the processor to determine that the loop is stored within a loop buffer circuit of the processor. The computer-executable instructions also cause the processor to determine a count of potential history register updates to a history register for the plurality of loop instructions. The computer-executable instructions additionally cause the processor to determine whether the count of potential history register updates exceeds the size of the history register. The computer-executable instructions also cause the processor to update a branch predictor of a branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential history register updates does not exceed the size of the history register.

[0014] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0016] Figure 1 is a diagram of an exemplary cycle of computer program instructions in an instruction stream;

[0017] Figure 2 is a diagram of an exemplary processor-based system including a processor having instruction processing circuitry including branch predictor update circuitry configured to selectively update a branch predictor for a loop executed from a loop buffer;

[0018] Figure 3 Shown in more detail Figure 2 Exemplary aspects of a branch predictor update circuit of;

[0019] Figure 4A and Figure 4B It is shown by Figure 2 and Figure 3 A flowchart of exemplary operations performed by a branch predictor update circuit of a loop buffer for selectively updating a branch predictor for a loop executed from a loop buffer;

[0020] Figure 5 is a diagram showing a method for Figure 2 and Figure 3A flowchart of exemplary operations of a branch predictor update circuit of a processor to determine a count of potential historical register updates;

[0021] Figure 6 is shown in some aspects for use by Figure 2 and Figure 3 A flowchart of additional exemplary operations of a branch predictor update circuit of the invention to determine how many updates to a branch predictor should be performed; and

[0022] Figure 7 is a block diagram of an exemplary processor-based system including a processor (such as Figure 2 The invention also provides an instruction processing circuit comprising a branch predictor update circuit for selectively updating a branch predictor for a loop executed from a loop buffer. DETAILED DESCRIPTION

[0023] Aspects disclosed herein include selectively updating a branch predictor for a loop executed from a loop buffer in a processor. The processor provides a branch predictor update circuit configured to detect a loop including a plurality of loop instructions and configured to determine a count of potential history register updates to a history register for the plurality of loop instructions, the plurality of loop instructions being stored in a loop buffer circuit of the processor. In some aspects, the count of potential history register updates may be determined as a product of a predicted count of loop iterations, a count of one or more branch instructions within the plurality of loop instructions, and a count of bits of the history register updated for each of the one or more branch instructions. If the count of potential history register updates does not exceed the size of the history register, the branch predictor update circuit is configured to update a branch predictor (i.e., a history register and / or a branch predictor table entry of a branch predictor table of a branch predictor circuit of the processor) based on the plurality of loop instructions. In aspects where the branch predictor to be updated is a history register, the branch predictor update circuit may "fast forward" updates to the history register by performing all updates to the history register before initiating execution of the loop from the loop buffer circuit. If the branch predictor update circuitry determines that the count of potential history register updates exceeds the size of the history register, then in some aspects the branch predictor update circuitry may initiate execution of the loop from the loop buffer circuitry without updating the branch predictor for the loop.

[0024] In aspects where the branch predictor circuitry provides multiple branch predictor tables associated with corresponding history registers of different sizes, it may be desirable to update only the branch predictor for the branch predictor table associated with the larger history register, while leaving the branch predictor for the branch predictor table associated with the smaller history register unchanged. In this regard, such aspects may provide that the branch predictor circuitry is further configured to determine whether the size of the history register exceeds a history register size threshold, and to update the branch predictor only if the size of the history register exceeds the history register size threshold.

[0025] Some aspects may provide that the branch predictor update circuitry performs updates to the branch predictor only for a subset of potential historical register updates that are performed during a loop iteration (e.g., in the case of a long running loop). In such aspects, the branch predictor update circuitry may be configured to determine whether a count of potential historical register updates exceeds an update count threshold. If so, the branch predictor update circuitry is configured to update the branch predictor of the branch predictor circuitry only for a subset of potential historical register updates. In some such aspects, the subset of potential historical register updates may be determined by the equation x+log 10 n-log 10 x is determined, where x is a non-zero integer representing an update count threshold, and n is a non-zero integer representing a count of potential history register updates. Thus, for example, if the branch predictor to be updated is a 100-bit history register, the update count threshold is 80, 1 bit is updated into the history register per loop iteration, and the count of potential history register updates is between 100 and 999, then the branch predictor will be updated 81 times.

[0026] in this regard, Figure 2 is a diagram of an exemplary processor-based system 200 including a processor 202. The processor 202, which may also be referred to as a "processor core" or a "central processing unit (CPU) core," may be an in-order processor or an out-of-order processor (OoP), and / or may be one of a plurality of processors 202 provided by the processor-based system 200. Figure 2 In the example of FIG. 1 , the processor 202 includes an instruction processing circuit 204 including one or more instruction pipelines 10 to 11 for processing instructions 206. N , the processing instruction 206 is fetched from the instruction memory (at Figure 2 Instruction memory 208 is retrieved for execution. As a non-limiting example, instruction memory 208 may be provided in or as part of system memory in processor-based system 200. Instruction cache ( Figure 2CACHE” 212 may also be provided in processor 202 to cache instructions 206 fetched from instruction memory 208 to reduce latency in fetch circuitry 210 .

[0027] Figure 2 The fetch circuit 210 in the example of is configured to fetch the instruction 206F when it reaches the execution circuit ( Figure 2 The instruction 206 is provided as fetched instruction 206F to one or more instruction pipelines 10 to 11 in the instruction processing circuit 204 before the instruction 206 is fetched as instruction 206F. N Different processing circuits or stages across the instruction processing circuit 204 provide instruction pipelines I0 to I1. N , to pre-process and process the fetched instructions 206F in a series of steps that can be performed simultaneously to increase throughput before the fetched instructions 206F are executed by the execution circuitry 214.

[0028] Continue to refer Figure 2 , the instruction processing circuit 204 includes a decoding circuit 218 configured to decode the extracted instruction 206F extracted by the extraction circuit 210 into a decoded instruction 206D to determine the required instruction type and action. The required instruction type and action encoded in the decoded instruction 206D can also be used to determine which instruction pipeline I0 to I1 should be placed in which the decoded instruction 206D N In this example, decoded instruction 206D is placed in instruction pipelines I0 to I N 206D and is then provided to the renaming circuit 220 in the instruction processing circuit 204. The renaming circuit 220 is configured to determine whether any register names in the decoded instruction 206D should be renamed to decouple any register dependencies that would prevent parallel or out-of-order processing.

[0029] Figure 2 The instruction processing circuit 204 in the processor 202 also includes a register access circuit ( Figure 2 The register access circuit 222 is configured to access a physical register in a physical register file (PRF) (not shown) based on a mapping entry of a logical register in a register mapping table (RMT) (not shown) mapped to a source register operand of the decoded instruction 206D to retrieve a generated value from the executed instruction 206E in the execution circuit 214. The register access circuit 222 is also configured to provide the generated value retrieved from the executed instruction 206E as a source register operand of the decoded instruction 206D to be executed.

[0030] In addition, in the instruction processing circuit 204, the scheduler circuit ( Figure 2 The title is "SCHED.CIRCUIT" 224 in the instruction pipeline I0 to I N 206D in a reserved entry until all source register operands for the decoded instruction 206D are available. The scheduler circuit 224 issues the decoded instruction 206D ready for execution to the execution circuit 214. Write circuitry 226 is also provided in the instruction processing circuit 204 to write or commit the resulting value from the executed instruction 206E back to a memory (such as a PRF), a cache, or a system memory.

[0031] Continue to refer Figure 2 , the instruction processing circuitry 204 also includes a branch predictor circuit 228. The branch predictor circuit 228 is configured to speculatively predict whether the result of the fetched branch instruction corresponding to the instruction of the taken path or the not-taken path in the instruction control flow path is fetched into the instruction pipelines I0 to I1. N For execution. For example, the fetched branch instruction may be a branch instruction 230 that includes a condition to be parsed by the instruction processing circuitry 204 to determine which instruction control flow path should be taken. In this way, in this example, the result of the branch instruction 230 does not have to be parsed in execution by the execution circuitry 214 before the instruction processing circuitry 204 can proceed to process the fetched instruction 206F. The prediction made by the branch predictor circuitry 228 may be provided to the fetch circuitry 210 as a branch prediction 232 to be used in determining the next instruction 206 to be fetched as the fetched instruction 206F.

[0032] Branch predictor circuit 228 uses a plurality of branch predictor tables 234(0)-234(T) to generate branch predictions such as branch prediction 232. It will be appreciated that while branch predictor tables 234(0)-234(T) are Figure 2234(0)-234(T) are shown as separate elements from the branch predictor circuit 228, but some aspects may provide that the branch predictor tables 234(0)-234(T) are implemented as integral elements of the branch predictor circuit 228. Each of the branch predictor tables 234(0)-234(T) stores a plurality of branch predictor table entries, such as branch predictor table entries 236(0)-236(C) and branch predictor table entries 238(0)-238(C). The branch predictor table entries 236(0)-236(C) and the branch predictor table entries 238(0)-238(C) are indexable entries (e.g., indexed by a hash of a program counter of a branch instruction, a branch history, and / or a path history) that include saturated counters, each of which represents a branch prediction as a signed value. The branch predictor circuit 228 is configured to speculatively predict an outcome of a branch instruction, such as the branch instruction 230, by retrieving a counter (e.g., as a non-limiting example, branch predictor table entries 236(0) and 238(0)) from each of a plurality of branch predictor tables in the branch predictor tables 234(0)-234(T), by optionally scaling each branch predictor table entry 236(0), 238(0) by a table specific scaling factor (not shown), and by then summing the retrieved branch predictor table entries 236(0), 238(0) using an adder circuit (not shown). The sign of the sum of the branch predictor table entries 236(0), 238(0) then indicates the branch prediction 232.

[0033] To facilitate branch prediction by branch predictor circuit 228, Figure 2 The branch predictor tables 234(0) to 234(T) in the example are associated with corresponding history registers 240(0) to 240(T). History registers 240(0) to 240(T) are used to capture previously observed program behavior relative to previously encountered branches, such as global branch history, path history, etc. Then, when making branch predictions, the branch predictor circuit 228 can correlate branch behavior with the contents of history registers 240(0) to 240(T). In some aspects, each of the branch predictor tables 234(0) to 234(T) can be associated with a corresponding history register 240(0) to 240(T) of increased length. Therefore, in this aspect, different history registers in the history registers 240(0) to 240(T) can have different sizes.

[0034] Instructions 206 may include a "loop," which, as used herein, refers to a sequence of instructions 206 that are repeatedly processed sequentially in a back-to-back manner.N When an instruction 206 is processed in one of the instruction pipelines 10 to 11, an instruction 206 that is part of a loop may be detected. N The loop buffer circuit 242 is configured to detect loops among the instructions 206, to capture (i.e., loop buffer) the instructions 206 in the detected loops, and to insert (i.e., replay) the captured loop instructions 206 into the instruction pipelines I0 to I1. N In this way, loop buffer circuit 242 enables instruction processing circuitry to avoid or reduce the need to re-fetch instruction 206 in a detected loop.

[0035] The loop buffer circuit 242 in the instruction processing circuit 204 of the processor 202 includes a loop detection circuit 244 and a loop replay circuit 246. The loop detection circuit 244 is configured to detect a loop among the instructions 206 to be executed. In this regard, in this example, the loop detection circuit 244 is communicatively coupled to the instruction pipelines I0 to I1. N The output of the decoding circuit 218 in the decoder 218 is used to receive the decoded instruction 206D. The loop detection circuit 244 is configured to receive the decoded instruction 206D and analyze the decoded instruction 206D to determine whether there are any loops in the decoded instruction 206D. If the loop detection circuit 244 detects a loop in the decoded instruction 206D, the loop detection circuit 244 may provide the instructions 206D in the detected loop to the loop replay circuit 246, or may store the decoded instruction 206D captured in the detected loop in a memory structure, such as a loop capture memory 248 (e.g., accessible by the loop replay circuit 246). The loop replay circuit 246 is configured to predict the instructions that will be executed in the instruction pipeline I0 to I1. N The detected loop is configured to predict a number of complete iterations of the detected loop that have been executed in the instruction pipeline 10 to 10 as a loop iteration prediction (not shown), and is configured to predict a loop exit branch of the decoded instruction 206D of the detected loop as a loop exit branch prediction (not shown), which loop exit branch will cause the detected loop to be executed in the instruction pipeline 10 to 10 N The loop replay circuit 246 is then configured to completely replay the instruction pipelines I0 to I1 for the number of complete iterations indicated by the loop iteration prediction. N Detected loops in .

[0036] However, as mentioned above, the use of loop buffer circuit 242 may cause problems with respect to updates to the branch predictor (i.e., history registers 240(0)-240(T) and / or branch predictor table entries 236(0)-236(C), branch predictor table entries 238(0)-238(C)) used by branch predictor circuit 228 for branch instructions within a loop replayed from loop buffer circuit 242. Thus, in this regard, Figure 2 The branch predictor update circuit 250 is configured to selectively update the branch predictor for the loop executed from the loop buffer. When a loop including a plurality of loop instructions stored in the loop buffer circuit 242 is detected, the branch predictor update circuit 250 determines to update the history register (e.g., Figure 2 If the count of potential history register updates does not exceed the size of history register 240(0), branch predictor update circuitry 250 is configured to update the branch predictor (i.e., history register 240(0) and / or history registers such as 240(0)) based on a plurality of loop instructions. Figure 2 If the branch predictor update circuitry 250 determines that the count of potential history register updates exceeds the size of the history register 240(0), then in some aspects the branch predictor update circuitry 250 may initiate execution of the loop from the loop buffer circuitry 242 without updating the branch predictor for the loop. In this way, program behavior for shorter run loops may be used to update the branch predictor, while program history stored by the branch predictor may be preserved when longer run loops are encountered.

[0037] To illustrate Figure 2 Exemplary components of the branch predictor update circuit 250 and the Figure 2 The operations performed by the branch predictor update circuit 250 provide Figure 3 .like Figure 3 As shown in FIG. 1 , an instruction stream 300 including a plurality of instructions 302 ( 0 ) to 302 (X) is executed (eg, by Figure 2 The plurality of instructions include instructions 302(L) to 302(L′) (also referred to herein as “loop instructions 302(L) to 302(L′)”), which include a branch instruction 302(B) (also referred to herein as “branch instruction 302(B)”) and together they constitute a loop 304. Figure 3 It also shows Figure 2 The branch predictor update circuit 250, Figure 2 The branch predictor table 234 (0) (which includes Figure 2The branch predictor table entry for Figure 3 (hereinafter referred to as "Counter") 236(0) to 236(C)), and Figure 2 The corresponding history register 240(0) (which includes multiple bits 306(0) to 306(H)).

[0038] exist Figure 3 In the example of Figure 3 Upon determining that loop 304 is stored in loop buffer circuit 242, branch predictor update circuit 250 determines a count 308 of potential history register updates to history register 240(0) for a plurality of loop instructions 302(L) through 302(L′). In some aspects, branch predictor update circuit 250 determines a count 308 of potential history register updates to history register 240(0) by first determining a prediction count 310 of a loop iteration of loop 304 (e.g., by referring to loop buffer circuit 242). Figure 2 The branch predictor update circuit 250 may determine a count 308 of potential history register updates. The branch predictor update circuit 250 may also determine a count 312 of branch instructions (i.e., branch instruction 302 (B)) within the plurality of loop instructions 302 (L) to 302 (L'). In addition, the branch predictor update circuit 250 may also determine a count 314 of bits 306 (0) to 306 (H) of the history register 240 (0), which is updated for each execution of the branch instruction 302 (B). The branch predictor update circuit 250 may then calculate the count 308 of potential history register updates as the product of the predicted count 310 of the loop iteration, the count 312 of branch instructions 302 (B) within the plurality of loop instructions 302 (L) to 302 (L'), and the count 314 of bits 306 (0) to 306 (H) of the history register 240 (0) that is updated for each execution of the branch instruction 302 (B). Thus, if it is predicted that there are 32 loop iterations, a single branch instruction 302(B), and one (1) bit in bits 306(0) through 306(H) of history register 240(0) is updated for each iteration of branch instruction 302(B), then the count 308 of potential history updates is calculated as 32 x 1 x 1, or 32.

[0039] The branch predictor update circuit 250 then determines whether the count 308 of potential history register updates exceeds the size of the history register 240 ( 0 ) (ie, Figure 3 If not exceeded, the branch predictor update circuit 250 updates the branch predictor of the branch predictor circuit 228 based on the plurality of loop instructions 302 (L) to 302 (L'). Figure 3 In some aspects of , the branch predictor may include a history register 240(0) associated with the branch predictor table 234(0). In such aspects, the branch predictor update circuitry 250 may update the branch predictor by updating the history register 240(0) based on a branch instruction 302(B) within a plurality of loop instructions 302(L) through 302(L'). Because each update to the history register 240(0) by a branch instruction 302(B) for each iteration of the loop 304 is the same, and a count 308 of potential history updates is pre-computed, some aspects of the branch predictor update circuitry 250 may "fast forward" updates to the history register 240(0) by performing all updates to the history register 240(0) prior to initiating execution of the loop 304 from the loop buffer circuitry 242. Based on Figure 3 Some aspects of the present invention may provide that the branch predictor is a branch predictor table entry (such as branch predictor table entry 236(0)). Thus, according to such aspects, branch predictor update circuitry 250 may update the branch predictor by updating branch predictor table entry 236(0) based on branch instructions 302(B) within the plurality of loop instructions 302(L) to 302(L').

[0040] In some aspects (such as Figure 2 ), branch predictor table 234(0) is one of a plurality of branch predictor tables 234(0) to 234(T), and history register 240(0) is one of a plurality of corresponding history registers 240(0) to 240(T) having increasing history lengths (i.e., number of bits). In such aspects, it may be desirable to update the branch predictor table only for history registers associated with lengths greater than history register size threshold 316, while avoiding table updates of the branch predictor for branch predictors associated with shorter history registers. Therefore, before updating the branch predictor, branch predictor update circuitry 250 may also determine whether the size of history register 240(0) exceeds history register size threshold 316. If not, the branch predictor (e.g., history register 240(0) or branch predictor table entry 236(0) as non-limiting examples) is updated as described above.

[0041] Some aspects may provide that the branch predictor update circuitry 250 performs updates to the branch predictor only for a subset of the potential historical register updates that will be performed during a loop iteration. In such aspects, the branch predictor update circuitry 250 determines a count 308 of potential historical register updates and also determines whether the count 308 of potential historical register updates exceeds an update count threshold 318. If so, the branch predictor update circuitry is configured to update the branch predictor of the branch predictor circuitry 228 only for the subset of potential historical register updates. The update count threshold 318 may be determined based on, for example, the number of historical register updates performed per loop iteration and the length of the history register 240(0).

[0042] In some such aspects, a subset of potential historical register updates may be represented by the equation x+log 10 n-log 10 x is determined, where x is a non-zero integer representing the update count threshold 318, and n is a non-zero integer representing the count 308 of potential historical register updates. These aspects enable the branch predictor update circuit 250 to capture all branch predictor updates resulting from branches replayed from the loop buffer for the first few iterations of the loop 304, while also preserving the history captured before the loop 304 and capturing approximately how long the loop 304 iterations have been. Some such aspects may provide other mechanisms for determining the size of the subset of potential historical register updates, such as dividing the count 308 of potential historical register updates by a constant, or determining the size of the subset of potential historical register updates by applying other logarithmic or exponential functions.

[0043] In order to illustrate some aspects of Figure 2 and Figure 3 Exemplary operations performed by the branch predictor update circuit 250 are as follows: Figure 4A and Figure 4B A flow chart 400 is provided. For clarity, in describing Figure 4A and Figure 4B Time reference Figure 2 and Figure 3 It is important to understand that Figure 4A and Figure 4B Some of the operations shown in the drawings may be performed in an order other than that shown herein, and / or may be omitted in some aspects. Figure 4A The operation in starts with the branch predictor updating circuits (such as Figure 2 and Figure 3 The branch predictor update circuit 250 of FIG. 250 is used to detect loops (e.g., Figure 3 A loop 304), the loop including multiple loop instructions among multiple instructions in the instruction stream (e.g., Figure 3The branch predictor update circuit 250 determines that the loop 304 is stored in a loop buffer circuit (such as a loop buffer circuit). Figure 3 The loop buffer circuit 242 of the loop buffer circuit 242 is then (block 404). The branch predictor update circuit 250 then determines the history registers (eg, Figure 2 and Figure 3 A count of potential history register updates (e.g., Figure 3 Count 308) (block 406). Figure 5 Example operations of block 406 for determining the count 308 of potential historical register updates in accordance with some aspects are discussed in greater detail.

[0044] In some aspects, branch predictor update circuitry 250 may determine whether the size of history register 240(0) exceeds a history register size threshold (such as Figure 3 If the size of the history register 240(0) does not exceed the history register size threshold 316 (block 408). If so, operations in this aspect continue at block 412. However, if the branch predictor update circuitry 250 determines at decision block 408 that the size of the history register 240(0) does not exceed the history register size threshold 316, the branch predictor update circuitry 250 initiates execution of the loop 304 from the loop buffer circuitry 242 without updating the branch predictor of the branch predictor circuitry 228 for the loop 304 (e.g., Figure 2 and Figure 3 history register 240(0) or branch predictor table entry 236(0)) (block 410).

[0045] The branch predictor update circuit 250 then determines a count of potential historical register updates (eg, Figure 3 The count 308 of potential history register updates exceeds the size of history register 240(0) (block 412). If it is determined at decision block 412 that the count 308 of potential history register updates exceeds the size of history register 240(0), then operation continues at block 410. Otherwise, operation continues at block 420. Figure 4B Continue at block 414 of .

[0046] Reference now Figure 4B If the branch predictor update circuitry 250 determines at decision block 412 that the count 308 of potential history register updates does not exceed the size of the history register 240(0), the branch predictor update circuitry 250 updates the branch predictor circuitry based on the plurality of loop instructions 302(L)-302(L') (e.g., Figure 2The branch predictor circuit 228 of the branch predictor (e.g., Figure 2 and Figure 3 The operation of block 414 for updating the branch predictor may include updating the history register 240(0) or the branch predictor table entry 236(0) of the loop buffer circuit 242 (block 414). In aspects where the branch predictor is a history register, such as the history register 240(0), the operation of block 414 for updating the branch predictor may include updating the history register 240(0) based on one or more branch instructions 302(B) within the plurality of loop instructions 302(L) through 302(L') (block 416). Some such aspects may provide that the operation of block 416 for updating the history register 240(0) may include performing all updates to the history register 240(0) prior to initiating execution of the loop 304 from the loop buffer circuit 242 (block 418). In aspects where the branch predictor is a branch predictor table entry (such as branch predictor table entry 236(0)), the operation of box 414 for updating the branch predictor may include updating a branch predictor table entry 236(0) among a plurality of branch predictor table entries 236(0) through 236(C) of a branch predictor table 234(0) of the branch predictor circuit 228 based on one or more branch instructions 302(B) within a plurality of loop instructions 302(L) through 302(L') (box 420).

[0047] Figure 5 A more detailed illustration of the method for determining the count 308 of potential historical register updates is provided in accordance with some aspects. Figure 4A 500 of exemplary operations of block 406 of FIG. Figure 5 Time reference Figure 2 and Figure 3 Components. Figure 5 , the operation begins with the branch predictor update circuit 250 determining the prediction count of the loop iteration of loop 304 (e.g., Figure 3 The branch predictor update circuit 250 also determines the count of one or more branch instructions 302 (B) within the plurality of loop instructions 302 (L) to 302 (L') (eg, Figure 3 The branch predictor update circuit 250 also determines the count of bits 306(0) through 306(H) of the history register 240(0) that are updated for each of the one or more branch instructions 302(B) (e.g., Figure 3Finally, the branch predictor update circuitry 250 determines the count 308 of potential history register updates as the product of the predicted count 310 of loop iterations, the count 312 of one or more branch instructions 302(B) within the plurality of loop instructions 302(L)-302(L'), and the count 314 of bits 306(0)-306(H) of the history register 240(0) updated for each of the one or more branch instructions 302(B) (block 508).

[0048] Some aspects may provide that, prior to performing the operations of block 414 for updating the branch predictor, the branch predictor update circuit 250 applies additional logic in determining how much updates should be made to the branch predictor. In this regard, Figure 6 Flowchart 600 is provided to illustrate exemplary operations performed by branch predictor update circuit 250. Figure 6 Time reference Figure 2 and Figure 3 components. Figure 6 The operations in begin with the branch predictor update circuit 250, whereby after determining a count of potential historical register updates (e.g., Figure 3 After that, it is determined whether the count 308 of potential historical register updates exceeds an update count threshold (eg, Figure 3 If the update count threshold 318 of the potential historical register updates is exceeded, the branch predictor update circuitry 250 updates the branch predictor 240(0), the branch predictor 236(0) of the branch predictor circuitry 228 (block 604). However, if the branch predictor update circuitry 250 determines at decision block 602 that the count 308 of potential historical register updates does not exceed the update count threshold 318, the branch predictor update circuitry 250 updates the branch predictor 240(0), the branch predictor 236(0) for each of the potential historical register updates (block 606).

[0049] Figure 7 is a block diagram of an exemplary processor-based system 700 including a processor 702 (eg, a microprocessor) including instruction processing circuitry 704 including instructions corresponding in functionality to Figure 2 The branch predictor update circuit 250 of the branch predictor update circuit ( Figure 7 As an example, the instruction processing circuit 704 may be Figure 2 As an example, the processor-based system 700 may be Figure 2200 in the processor-based system. The processor-based system 700 may be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

[0050] In this example, the processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc. The processor 702 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor 702 includes an instruction cache 708, which is a temporary fast access memory storage device for instructions accessible by the instruction processing circuit 704. Instructions fetched or pre-fetched from a memory (such as from a system memory 710 via a system bus 712) are stored in the instruction cache 708. The instruction processing circuit 704 is configured to process the instructions fetched into the instruction cache 708 and process the instructions for execution.

[0051] The processor 702 and the system memory 710 are coupled to a system bus 712 and may be coupled to peripheral devices included in the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information on the system bus 712. For example, the processor 702 may communicate a bus transaction request to a memory controller 714 in the system memory 710 as an example of a slave device. Although not shown in FIG. Figure 7 710, but multiple system buses 712 may be provided, each of which constitutes a different structure. In this example, a memory controller 714 is configured to provide memory access requests to a memory array 716 in the system memory 710. The memory array 716 includes an array of storage bit cells for storing data. As non-limiting examples, the system memory 710 may be a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0052] Other devices may be connected to the system bus 712. Figure 7, as shown in , these devices may include system memory 710, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. (Multiple) input device 718 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. (Multiple) output device 720 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 722 may be any device configured to allow data to be exchanged to and from network 726. Network 726 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LAN), wireless local area networks (WLAN), wide area networks (WAN), BLUETOOTH TM The modem 722 may be configured to support any type of communication protocol as desired. The processor 702 may also be configured to access (multiple) display controllers 724 via the system bus 712 to control information sent to one or more displays 728. (Multiple) displays 728 may include any type of display, including but not limited to cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, etc.

[0053] Figure 7 The processor-based system 700 in FIG. 7 may include a set of instructions 730 to be executed by the processor 702 according to the instructions for any desired application. The instructions 730 may be stored in the system memory 710, the processor 702, and / or the instruction cache 708 as examples of non-transitory computer-readable media 732. The instructions 730 may also reside completely or at least partially within the system memory 710 and / or within the processor 702 during its execution. The instructions 730 may also be sent or received over the network 726 via the modem 722, so that the network 726 includes the computer-readable medium 732.

[0054] Although the computer-readable medium 732 is shown as a single medium in the exemplary embodiment, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store a set of one or more instructions. The term "computer-readable medium" should also be understood to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and cause the processing device to perform any one or more of the methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0055] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components, or may be embodied in machine executable instructions, which may be used to cause a general or special purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0056] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. The machine-readable medium includes any mechanism for storing or sending information in a form readable by a machine (e.g., a computer). For example, the machine-readable medium includes: a machine-readable storage medium (e.g., a ROM, a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.), etc.

[0057] Unless otherwise specifically stated, and as is apparent from the foregoing discussion, it should be understood that throughout the description, discussions utilizing terms such as "processing," "computing," "determining," "displaying," etc. refer to the actions and processes of a computer system, or similar electronic computing device, that manipulate data represented as physical (electronic) quantities within the computer system's registers and memory, and transform that data and memory into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage, transmission, or display devices.

[0058] The algorithms and displays presented herein are not inherently related to any particular computer or other device. According to the description herein, various systems can be used together with the program, or it can be proved that it is convenient to construct a more specialized device to perform the required method steps. The required structure for the various systems in the execution system will emerge from the above description. In addition, the embodiments described herein are described without reference to any specific programming language. It will be understood that various programming languages ​​can be used to implement the description of the embodiments as described herein.

[0059] Those skilled in the art will also understand that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the components of the distributed antenna system described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information required. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functions. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present embodiment.

[0060] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the controller may be a processor. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0061] The embodiments disclosed herein may be embodied in hardware and in instructions stored in hardware, and may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and the storage medium may reside in a remote station, a base station, or a server as discrete components.

[0062] It should also be noted that the operational steps described in any exemplary embodiment of the exemplary embodiments herein are described to provide examples and discussions. The described operations can be performed in many different orders in addition to the order shown. In addition, the operations described in a single operational step can actually be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that any of a variety of technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0063] Unless explicitly stated otherwise, it is not intended that any method described herein be construed as requiring that the steps of the method be performed in a specific order. Therefore, in the absence of a method claim actually reciting the order in which its steps are to be followed, or in the absence of other specific statements in the claims or description that the steps are limited to a specific order, it is not intended that any specific order be inferred.

[0064] It is obvious to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since those skilled in the art can think of modifications, combinations, sub-combinations and variations of the disclosed embodiments that incorporate the spirit and essence of the present invention, the present invention should be interpreted as including all within the scope of the attached claims and their equivalents.

Claims

1. A processor, comprising: an instruction processing circuit configured to process an instruction stream including a plurality of instructions in an instruction pipeline; a branch predictor circuit, the branch predictor circuit comprising a history register; A branch predictor update circuit, wherein the branch predictor update circuit is configured to: detecting a loop, the loop comprising a plurality of loop instructions among the plurality of instructions in the instruction stream; determining that the loop is stored in a loop buffer circuit of the processor; determining a count of potential history register updates to the history register for the plurality of loop instructions; determining whether the count of potential history register updates exceeds the size of the history register; as well as In response to determining that the count of potential history register updates does not exceed the size of the history register, updating a branch predictor of the branch predictor circuitry based on the plurality of loop instructions.

2. The processor of claim 1 , wherein the branch predictor update circuit is configured to determine the count of potential historical register updates by being configured to: determining a predicted count of loop iterations of the loop; determining a count of one or more branch instructions within the plurality of loop instructions; determining a count of bits of the history register that are updated for each of the one or more branch instructions; as well as The count of potential history register updates is determined as a product of a predicted count of the loop iterations, the count of the one or more branch instructions within the plurality of loop instructions, and a count of the bits of the history register updated for each of the one or more branch instructions.

3. The processor of claim 1 , wherein: The branch predictor includes the history register; and The branch predictor update circuit is configured to update the branch predictor by being configured to update the history register based on one or more branch instructions within the plurality of loop instructions.

4. The processor of claim 3 , wherein the branch predictor update circuit is configured to update the history register based on the one or more branch instructions within the plurality of loop instructions by being configured to perform all updates to the history register prior to initiating execution of the loop from the loop buffer circuit.

5. The processor of claim 1 , wherein: The branch predictor comprises a branch predictor table entry of a plurality of branch predictor table entries of a branch predictor table of the branch predictor circuit; and The branch predictor update circuit is configured to update the branch predictor by being configured to update the branch predictor table entry based on one or more branch instructions within the plurality of loop instructions.

6. The processor of claim 1, wherein: The branch predictor circuit includes a plurality of branch prediction tables and a corresponding plurality of history registers including the history register; The branch predictor update circuit is further configured to determine whether the size of the history register exceeds a history register size threshold; as well as Further in response to determining that the size of the history register exceeds the history register size threshold, the branch predictor update circuitry is configured to update the branch predictor of the branch predictor circuitry based on the plurality of loop instructions.

7. The processor of claim 1, wherein: The branch predictor update circuitry is further configured to determine whether the count of potential historical register updates exceeds an update count threshold; and Further in response to determining that the count of potential historical register updates exceeds the update count threshold, the branch predictor update circuit is configured to update the branch predictor of the branch predictor circuit based on the plurality of loop instructions by being configured to update the branch predictor of the branch predictor circuit only for a subset of the potential historical register updates.

8. The processor of claim 7, wherein the size of the subset of the potential history register updates is given by the equation x+log 10 n-log 10 x, where x is a non-zero integer representing the update count threshold and n is a non-zero integer representing a count of potential history register updates.

9. The processor of claim 1 , wherein the branch predictor update circuit is further configured to, in response to determining that the count of potential history register updates exceeds the size of the history register, initiate execution of the loop from the loop buffer circuit without updating the branch predictor of the branch predictor circuit for the loop.

10. A method comprising: detecting a loop, the loop comprising a plurality of loop instructions among a plurality of instructions in an instruction stream; determining that the loop is stored in a loop buffer circuit; determining a count of potential history register updates to a history register for the plurality of loop instructions; determining whether the count of potential history register updates exceeds the size of the history register; as well as In response to determining that the count of potential history register updates does not exceed the size of the history register, updating a branch predictor of a branch predictor circuit based on the plurality of loop instructions.

11. The method according to claim 10, wherein: The branch predictor includes the history register; and Updating the branch predictor includes updating the history register based on one or more branch instructions within the plurality of loop instructions.

12. The method of claim 11 , wherein updating the history register based on the one or more branch instructions within the plurality of loop instructions comprises: All updates to the history register are performed prior to initiating execution of the loop from the loop buffer circuit.

13. The method of claim 10, wherein updating the branch predictor comprises: A branch predictor table entry of a plurality of branch predictor table entries of a branch predictor table of the branch predictor circuit is updated based on one or more branch instructions within the plurality of loop instructions.

14. The method of claim 10, further comprising determining whether the size of the history register exceeds a history register size threshold; Wherein the branch predictor updating the branch predictor circuitry based on the plurality of loop instructions is further responsive to determining that the size of the history register exceeds the history register size threshold.

15. The method according to claim 10, further comprising: determining that a count of the potential history register updates exceeds an update count threshold; Wherein further in response to determining that the count of the potential historical register updates exceeds the update count threshold, updating the branch predictor of the branch predictor circuitry based on the plurality of loop instructions comprises updating the branch predictor of the branch predictor circuitry for only a subset of the potential historical register updates.

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