Dry etching method for single-crystal silicon wafer, method for manufacturing single-crystal silicon wafer, and single-crystal silicon wafer

Abstract

Provided is a dry etching method for forming a rough surface on a single crystal silicon wafer, the dry etching method including: using a single crystal silicon wafer having a natural oxide film (SiO2) on the surface thereof as a single crystal silicon wafer; and a step for performing a dry etching treatment on the surface of the silicon single crystal wafer on which the natural oxide film is present using a gas containing at least fluorine, and in the dry etching treatment, the etching selection ratio of Si to SiO2 as calculated from (etching rate of Si / etching rate of SiO2) is 18 or more, the etching amount of SiO2 is 2.5 nm or more, and the etching rate of SiO2 is 2.5 nm or more. Therefore, a rough surface is formed on the monocrystalline silicon wafer. As a result, provided are: a dry etching method for a silicon wafer, which is capable of forming a rough surface on the silicon wafer; and a method for manufacturing a silicon wafer, which is capable of forming a rough surface only on one surface of the silicon wafer.

Description

Technical Field

[0001] The present invention relates to a dry etching method for a silicon wafer capable of forming a rough surface on a semiconductor silicon wafer, and a method for manufacturing a silicon wafer having a rough surface formed only on one side of the silicon wafer. Background Art

[0002] The manufacturing process of silicon wafers for semiconductor devices consists of a single crystal manufacturing process of growing a single crystal rod using the Czochralski method (CZ method) and a wafer processing process of slicing the single crystal rod and processing it into a mirror-like shape. Furthermore, in order to provide added value, it sometimes includes a tempering process for heat treatment or an epitaxial growth process for forming an epitaxial layer.

[0003] In the process of processing into a mirror-like shape, in order to obtain a wafer with high flatness, a DSP (double-sided grinding) process is currently adopted in which both sides are ground into a mirror-like shape, and a CMP (single-sided grinding) process is performed afterwards. In these grinding processes, from the perspective of particle quality, the wafer is sometimes transported while being stored in a water slot or the like. Furthermore, in the CMP process, it is necessary to use a robot or the like to clamp the wafer stored in the water and transport it to the CMP device. In addition, after CMP grinding, it is also necessary to clamp the wafer wetted by an abrasive or pure water, and transport it to the washing process as needed.

[0004] In this way, in the wafer processing process, the wafer needs to be transported in a wet environment rather than a dry environment. However, especially in such a wet environment, when the wafer adsorbed by the clamp is released, since the wafer is double-sided polished and has a high flatness, it cannot be released even if the clamp is released, which will cause poor transportation. The reason is believed to be affected by the roughness of the wafer surface to be clamped. It is believed that if the roughness of the wafer surface to be clamped is too good, the contact area with the clamp will increase, and even if the clamp is released, the wafer will still not be easy to release. In contrast, it is believed that if the surface roughness of the wafer is poor, the contact area will be reduced and the wafer will be easy to release.

[0005] Generally speaking, the clamped surface is very likely to form clamp marks, which reduces the quality, so the clamped surface is mostly the back side of the silicon wafer. Therefore, from the perspective of reducing transportation defects, a method for manufacturing a wafer in which only the back side of the silicon wafer is roughened is particularly sought.

[0006] Generally speaking, it is known that etching that dissolves Si or SiO2 will affect the surface roughness of silicon wafers. For example, if Si is immersed in an aqueous solution of NaOH or KOH, which is a strong base, the surface roughness will be like Si+2H2O+2OH - →SiO2(OH)2 2-+2H2, Si reacts with water and hydroxyl groups, thereby dissolving in the form of hydroxide, thereby etching Si. Furthermore, it is known that the surface roughness deteriorates due to the anisotropy of Si as the etching progresses.

[0007] Here, the etching methods include: a wet method using a chemical solution and a dry method using a plasma-enhanced gas. With the miniaturization of semiconductor devices, the dry method has become the mainstream in the manufacturing process of semiconductor devices rather than the wet method. Dry etching is a method of activating the gas supplied to the reaction container by plasma discharge, causing it to react with Si on the surface of the wafer, thereby initiating an etching reaction. As a representative gas, a gas containing fluorine (F) or chlorine (Cl) can be used. For example, if CF4 is considered as a fluorocarbon gas, the F activated by plasma discharge reacts with Si to form volatile SiF4, and Si is etched.

[0008] Such dry etching technology is often used to form pattern elements in the manufacturing process of semiconductor devices. Compared with wet etching, dry etching has higher controllability and reproducibility.

[0009] Patent Document 1 discloses a technique for etching polycrystalline or amorphous Si with high selectivity to silicon compounds by using plasma etching with a gas composed of 0.1 to 20% by volume of a halogen compound, water or a hydroxyl compound, and the remainder being oxygen. However, this is not a technique for etching single crystal silicon.

[0010] Patent Document 2 discloses a method for selectively etching silicon-based materials by adjusting the fluorine-based active species to be acted on according to the silicon-based material to be etched. In particular, a method for using only fluorine-based active species without adding water vapor when single crystal Si is disclosed, but there is no description of the specific etching selectivity or etching rate.

[0011] Non-patent document 1 discloses a Si etching technique using a gas mixed with CF4 and O2. Specifically, it is described that the Si etching rate is changed by adding O2 to CF4.

[0012] On the other hand, dry etching technology is sometimes used in the wafer manufacturing process. Patent document 3 discloses a technology that performs dry etching on the entire surface of a raw wafer that has a processing deformation layer after grinding to remove the processing deformation layer, and then manufactures a silicon wafer by double-sided grinding. In this way, dry etching in the wafer manufacturing process is mainly used to remove the processing deformation layer.

[0013] Prior art literature

[0014] Patent Literature

[0015] Patent Document 1: Japanese Patent Application Publication No. 2004-356557.

[0016] Patent document 2: Japanese Patent Application Publication No. 2000-164559.

[0017] Patent document 3: Japanese Patent No. 7028353.

[0018] (Non-patent literature)

[0019] Non-patent document 1: Dry etching technology for manufacturing LSI (Metal Surface Technology 30 (5), 256-268, 1979) Summary of the invention

[0020] 1. Technical issues to be resolved

[0021] As described above, in order to reduce handling defects in the processing steps, a silicon wafer whose back side to be gripped is rough is required.

[0022] The present invention is made to solve the above-mentioned problems, and its object is to provide a dry etching method of a silicon wafer capable of forming a rough surface on the silicon wafer and a manufacturing method of a silicon wafer in which a rough surface is formed only on one side of the silicon wafer.

[0023] (II) Technical solution

[0024] In order to solve the above technical problems, the present invention provides a dry etching method for a single crystal silicon wafer, which forms a rough surface on the single crystal silicon wafer.

[0025] The dry etching method comprises the steps of using a single crystal silicon wafer having a natural oxide film (SiO2) on its surface as the single crystal silicon wafer, and performing dry etching on the surface of the single crystal silicon wafer having the natural oxide film using a gas containing at least fluorine, and

[0026] In the dry etching process, the etching selectivity ratio of Si to SiO2 calculated by (etching rate of Si / etching rate of SiO2) is set to 18 or more, and the etching amount of SiO2 is set to 2.5 nm or more, thereby forming a rough surface on the single crystal silicon wafer.

[0027] Such a dry etching method for a single crystal silicon wafer can form a rough surface by utilizing the effect that Si is preferentially etched.

[0028] In addition, it is preferred that the etching rate of Si is set to a value calculated using a single crystal silicon wafer, and the etching rate of SiO 2 is set to a value calculated using a single crystal silicon wafer with a thermal oxide film.

[0029] As long as such a method is used, the etching behavior of SiO2 and Si can be evaluated with good precision. In particular, when confirming the dry etching rate of Si, polycrystalline is generally used, but from the perspective of evaluating with higher precision, it is preferred to use a single crystal silicon wafer.

[0030] Furthermore, in the dry etching process, it is preferable that the etching amount of Si is set to 200 nm or less.

[0031] By controlling the etching amount in this manner, a rough surface can be appropriately formed.

[0032] Furthermore, it is preferable that a fluorocarbon-based gas is used as the fluorine-containing gas in the dry etching process.

[0033] Thus, by using the fluorocarbon-based gas, a rough surface can be appropriately formed.

[0034] Furthermore, it is preferred that CF 4 be used as the fluorocarbon-based gas in the dry etching process.

[0035] In this way, by using CF4 gas, a rough surface can be appropriately formed.

[0036] Furthermore, it is preferred that, in the dry etching process, oxygen is added to the fluorine-containing gas, thereby adjusting the etching selectivity ratio of Si to SiO 2 , the etching rate of Si, and the etching rate of SiO 2 .

[0037] By adding O2 in this way, the etching selectivity or etching rate can be easily controlled.

[0038] Furthermore, it is preferable that the natural oxide film is formed by SC1 cleaning, SC2 cleaning, or O3 cleaning.

[0039] Such a method can form a natural oxide film uniformly.

[0040] In addition, the present invention provides a method for manufacturing a single crystal silicon wafer, which comprises the following steps:

[0041] Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface;

[0042] Step (2): using a single-wafer dry etching device to perform dry etching on one side of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method of the single crystal silicon wafer described above; and

[0043] Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing of the surface opposite to the single surface on which the rough surface is formed, thereby obtaining a single crystal silicon wafer having a rough surface formed only on one surface.

[0044] With such a manufacturing method, dry etching can be performed in a single-wafer manner, and a wafer having a rough surface formed only on one side can be manufactured, and conveyance defects can be reduced.

[0045] In addition, the present invention provides a method for manufacturing a single crystal silicon wafer, which comprises the following steps:

[0046] Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface;

[0047] Step (2): using a batch type dry etching device to perform dry etching on both sides of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method of the single crystal silicon wafer described above; and

[0048] Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing to obtain a single crystal silicon wafer having a rough surface formed only on one side.

[0049] With such a manufacturing method, dry etching can be performed in a batch system, wafers having a rough surface formed only on one side can be manufactured, and conveyance defects can be reduced.

[0050] In addition, the present invention provides a single crystal silicon wafer,

[0051] Taking the three-dimensional arithmetic mean height Sa as an indicator, Sa on the surface side is 0.2 nm or less, and Sa on the back side is 0.5 nm or more.

[0052] Such single crystal silicon wafers can reduce conveyance defects.

[0053] In addition, the present invention provides a single crystal silicon wafer,

[0054] The three-dimensional arithmetic mean height Sa is used as an index, and (Sa on the back side / Sa on the front side) is 5 or more.

[0055] Such single crystal silicon wafers can reduce conveyance defects.

[0056] (III) Beneficial effects

[0057] As long as it is the dry etching method of the single crystal silicon wafer of the present invention, a rough surface can be formed on the single crystal silicon wafer. In addition, as long as it is the manufacturing method of the single crystal silicon wafer of the present invention, a single crystal silicon wafer with high flatness formed on only one side with a rough surface can be manufactured. In addition, the silicon wafer of the present invention can reduce the handling defects in the processing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 1 is a flow chart showing an example of a dry etching method for a single crystal silicon wafer according to the present invention.

[0059] Figure 2 This is a flow chart showing an example of a method for manufacturing a single crystal silicon wafer according to the present invention.

[0060] Figure 3 This is a graph showing the haze after dry etching of a single crystal silicon wafer having a natural oxide film by adding O 2 to CF 4 at various concentrations.

[0061] Figure 4 It is a graph showing the etching rates of single crystal Si and thermal oxide film SiO2 under various dry etching processing conditions.

[0062] Figure 5 It is a graph showing the etching selectivity ratio of Si to SiO2 under various dry etching processing conditions.

[0063] Figure 6 This is a graph showing the dependency of the haze value on the etching treatment time under various dry etching treatment conditions.

[0064] Figure 7 It is a graph showing the etching amount of SiO2 with respect to the processing time under various dry etching processing conditions.

[0065] Figure 8 This is a graph showing the three-dimensional arithmetic mean height Sa of the rough surface side of a single crystal silicon wafer having a rough surface formed thereon, measured by AFM, under various dry etching processing conditions and processing time.

[0066] Fig. 9 Schematic diagram showing an example of a single crystal silicon wafer of the present invention. DETAILED DESCRIPTION

[0067] As described above, it is sought to develop a dry etching method for a silicon wafer capable of forming a rough surface on the silicon wafer and a method for manufacturing a silicon wafer in which a rough surface is formed only on one side of the silicon wafer.

[0068] In order to solve the above technical problems, the inventors of the present application have conducted in-depth research on whether it is possible to induce etching on the surface of the wafer to form a rough surface by using dry etching, which has higher controllability and reproducibility than wet etching, on a single crystal silicon wafer, and performing dry etching with a fluorine-containing gas. As a result, it was found that, especially for a single crystal silicon wafer with a natural oxide film, if etching is performed under conditions where the etching selectivity ratio of Si to SiO2 is high, Si will be rapidly etched at the position where Si has been exposed during etching, and a rough surface will be formed, and the formation of the rough surface can be controlled by adjusting the etching selectivity ratio and the SiO2 etching amount, thereby completing the present invention.

[0069] That is, the present invention is a dry etching method for forming a rough surface on a single crystal silicon wafer, the dry etching method comprising the steps of using a single crystal silicon wafer having a natural oxide film (SiO2) on the surface as the single crystal silicon wafer, and performing dry etching on the surface of the single crystal silicon wafer having the natural oxide film using a gas containing at least fluorine, and

[0070] In the dry etching process, the etching selectivity ratio of Si to SiO2 calculated by (etching rate of Si / etching rate of SiO2) is set to 18 or more, and the etching amount of SiO2 is set to 2.5 nm or more, thereby forming a rough surface on the single crystal silicon wafer.

[0071] Hereinafter, the present invention will be described in detail with reference to the drawings as an example of an embodiment, but the present invention is not limited thereto.

[0072] In addition, the "surface" in "a single crystal silicon wafer having a natural oxide film on the surface" refers not only to the surface of the so-called surface (front side) / back side of the wafer, but also to a part or all of the part that can be observed from the outside of the wafer. Hereinafter, in this specification, it is appropriately interpreted whether "surface" is used in any of the above meanings or in other meanings according to the context.

[0073] [Dry etching method for single crystal silicon wafer]

[0074] Figure 1 FIG. 2 is a flow chart showing an example of a dry etching method for a single crystal silicon wafer of the present invention. Figure 1 As shown, first prepare a single crystal silicon wafer with a rough surface to be formed. The conductivity type or diameter of the wafer is not limited, but a natural oxide film needs to be formed on the surface of the wafer. The natural oxide film is preferably formed by SC1 cleaning, SC2 cleaning or O3 cleaning.

[0075] like Figure 1As shown, then, the surface of the prepared single crystal silicon wafer with a natural oxide film is subjected to a dry etching process using a gas containing at least fluorine. At this time, the dry etching process can be performed on a portion of the wafer surface (the surface (front) or back of the wafer), or on the entire wafer surface (the entire surface), preferably on the entire wafer surface (the entire surface). In the dry etching process, the etching selectivity of Si relative to SiO2 calculated by (etching rate of Si / etching rate of SiO2) is set to 18 or more, and the etching amount of SiO2 is set to 2.5 nm or more, thereby forming a rough surface on the single crystal silicon wafer. The dry etching process is described in detail below.

[0076] In dry etching, for a single crystal silicon wafer, a fluorine (F)-containing gas is activated by plasma discharge, and the active species of F act on Si to generate volatile SiF4, thereby etching Si (Si+4F→SiF4). As a fluorine-containing gas, CF4, C2F6, C3F8, C4F8 of a fluorocarbon system or SF6, NF3 of an inorganic fluorine system can be used, without particular limitation. As long as it contains fluorine, it can also contain chlorine.

[0077] Here, the formation of a rough surface by dry etching using CF 4 as a fluorine-containing gas is described in detail from the perspective of the presence or absence of a natural oxide film on the wafer surface and the etching behavior of Si and SiO 2 .

[0078] Figure 3 In FIG. 1 , the results of evaluating haze are shown as an example, which is a roughness index obtained by using a particle counter after etching a single crystal silicon wafer having a natural oxide film formed by washing with SC1 using only CF4 or etching a single crystal silicon wafer having a natural oxide film formed by washing with SC1 using O2 added to CF4 at various concentrations. In addition, all etching conditions except the gas ratio are set to normal.

[0079] The larger the haze value, the rougher the surface, that is, it can be judged that a rough surface is formed. If the influence of the O2 ratio is observed, when the O2 ratio is 0-20 volume %, the haze value becomes greater than the standard product that has not been dry-etched, and in particular, it shows a tendency that the smaller the O2 ratio, the greater the roughness. On the other hand, the haze values ​​of the O2 ratios of 50 and 80 volume % are the same as those of the standard product, so no rough surface is formed.

[0080] Furthermore, the same treatment was performed on the wafer whose exposed surface had been cleaned with hydrofluoric acid to remove the native oxide film, but the haze was still at the same level as the standard product. Therefore, it can be seen that the etching conditions and the presence of the native oxide film affect the roughening process.

[0081] As its observation, Figure 4The etching rates of Si and SiO2 are shown. In addition, as a specific method for calculating the etching rate, the etching rate of Si is calculated by etching a single crystal silicon wafer for a specified time, and the wafer thickness before etching is subtracted from the wafer thickness after etching. The etching rate of SiO2 is calculated by etching a single crystal silicon wafer with a thermal oxide film grown by thermal oxidation for a specified time, and the thermal oxide film thickness before etching is subtracted from the thermal oxide film thickness after etching.

[0082] according to Figure 4 The etching rate of Si and SiO2 will increase by mixing a small amount of O2. However, when the O2 ratio is 50% by volume or more, the etching rate tends to decrease. This is probably because the addition of a small amount of O2 will increase the fluorine active species. If excessive addition is added, an oxide film will form on the surface, which will hinder etching.

[0083] Then, in Figure 5 The result of the etching selectivity ratio of Si to SiO2 calculated by (etching rate of Si / etching rate of SiO2) is shown in FIG. The higher the etching selectivity ratio, the more Si is preferentially etched. As can be seen from the graph, the smaller the O2 ratio, the higher the etching selectivity ratio.

[0084] If Figure 3 By comparing the results, it can be seen that when the etching selectivity is above 18, the haze value increases, that is, a rough surface is formed. Therefore, in order to form a rough surface, the etching selectivity must be above 18. There is no particular limit to the upper limit of the etching selectivity, for example, it can be set to below 28. Based on the above results, the roughening mechanism is considered. If the natural oxide film is regarded as SiO2, if SiO2, which is more etch-resistant than Si, is etched, Si will be partially exposed on the surface, and Si will be etched preferentially. In this environment, Si will be rapidly etched. As a result, it is believed that bumps and depressions will be formed on the surface of the wafer, that is, a rough surface will be formed.

[0085] Next, the graph showing the effect of treatment time when the O2 ratio is 0-10% is Figure 6 In addition, Figure 4 The graph of SiO2 etching amount calculated based on SiO2 etching rate at each O2 ratio is as follows: Figure 7 .

[0086] according to Figure 6, the haze values ​​when the O2 ratio was 0% and 2.5% and the treatment time was 30 seconds were the same as the standard, so no rough surface was formed. However, the haze value increased after the treatment time was 60 seconds, so when the O2 ratio was 0% and 2.5%, roughening continued after the treatment time was 60 seconds. Then, when the O2 ratio was 5%, 7.5%, and 10%, the haze value began to increase from the treatment time of 30 seconds, so when the O2 ratio was 5%, 7.5%, and 10%, roughening was carried out when the treatment time was 30 seconds.

[0087] Can be based on Figure 7 The difference is explained by the etching amount of SiO2. It is believed that in order to perform roughening as described above, it is necessary to locally etch the natural oxide film on the outermost surface to expose Si on the surface. When the processing time is 60 seconds, the etching amount of SiO2 with an O2 ratio of 0% and 2.5% formed with a rough surface is 14.1Å and 14.6Å respectively when the processing time is 30 seconds, and 28.3Å and 29.2Å respectively when the processing time is 60 seconds. When the processing time is 30 seconds, the etching amount of SiO2 with an O2 ratio of 5%, 7.5%, and 10% formed with a rough surface is 30.9Å, 44.9Å, and 54.3Å respectively when the processing time is 30 seconds. Therefore, by etching so that the Si / SiO2 selectivity is 18 or more and SiO2 is 25Å (2.5 nm) or more, a rough surface can be formed. The upper limit of the etching amount of SiO2 is not particularly limited, for example, it can be set to 300Å (30 nm) or less.

[0088] Further observation Figure 6 The haze value shows a tendency to gradually decrease after reaching a maximum value at a predetermined processing time. If etching is performed excessively, the roughness of the rough surface formed will decrease, and it is also desirable to shorten the etching time from the perspective of throughput or cost. Figure 6 When the O2 ratio is 0%, 2.5%, 5%, 7.5%, and 10%, the treatment time for the maximum haze value is 120 seconds, 120 seconds, 60 seconds, 30 seconds, and 30 seconds, respectively. Figure 4 The etching amount of Si at this time can be calculated to be 1600Å, 1400Å, 1400Å, 1000Å, 1000Å respectively, so by the Si etching amount being set to below 2000Å (200 nm), a rough surface can be formed efficiently. The lower limit of the Si etching amount is not particularly limited, for example, can be set to more than 700Å (70 nm). In addition, as long as it is such an etching amount, a rough surface can be formed, and the flatness formed in the double-sided grinding process can not be deteriorated.

[0089] Figure 8The results of evaluating the surface roughness of a roughened single crystal silicon wafer using an atomic force microscope (AFM) are shown in Figure 2. For the sample, the single crystal silicon wafer after SC1 washing was etched for 20 seconds and 30 seconds under the above-mentioned O2 ratio of 7.5% and 10%. In addition, when the O2 ratio was 7.5% and 10%, the etching amount of SiO2 when the processing time was 20 seconds was 29.9Å (2.99 nm) and 36.2Å (3.62 nm), respectively, and it was confirmed to be 25Å (2.5 nm) or more. The roughness indicator uses the three-dimensional arithmetic mean height Sa. Compared with the standard product, when the O2 ratio was 7.5% and 10%, the Sa value increased when the processing time was 20 seconds and 30 seconds, forming a rough surface. In particular, when the O2 ratio was 10%, Sa was 0.94 nm when the processing time was 30 seconds, which was very high, and a rough surface was formed even when the Sa value was used as an indicator. By performing the dry etching process as described above, a rough surface can be formed.

[0090] [Method for manufacturing single crystal silicon wafer]

[0091] Furthermore, the present invention provides a method for manufacturing a single crystal silicon wafer using the dry etching method for a single crystal silicon wafer of the present invention.

[0092] A first embodiment of the method for manufacturing a single crystal silicon wafer of the present invention comprises the following steps:

[0093] Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface;

[0094] Step (2): using a single-wafer dry etching device to perform dry etching on one side of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method for single crystal silicon wafers of the present invention; and

[0095] Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing of the surface opposite to the single surface on which the rough surface is formed, thereby obtaining a single crystal silicon wafer having a rough surface formed only on one surface.

[0096] The second embodiment of the method for manufacturing a single crystal silicon wafer of the present invention comprises the following steps:

[0097] Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface;

[0098] Step (2): using a batch type dry etching device to perform dry etching on both sides of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method of the single crystal silicon wafer described above; and

[0099] Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing to obtain a single crystal silicon wafer having a rough surface formed only on one side.

[0100] The first scheme and the second scheme differ in the following aspects: in step (2), whether the dry etching method based on the present invention is performed on one side of the double-sided polished wafer or on both sides. As described below, either scheme can obtain a single crystal silicon wafer with a rough surface formed only on one side.

[0101] Figure 2 FIG. 1 is a flow chart showing an example of a method for manufacturing a single crystal silicon wafer including the dry etching method of the present invention. Figure 2 The method for manufacturing a single crystal silicon wafer of the present invention is described, but the present invention is not limited thereto.

[0102] (Process (1))

[0103] In step (1), a double-sided polished wafer having a natural oxide film on its surface is prepared.

[0104] Figure 2 In one example shown, a silicon single crystal wafer (double-sided polished wafer) having a natural oxide film formed thereon can be prepared by subjecting a silicon crystal rod to a slicing process, a chamfering process, a precision polishing or grinding process, an etching process, a double-sided polishing process, and a cleaning process. However, process (1) is not limited thereto. Each process is described below.

[0105] Slicing process

[0106] The slicing step is, for example, a step of slicing a silicon ingot into disk-shaped silicon wafers using a wire saw.

[0107] Chamfering process

[0108] The chamfering step is a step of chamfering the outer periphery of the silicon wafer obtained in the slicing step, for example, using a grinding wheel plated with diamond abrasive grains, in order to prevent chipping or cracking of the edge of the silicon wafer obtained in the slicing step.

[0109] Precision grinding or lapping process

[0110] The precision grinding or grinding process is a process for the purpose of removing and flattening the processing deformation layer formed on the front and back sides of the silicon wafer during the slicing process. The precision grinding process, for example, allows a precision grinding liquid to flow between the silicon wafer held by the grinding disk and the carrier, and mechanically grinds the surface of the silicon wafer by rotation and friction under pressure. The precision grinding liquid is a mixture of aluminum oxide or zirconium oxide abrasives, water, and a surfactant. The grinding process, for example, uses a grinding wheel electroplated with diamond abrasives to grind the silicon wafer. Grinding can be performed on one side separately or on both sides at the same time, and it can be either method.

[0111] Etching process

[0112] In the etching process, the processing deformation layer on the front and back sides of the silicon wafer introduced in the precision grinding process and the grinding process is removed. For example, the processing deformation layer can be removed by alkaline etching using an aqueous solution of NaOH or KOH or acid etching mixed with hydrofluoric acid and nitric acid.

[0113] Double-sided grinding process

[0114] In the double-sided polishing process, the front and back sides of the single crystal silicon wafer are processed into polished surfaces and the flatness is improved. For example, a polishing cloth and a polishing slurry are used to polish both sides of the single crystal silicon wafer at the same time after the processing deformation layer after etching is removed.

[0115] Washing process

[0116] In the washing process, slurry residues such as silicon dioxide attached in the double-sided polishing process are removed. For example, silicon dioxide can be effectively removed by performing SC1 washing using a liquid consisting of ammonia water, hydrogen peroxide water and water or O3 washing using O3 water (ozone water). In addition, SC2 washing can also be performed using a liquid consisting of hydrochloric acid, hydrogen peroxide and water.

[0117] Here, the surface of the single crystal silicon wafer immediately after the double-sided grinding process becomes the so-called exposed surface where the silicon surface is exposed. For this exposed surface, the silicon surface is oxidized by performing SC1 washing, SC2 washing or O3 washing with oxidation, thereby forming a natural oxide film on the surface. Therefore, the above-mentioned washing is a process of removing silicon dioxide and forming a natural oxide film, and a single crystal silicon wafer (double-sided grinding wafer) with a natural oxide film can be easily prepared.

[0118] In addition, the cleaning conditions are not particularly limited as long as they are conditions that can achieve the removal of silicon dioxide and the formation of a natural oxide film. For example, as cleaning by oxidation, SC1 cleaning, SC2 cleaning, and O3 cleaning can be performed using a general method.

[0119] (Process (2))

[0120] Dry etching process (forming rough surface)

[0121] Then, using Figure 1 The dry etching method shown, that is, the dry etching method of the present invention described above, forms a rough surface by dry etching the single crystal silicon wafer having a natural oxide film on the surface obtained in this way.

[0122] The dry etching treatment method can be either a single-wafer type for single-wafer treatment or a batch type for one-time treatment of multiple wafers. Furthermore, for the treatment surface, either single-sided treatment or double-sided treatment can be performed. The dry etching conditions of at least the surface on which the rough surface is to be formed are set in a manner that is set to the dry etching conditions of the present invention. Thereafter, for example, when a rough surface is to be formed only on the back side, the first scheme of the present invention can be used to process only the back side of one side in a single-wafer type. Even if double-sided treatment is performed in a batch type by the second scheme of the present invention, a single crystal silicon wafer with a single side made into a normal grinding surface can be manufactured by grinding the surface side in the single-sided grinding process described later.

[0123] (Process (3))

[0124] Then, in step (3), a single crystal silicon wafer having a rough surface formed only on one side is obtained. Figure 2 As shown, a mirror chamfering process, a single-side polishing process and a final cleaning process can be performed. However, step (3) is not limited to this.

[0125] Mirror chamfering process

[0126] In the mirror chamfering step, the chamfered portion of the single crystal silicon wafer processed by dry etching is mirror-finished using a polishing cloth and a polishing slurry.

[0127] Single-side grinding process

[0128] The single-sided grinding process is a process in which a final wafer surface is constructed on a single side of a silicon wafer using a grinding cloth and a grinding slurry. At this time, when a rough surface is formed only on one side in the dry etching process (the first solution), by grinding the surface on the opposite side of the rough surface, a single crystal silicon wafer having only a single side as a rough surface can be manufactured. Usually, the rough surface is desired to be the back side, so the grinding surface is set to the silicon wafer surface (front side). In addition, when a rough surface is formed on two sides in the dry etching process (the second solution), by grinding the surface side of the silicon wafer, a single crystal silicon wafer having only a single side formed with a rough surface can still be manufactured in the same manner.

[0129] Final washing process

[0130] In the final cleaning process, particles and metal impurities attached to the silicon wafer are removed.

[0131] Through such a manufacturing process, a silicon wafer can be manufactured in which the three-dimensional arithmetic mean height Sa is 0.2 nm or less on the front side and 0.5 nm or more on the back side.

[0132] Practically evaluate Figure 2 Sa values ​​of the surface and back of the silicon wafer manufactured by the process. The dry etching conditions were set to an O2 ratio of 10%, and processing time of 20 seconds and 30 seconds. The Sa with a processing time of 20 seconds was 0.068 nm on the surface side and 0.51 nm on the back side, and (back side Sa / surface side Sa) was 7.5. The Sa with a processing time of 30 seconds was 0.071 nm on the surface side and 0.92 nm on the back side, and (back side Sa / surface side Sa) was 13.0. In addition, when the dry etching process was not performed, the Sa was 0.069 nm on the surface side and 0.21 nm on the back side, and (back side Sa / surface side Sa) was 3.04. Therefore, by using the method for manufacturing a single crystal silicon wafer using dry etching processing of the present invention, a silicon wafer having a rough surface formed only on the back side can be manufactured.

[0133] Furthermore, as long as the silicon wafer has a rough surface formed only on the back side, there is no possibility of gripping failure even in a wet environment, and stable production is possible.

[0134] [Single crystal silicon wafer]

[0135] The present invention also provides a single crystal silicon wafer having a three-dimensional arithmetic mean height Sa as an index, wherein Sa on the front side is 0.2 nm or less and Sa on the back side is 0.5 nm or more. Fig. 9 An example of a single crystal silicon wafer of the present invention is shown in FIG. The single crystal silicon wafer 10 of the present invention has a surface 1 and a back side 2, and the back side 2 is a rough surface. Here, the Sa on the surface 1 side is less than 0.2 nm, and the Sa on the back side 2 is greater than 0.5 nm. In addition, there is no particular restriction on the lower limit of Sa on the surface side, for example, it can be greater than 0.01 nm, preferably greater than 0.03 nm. In addition, there is no particular restriction on the upper limit of Sa on the back side, for example, it can be less than 5 nm, preferably less than 2 nm.

[0136] The present invention further provides a single crystal silicon wafer, wherein the three-dimensional arithmetic mean height Sa is used as an index, and (Sa on the back side / Sa on the front side) is 5 or more. Fig. 9 The single crystal silicon wafer of the present invention is described. The single crystal silicon wafer 10 of the present invention has a surface 1 and a back surface 2, and the back surface 2 is a rough surface. Here, (Sa on the back surface 2 side / Sa on the surface 1 side) is 5 or more. In addition, the upper limit of (Sa on the back surface side / Sa on the surface surface side) is not particularly limited, for example, it is 30 or less, preferably 20 or less.

[0137] The single crystal silicon wafer of the present invention can be manufactured by the manufacturing method of the single crystal silicon wafer of the present invention described above. With such a single crystal silicon wafer, it is possible to reduce conveyance defects.

[0138] Example

[0139] Hereinafter, the present invention will be further described based on Examples. However, these Examples are merely illustrative examples and should not be construed in a limitative manner.

[0140] (Example)

[0141] For the embodiment, according to Figure 2 According to the flowchart shown in FIG. 1 , 50 P-type silicon single crystal wafers with a diameter of 300 mm and a rough surface formed only on the back side are manufactured. The manufacturing method of the single crystal silicon wafer in this embodiment is described below.

[0142] In the slicing process, a wire saw is used to cut a silicon single crystal rod into disk-shaped silicon wafers. The surface of the cut silicon wafer is formed with undulations and a processing deformation layer generated during cutting.

[0143] In the chamfering process, the outer periphery of the roughly cut silicon wafer is chamfered using a 3000-mesh diamond-plated grinding wheel, which forms the chamfered shape and prevents defects or cracks in the wafer manufacturing process.

[0144] In the precision grinding process, in order to remove and flatten the processing deformation layer formed on the surface during the slicing process, a precision grinding liquid is used to flow between the grinding disk and the silicon wafer held by a carrier, and the surface of the silicon wafer is mechanically precision ground by rotation and friction under pressure.

[0145] In the etching step, in order to remove the process strain layers on the front and back surfaces of the silicon wafer introduced in the precision grinding step, the silicon wafer is immersed in a NaOH aqueous solution to obtain a silicon wafer from which the process strain layers have been removed.

[0146] In the double-side polishing process, the etched silicon wafer is polished simultaneously with the polishing cloth and the polishing slurry, and both sides of the silicon wafer are processed into polished surfaces and flattened at the same time.

[0147] In the cleaning process, SC1 cleaning is performed using a chemical solution composed of ammonia water, hydrogen peroxide water, and water to remove silicon dioxide remaining in the double-side polishing process and form a natural oxide film on the surface.

[0148] In the dry etching process, since a rough surface is formed only on the back side of the silicon wafer with a natural oxide film, a single-chip dry etching device is used, and only the back side is set as the processing surface. For the mixed gas of CF4-90 volume % and O2-10 volume %, high-frequency excitation is used to form fluorine active species, and the fluorine active species are supplied to the wafer surface, thereby etching. In addition, the total gas flow rate is set to 420sccm, the chamber pressure is set to 40Pa, and the stage temperature supporting the wafer is set to 70°C. In addition, under this condition, the Si etching rate calculated using a single crystal silicon wafer is 2000Å / minute, and the SiO2 etching rate calculated using a single crystal silicon wafer with a thermal oxide film is 109Å / minute, thereby obtaining an etching selectivity ratio of Si to SiO2 of 18.4. The processing time is set to 30 seconds (the etching amount of SiO2 is set to 54.5Å) in such a way that the etching amount of SiO2 becomes 25Å (2.5 nm) or more. Thus, a rough surface is formed on the back side.

[0149] In the mirror chamfering step, the chamfered portion of the dry-etched silicon wafer is mirror-finished using a polishing cloth and a polishing slurry, thereby obtaining a mirror surface without a processing deformation layer at the chamfered portion.

[0150] In the single-side polishing process, the front side of the silicon wafer opposite to the rough surface is polished using a polishing cloth and a polishing slurry, thereby forming a good polished surface on the front side.

[0151] In the final cleaning process, particles and metal impurities attached to the silicon wafer are removed. Here, a batch cleaning machine is used, using SC1 and SC2 cleaning solutions.

[0152] Take out one of the obtained silicon wafers, and evaluate the roughness of the surface side and the back side with an AFM with an observation field of 2μm. The three-dimensional arithmetic mean height Sa is 0.065 nm on the surface side and 0.94 nm on the back side. (Back side Sa / surface side Sa) is 14.5, confirming that a rough surface is formed only on the back side. Afterwards, the handling test was repeated 200 times, and the results showed that all 200 times were able to be handled well. The handling test clamped the back side of the wafer stored in water and unloaded the wafer on the stage of the grinder.

[0153] (Comparative Example)

[0154] In the comparative example, 50 P-type silicon single crystal wafers with a diameter of 300 mm were manufactured by the same steps as those in the example except that only the dry etching step in the example was performed.

[0155] Take out one of the obtained silicon wafers, and evaluate the roughness of the surface side and the back side by AFM with an observation field of 2 μm. The three-dimensional arithmetic mean height Sa is 0.067 nm on the surface side and 0.22 nm on the back side. (Back side Sa / Surface side Sa) is 3.28, and the Sa value ratio on the back side is very small compared with the embodiment. After that, the handling test was repeated 200 times, and the result was that the wafer could not be detached from the clamp 4 times out of 200 times. The handling test clamped the back side of the wafer stored in the water and removed the wafer from the stage of the grinder.

[0156] Based on the above results, by using the dry etching method of the present invention, a single crystal silicon wafer having a rough surface formed only on the back side can be manufactured, and handling defects can be reduced. In particular, a single crystal silicon wafer can be manufactured, which can be controlled to any (target) surface roughness, and the back roughness (Sa on the back side / Sa on the surface side) is well controlled and reproducible, and the quality is stable.

[0157] This specification includes the following inventions.

[0158] [1] A dry etching method for a single crystal silicon wafer, which is a dry etching method for forming a rough surface on a single crystal silicon wafer, wherein:

[0159] The method comprises the steps of using a single crystal silicon wafer having a natural oxide film (SiO2) on its surface as the single crystal silicon wafer, and performing a dry etching process on the surface of the single crystal silicon wafer having the natural oxide film by using a gas containing at least fluorine, and

[0160] In the dry etching process, the etching selectivity ratio of Si to SiO2 calculated by (etching rate of Si / etching rate of SiO2) is set to 18 or more, and the etching amount of SiO2 is set to 2.5 nm or more, thereby forming a rough surface on the single crystal silicon wafer.

[0161] [2] A dry etching method for a single crystal silicon wafer according to the above-mentioned [1], wherein the etching rate of Si is set to a value calculated using a single crystal silicon wafer, and the etching rate of SiO2 is set to a value calculated using a single crystal silicon wafer with a thermal oxide film.

[0162] [3] The dry etching method for a single crystal silicon wafer according to [1] or [2] above, wherein in the dry etching process, the etching amount of Si is set to 200 nm or less.

[0163] [4] The dry etching method for a single crystal silicon wafer according to [1], [2] or [3] above, wherein a fluorocarbon-based gas is used as the fluorine-containing gas in the dry etching process.

[0164] [5] The dry etching method for a single crystal silicon wafer according to [4] above, wherein CF4 is used as the fluorocarbon-based gas in the dry etching process.

[0165] [6] A dry etching method for a single crystal silicon wafer according to [1], [2], [3], [4] or [5] above, wherein, during the dry etching process, oxygen is added to the fluorine-containing gas, thereby adjusting the etching selectivity of Si relative to SiO2, the etching rate of Si and the etching rate of SiO2.

[0166] [7] A dry etching method for a single crystal silicon wafer according to [1], [2], [3], [4], [5] or [6], wherein the natural oxide film is formed by SC1 washing, SC2 washing or O3 washing.

[0167] [8] A method for manufacturing a single crystal silicon wafer, comprising the following steps:

[0168] Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface;

[0169] Step (2): using a single-wafer dry etching device, dry etching one side of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method for single crystal silicon wafers described in [1], [2], [3], [4], [5], [6] or [7] above; and

[0170] Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing of the surface opposite to the single surface on which the rough surface is formed, thereby obtaining a single crystal silicon wafer having a rough surface formed only on one surface.

[0171] [9] A method for manufacturing a single crystal silicon wafer, comprising the following steps:

[0172] Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface;

[0173] Step (2): using a batch dry etching apparatus, dry etching both sides of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method for single crystal silicon wafers described in [1], [2], [3], [4], [5], [6] or [7] above; and

[0174] Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing to obtain a single crystal silicon wafer having a rough surface formed only on one side.

[0175]

[10] A single crystal silicon wafer, wherein, taking a three-dimensional arithmetic mean height Sa as an indicator, Sa on the front side is less than 0.2 nm and Sa on the back side is greater than 0.5 nm.

[0176]

[11] A single crystal silicon wafer, wherein, taking a three-dimensional arithmetic mean height Sa as an index, (Sa on the back side / Sa on the front side) is 5 or more.

[0177] The present invention is not limited to the above-mentioned embodiments. The above-mentioned embodiments are merely examples, and any technical solution having substantially the same configuration and exhibiting the same function and effect as the technical concept described in the claims of the present invention is included in the technical scope of the present invention.

Claims

1. A dry etching method for a single crystal silicon wafer, which is a dry etching method for forming a rough surface on a single crystal silicon wafer, characterized in that: The method comprises the steps of using a single crystal silicon wafer having a natural oxide film (SiO2) on its surface as the single crystal silicon wafer, and performing a dry etching process on the surface of the single crystal silicon wafer having the natural oxide film by using a gas containing at least fluorine, and In the dry etching process, the etching selectivity ratio of Si to SiO2 calculated by (etching rate of Si / etching rate of SiO2) is set to 18 or more, and the etching amount of SiO2 is set to 2.5 nm or more, thereby forming a rough surface on the single crystal silicon wafer.

2. The dry etching method for a single crystal silicon wafer according to claim 1, characterized in that: The etching rate of Si is set to a value calculated using a single crystal silicon wafer, and the etching rate of SiO 2 is set to a value calculated using a single crystal silicon wafer with a thermal oxide film.

3. The dry etching method for a single crystal silicon wafer according to claim 1, characterized in that: In the dry etching process, the etching amount of Si is set to 200 nm or less.

4. The dry etching method for a single crystal silicon wafer according to claim 1, characterized in that: In the dry etching process, a fluorocarbon-based gas is used as the fluorine-containing gas.

5. The dry etching method for a single crystal silicon wafer according to claim 4, characterized in that: In the dry etching process, CF 4 is used as the fluorocarbon-based gas.

6. The dry etching method for a single crystal silicon wafer according to claim 1, characterized in that: In the dry etching process, oxygen is added to the fluorine-containing gas, thereby adjusting the etching selectivity of Si to SiO 2 , the etching rate of Si, and the etching rate of SiO 2 .

7. The dry etching method for a single crystal silicon wafer according to claim 1, characterized in that: The natural oxide film is formed by SC1 cleaning, SC2 cleaning, or O3 cleaning.

8. A method for manufacturing a single crystal silicon wafer, characterized in that: The process includes the following steps: Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface; Step (2): using a single-wafer dry etching device to perform dry etching on one side of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method for a single crystal silicon wafer according to any one of claims 1 to 7; and Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing of the surface opposite to the single surface on which the rough surface is formed, thereby obtaining a single crystal silicon wafer having a rough surface formed only on one surface.

9. A method for manufacturing a single crystal silicon wafer, characterized in that: The process includes the following steps: Step (1): after double-sided polishing of the raw wafer from which the processing deformation layer has been removed, a natural oxide film is formed by SC1 cleaning, SC2 cleaning or O3 cleaning, thereby preparing a double-sided polished wafer having a natural oxide film on the surface; Step (2): using a batch type dry etching apparatus, performing a dry etching process on both sides of the double-sided polished wafer, wherein the dry etching process forms a rough surface using the dry etching method for a single crystal silicon wafer according to any one of claims 1 to 7; and Step (3): The double-sided polished wafer subjected to the dry etching process is subjected to single-side polishing to obtain a single crystal silicon wafer having a rough surface formed only on one side.

10. A single crystal silicon wafer, characterized in that: Taking the three-dimensional arithmetic mean height Sa as an indicator, Sa on the surface side is 0.2 nm or less, and Sa on the back side is 0.5 nm or more.

11. A single crystal silicon wafer, characterized in that: Taking the three-dimensional arithmetic mean height Sa as an index, (Sa on the back side / Sa on the front side) is 5 or more.

Images