Package architecture with vertically stacked integrated circuit dies with planarized edges

Abstract

An embodiment of an integrated circuit (IC) die includes a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region includes: a dielectric material; layers of conductive traces in the dielectric material, each layer of conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; a conductive via through the dielectric material; and a bond pad on the first surface, the bond pad comprising a portion of the conductive trace exposed on the first surface, and the second region comprising a material different from the dielectric material.

Description

Technical Field

[0001] The present disclosure relates to techniques, methods, and apparatus related to a packaging architecture having vertically stacked integrated circuit dies with planarized edges. Background Art

[0002] When electronic circuits are typically manufactured on wafers of semiconductor materials such as silicon, they are referred to as integrated circuits (ICs). Wafers with such ICs are typically cut into many individual dies. The dies may be packaged into an IC package, which contains one or more dies and other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated into an electronic system (such as a consumer electronic system) or a server (such as a mainframe). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. The embodiments are shown in the figures of the accompanying drawings by way of example and not limitation.

[0004] Figure 1 is a schematic cross-sectional view of an example IC die according to some embodiments of the present disclosure.

[0005] Figure 2 yes Figure 1 Schematic cross-sectional perspective view of a portion of an example IC die.

[0006] Figure 3A is a schematic cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure.

[0007] Figure 3B yes Figure 3A Schematic cross-sectional view of a portion of an example microelectronic assembly.

[0008] Figure 3C According to some embodiments of the present disclosure Figure 3A Schematic cross-sectional view of a portion of an example microelectronic assembly.

[0009] Figure 3D According to some embodiments of the present disclosure Figure 3A Schematic cross-sectional view of a portion of an example microelectronic assembly.

[0010] Figure 4 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure.

[0011] Figure 5A is a simplified top view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0012] Figure 5B yes Figure 5A A simplified perspective illustration of a portion of an example microelectronic assembly.

[0013] Figure 6 is a schematic cross-sectional perspective view of a portion of another example IC die according to some embodiments of the present disclosure.

[0014] Figure 7 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0015] Figure 8 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0016] Fig. 9 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0017] Fig.10 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0018] Fig.11 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0019] Fig.12 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0020] Fig.13 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0021] FIG. 14A to FIG. 14K are schematic cross-sectional views of various stages of fabrication of an example microelectronic assembly according to some embodiments of the present disclosure.

[0022] Fig.15 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any embodiment disclosed herein.

[0023] Fig.16 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any embodiment disclosed herein.

[0024] Fig.17 is a block diagram of an example computing device including one or more microelectronic assemblies according to any embodiment disclosed herein. DETAILED DESCRIPTION

[0025] Overview

[0026] For the purpose of illustrating the IC packaging described herein, it is important to understand the phenomena that may play a role during the assembly and packaging of the IC. The following basic information can be considered as a basis on which the present disclosure can be properly interpreted. This information is provided for explanation purposes only and therefore should not be interpreted in any way to limit the broad scope of the present disclosure and its potential applications.

[0027] The trend in the computer industry is to utilize multiple processors in large servers, where multiple processors are coupled together in a single package, such as a multi-chip module (MCM). Multiple processors, along with other IC dies containing memory circuits (e.g., cache memory circuits, high-bandwidth memory circuits, etc.), are interconnected, for example, by a high-speed data bus in the package substrate of the MCM, so that all processors can operate together. However, current technology in such MCMs is inherently limited in its ability to scale to the bandwidth / distance requirements of next-generation servers, which may have signal speeds greater than 10 GHz and / or data speeds of 3-10 terabytes per second. Due to various reasons (one of which is the configuration of multiple processors coupled together inside the package), some limitations are primarily associated with bandwidth reduction, signal delay, signal loss, and signal distortion.

[0028] Current packaging architectures (whether 2D, 2.5D or 3D) utilize multiple IC dies that are oriented parallel to each other and interconnected by various interconnects (such as copper microbumps, solder balls, etc.). In a general sense, any typical IC die includes a substrate, an active area in the substrate, and a metallization stack on the substrate, the active area including transistors and other active circuits, and the metallization stack shares contact areas with the active area. The metallization stack is an area of ​​the IC die in which various devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with conductive traces and conductive vias. The general metals used for conductive traces and conductive vias are copper and aluminum. The metallization stack typically includes contact pads, insulating layers (e.g., interlayer dielectric (ILD) materials, such as silicon oxide), conductive layers including conductive traces, and bonding sites for chip-to-chip or chip-to-package connections. Modern IC dies may include more than 10 conductive layers in the metallization stack.

[0029] Conventionally, various such IC dies can be stacked within a package in various ways: (1) back-to-back, with the substrate of one IC die in direct contact with the substrate of another IC die; (2) back-to-face, with the substrate of one IC die in direct contact with the metallization stack of another IC die; and (3) face-to-face, with the metallization stacks of two IC dies in direct contact. In all of these configurations, the IC dies are parallel to each other, with the active circuits arranged in planes parallel to the contact areas of adjacent IC dies. Such architectures have certain inherent limitations. For example, a computing IC die that includes high-performance computing circuits that generate a large amount of heat must be placed on top of any such stack so that the heat can be properly dissipated. Such placement limits the number of high-power computing IC dies that can be placed in a package with a limited (or constrained) footprint.

[0030] Thus, embodiments of microelectronic assemblies disclosed herein include a first IC die coupled to a second IC die via interconnects on a first surface of the first IC die and a second surface of the second IC die such that the first surface contacts the second surface, and the first IC die includes a substrate attached to a metallization stack along a planar interface orthogonal to the first surface. The interconnects include a dielectric-dielectric bond and a metal-metal bond, the metal-metal bond including a first bond pad in the first IC die and a second bond pad in the second IC die. The metallization stack of the first IC die includes multiple layers of conductive traces in a dielectric material, and the first bond pad includes a portion of the conductive trace exposed on the first surface.

[0031] Embodiments described herein disclose an IC die, comprising: a first region, the first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region, the second region being attached to the first region along a planar interface orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; a layer of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface, such that the conductive traces are orthogonal to the first surface; a conductive via passing through the dielectric material; and a bonding pad on the first surface, the bonding pad comprising a portion of the conductive trace exposed on the first surface, and the second region comprising a material different from the dielectric material.

[0032] Each of the structures, components, packaging, methods, devices, and systems of the present disclosure may have several innovative aspects, no single aspect of which is solely responsible for all of the desirable properties disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0033] In the following detailed description, various aspects of the illustrative embodiments may be described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art.

[0034] The terms "circuit" and "electronic circuit" refer to one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide a desired function. These terms also refer to analog circuits, digital circuits, hard-wired circuits, programmable circuits, microcontroller circuits, and / or any other type of physical hardware electrical and / or electronic components.

[0035] The term "integrated circuit" refers to an electrical circuit integrated into a single piece of semiconductor or similar material.

[0036] In some embodiments, the IC die disclosed herein may include a substantially single-crystal semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body) on which an integrated circuit is manufactured using conventional semiconductor processing methods. The semiconductor base material may include, for example, an N-type or P-type material. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more IC dies may include an alternative material, which may or may not be combined with silicon, the alternative material including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In further other embodiments, the base material may include a compound semiconductor, for example, a first sub-lattice having at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice having at least one element from Group V of the periodic table (e.g., P, As, Sb). In further other embodiments, the base material may include an intrinsic IV or III-V semiconductor material or alloy that has not been intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In still further other embodiments, the die may include an amorphous material such as a polymer; for example, the base material may include a silica-filled epoxy. In other embodiments, the base material may include a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Typically, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, magnesium, etc. Although a few examples of materials for the die are described herein, any material or structure that can be used as a base (e.g., base material) on which IC circuits and structures as described herein are built falls within the spirit and scope of the present disclosure.

[0037] Unless otherwise described, IC dies described herein include one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) certain functions. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuits (e.g., ICs that implement one or more of memory devices, memory arrays, control logic configured to control memory devices and arrays, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuits (e.g., ICs that implement one or more of I / O functions, arithmetic operations, pipelining of data, etc.).

[0038] In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die." Note that the terms "chip," "die," and "IC die" are used interchangeably herein.

[0039] Unless otherwise specified, the term "insulation" means "electrical insulation" and the term "conduction" means "electrical conduction." For optical signals and / or devices, components and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction."

[0040] The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

[0041] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0042] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material that solidifies after treatment as described herein) that is substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials are materials used for bottom fills and moldings or similar moldings in packaging applications, including, for example, materials used for organic interposers, packaging supports, and other such components.

[0043] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those elements monolithically integrated within the IC, those elements mounted on the IC, or those elements connected to the IC. Depending on the components associated with the IC, the IC described herein may be analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc. The IC described herein may be used in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0044] In various embodiments of the present disclosure, the transistor described herein may be a field effect transistor (FET), such as a MOSFET. In a number of embodiments, the FET is a four-terminal device. In SOI or nanoribbon or all-around gate (GAA) FET, the FET is a three-terminal device that includes a source, a drain, and a gate terminal, and uses an electric field to control the current flowing through the device. FETs typically include: a channel material; a source region and a drain region disposed in and / or on the channel material; and a gate stack, the gate stack including a gate electrode material disposed on a portion of the channel material located between the source region and the drain region ("channel portion"), or referred to as a "work function" material, and optionally, the gate stack also includes a gate dielectric material between the gate electrode material and the channel material.

[0045] In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components to facilitate the transmission of electrical signals between them; an optical interconnect provides an optical connection between two optical components to facilitate the transmission of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the interconnect being described will be understood herein with reference to the signal medium associated with the interconnect being described. Therefore, when used with respect to an electronic device (such as an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to one or more elements associated with the IC or / and providing an electrical connection between various such elements. In such cases, the term "interconnect" can refer to both electrical traces (sometimes also referred to as "lines", "wiring", "metal lines" or "trench") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, to highlight the fact that these elements include conductive materials such as metals. Likewise, when used with respect to devices that also operate on optical signals, such as photonic ICs (PICs), "interconnect" may also describe any element formed of light-conducting materials for providing an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0046] The term "waveguide" refers to any structure used to guide light to propagate from one location to another, typically through a substrate material such as silicon or glass. In various examples, the waveguide can be formed from silicon, doped silicon, silicon nitride, glass (such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80wt% SiO2, 7-13wt% B2O3, 4-8wt% Na2O or K2O, and 2-8wt% Al2O3), etc. The waveguide can be formed using various techniques, including but not limited to in-situ waveguide formation. For example, in some embodiments, the waveguide can be formed in-situ in the glass using low temperature glass-to-glass bonding or by laser direct writing. The waveguide formed in-situ can have lower loss characteristics.

[0047] The term "conductive trace" may be used to describe conductive elements that are separated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics disposed within the IC die. Within package substrates and printed circuit boards (PCBs), such insulating materials include organic materials such as Ajinomoto Buildup Film (ABF), polyimide, or epoxy. Such conductors are typically arranged in several levels or layers of a metallization stack.

[0048] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductors at different levels of a metallization stack. To this end, the via may be disposed substantially perpendicular to the plane of the IC die / chip or a support structure on which the IC structure is disposed, and may interconnect two conductors in adjacent levels or two conductors in non-adjacent levels.

[0049] The term "package substrate" may be used to describe any substrate material that facilitates packaging together any collection of semiconductor die and / or other electrical components (e.g., passive electrical components). As used herein, a package substrate may be formed of any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate including a buildup layer (e.g., ABF layer).

[0050] The term "metallization stack" may be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of a package substrate and / or an IC die / chip.

[0051] As used herein, the term "pitch" of interconnects refers to the center-to-center distance between adjacent interconnects.

[0052] In the context of a stack of dies coupled to each other or in the context of a die coupled to a package substrate, the term "interconnect" may also refer to a die-to-die (DTD) interconnect and a die-to-package substrate (DTPS) interconnect, respectively. A DTD interconnect may also be referred to as a first-level interconnect (FLI). A DTPS interconnect may also be referred to as a second-level interconnect (SLI).

[0053] Although not specifically shown in all current descriptions in order not to clutter the figures, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the package substrate or the second die may include a second set of conductive contacts. One or more conductive contacts in the first set may then be electrically and mechanically coupled to some conductive contacts in the second set via the DTD or DTPS interconnect.

[0054] In some embodiments, the pitch of the DTD interconnects may be different than the pitch of the DTPS interconnects, although in other embodiments, these pitches may be substantially the same.

[0055] The DTPS interconnect disclosed herein can take any suitable form. In some embodiments, a group of DTPS interconnects can include solder (e.g., solder bumps or solder balls that undergo thermal reflow to form DTPS interconnects). DTPS interconnects including solder can include any appropriate solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a group of DTPS interconnects can include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. Anisotropic conductive materials can include conductive materials dispersed in non-conductive materials. In some embodiments, anisotropic conductive materials can include microscopic conductive particles embedded in a binder or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy resin or an acrylic-based material). In some embodiments, the conductive particles can include polymers and / or one or more metals (e.g., nickel or gold). For example, the conductive particles can include gold coated with nickel or copper coated with silver, which are in turn coated with polymers. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on both sides of the anisotropic conductive material), the conductive materials near the compressed area may contact each other, thereby forming a conductive path from one side of the film to the other side in the compressed area.

[0056] The DTD interconnects disclosed herein may take any suitable form. In some embodiments, some or all of the DTD interconnects in the microelectronic assembly or IC package as described herein may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the conductive contacts on both sides of the DTD interconnects may be bonded together (e.g., under elevated pressure and / or temperature) without using an intermediate solder or anisotropic conductive material. In some metal-to-metal interconnects, dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the metals bonded together (e.g., between copper pads or pillars providing associated conductive contacts). In some embodiments, one side of the DTD interconnect may include a metal pillar (e.g., a copper pillar), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) recessed in the dielectric. In some embodiments, a metal-to-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal (e.g., silver) whose oxide is conductive. In some embodiments, a metal-to-metal interconnect may include a metal nanostructure (e.g., a nanorod) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be constrained to mitigate mechanical failure.

[0057] In some embodiments, the dies on both sides of a set of DTD interconnects may be bare (eg, unpackaged) dies.

[0058] In some embodiments, the DTD interconnect may include solder. For example, the DTD interconnect may include a conductive bump or column (e.g., a copper bump or column) attached to a corresponding conductive contact by solder. In some embodiments, a thin solder cap may be used in a metal-to-metal interconnect to provide flatness, and the solder may become an intermetallic compound during processing. In some embodiments, the solder used in some or all of the DTD interconnects may have a higher melting point than the solder included in some or all of the DTPS interconnects. For example, when the DTD interconnect in an IC package is formed before the DTPS interconnect is formed, the solder-based DTD interconnect may use a higher temperature solder (e.g., having a melting point greater than 200 degrees Celsius), while the DTPS interconnect may use a lower temperature solder (e.g., having a melting point less than 200 degrees Celsius). In some embodiments, the higher temperature solder may include tin; tin and gold; or tin, silver and copper (e.g., 96.5% tin, 3% silver and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (eg, eutectic tin-bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0059] In some embodiments, a set of DTD interconnects may include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects. In some embodiments, DTD interconnects may be used as data transmission channels, while DTPS interconnects may be used for power and ground lines, etc.

[0060] In a microelectronic assembly or IC package as described herein, some or all DTD interconnects may have finer spacing than DTPS interconnects. In some embodiments, the DTPS interconnect disclosed herein may have a spacing between about 80 microns and 300 microns, while the DTD interconnect disclosed herein may have a spacing between about 0.5 microns and 100 microns, depending on the type of DTD interconnect. An example of silicon-level interconnect density is provided by the density of some DTD interconnects. In some embodiments, the DTD interconnect may have a spacing that is too fine to be directly coupled to a package substrate (e.g., too fine to be used as a DTPS interconnect). Since the similarity of materials in different tube cores on both sides of a group of DTD interconnects is greater than the similarity of materials between the tube core and the package substrate on both sides of a group of DTPS interconnects, the DTD interconnect may have a smaller spacing than the DTPS interconnect. In particular, the difference in the material composition of the tube core and the package substrate may cause the tube core and the package substrate to produce differential expansion and contraction due to the heat generated during operation (and the heat applied during each manufacturing operation). To mitigate damage (e.g., cracking, solder bridging, etc.) caused by such differential expansion and contraction, the DTPS interconnects in any microelectronic assembly or IC package as described herein can be formed to be larger and farther apart than the DTD interconnects, which can experience less thermal stress due to the greater material similarity of the die pairs on both sides of the DTD interconnects.

[0061] It should be appreciated that one or more levels of bottom filler (e.g., organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC package described herein and may not be labeled to avoid cluttering the drawings. In various embodiments, the various levels of bottom filler may include the same or different insulating materials. In some embodiments, the levels of bottom filler may include a thermosetting epoxy with silicon oxide particles; in some embodiments, the levels of bottom filler may include any suitable material capable of performing bottom fill functions, such as supporting the die and reducing thermal stress on the interconnect. In some embodiments, the selection of bottom fill material may be based on design considerations, such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of bottom fill material may be based on material properties and processing conditions, such as factors such as curing temperature, glass transition temperature, viscosity, and chemical resistance; in some embodiments, the selection of bottom fill material may be based on both design and processing considerations.

[0062] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided in the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material, including a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0063] The terms "substantially," "close," "approximately," "near," and "approximately" generally mean within + / - 20% of a target value (e.g., within + / - 5 or 10% of a target value), based on the context of a particular value as described herein or as known in the art.

[0064] Terms indicating the orientation of various elements (e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements) generally refer to within + / - 5%-20% of the target value, based on the context of specific values ​​as described herein or as known in the art.

[0065] The term "connected" means a direct connection between the things being connected (which may be one or more of a mechanical, electrical and / or thermal connection) without any intermediary devices, while the term "coupled" means a direct connection between the things being connected, or an indirect connection through one or more passive or active intermediary devices.

[0066] This specification uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments.

[0067] Furthermore, as used with respect to embodiments of the present disclosure, the terms "comprising," "including," "having," and the like are synonymous.

[0068] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0069] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. Conversely, a first layer described as being "on" a second layer refers to the layer that is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intervening layers.

[0070] As used herein, the term "disposed" refers to placing, positioning, placing, and / or arranging, rather than to any particular method of formation.

[0071] When the term "between" is used with respect to a measuring range, the term "between" includes the ends of the measuring range.

[0072] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0073] Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, a "conductive material" may include one or more conductive materials. In another example, a "dielectric material" may include one or more dielectric materials.

[0074] Unless otherwise indicated, the use of the ordinal adjectives "first," "second," and "third," etc., used to describe common objects simply indicates that different instances of similar objects are mentioned and is not intended to imply that the objects so described must be in a given order, whether temporally, spatially, in ranking, or in any other manner.

[0075] In the following detailed description, reference is made to the accompanying drawings which form a part of the detailed description, and in the accompanying drawings, embodiments that can be practiced are shown by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense.

[0076] The drawings are not necessarily drawn to scale.

[0077] In the figures, the same reference numerals refer to the same or similar elements / materials shown, and therefore, unless otherwise stated, where elements / materials with the same reference numerals are shown, the explanation of the elements / materials with a given reference numeral provided in the context of one of the figures applies to the other figures. In addition, singular and plural forms of the reference numerals may be used with the reference numerals to refer to a single or multiple elements of the same or similar type, kind or class of elements, respectively.

[0078] In addition, in the figures, some schematic diagrams of example structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that such schematic diagrams may not reflect real-world process limitations, which may cause features to appear less than "ideal" when inspecting any structure described herein using, for example, images of suitable characterization tools, such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers. In such images of actual structures, possible processing and / or surface defects may also be visible, such as surface roughness, curvature or profile deviations, pits or scratches, imperfectly straight edges of materials, tapered vias or other openings, unintentional rounding of corners or thickness variations of different material layers, occasional screw dislocations, edge dislocations, or combined dislocations within one or more crystal regions, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing and / or packaging.

[0079] Note that in the accompanying drawings, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) for ease of illustration only; in fact, some or all of them may be misaligned. In addition, there may be other components in the assembly that are not shown in the drawings, such as bonding pads, landing pads, metallizations, etc., to prevent confusion. In addition, the drawings are intended to show the relative arrangement of the components within their assemblies, and generally speaking, such assemblies may include other components that are not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal relief). For example, in some additional embodiments, the assembly as shown may include more dies and other electrical components. In addition, although some components of the assembly are shown as flat rectangles or formed by rectangular solid lines in the drawings, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, as indicated by the manufacturing process used to manufacture the various components and sometimes unavoidable.

[0080] In the figures, specific numbers and arrangements of structures and components are described for illustrative purposes, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0081] Furthermore, unless otherwise stated, the structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes, and operating conditions.

[0082] For convenience, if there are graph collections named with different letters (e.g. Fig.10 A-10C), such a collection may be referred to herein without a letter (e.g., referred to as " Fig.10 ”). Similarly, if there is a collection of reference numerals designated with different letters (e.g., 112a-112e), then such collection may be referenced herein without the letters (e.g., referred to as “112”).

[0083] The various operations may be described as multiple discrete sequential actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must rely on the order. In particular, these operations may not be performed in the order of introduction. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0084] Example Embodiments

[0085] Figure 1 is a schematic cross-sectional view of an example IC die 100 (multiple "IC die 100") according to some embodiments of the present disclosure. In the illustrated embodiment, IC die 100 includes a metallization stack 102 having a surface 104 orthogonal to another surface 106. In various embodiments, surfaces 104 and 106 and their respective edges are planarized. In a typical IC die other than IC die 100, the two differ in at least that the typical IC die does not have planarized edges along the thickness, and the vertical surface corresponding to surface 104 will be rough when the IC die is singulated from a wafer and undergoes a sawing operation. In contrast, surface 104 of IC die 100 can be flat and planar, wherein the surface roughness is less than 10 angstroms and the total thickness variation (TTV) across surface 104 is less than 3 microns.

[0086] Metallization stack 102 can be attached to substrate 110 having active area 112 along planar interface 108. Planar interface 108 can be orthogonal to surface 104 and parallel to surface 106. In some embodiments, active area 112 including transistors, diodes and other active circuits can be close to planar interface 108. In some other embodiments, active area 112 may not exist, or alternatively, transistors, diodes and other active circuits may not exist in active area 112. Substrate 110 can have another surface 114 coplanar with surface 104. In some embodiments, substrate 110 includes semiconductor materials listed in the previous section. In other embodiments, substrate 110 can include glass, ceramics or other materials suitable for manufacturing functional elements of IC.

[0087] In various embodiments, the metallization stack 102 includes a dielectric material 116, a plurality of layers 118 of conductive traces 120 in the dielectric material 116, each layer 118 of the conductive traces 120 being parallel to the surface 106, such that the conductive traces 120 are orthogonal to the surface 104. In some embodiments, the dielectric material 116 may include silicon oxide; in other embodiments, the dielectric material 116 may include any suitable dielectric material used as an interlayer dielectric (ILD) in a typical semiconductor IC die and as described in the previous subsection. In various embodiments, the conductive traces 120 may include copper. In some embodiments, there may be 2 to 6 layers of the conductive traces 120 in the plurality of layers 118. In various embodiments, the thickness of each layer 118 may vary between 3 microns and 5 microns. Conductive vias 122 passing through the dielectric material 116 may conductively connect the conductive traces 120 in each layer 118 to the active circuits in the active area 112. The conductive vias 122 are orthogonal to the conductive traces 120. Conductive traces 120 may extend up to surface 104 such that portions of conductive traces 120 are exposed on surface 104; such exposed portions may form bonding pads 124. In various embodiments, there may be several layers 118 of conductive traces 120 between planar interface 108 and surface 106, wherein 2 to 6 layers closest to surface 106 may have conductive traces 120 exposed on surface 104 as bonding pads 124.

[0088] In various embodiments, the IC die 100 can be less than 100 microns along a first axis through the thickness of the IC die 100, less than 35 millimeters along a second axis orthogonal to the first axis (e.g., along the length of the IC die 100), and less than 5 millimeters along a third axis orthogonal to the first and second axes (e.g., along the width of the IC die 100). In other words, in various embodiments, the length of the IC die 100 can be nearly 5 times greater than its width.

[0089] Figure 21 is a simplified perspective view of a portion of the IC die 100. The substrate 110 may include one or more through-substrate vias (TSVs) 202. The active circuit 204 may be in an active region 112 near the planar interface 108 between the metallization stack 102 and the substrate 110. Each layer 118 may have a different thickness than the other layers. In some embodiments, the thickness of the layer 118 increases toward the surface 106 as the distance from the planar interface 108 increases. Therefore, the conductive traces 120 in such layers 118 may have different thicknesses, and accordingly, the bonding pads 124 may also have different sizes, depending on the layer in which they are located. For example, the bonding pad 124A closer to the surface 106 may be larger (e.g., thicker, wider, longer) than the bonding pad 124B closer to the planar interface 108. In some embodiments, the bonding pad 124 may extend through 2 to 6 layers closest to the surface 106. In some embodiments, the linear dimension (eg, length, width, or diagonal dimension) of the largest bond pad 124 can be less than 5 microns. In some embodiments, the bond pads 124 can be spaced apart by a pitch less than 9 microns.

[0090] FIG. 3A to FIG. 3D Simplified schematic cross-sections of various configurations of a microelectronic assembly 300 are shown according to embodiments of the present disclosure. Figure 3A A microelectronic assembly 300 is shown that includes a plurality of IC dies 100, e.g., 100(1), 100(2), and 100(3), coupled to another IC die 302 via interconnects 304 such that a surface 104 of any one of the IC dies 100 is in direct contact with a surface 306 of the IC die 302. Figure 1 to Figure 2 As depicted, the surface 104 is orthogonal to the planar interface 108 between the active region 112 of any of the IC dies 100 and the metallization stack 102. In some embodiments, the IC dies 100 may include active circuitry (e.g., transistors, diodes) in the active region 112. In other embodiments, one or more of the IC dies 100 may not include active circuitry in the active region 112; in such embodiments, the active region 112 may be merged with the substrate 110 (e.g., not present).

[0091] In various embodiments, IC die 302 may include an interposer with conductive traces to enable conductive coupling of IC die 100 with other IC die and / or package substrates, and IC die 302 may not have any active circuits therein. In other embodiments, IC die 302 may include active circuits. In multiple embodiments, IC die 100 may be conductively coupled through conductive pathways in IC die 302. For example, IC die 302 may include an on-chip network that interconnects computing circuits of IC die 100 together. In various embodiments, IC die 100 may be conductively coupled to IC die 302 through interconnect 304, which may include hybrid bonding. In such a configuration, surface 114 of substrate 110 of IC die 100 may be in direct contact with surface 306 of IC die 302.

[0092] Figure 3B is a schematic cross-sectional view of details of a particular one of the interconnects 304 in the microelectronic assembly 300. Note that although only the interconnect 304 is shown, the same structure and description can be applied to any other such interconnects including hybrid bonding in the microelectronic assembly 300. In a general sense, the interconnect 304 can include metal-to-metal bonding between the bond pads 124 of the IC die 100 and the bond pads 308 of the IC die 302, and dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding) in the respective dielectric materials 116 and 310 of the IC die 100 and 302 at the interface between the respective surfaces 104 and 306 between the IC die 100 and 302. The bond pad 124 belonging to the IC die 100 can be bonded to the bond pad 308 of the IC die 302. As shown in Figure 1 to Figure 2 As noted in the description of , bonding pad 124 may include a portion of conductive trace 120 exposed on surface 104; bonding pad 308 may include a conventional conductive structure plated on surface 306. Dielectric material 116 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) in IC die 100 may be bonded to dielectric material 310 in IC die 302. In some embodiments, dielectric material 310 of IC die 302 is the same as dielectric material 116 of IC die 100. In various embodiments, dielectric material 310 includes silicon oxide, silicon nitride, silicon carbonitride, and other such inorganic materials commonly used in the manufacture of semiconductor IC dies. The bonded metal and dielectric materials form interconnect 304, including hybrid bonding, to provide electrical and mechanical coupling between IC die 100 and IC die 302. In various embodiments, interconnect 304 may have a linear dimension of less than 5 microns, and between adjacent interconnects, interconnect 304 may have a pitch of less than 10 microns.

[0093] Back to Figure 3A, IC die 100 can be coupled to IC die 302 such that metallization stack 102 of one of IC die 100 (e.g., 100(1)) can be in direct contact with substrate 110 of adjacent IC die 100 (e.g., 100(2)). In some such embodiments, IC die 100(1) and 100(2) can be bonded to each other at least by dielectric-to-dielectric bonding. In some embodiments, including as described in reference Figure 3B The described metal-to-metal bonded and dielectric-to-dielectric bonded interconnects 304 may be present at a planar contact interface between the contacting IC dies 100(1) and 100(2). In some such embodiments, conductive contact between active regions 112 of IC dies 100(1) and 100(2) may be achieved via conductive traces 120 in IC die 100(1), interconnects 304 between the planar interface between IC dies 100(1) and 100(2), and TSVs 202 in IC die 100(2); in such embodiments, TSVs 202 are in conductive contact with interconnects 304 between IC dies 100(1) and 100(2). In other embodiments (not shown), the metallization stacks 102 of IC dies 100(1) and 100(2) may be in contact in a face-to-face configuration. In still other embodiments (not shown), the substrates 110 of IC dies 100 ( 1 ) and 100 ( 2 ) may be contacted in a back-to-back configuration.

[0094] In various embodiments, the IC die 100 can be arranged in parallel rows with each other so that there are gaps 312 between adjacent IC die 100. In some embodiments, the gaps 312 can be consistent across the microelectronic assembly 300, and the gaps 312 can be on the order of a few millimeters (e.g., less than 5 millimeters); in other embodiments, the gaps 312 can be inconsistent, with some IC die 100 being closer to each other than other IC die 100. In some such embodiments, the IC die 100 can include circuits that consume power and generate heat during operation. For example, the IC die 100 can include computing circuits of a microprocessor. The gaps 312 can be configured to allow a cooling fluid to flow through them. In some embodiments, the cooling fluid (not shown) can be air; in other embodiments, the cooling fluid can be a liquid coolant.

[0095] Figure 3C313 is a schematic cross-sectional view of a portion 313 of a microelectronic assembly 300 according to some embodiments of the present disclosure. The IC die 302 may include a metallization stack 314 attached to a substrate 316 having an active region 318. The substrate 316 is attached to the metallization stack 314 along another planar interface 320 parallel to the surface 306. In some embodiments, the active region 318 includes an active circuit 204 (not shown), which includes a transistor and a diode. In such embodiments, the active region 318 may be near the planar interface 320. In some embodiments, the active region 318 may not be present. The metallization stack 314 includes a conductive trace 322 in the dielectric material 310. The conductive trace 322 may be coupled to the bonding pad 308 through a conductive via 324.

[0096] Figure 3D According to some embodiments of the present disclosure Figure 3A Schematic cross-sectional view of a portion 313 of a microelectronic assembly 300 .

[0097] IC die 302 may be substantially similar to Figure 3C , except that it is inverted so that the substrate 316 is close to the IC die

[0098] 100. In such embodiments, the IC die 302 may include an interface layer 326 (e.g., a bonding layer) on a side of the substrate 316 opposite the metallization stack 314. The interface layer 326 includes a bonding pad 308 and a dielectric material 328, such that the interconnect 304 is formed by a metal-to-metal bond of the bonding pads 124 and 308 and a dielectric-to-dielectric bond of the dielectric materials 116 and 328. In some embodiments, the dielectric material 328 is the same as the dielectric material 310. In some embodiments, the dielectric material 328 is the same as the dielectric material 116 of the IC die 100. In various embodiments, the dielectric material 328 includes silicon oxide, silicon nitride, silicon carbonitride, and other such inorganic materials commonly used in the manufacture of semiconductor IC dies. In such embodiments, the IC die 302 may also include a TSV 330 in the substrate 316 between the interface layer 326 and the metallization stack 314. TSVs 330 may enable electrical connection between interconnects 304 and active regions 318 and / or conductive traces 322 in IC die 302 .

[0099] Figure 4 is a schematic cross-sectional view of another example microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 3A302, except that IC die 302 can be coupled to a stack of other IC dies 402 (e.g., 402(1), 402(2), etc.) such that IC die 302 is the topmost one in the stack of IC dies 402. In some embodiments, the stack of IC dies 402 (including IC die 302) can include high bandwidth memory (HBM) circuitry, and the vertically stacked IC die 100 on IC die 302 can include computing circuitry that can directly interface with the HBM circuitry through interconnects 304 and TSVs (not shown) in IC die 302 and IC die 402. Various other circuit configurations are also included within the broad scope of the embodiments disclosed herein.

[0100] Figure 5A 3 is a simplified top view of a microelectronic assembly 300 according to some embodiments of the present disclosure. Multiple IC dies 100 may be coupled to a surface 306 of an IC die 302 on respective surfaces 104. The embodiment shown in the figure includes Figure 3A 31 , except that the IC die 100 are arranged in a regular array 502 consisting of rows (or columns) with gaps 312 between the IC die 100. The gaps 312 can be uniform in some embodiments and can be non-uniform in other embodiments. The gaps 312 can be configured to allow cooling fluid to flow over and around the IC die 302. In the embodiment shown, each IC die 100 can span the width (or length) of the IC die 302; for example, the IC die 302 can be approximately 33 to 35 millimeters wide, and the IC die 100 can also have similar dimensions along the mutual contact area with the IC die 302. In some embodiments, the IC die 100 can be arranged in both rows and columns, depending on the area availability on the surface 306 of the IC die 302.

[0101] In some embodiments (as shown), the metallization stack 102 of any one of the IC dies 100 in any row (or column) of the array 502 is proximate to the substrate 110 of the adjacent IC die 100 in the same row (or column). In some other embodiments (not shown), the metallization stacks 102 or substrates 110 of the adjacent IC dies 100 in any row (or column) of the array 502 face each other. In still other embodiments (not shown), in some rows (or columns), the metallization stack 102 of any one of the IC dies 100 in any row (or column) of the array 502 may be proximate to the substrate 110 of the adjacent IC die 100 in the same row (or column), and in other rows (or columns), the metallization stacks 102 or substrates 110 of the adjacent IC dies 100 in any row (or column) may face each other.

[0102] In some embodiments, IC die 100 may include computing circuits, and IC die 302 may include on-chip network circuits that conductively couple an array of IC die 100. In some other embodiments, some IC die 100 may include graphics processing circuits, and other IC die may include computer circuits, and IC die 302 may include memory circuits. Any suitable circuit configuration may be provided between IC die 100 and IC die 302 in microelectronic assembly 300, as desired and based on particular requirements.

[0103] Figure 5B yes Figure 5A 300 . Note that for ease of illustration and to avoid cluttering the drawing, the figure is not drawn to scale and detailed features are not shown. Multiple IC dies 100 can be coupled to a surface 306 of an IC die 302 on respective surfaces 104. In various embodiments, the IC die 302 can be large in size, for example, as large as a conventional reticle, which occupies an area of ​​about 850 square millimeters. The IC die 100 can be uniform in size, for example, the contact area between the IC die 100 and the IC die 302 is approximately in the range of between 25 millimeters by 100 microns and 33 millimeters by 100 microns, and the height of the IC die 100 above the surface 306 of the IC die 302 does not exceed 5 millimeters. In some other embodiments, the contact area between any one IC die 100 and the IC die 302 can be approximately 5 millimeters by 100 microns, and the height of the IC die 100 above the surface 306 of the IC die 302 can be no more than 35 millimeters.

[0104] Figure 61 is a simplified cross-sectional perspective view of a portion of an example IC die 100 according to various embodiments. The metallization stack 102 of the IC die 100 may have: a surface 602 orthogonal to the surfaces 104 and 106; a surface 604 parallel to the surface 104 and orthogonal to the surfaces 106 and 602; a surface 606 parallel to the surface 602 and orthogonal to the surfaces 104, 604, and 106. One or more of these surfaces (e.g., surfaces 104, 106, 602, 604, and / or 606) may be flat and planar, with a surface roughness of less than 10 angstroms and a TTV of less than 3 microns. More than one of these surfaces 104, 106, 602, 604, and 606 may further include bonding pads 124. In various embodiments, the bonding pads 124 on each of the surfaces 104, 106, 602, 604, and 606 may have different sizes and spacings. In some embodiments, the bond pads 124 on the surface 106 may all have a uniform size, while the bond pads on the surfaces 104 , 602 , 604 , and 606 may have bond pads 124 that increase in size as they get closer to the surface 106 .

[0105] Figure 7 304 is a schematic cross-sectional view of a microelectronic assembly 300 according to some embodiments of the present disclosure. The microelectronic assembly 300 includes IC dies 100 coupled end-to-end to each other along surfaces 104 and 114 that are orthogonal to respective planar interfaces 108 between respective metallization stacks 102 and substrates 110. Respective conductive traces 120 (not labeled so as not to clutter the drawing) are parallel to respective planar interfaces 108 and orthogonal to respective surfaces 104. For example, IC dies 100(1) and 100(2) are coupled along a common surface 104 that is orthogonal to respective planar interfaces 108(1) and 108(2). The metallization stack 102(1) of the IC die 100(1) is in direct contact with the metallization stack 102(2) and is conductively coupled to the metallization stack 102(2) through interconnects 304. Substrate 110(1) of IC die 100(1) is in direct contact with substrate 110(2) of IC die 100(2) along surface 114. In some embodiments, substrate 110(1) may be bonded to substrate 110(2) by oxide-oxide or other inorganic dielectric-inorganic dielectric bonding.

[0106] In some embodiments, IC die 100 may be coupled along a surface 604 that is parallel to surface 104. For example, IC die 100(2) and 100(3) are coupled along a common surface 604 that is orthogonal to respective planar interfaces 108(2) and 108(3) and parallel to surface 104. Metallization stack 102(2) of IC die 100(2) is in direct contact with metallization stack 102(3) and is conductively coupled to metallization stack 102(3) at least via dielectric-to-dielectric bonds (not labeled). In some embodiments (not shown) where surface 604 includes bonding pads, interconnects 304 including metal-to-metal bonds and dielectric-to-dielectric bonds may be present between IC die 100(2) and 100(3). Substrate 110(2) of IC die 100(2) is in direct contact with substrate 110(3) of IC die 100(3) along surface 702. In some embodiments, substrate 110 ( 2 ) may be bonded to substrate 110 ( 3 ) by oxide-oxide or other inorganic dielectric-inorganic dielectric bonding.

[0107] Figure 8 is a schematic cross-sectional view of a microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to Figure 3A The embodiment in FIG. 1 is different in that IC die 100 ( 1 ) is coupled end-to-end with IC die 100 ( 2 ) to form a stack of IC dies. Therefore, Figure 3A Any single IC die 100 in Figure 8 104. The embodiment shown is replaced by a corresponding stack of IC die 100 coupled end-to-end as further described. IC die 100(1) and 100(2) can be in direct contact end-to-end along a surface 604 opposite to surface 104 of IC die 100(1). Conductive trace 120(1) of IC die 100(1) can be conductively coupled to conductive trace 120(2) of IC die 100(2) via interconnect 304 on surface 604. Substrates 110(1) and 110(2) can be in direct contact at surface 702. In some embodiments, substrates 110(1) and 110(2) (surface 114) can be bonded along common surface 702 via dielectric-to-dielectric bonding.

[0108] As reference Figure 3AAs depicted, IC die 100(1) can be in contact with surface 306 of IC die 302 along surface 104. Conductive traces 120(1) of IC die 100(1) can be conductively coupled to conductive traces 322 of IC die 302 via interconnects 304 on surface 306. Surface 114 of substrate 110(1) of IC die 100(1) can be in contact with surface 306 of IC die 302. In some embodiments, surface 114 can be bonded to surface 306 via dielectric-to-dielectric bonding. In some embodiments, IC die 302 includes a metallization stack 314 attached to a substrate 316 having an active region 318. Substrate 316 is attached to metallization stack 314 along a planar interface 320 that is parallel to surface 306. In some embodiments, active region 318 includes active circuitry 204 (not shown), including transistors and diodes. In such embodiments, active region 318 can be proximate planar interface 320. In some embodiments, active area 318 may not be present. Metallization stack 314 includes conductive traces 322 in dielectric material 310. In some embodiments, microelectronic assembly 300 also includes multiple stacks of IC die 100 arranged in mutually parallel rows and columns, with a "bottom" IC die 100 coupled to surface 306 of IC die 302. Although only two IC die 100 are shown in any one "vertical" stack, any number of IC die 100 may be coupled together to form a stack as desired, based on particular requirements, and as permitted by the mechanical integrity specifications of microelectronic assembly 300.

[0109] Fig. 9 is a schematic cross-sectional view of a microelectronic assembly 300 according to some embodiments of the present disclosure. The embodiment shown in the figure is substantially similar to Figure 8 1 and 3. The embodiment of the present invention is different in that surface 104(2) of IC die 100(2) is coupled to another IC die 302(2). Thus, the configuration provides two parallel IC dies 302(1) and 302(2) with multiple stacks of IC dies 100 orthogonally coupled therebetween. Respective surfaces 104(1) and 104(2) of IC dies 100(1) and 100(2) can be coupled to respective surfaces 306(1) and 306(2) of IC dies 302(1) and 302(2) via interconnects (not shown). Any number of IC dies 100 can be included in each stack as permitted by the mechanical integrity of microelectronic assembly 300 and other design conditions. Power can be delivered to IC die 302 via one or more IC dies 100(1) and 100(2).

[0110] Fig.10is a schematic cross-sectional view of a microelectronic assembly 300 according to some embodiments of the present disclosure. Figure 3A The IC dies 302(1) and 302(2) are parallel to each other and orthogonal to the IC die 100. Multiple IC dies 100(1) and 100(2) can be arranged in an array of rows and columns on the respective IC dies 302(1) and 302(2) as needed based on specific requirements as described with reference to FIG. 5 .

[0111] In addition, surface 104(1) of IC die 100(1) is coupled to surface 306(1) of IC die 302(1) via interconnects 304. Surface 604 of IC die 100(1) is coupled to surface 1002 of IC die 302(2) via other interconnects 304. Surface 306(2) of IC die 302(2) is coupled to surface 104(2) of IC die 100(2) via further other interconnects 304. Metallization stack 314(2) of IC die 302(2) may be conductively coupled to interconnects 304 at surface 1002 via TSVs 330 that pass through substrate 316(2) of IC die 302(2). As in other embodiments described herein with reference to other figures, bonding surfaces 104(1) and 104(2) are orthogonal to planar interfaces 108(1) and 108(2) and parallel to surfaces 306(1) and 306(2) and parallel to planar interfaces 320(1) and 320(2). In some embodiments, not all IC dies 100(1) may be coupled to IC die 302(2) via interconnect 304. In such embodiments, IC die 100(1) (e.g., IC die 100(1A)) is not coupled to IC die 302(2) via interconnect 304, but may be bonded to substrate 316(2) via dielectric-to-dielectric bonding (not shown). Power may be delivered to IC die 302(2) via one or more IC dies 100(1).

[0112] Note that although only two IC dies 302 are shown stacked in parallel with IC die 100 between them, any number of IC dies 302 may be stacked as desired and based on particular needs as mechanical integrity specifications and other requirements of microelectronic assembly 300 may allow.

[0113] Fig.11 is a simplified cross-sectional view of an embodiment of a microelectronic assembly 300. The microelectronic assembly 300 shown in the figure is substantially similar to Figure 3A312, except that the dielectric material 1102 can encapsulate various components of the microelectronic assembly 300. For example, the dielectric material 1102 can surround the IC die 100 (e.g., in the gap 312) and contact the surface 306 of the IC die 302. In various embodiments, the dielectric material 1102 includes an inorganic dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the dielectric material 1102 includes an organic polymer with a thermally conductive filler. In other embodiments, the dielectric material 1102 includes an organic polymer without a thermally conductive filler. In some embodiments, for example, depending on the specific size of the IC die 100 (e.g., the height of the IC die 100 above the IC die 302 is large relative to the contact area between the IC die 100 and the IC die 302), the dielectric material 1102 can provide mechanical stability to the IC die 100. In other embodiments, the dielectric material 1102 can provide heat transfer capabilities for conducting heat away from the IC die 100.

[0114] Fig.12 is a schematic cross-sectional view of a microelectronic assembly 300 according to some embodiments of the present disclosure. The microelectronic assembly 300 shown in the figure is substantially similar to Fig.10 1 and 302 (2)). In some embodiments, dielectric material 1102 may be provided to encapsulate various components of microelectronic assembly 300, except that dielectric material 1102 may encapsulate various components of microelectronic assembly 300. For example, dielectric material 1102 may surround IC die 100(1) and 100(2) (e.g., in gap 312) and contact surfaces 306(1) and 306(2) of IC die 302(1) and 302(2), respectively. In some embodiments, dielectric material 1102 may provide mechanical stability to IC die 100(1) and 100(2), for example, depending on the particular dimensions of IC die 100 (e.g., the number of IC die 100(1) between IC die 302(1) and 302(2)). In other embodiments, dielectric material 1102 may provide thermal transfer capabilities for conducting heat away from IC die 100(1) and / or 100(2).

[0115] In some embodiments (not shown), the material of dielectric material 1102 disposed above IC die 302(2) may be different than the material disposed below IC die 302(2). For example, an inorganic material may be around IC die 100(1) and an organic thermally conductive material may be around IC die 100(2). In some embodiments (not shown), dielectric material 1102 may be present between IC die 302(1) and 302(2) but not around IC die 100(2), or vice versa.

[0116] Fig.13FIG. 3 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. The microelectronic assembly 300 shown in the figure is substantially similar to FIG. Fig. 9 1 and 302 (2)). In some embodiments, dielectric material 1102 may be provided to encapsulate various components of microelectronic assembly 300, except that dielectric material 1102 may encapsulate various components of microelectronic assembly 300. For example, dielectric material 1102 may surround IC die 100(1) and 100(2) (e.g., in gap 312) and contact surfaces 306(1) and 306(2) of IC die 302(1) and 302(2), respectively. In some embodiments, dielectric material 1102 may provide mechanical stability to IC die 100(1) and 100(2), for example, depending on the particular dimensions of IC die 100 (e.g., the number of IC die 100(1) between IC die 302(1) and 302(2)). In other embodiments, dielectric material 1102 may provide thermal transfer capabilities for conducting heat away from IC die 100(1) and / or 100(2).

[0117] In various embodiments, reference Figures 1 to 13 Any of the features discussed herein may be combined with any other features to form a package having one or more IC dies as described herein, for example, to form a modified IC die 100 or a modified microelectronic assembly 300. Some such combinations are described above, but further combinations and modifications are possible in various embodiments. In addition, within the broad scope of the embodiments, the features described herein may be combined in a suitable manner based on specific needs. Figures 1 to 13 Various embodiments described in any of .

[0118] Example Method

[0119] FIG. 14A to FIG. 14K is a schematic cross-sectional view of various stages of fabrication of a microelectronic assembly 300 according to some embodiments of the present disclosure. Fig.14A 14 is a simplified cross-sectional view of an assembly 1400 including a carrier 1402 to which a wafer 1404 is attached (e.g., fused, bonded) by a layer of attachment material 1406. In various embodiments, the carrier 1402 comprises a wafer of any solid material capable of withstanding the temperatures, pressures, and chemicals used in semiconductor processing; examples of the carrier 1402 include semiconductor wafers, glass wafers, ceramic wafers, and the like. In some embodiments, the attachment material 1406 is silicon oxide. In the orientation shown in the figure (by way of example only), the carrier 1402 is positioned relative to the wafer 1404 such that the wafer 1404 is horizontal, the carrier 1402 is below the wafer 1404, and the surface of the wafer 1404 opposite the carrier 1402 faces upward.

[0120] Wafer 1404 may include a plurality of IC dies 100 (not specifically shown), as shown in FIG. Figure 1 1404. The IC die 100 of FIG. 1404 may be similar to each IC die 100 described in the other figures. For example, each IC die may include a metallization stack 102 attached to a substrate 110, wherein the conductive traces 120 are parallel to a planar interface 108 (not labeled) between the metallization stack 102 and the substrate 110. Each IC die 100 may be as wide and as long as any other IC die in the wafer 1404. The metallization stack 102 of the IC die 100 may be close to the carrier 1402 and fused to the carrier 1402 by the attaching material 1406. In some embodiments (as shown), the substrate 110 may have a thickness of about 700 microns, so that the TSVs 202 are buried inside the substrate 110 and may not be exposed on the surface of the substrate 110 opposite the carrier 1402.

[0121] Fig. 14B is a simplified cross-sectional view of assembly 1420 after further processing of assembly 1400. Wafer 1404 may be polished (e.g., thinned) such that TSVs 202 may be exposed on a surface 1412 of wafer 1404, surface 1412 being opposite to carrier 1402. Interface layer 1414 may be formed on surface 1412. For example, wafer 1404 having a thickness ranging between 700 microns and 800 microns prior to planarization may be thinned to a thickness of approximately 50 microns to 100 microns after planarization.

[0122] In some embodiments, the interface layer 1414 may include a metal bonding pad 1416 in a dielectric material 1418 (such as silicon oxide). In multiple embodiments, the interface layer 1414 may be sacrificed and destroyed in subsequent operations. In some embodiments, a layer of attachment material 1406 may be formed on the surface 1412 before forming the interface layer 1414. The interface layer 1414 may be formed using any known process in the art, including a semi-additive process (SAP). For example, the bonding pad 1416 may be deposited first, and then the dielectric material 1418 may be deposited around the bonding pad 1416. In other embodiments, the dielectric material 1418 may be deposited and etched to create a via for forming the bonding pad 1416. In some embodiments, the bonding pad 14116 may not be formed at all. The interface layer 1414 may also include another layer of attachment material 1406. These described operations may result in the formation of a tier 1424 including features and materials between the attach material 1406 in contact with the carrier wafer 1402 and the attach material 1406 on an exposed surface of the assembly 1420 opposite the carrier wafer 1402. The tier 1424 includes the thinned wafer 1404, the interface layer 1414, and the layers of attach material 1406.

[0123] Fig. 14C is a simplified cross-sectional view of assembly 1430 after further processing of assembly 1420. Fig. 14B The described operations may be repeated multiple times, each time forming a separate level 1424, so that the assembly 1430 includes a stack of levels 1424 above the carrier 1402. In some embodiments, the assembly 1430 may include a stack of 5 to 10 wafers. Any number of levels 1424 may be formed above the carrier 1402 as permitted by various manufacturing constraints beyond the scope of the present disclosure. In some embodiments, the number of levels 1424 may be determined by the desired thickness of the assembly 1430. For example, the desired thickness may not exceed 2 millimeters. Depending on whether the interface layer 1414 includes a metal bonding pad 1416, adjacent wafers 1404 may be conductively coupled to each other. In embodiments where the metal bonding pad 1416 is not present, adjacent wafers 1404 may not be conductively coupled.

[0124] Fig.14D 14 is a simplified cross-sectional view after further processing of assembly 1430. A second carrier 1402 can be attached to a surface of the topmost wafer opposite carrier 1402 in assembly 1430. The stack of levels 1424 with carriers 1402 on the top and bottom can be singulated (e.g., sliced, diced) vertically into multiple stacks. The individual IC dies 100 can be configured as shown in reference Figure 1 The surfaces 104 (not labeled) of the bond pads described are singulated to produce cut surfaces 1442, each cut surface 1442 being orthogonal to the interface between adjacent wafers 1404 (and / or levels 1424). Each stack 1440 can be as wide (and / or as long) as any one of the IC dies 100. For example, in some embodiments where singulation is performed so that each stack 1440 is as wide as any one of the IC dies 100, each stack can be no more than 5 mm wide and no more than 25 mm long (e.g., 50 mm long or 100 mm long). In some other embodiments where singulation is performed so that each stack 1440 is as long as any one of the IC dies 100, each stack can be more than 5 mm wide (e.g., 10 mm wide, 20 mm wide, etc.) and no more than 25 mm long. In further other embodiments, singulation can be performed so that each stack 1440 is as wide and as long as any one of the IC dies 100, for example, no more than 5 mm wide and no more than 25 mm long. In some embodiments, the thickness of stack 1440 may not exceed 2 mm.

[0125] Fig.14Eis a simplified cross-sectional view of the stack 1440 after being rotated ninety degrees so that the cut surfaces 1442 are horizontal (eg, on the top and bottom) and the carrier 1402 is on the side, as are the planar interfaces between adjacent wafers 1404 (or levels 1424).

[0126] Fig.14F and Figure 14G is a simplified cross-sectional perspective view of stack 1440 . Fig.14F Before rotating ninety degrees (e.g., as shown along Fig.14D ) in the orientation shown in FIG. 1 , and Figure 14G After a ninety degree rotation (e.g., as shown in FIG. Fig.14E Stack 1440 having an orientation shown in FIG.

[0127] Fig.14H is a simplified cross-sectional view of assembly 1450 after further processing of stack 1440. Multiple stacks 1440 are attached to a horizontal bonding surface 1452 of another carrier 1402 such that the interface between adjacent wafers 1404 (or levels 1424) is orthogonal to the bonding surface of carrier 1402. In some embodiments, a layer of attach material 1406 on surface 1452 can facilitate bonding of stack 1440 to carrier 1402. In such a configuration, cut surface 1442 of stack 1440 is opposite surface 1452 of carrier 1402.

[0128] Fig.14I 14 is a simplified cross-sectional view of assembly 1460 after further processing of assembly 1450. Gap filler material 1462 may be deposited around multiple stacks 1440 above surface 1452 of carrier 1402. Sufficient gap filler material 1462 may be deposited so that gap filler material 1462 extends over the entire height of stacks 1440 above surface 1452 such that a continuous horizontal surface (opposite surface 1452 of carrier 1402) including gap filler material 1462 and surfaces 1442 of vertical stacks 1440 is exposed. The gap filler material may include an organic dielectric material suitable for a subsequent polishing operation during which the continuous horizontal surface is planarized to expose bond pads 124 of individual IC dies 100. As described with reference to Figure 1 As discussed, each bond pad 124 is a portion of the conductive trace 120 that is exposed on the side surface 104 of the IC die 100 .

[0129] Fig.14J14 is a simplified cross-sectional view of assembly 1470 after further processing of assembly 1460, wherein horizontal carrier 1402 is debonded by any means known in the art. In some embodiments, stack 1440 can be rotated 180 degrees so that the surface previously bonded to horizontal carrier 1402 is exposed on the top. Horizontal carrier 1402 can be attached to a planarized surface, and planarization of the top surface is performed to expose bonding pads thereon. In some embodiments, depending on the final configuration of IC die 100 in microelectronic assembly 300, this second planarization process can be omitted.

[0130] In some embodiments, the assembly 1470 may be further singulated so that each stack is as wide and as long as the individual IC dies. Fig.14D As described, if the stack 1440 is formed by singulation along the width of the IC die 100, then in the operation as described herein, singulation is performed along the length of the IC die 100; on the other hand, in the previous operation, as described in reference Fig.14D As described, if stack 1440 is formed by singulation along the length of IC die 100, then in operations as described herein, singulation is performed along the width of IC die 100. In embodiments where assembly 1470 includes stack 1440 that is as wide and as long as IC die 100 (e.g., no more than 5 mm wide and no more than 25 mm long in some embodiments), no further singulation may be performed at this stage of the operation.

[0131] In some embodiments, the stack may be subjected to planarization of all cut surfaces so that all four side surfaces and corresponding edges of any IC die 100 are planarized and the bonding pads 124 are exposed thereon, for example, as described in reference Figure 6 Subsequently, the gap filling material 1602 may be removed, for example by etching with a cleaner, and the carriers 1402 on the individual stacks may be debonded.

[0132] Figure 14K The results at the end of the treatment are shown in FIG. Figures 1 to 13Individual IC dies 100 are described. Each individual IC die 100 may be separated from the other IC dies within stack 1440 by suitable means known in the art. Separation may include destroying (e.g., sacrificing) interface layer 1414 while separating IC dies 100 from one another, for example, by chemical mechanical polishing (CMP) of interface layer 1414. In some embodiments, interface layer 1414 may be retained on edge dies (e.g., topmost or bottommost) in stack 1440, while interface layer 1414 may be removed from other dies in stack 1440. For example, interface layer 1414 is retained in some IC dies (e.g., in scenarios where such IC dies are bonded to other components, carriers, bulk silicon, etc.), so that bond pads may be desired on the top (or bottom) surface for further processing as needed and based on specific requirements.

[0133] Although FIG. 14 shows various operations performed in a particular order, this is merely illustrative, and the operations discussed herein may be appropriately reordered and / or repeated. In addition, additional processes not shown may also be performed without departing from the scope of the present disclosure. In addition, the various operations discussed herein for FIG. 14 may be modified according to the present disclosure to manufacture other microelectronic packages in the microelectronic package 300 disclosed herein. Although each of the various operations is shown once in FIG. 14, the operations may be repeated frequently as needed. For example, one or more operations may be performed in parallel to manufacture and test a plurality of microelectronic packages substantially simultaneously. In another example, operations may be performed in different orders to reflect the structure of a specific microelectronic package in which one or more substrates or other components as described herein may be included.

[0134] In addition, the operations shown in Figure 14 can be combined or can include more details than those described. For example, without departing from the scope of the present disclosure, the operations can be modified in a suitable manner so that the IC die 100 does not have a semiconductor substrate but is manufactured on other materials such as glass or ceramic materials. Further, the various operations shown and described can also include other manufacturing operations related to the manufacture of other parts of the microelectronic assembly described herein, or other manufacturing operations related to the manufacture of any device that may include the microelectronic assembly as described herein. For example, operations not shown in Figure 14 can include various cleaning operations, additional surface planarization operations, operations for surface roughening, operations for including barrier layers and / or adhesion layers as needed, and / or operations for incorporating the microelectronic package as described herein into an IC component, a computing device, or any desired structure or device or incorporating the microelectronic package as described herein with an IC component, a computing device, or any desired structure or device.

[0135] Example Equipment and Parts

[0136] The packages disclosed herein (e.g., Figure 1-1 4 or any further embodiments described herein) may be included in any suitable electronic component. Figure 15-17 Various examples of packages, components, and devices are shown that may be used with or include any of the IC packages as disclosed herein.

[0137] Fig.15 is a side cross-sectional view of an example IC package 2200, which may include an IC package according to any embodiment disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0138] As shown, the package substrate 2252 may be formed of an insulator (e.g., ceramic, a built-up film, an epoxy film with filler particles therein, etc.), and may have conductive pathways extending through the insulator between the first side 2272 and the second side 2274, or extending between different locations on the first side 2272, and / or extending between different locations on the second side 2274. These conductive pathways may take the form of any of the interconnect structures including wires and / or vias.

[0139] The packaging substrate 2252 may include conductive contacts 2263, which are coupled to conductive paths 2262 passing through the packaging substrate 2252, thereby allowing the circuits within the tube core 2256 and / or the interposer 2257 to be electrically coupled to individual conductive contacts in the conductive contacts 2264 (or to other devices not shown included in the packaging substrate 2252).

[0140] IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257, first level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first level interconnects 2265 shown in the figure are solder bumps, but any suitable first level interconnects 2265 may be used, such as solder bumps, solder pillars, or bond wires.

[0141] The IC package 2200 may include one or more dies 2256, which are coupled to the interposer 2257 via the conductive contacts 2254 of the dies 2256, the first-level interconnects 2258, and the conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, thereby allowing the circuitry within the die 2256 to be electrically coupled to individual conductive contacts in the conductive contacts 2261 (or to other devices not shown included in the interposer 2257). The first-level interconnects 2258 shown in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder columns, or bond wires. As used herein, "conductive contacts" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; the conductive contacts may be recessed into the surface of a component, flush with the surface of a component, or extend away from the surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0142] In some embodiments, an underfill material 2266 may be disposed around the first level interconnect 2265 between the package substrate 2252 and the interposer 2257, and a molding 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. An example material that may be used for the underfill material 2266 and the molding 2268 is a suitable epoxy. A second level interconnect 2270 may be coupled to the conductive contacts 2264. The second level interconnect 2270 shown in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second level interconnect 2270 may be used (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement). The second level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference Fig.16 discussed.

[0143] In various embodiments, any of the dies 2256 may be a microelectronic assembly 300 as described herein. In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The die 2256 may include circuits that perform any desired functions. For example, in addition to one or more of the dies 2256 being a microelectronic assembly 300 as described herein, one or more of the dies 2256 may be a logic die (e.g., a silicon-based die), one or more of the dies 2256 may be a memory die (e.g., an HBM), etc. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0144] Although the IC package 2200 shown in the figure is a flip chip package, other packaging architectures can be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 can include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0145] In some embodiments, interposer 2257 may not be included in IC package 2200 ; instead, die 2256 may be coupled directly to conductive contacts 2263 at first side 2272 via first level interconnects 2265 .

[0146] Fig.16is a cross-sectional side view of an IC device assembly 2300, which may include components having one or more microelectronic assemblies 300 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposing second side 2342 of the circuit board 2302; typically, the components may be disposed on one or both of the sides 2340 and 2342. In particular, any suitable component among the components of the IC device assembly 2300 may include any of the one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may employ the IC packages discussed above with reference to the IC device assembly 2300. Fig.15 The IC package 2200 may be in the form of any of the embodiments discussed.

[0147] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 2302 (optionally in combination with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB packaging substrate.

[0148] As shown, in some embodiments, the IC device assembly 2300 can include a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling feature 2316. The coupling feature 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (as shown), protrusions and recesses of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0149] Package structure 2336 on interposer may include IC package 2320 coupled to interposer 2304 via coupling component 2318. Coupling component 2318 may take any suitable form depending on the desired functionality, such as the forms discussed above with reference to coupling component 2316. In some embodiments, IC package 2320 may be or include, for example, as described above with reference to Fig.15 IC package 2200 is described. In some embodiments, IC package 2320 may include at least one microelectronic assembly 300 as described herein. In order not to clutter the drawings, microelectronic assembly 300 is not shown in detail.

[0150] Although a single IC package 2320 is shown, multiple IC packages can be coupled to the interposer 2304; indeed, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can redistribute connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling component 2316 to facilitate coupling to the circuit board 2302.

[0151] In the embodiment shown in the figure, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0152] The interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 2304 may be formed of alternative rigid or flexible materials, which may include materials such as silicon, germanium, and other III-V and IV materials as described above for use in semiconductor substrates. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 may also include embedded devices 2314, including both passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 2304. The interposer-on-package structure 2336 may take the form of any interposer-on-package structure known in the art.

[0153] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0154] In some embodiments, the IC device assembly 2300 may include a package-on-package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332, which are coupled together via a coupling component 2330, such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling component 2316 discussed above, and the IC packages 2326 and / or 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any of the package-on-package structures known in the art.

[0155] Fig.17 2400, which may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable component in the components of computing device 2400 may include a microelectronic assembly (e.g., 100) according to any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include IC package 2200 (e.g., as Fig.15 In yet another example, any one or more of the components of computing device 2400 may include IC device assembly 2300 (e.g., Fig.16 shown).

[0156] The figure shows that multiple components are included in the computing device 2400, but any one or more of these components can be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the computing device 2400 can be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system on chip (SOC) die.

[0157] Additionally, in various embodiments, computing device 2400 may not include one or more of the components shown in the figure, but computing device 2400 may include interface circuitry for coupling to the one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0158] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0159] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications to transmit data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wiring, although in some embodiments they may not.

[0160] The communication chip 2412 can implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendment), LTE project and any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an abbreviation standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing of the IEEE802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 can operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols named 3G, 4G, 5G and higher versions. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0161] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 2412 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, while the second communication chip 2412 can be dedicated to wired communications.

[0162] The computing device 2400 may include a battery / power circuit 2414. The battery / power circuit 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

[0163] Computing device 2400 may include a display device 2406 (or corresponding interface circuitry as discussed above). For example, display device 2406 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0164] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds, for example.

[0165] Computing device 2400 may include audio input device 2418 (or corresponding interface circuitry as discussed above). Audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0166] Computing device 2400 may include GPS device 2416 (or corresponding interface circuitry as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0167] Computing device 2400 may include other output devices 2410 (or corresponding interface circuitry as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0168] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0169] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0170] Select Example

[0171] The following paragraphs provide various examples of the embodiments disclosed herein.

[0172] Example 1 provides an IC die (eg, 100), including (eg, Figure 1 ): a first region (e.g., 102) having a first surface (e.g., 104) and a second surface (e.g., 106), the first surface being orthogonal to the second surface; and a second region (e.g., 110, 112) attached to the first region along a planar interface (e.g., 108) that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface (e.g., 114) that is coplanar with the first surface; wherein: the first region comprises: a dielectric material (e.g., 116); a plurality of layers (e.g., 118) of conductive traces (e.g., 120) in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; a conductive via (e.g., 122) passing through the dielectric material, the conductive via being orthogonal to the conductive trace; and a bonding pad (e.g., 124) on the first surface, the bonding pad comprising a portion of the conductive trace exposed on the first surface, and the second region comprising a material different from the dielectric material.

[0173] Example 2 provides the IC die of Example 1, wherein the second region includes a semiconductor material.

[0174] Example 3 provides the IC die of any of Examples 1-2, further comprising (e.g., Figure 2 ) TSVs (e.g., 202) in the second region.

[0175] Example 4 provides the IC die of any of Examples 1-3, wherein the second region includes at least one of a transistor and a diode (eg, 204 ) proximate a planar interface between the first region and the second region.

[0176] Example 5 provides the IC die of any of Examples 1-3, wherein the second region does not include any transistors or diodes.

[0177] Example 6 provides the IC die of any of Examples 1-5, wherein the first surface is flat and planar, wherein the surface roughness is less than 10 angstroms, and wherein the TTV of the entire first surface is less than 3 microns.

[0178] Example 7 provides the IC die of Example 6, wherein a surface opposite the first surface and orthogonal to the second surface is flat and planar, wherein the surface roughness is less than 10 angstroms and the TTV across the surface is less than 3 microns.

[0179] Example 8 provides the IC die of any of Examples 1-7, wherein the bond pads (eg, 124A, 124B) have different sizes.

[0180] Example 9 provides the IC die of any of Examples 1-8, wherein (e.g., Figure 6 ), the bonding pad includes a first bonding pad, and the first region also includes a second bonding pad on the second surface.

[0181] Example 10 provides the IC die of any of Examples 1-9, wherein the plurality of layers of conductive traces includes 2 to 6 layers.

[0182] Example 11 provides the IC die of any of Examples 1-10, wherein each of the plurality of layers of conductive traces has a thickness between 3 microns and 5 microns.

[0183] Example 12 provides the IC die of any of Examples 1-11, wherein: a linear dimension of a largest of the bond pads is less than 5 microns, and a pitch between adjacent bond pads is less than 9 microns.

[0184] Example 13 provides the IC die of any of Examples 1-12, wherein: the IC die is less than 100 microns along a first axis, less than 35 millimeters along a second axis orthogonal to the first axis, and less than 5 millimeters along a third axis orthogonal to the first axis and the second axis, and the first axis is parallel to the first surface and perpendicular to the second surface.

[0185] Example 14 provides the IC die of any of Examples 1-13, wherein the dielectric material includes a compound containing silicon and oxygen.

[0186] Example 15 provides the IC die of any of Examples 1-14, wherein the bond pad comprises copper.

[0187] Example 16 provides the IC die of any of Examples 1-15, wherein edges of the first surface and the second surface are planarized.

[0188] Example 17 provides the IC die of any of Examples 1-16, wherein the first region further includes (e.g., Figure 6 ): a bonding pad on the second surface (e.g., 106); a bonding pad on a fourth surface (e.g., 602), the fourth surface being orthogonal to the first surface (e.g., 104) and the second surface (e.g., 106); a bonding pad on a fifth surface (e.g., 604), the fifth surface being parallel to the first surface and orthogonal to the second surface and the fourth surface; and a bonding pad on a sixth surface (e.g., 606), the sixth surface being parallel to the fourth surface and orthogonal to the first surface, the second surface, and the fifth surface.

[0189] Example 18 provides the IC die of Example 17, wherein the first surface, the second surface, the fourth surface, the fifth surface, and the sixth surface are flat and planar, wherein the surface roughness is less than 10 angstroms and the TTV is less than 3 microns.

[0190] Example 19 provides the IC die of any of Examples 17-18, wherein the bond pads on any of the first surface, the second surface, the fourth surface, the fifth surface, and the sixth surface have different sizes and pitches.

[0191] Example 20 provides the IC die of any of Examples 17-18, wherein the bonding pads on the second surface have a uniform size, and the bonding pads on the first, fourth, fifth, and sixth surfaces increase in size as they approach the second surface.

[0192] Example 21 provides a microelectronic assembly (e.g., 300) including (e.g., Figure 3A-3B ): a first IC die (e.g., 100) coupled to a second IC die via interconnects (e.g., 304) on a first surface (e.g., 104) of the first IC die and a second surface (e.g., 306) of the second IC die (e.g., 302) such that the first surface is in contact with the second surface, wherein: the interconnects include dielectric-to-dielectric bonding and metal-to-metal bonding, the metal-to-metal bonding including a first bonding pad (e.g., 124) in the first IC die and a second bonding pad (e.g., 308) in the second IC die (e.g., Figure 3B ), the first IC die includes a substrate (e.g., 110, 112) attached to a metallization stack (e.g., 102) along a planar interface (e.g., 108) orthogonal to a first surface (e.g., 104), the metallization stack includes multiple layers (e.g., 118) of conductive traces (e.g., 120) in a dielectric material (e.g., 116), and a first bonding pad includes a portion of the conductive trace exposed on the first surface.

[0193] Example 22 provides the microelectronic assembly of Example 21, wherein (eg, FIG. 5 ) the area of ​​the second surface of the second IC die is approximately 850 square millimeters.

[0194] Example 23 provides the microelectronic assembly of any of Examples 21-22, further comprising (e.g., Fig.11 ): Another dielectric material (eg, 1102) surrounding the first IC die, the other dielectric material being in contact with a second surface of the second IC die.

[0195] Example 24 provides the microelectronic assembly of Example 23, wherein the other dielectric material includes an organic polymer having a thermally conductive filler.

[0196] Example 25 provides the microelectronic assembly of any of Examples 21-24, wherein the substrate of the first IC die contacts the second surface of the second IC die.

[0197] Example 26 provides the microelectronic assembly of any of Examples 21-25, wherein the substrate of the first IC die includes at least one of a transistor and a diode.

[0198] Example 27 provides the microelectronic assembly of any of Examples 21-26, wherein the first bond pad comprises a portion of the conductive trace exposed on the first surface.

[0199] Example 28 provides the microelectronic assembly of any of Examples 21-27, wherein the interconnects have a pitch of less than 10 microns between adjacent interconnects.

[0200] Example 29 provides the microelectronic assembly of any of Examples 21-28, wherein (for example, Figure 3C ): the substrate is a first substrate, the metallization stack is a first metallization stack, and the dielectric material is a first dielectric material, the second IC die includes a second metallization stack (e.g., 314) and a second substrate (e.g., 316, 318), the second substrate is attached to the second metallization stack along another planar interface (e.g., 320) parallel to the second surface (e.g., 306), and the second metallization stack includes a conductive trace (e.g., 322) in the second dielectric material (e.g., 310), and the conductive trace is coupled to the second bonding pad (e.g., 308) through a conductive via (e.g., 324).

[0201] Example 30 provides the microelectronic assembly of Example 29, wherein the dielectric-to-dielectric bond includes a first dielectric material of the first IC die and a second dielectric material of the second IC die.

[0202] Example 31 provides the microelectronic assembly of any of Examples 29-30, wherein the first dielectric material and the second dielectric material include a compound containing silicon and oxygen.

[0203] Example 32 provides the microelectronic assembly of any of Examples 29-31, wherein the second substrate includes at least one of a transistor and a diode.

[0204] Example 33 provides the microelectronic assembly of any of Examples 29-31, wherein the second substrate does not include any transistors or diodes.

[0205] Example 34 provides the microelectronic assembly of any of Examples 21-33, wherein (for example, Figure 3D ): the substrate is a first substrate, the metallization stack is a first metallization stack, the conductive trace is a first conductive trace, and the dielectric material is a first dielectric material, the second IC die includes a second metallization stack (e.g., 314), a second substrate (e.g., 316, 318), the second substrate is attached to the second metallization stack along another planar interface (e.g., 320) parallel to the second surface (e.g., 306), the second IC die also includes at least one interface layer (e.g., 326) on a side of the second substrate opposite to the second metallization stack, the interface layer includes a second bonding pad in a layer of a second dielectric material (e.g., 328), and the second metallization stack includes a second conductive trace (e.g., 322) in a third dielectric material (e.g., 310), the second conductive trace is coupled through a conductive via (e.g., 324).

[0206] Example 35 provides the microelectronic assembly of Example 34, wherein the second IC die further includes a TSV (eg, 330 ) in the second substrate between the interface layer and the second metallization stack.

[0207] Example 36 provides the microelectronic assembly of Example 35, wherein the TSV conductively couples the second bond pad with a second conductive trace in the second metallization stack.

[0208] Example 37 provides the microelectronic assembly of Example 21, further comprising (e.g., Figure 3A ) A plurality of first IC dies coupled to a second IC die along a corresponding first surface of the first IC die, wherein: each first IC die includes a corresponding substrate attached to a corresponding metallization stack along a corresponding planar interface, and the corresponding planar interface is orthogonal to the corresponding first surface.

[0209] Example 38 provides the microelectronic assembly of Example 37, wherein (for example, Figure 3A ): The planar interface is a first planar interface, at least two first IC dies among the multiple IC dies (for example, 100(1), 100(2)) are in contact with each other along a second planar interface orthogonal to the first surface, and the at least two first IC dies in contact are bonded along the second planar interface at least by dielectric-dielectric bonding.

[0210] Example 39 provides the microelectronic assembly of Example 38, wherein the at least two first IC dies are further bonded along the second planar interface by metal-to-metal bonding.

[0211] Example 40 provides the microelectronic assembly of Example 39, wherein: the corresponding metallization stack of one of at least two first IC dies contacts the corresponding substrate of another of at least two first IC dies along a second planar interface, the corresponding substrate of the other of at least two first IC dies includes a TSV (e.g., 202), and the TSV is in conductive contact with the metal-metal bond along the second planar interface.

[0212] Example 41 provides the microelectronic assembly of Example 39, wherein: the corresponding metallization stack of one of at least two first IC dies contacts the corresponding metallization stack of another of at least two first IC dies along a second planar interface, and the corresponding conductive traces in the at least two IC dies are conductively contacted along the second planar interface by metal-to-metal bonding.

[0213] Example 42 provides the microelectronic assembly of Example 38, wherein a respective substrate of one of the at least two first IC dies contacts a respective substrate of another of the at least two first IC dies along a second planar interface.

[0214] Example 43 provides the microelectronic assembly of any of Examples 37-42, wherein (for example, Fig.11 ): The first IC dies in the plurality of first IC dies are parallel to each other and spaced apart from each other, the microelectronic assembly further comprises another dielectric material (e.g., 1102) encapsulating the plurality of first IC dies, and the another dielectric material is in the space between adjacent first IC dies in the first IC dies.

[0215] Example 44 provides the microelectronic assembly of any of Examples 37-42, wherein (for example, Figure 3A ): The first IC dies among the plurality of first IC dies are parallel to each other, and there are gaps (eg, 312) between adjacent first IC dies among the first IC dies.

[0216] Example 45 provides the microelectronic assembly of Example 44, wherein the gap is uniform across the microelectronic assembly.

[0217] Example 46 provides the microelectronic assembly of Example 44, wherein the gap is non-uniform across the microelectronic assembly, wherein some of the first IC dies are closer together than other of the first IC dies.

[0218] Example 47 provides the microelectronic assembly of any of Examples 44-46, wherein the gap is configured for a cooling fluid to flow through the gap.

[0219] Example 48 provides the microelectronic assembly of Example 47, wherein the cooling fluid is air.

[0220] Example 49 provides the microelectronic assembly of Example 47, wherein the cooling fluid is a liquid coolant.

[0221] Example 50 provides the microelectronic assembly of any of Examples 47-49, wherein the first plurality of IC dies include circuits configured to consume power and generate heat during operation.

[0222] Example 51 provides the microelectronic assembly of any of Examples 21-50, further comprising (e.g., Figure 4 ) a stack of second IC dies, the first IC die being attached to a topmost one of the stack of second IC dies.

[0223] Example 52 provides the microelectronic assembly of any of Examples 37-51, wherein (eg, FIG. 5 ) the plurality of first IC dies are arranged in an array of rows and columns (eg, 502 ).

[0224] Example 53 provides the microelectronic assembly of Example 52, wherein the metallization stack of any one of the first IC dies in any row or column of the array is proximate to the substrate of an adjacent one of the first IC dies in the same row or column.

[0225] Example 54 provides the microelectronic assembly of Example 52, wherein the metallization stacks or substrates of adjacent first IC dies in any row or column of the array face each other.

[0226] Example 55 provides the microelectronic assembly of any of Examples 37-54, wherein the first IC die is conductively coupled through a conductive via in the second IC die.

[0227] Example 56 provides the microelectronic assembly of Example 21, wherein (for example, Fig.10): the planar interface is a first planar interface, the interconnect is a first interconnect, the first IC die (e.g., 100(1)) has a third surface (e.g., 604) opposite to the first surface (e.g., 104(1)), the microelectronic assembly further comprising: a third IC die (e.g., 302(2)) parallel to the second IC die, the third IC die having a fourth surface (e.g., 1002) and a fifth surface (e.g., 306(2)), the fifth surface being opposite to the fourth surface, the fourth surface being coupled to the third surface of the first IC die via a second interconnect; and a fourth IC die parallel to the first IC die, the fourth IC die having a sixth surface (e.g., 104(2)) ), the sixth surface is coupled to the fifth surface of the third IC die via a third interconnect, the second IC die includes a corresponding substrate (e.g., 318(1)) attached to a corresponding metallization stack (e.g., 314(1)) along a second planar interface (e.g., 320(1)) orthogonal to the first planar interface, the third IC die includes a corresponding substrate (e.g., 318(2)) attached to a corresponding metallization stack (e.g., 314(2)) along a third planar interface (e.g., 320(2)) orthogonal to the first planar interface, and the fourth IC die includes a corresponding substrate attached to the corresponding metallization stack along a fourth planar interface parallel to the first planar interface.

[0228] Example 57 provides the microelectronic assembly of Example 56, wherein the second interconnect and the third interconnect include dielectric-to-dielectric bonds.

[0229] Example 58 provides the microelectronic assembly of Example 57, wherein the second interconnect and the third interconnect further comprise metal-to-metal bonding.

[0230] Example 59 provides the microelectronic assembly of Example 58, wherein the metal-to-metal bond of the second interconnect includes a portion of a conductive trace in the metallization stack of the first IC die that is exposed at the third surface.

[0231] Example 60 provides the microelectronic assembly of any of Examples 56-59, wherein the third IC die further comprises a TSV (eg, 330 ) passing through a respective substrate of the third IC die.

[0232] Example 61 provides the microelectronic assembly of any of Examples 56-60, further comprising (e.g., Fig.10): a first plurality of first IC dies coupled to a second surface of a second IC die along a corresponding first surface of the first IC die, the first plurality of first IC dies also coupled to a fourth surface of a third IC die along a corresponding third surface of the first IC die; and a second plurality of fourth IC dies coupled to a fifth surface of the third IC die along a corresponding sixth surface of the fourth IC die, wherein: each first IC die comprises a corresponding substrate attached to a corresponding metallization stack along a corresponding planar interface orthogonal to the corresponding first surface, and each fourth IC die comprises a corresponding substrate attached to a corresponding metallization stack along a corresponding planar interface orthogonal to the corresponding sixth surface.

[0233] Example 62 provides the microelectronic assembly of any of Examples 56-61, wherein: the first IC dies in the first plurality of first IC dies are parallel to and spaced apart from each other, and the fourth IC dies in the second plurality of fourth IC dies are parallel to and spaced apart from each other.

[0234] Example 63 provides the microelectronic assembly of Example 62, further comprising (e.g., Fig.12 ) encapsulates a first plurality of first IC dies and a second plurality of second IC dies, wherein the another dielectric material is in spaces between adjacent first IC dies in the first IC dies and in spaces between adjacent fourth IC dies in the fourth IC dies.

[0235] Example 64 provides a microelectronic assembly (e.g., Figure 7 , Figure 8 ), comprising: a first IC die (e.g., 100(1)) having a surface (e.g., 104, 114), the first IC die comprising a first region (e.g., 102(1)) and a second region (e.g., 110(1)), the second region being attached to the first region along a first planar interface orthogonal to the surface; and a second IC die (e.g., 100(2)) coupled to the first IC die on the surface, the second IC die comprising a third region and a fourth region, the fourth region being attached to the third region along a second planar interface orthogonal to the surface, wherein: the first region and the third region comprise corresponding metallization stacks having conductive traces orthogonal to the surface, and the second region and the fourth region comprise corresponding substrates having active circuits proximate to and parallel to the corresponding planar interfaces.

[0236] Example 65 provides the microelectronic assembly of Example 64, wherein: the second IC die is coupled to the first IC die on the surface (e.g., 104) via metal-to-metal bonding and dielectric-to-dielectric bonding, the metal-to-metal bonding comprising portions of corresponding conductive traces of the first IC die and the second IC die.

[0237] Example 66 provides the microelectronic assembly of Example 64, wherein the second IC die is coupled to the first IC die on the surface (eg, 604) by dielectric-to-dielectric bonding.

[0238] Example 67 provides the microelectronic assembly of any of Examples 64-66, wherein (e.g., Figure 8 ): the surface is a first surface (e.g., 604), the first IC die has a second surface (e.g., 104) opposite to the first surface, and the microelectronic assembly also includes a third IC die (e.g., 302), and the third surface (e.g., 306) of the third IC die is coupled to the second surface of the first IC die.

[0239] Example 68 provides the microelectronic assembly of Example 67, wherein the third IC die includes a respective substrate (eg, 318) attached to the respective metallization stack (eg, 314) along a third planar interface (eg, 320) parallel to the first surface and the second surface.

[0240] Example 69 provides a microelectronic assembly of any of Examples 67-68 (e.g., Figure 8 ), wherein the first IC die and the second IC die together are an IC die stack, and the microelectronic assembly further comprises a plurality of IC die stacks arranged in parallel rows and columns and coupled to a third surface of a third IC die.

[0241] Example 70 provides the microelectronic assembly of Example 67, wherein (for example, Fig. 9 ): The second IC die has a fourth surface (e.g., 104(2)) opposite to the first surface (e.g., 604), and the microelectronic assembly also includes a fourth IC die (e.g., 302(2)) parallel to the third IC die (e.g., 302(1)), and a fifth surface (e.g., 306(2)) of the fourth IC die is coupled to the fourth surface of the second IC die.

[0242] Example 71 provides the microelectronic assembly of Example 70, wherein (for example, Fig. 9 ), the first IC die and the second IC die together are an IC die stack, and the microelectronic assembly further comprises a plurality of IC die stacks arranged in parallel rows and columns, each IC die stack coupled to a third surface of a third IC die and a fifth surface of a fourth IC die.

[0243] Example 72 provides the microelectronic assembly of Example 71, wherein (for example, Fig.13): The IC die stacks in the multiple IC die stacks are parallel to each other and spaced apart from each other, the microelectronic assembly also includes another dielectric material (e.g., 1102) encapsulating the multiple IC die stacks, and the other dielectric material is in the space between adjacent IC die stacks in the IC die stacks.

[0244] Example 73 provides a method for manufacturing an IC die with a planarized edge, comprising (e.g., FIG. 14): providing a first carrier (e.g., 1402) and a wafer (e.g., 1404) bonded to the first carrier, the wafer comprising a plurality of IC die manufactured thereon, each IC die comprising a substrate attached to a metallization stack along a planar interface, the metallization stack comprising conductive traces parallel to the planar interface, each IC die being as wide and as long as any other IC die in the wafer; positioning the first carrier and the wafer horizontally so that the first carrier is below the wafer and a surface of the wafer opposite to the first carrier (e.g., 1412) faces upward; forming an interface layer (e.g., 1414) on a surface of the wafer opposite to the first carrier, the interface layer comprising a material containing silicon and oxygen (e.g., 1418); attaching another wafer to the interface layer; repeating the formation of the interface layer and attaching another wafer until a desired height is obtained above the first carrier; A second carrier is attached to a surface of the topmost wafer opposite to the first carrier; singulating vertically to form a plurality of stacks along a surface of the IC die configured to have bonding pads, the surface configured to have bonding pads being orthogonal to an interface between adjacent wafers in the stack such that each stack is as wide or as long as any one IC die; rotating each stack ninety degrees such that the first carrier and the second carrier are vertically oriented and the interface between adjacent wafers is vertical; attaching the plurality of stacks to a horizontal bonding surface of a third carrier such that the interface between adjacent wafers is orthogonal to the bonding surface of the third carrier; depositing a dielectric material around the plurality of stacks over the bonding surface of the third carrier such that a continuous horizontal surface is exposed opposite to the third carrier; flattening the continuous horizontal surface to expose the bonding pads of the IC die in the wafer, each bonding pad comprising a portion of a corresponding conductive trace; removing the dielectric material; and separating the IC die from each stack.

[0245] Example 74 provides the method of Example 73, wherein the interface layer further includes a metal bonding pad (e.g., 1416).

[0246] Example 75 provides a method of any one of Examples 73-74, wherein: the stack is a first stack, each first stack is as wide as any one IC die, each first stack is longer than any one IC die, and the method further includes: after flattening the continuous horizontal surface, singulating the first stack into second stacks, each second stack is as long as any one IC die.

[0247] Example 76 provides the method of any of Examples 73-75, wherein providing a first carrier and a wafer bonded to the first carrier includes: forming a layer including silicon and oxygen (e.g., 1406) on the first carrier; and bonding the wafer to the layer including silicon and oxygen.

[0248] Example 77 provides the method of any of Examples 73-76, further comprising: planarizing a surface of the wafer opposite to the carrier before forming the interface layer.

[0249] Example 78 provides the method of Example 77, wherein at least one wafer has a thickness in a range between 700 microns and 800 microns before planarization and has a thickness in a range between 50 microns and 100 microns after planarization.

[0250] Example 79 provides the method of any of Examples 77-78, wherein at least one of the IC dies includes a TSV passing through the respective substrate, and planarization is performed until a surface of the TSV is exposed on the wafer.

[0251] Example 80 provides the method of any of Examples 73-79, wherein: the dielectric material comprises an organic polymer, and removing the dielectric material comprises etching with a cleaner.

[0252] Example 81 provides the method of any of Examples 73-80, wherein separating the IC die from each stack includes releasing the wafers from the first carrier and the second carrier, and debonding each IC die from an interface layer between the wafers by CMP of each interface layer.

[0253] Example 82 provides the method of any of Examples 73-81, wherein the wafers are non-conductively connected to each other.

[0254] Example 83 provides the method of any of Examples 73-82, wherein the subset of the interface layers includes metal bonding pads such that wafers adjacent to the subset of the interface layers are conductively connected to each other through the metal bonding pads.

[0255] Example 84 provides the method of any of Examples 73-83, wherein the number of wafers in each stack is in a range between 5 and 10.

[0256] Example 85 provides the method of any of Examples 73-84, wherein planarizing the continuous horizontal surface comprises CMP.

[0257] Example 86 provides the method of any of Examples 73-85, wherein any one IC die is no more than 5 mm wide and no more than 35 mm long.

[0258] The above description of the embodiments shown in the present disclosure (including the contents described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

Claims

1. An integrated circuit (IC) die, comprising: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; as well as a second region attached to the first region along a planar interface normal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface; in: The first area includes: Dielectric materials; a plurality of layers of conductive traces in the dielectric material, each layer of conductive traces being parallel to the second surface, such that the conductive trace is orthogonal to the first surface; a conductive via through the dielectric material, the conductive via being orthogonal to the conductive trace; and a bonding pad on the first surface, the bonding pad comprising a portion of the conductive trace exposed on the first surface, and The second region includes a material different from the dielectric material.

2. The IC die according to claim 1, wherein: The second region includes at least one of a transistor and a diode proximate the planar interface between the first region and the second region.

3. The IC die according to any one of claims 1 to 5, wherein: The second region does not include any transistors or diodes.

4. The IC die according to any one of claims 1 to 3, wherein: The first surface is flat and planar, wherein the surface roughness is less than 10 angstroms and the total thickness variation (TTV) across the first surface is less than 3 microns.

5. The IC die of claim 4, wherein: A surface opposite the first surface and orthogonal to the second surface is flat and planar, wherein the surface roughness is less than 10 angstroms and the TTV of the entire first surface is less than 3 microns.

6. The IC die according to any one of claims 1 to 5, wherein: The bond pads include a first bond pad, and the first region also includes a second bond pad on the second surface.

7. The IC die of any one of claims 1 to 6, wherein: The IC die is less than 100 microns along a first axis, less than 35 millimeters along a second axis orthogonal to the first axis, and less than 5 millimeters along a third axis orthogonal to the first axis and the second axis, and The first axis is parallel to the first surface and perpendicular to the second surface.

8. The IC die according to any one of claims 1 to 7, wherein: The first area also includes: a bonding pad on the second surface; a bonding pad on a fourth surface, the fourth surface being orthogonal to the first surface and the second surface; a bonding pad on a fifth surface, the fifth surface being parallel to the first surface and orthogonal to the second surface and the fifth surface; and A bonding pad is provided on a sixth surface, the sixth surface being parallel to the fourth surface and being orthogonal to the first surface, the second surface and the fifth surface.

9. A microelectronic assembly comprising: a first IC die coupled to the second IC die via interconnects on a first surface of the first IC die and a second surface of the second IC die such that the first surface is in contact with the second surface, in: The interconnects include dielectric-dielectric bonding and metal-metal bonding, The metal-to-metal bond includes a first bonding pad in the first IC die and a second bonding pad in the second IC die, The first IC die includes a substrate attached to a metallization stack along a planar interface orthogonal to the first surface, The metallization stack includes multiple layers of conductive traces in a dielectric material, and The first bond pad includes a portion of the conductive trace exposed on the first surface.

10. The microelectronic assembly of any one of claims 9, further comprising another dielectric material surrounding the first IC die, the other dielectric material contacting the second surface of the second IC die.

11. The microelectronic assembly according to any one of claims 9 to 10, wherein: The substrate of the first IC die is in contact with the second surface of the second IC die.

12. A microelectronic assembly according to any one of claims 9 to 11, wherein: The interconnects have a pitch of less than 10 microns between adjacent interconnects.

13. A microelectronic assembly according to any one of claims 9 to 12, wherein: the substrate is a first substrate, the metallization stack is a first metallization stack, and the dielectric material is a first dielectric material, The second IC die includes a second metallization stack and a second substrate, The second substrate is attached to the second metallization stack along another planar interface parallel to the second surface, and The second metallization stack includes a conductive trace in a second dielectric material, the conductive trace coupled to the second bond pad through a conductive via.

14. A microelectronic assembly according to any one of claims 9 to 13, wherein: the substrate is a first substrate, the metallization stack is a first metallization stack, the conductive trace is a first conductive trace, and the dielectric material is a first dielectric material, The second IC die includes a second metallization stack, a second substrate, the second substrate is attached to the second metallization stack along another planar interface parallel to the second surface, The second IC die also includes at least one interface layer on a side of the second substrate opposite the second metallization stack, the interface layer including the second bond pad in a layer of a second dielectric material, and The second metallization stack includes a second conductive trace in a third dielectric material, the second conductive trace coupled through a conductive via.

15. The microelectronic assembly of claim 9, further comprising a plurality of first IC dies coupled to the second IC die along respective first surfaces of the first IC die, wherein: Each first IC die includes a respective substrate attached to a respective metallization stack along a respective planar interface, and The respective planar interfaces are orthogonal to the respective first surfaces.

16. A microelectronic assembly as claimed in claim 15, wherein: The planar interface is a first planar interface, At least two first IC dies of the plurality of IC dies are in contact with each other along a second planar interface normal to the first surface, and the at least two first IC dies in contact are bonded along the second planar interface at least by dielectric-to-dielectric bonding.

17. A microelectronic assembly according to any one of claims 15 to 16, wherein: The first IC dies of the plurality of first IC dies are parallel to each other and spaced apart from each other, The microelectronic assembly also includes another dielectric material encapsulating the plurality of first IC dies, and The another dielectric material is in spaces between adjacent ones of the first IC dies.

18. A microelectronic assembly according to any one of claims 15 to 17, wherein: The first IC dies in the plurality of first IC dies are parallel to each other, and There are gaps between adjacent ones of the first IC dies.

19. A microelectronic assembly according to any one of claims 15 to 18, wherein: The plurality of first IC dies are arranged in an array of rows and columns.

20. The microelectronic assembly of claim 9, wherein: The planar interface is a first planar interface, the interconnect being a first interconnect, The first IC die has a third surface opposite to the first surface, The microelectronic assembly further comprises: a third IC die having a fourth surface and a fifth surface, the fifth surface opposite the fourth surface, the fourth surface coupled to the third surface of the first IC die through a second interconnect; and a fourth IC die having a sixth surface, the sixth surface coupled to the fifth surface of the third IC die via a third interconnect, in: the second IC die comprising a respective substrate attached to a respective metallization stack along a second planar interface orthogonal to the first planar interface, The third IC die includes a respective substrate attached to a respective metallization stack along a third planar interface orthogonal to the first planar interface, and The fourth IC die includes a respective substrate attached to a respective metallization stack along a fourth planar interface parallel to the first planar interface.

21. A method of manufacturing an IC die having planarized edges, comprising: providing a first carrier and a wafer bonded to the first carrier, the wafer including a plurality of IC dies fabricated thereon, each IC die including a substrate attached to a metallization stack along a planar interface, the metallization stack including conductive traces parallel to the planar interface, each IC die being as wide and as long as any other IC die in the wafer; Positioning the first carrier and the wafer horizontally so that the first carrier is below the wafer and a surface of the wafer opposite to the first carrier faces upward; forming an interface layer on the surface of the wafer opposite to the first carrier, the interface layer comprising a material containing silicon and oxygen; attaching another wafer to the interface layer; Repeating forming the interface layer and attaching another wafer until a desired height is obtained above the first carrier; attaching a second carrier to a surface of the topmost wafer opposite the first carrier; vertically singulating to form a plurality of stacks along surfaces of the IC die configured with bonding pads, the surfaces configured with bonding pads being orthogonal to interfaces between adjacent wafers in the stacks, such that each stack is as wide or as long as any one IC die; rotating each stack ninety degrees so that the first carrier and the second carrier are oriented vertically and the interface between adjacent wafers is vertical; attaching the plurality of stacks to a horizontal bonding surface of a third carrier such that the interface between adjacent wafers is orthogonal to the bonding surface of the third carrier; depositing a dielectric material around the plurality of stacks over the bonding surface of the third carrier such that a continuous horizontal surface is exposed opposite the third carrier; planarizing the continuous horizontal surface to expose bond pads of the IC dies in the wafer, each bond pad comprising a portion of a corresponding conductive trace; removing the dielectric material; as well as The IC dies are separated from each stack.

22. The method according to any one of claims 21, wherein: The stack is a first stack, Each first stack is as wide as any one IC die, Each first stack is longer than any one IC die, and The method further includes singulating the first stack into second stacks after planarizing the continuous horizontal surface, each second stack being as long as any one IC die.

23. The method according to any one of claims 21-22, wherein: Providing the first carrier and the wafer bonded to the first carrier includes: forming a layer including silicon and oxygen on the first carrier; and The wafer is bonded to the layer comprising silicon and oxygen.

24. The method according to any one of claims 21 to 23, wherein: The dielectric material comprises an organic polymer, and Removing the dielectric material includes etching with a cleaner.

25. The method according to any one of claims 21 to 24, wherein: Separating the IC die from each stack includes: releasing the wafer from the first carrier and the second carrier, and Each IC die is debonded from the interface layers between the wafers by chemical mechanical polishing (CMP) of each interface layer.

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